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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.27 98.14 95.96 97.44 88.89 98.26 98.17 90.05


Total test records in report: 3740
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T3569 /workspace/coverage/default/9.usbdev_stream_len_max.3216796516 Aug 08 06:15:02 PM PDT 24 Aug 08 06:15:06 PM PDT 24 1304477634 ps
T3570 /workspace/coverage/default/43.usbdev_device_timeout.3876588119 Aug 08 06:20:01 PM PDT 24 Aug 08 06:20:36 PM PDT 24 3871954288 ps
T3571 /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2413758112 Aug 08 06:15:02 PM PDT 24 Aug 08 06:15:10 PM PDT 24 5860122088 ps
T3572 /workspace/coverage/default/2.usbdev_iso_retraction.1905487405 Aug 08 06:13:35 PM PDT 24 Aug 08 06:14:11 PM PDT 24 5035098966 ps
T3573 /workspace/coverage/default/18.usbdev_in_iso.4031865445 Aug 08 06:16:37 PM PDT 24 Aug 08 06:16:39 PM PDT 24 206280794 ps
T3574 /workspace/coverage/default/20.usbdev_phy_pins_sense.236228970 Aug 08 06:16:56 PM PDT 24 Aug 08 06:16:57 PM PDT 24 55283239 ps
T3575 /workspace/coverage/default/40.usbdev_fifo_rst.3831312501 Aug 08 06:20:04 PM PDT 24 Aug 08 06:20:07 PM PDT 24 261366767 ps
T3576 /workspace/coverage/default/44.usbdev_out_iso.4395611 Aug 08 06:20:16 PM PDT 24 Aug 08 06:20:17 PM PDT 24 155672753 ps
T3577 /workspace/coverage/default/33.usbdev_max_length_in_transaction.547568889 Aug 08 06:18:50 PM PDT 24 Aug 08 06:18:52 PM PDT 24 253943978 ps
T3578 /workspace/coverage/default/9.usbdev_endpoint_access.136807962 Aug 08 06:15:02 PM PDT 24 Aug 08 06:15:04 PM PDT 24 869962717 ps
T3579 /workspace/coverage/default/22.usbdev_random_length_out_transaction.4270270958 Aug 08 06:17:20 PM PDT 24 Aug 08 06:17:22 PM PDT 24 219050988 ps
T3580 /workspace/coverage/default/22.usbdev_in_stall.3856242580 Aug 08 06:17:06 PM PDT 24 Aug 08 06:17:06 PM PDT 24 156696313 ps
T3581 /workspace/coverage/default/38.usbdev_device_address.3032573590 Aug 08 06:19:21 PM PDT 24 Aug 08 06:20:42 PM PDT 24 51832557492 ps
T3582 /workspace/coverage/default/17.usbdev_out_iso.1348917943 Aug 08 06:16:34 PM PDT 24 Aug 08 06:16:35 PM PDT 24 170596347 ps
T3583 /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1698043127 Aug 08 06:17:30 PM PDT 24 Aug 08 06:17:31 PM PDT 24 177010251 ps
T3584 /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1912126661 Aug 08 06:19:35 PM PDT 24 Aug 08 06:19:58 PM PDT 24 3131448745 ps
T3585 /workspace/coverage/default/37.usbdev_device_address.4224601359 Aug 08 06:19:24 PM PDT 24 Aug 08 06:20:06 PM PDT 24 23673653073 ps
T3586 /workspace/coverage/default/7.usbdev_streaming_out.1094569504 Aug 08 06:14:42 PM PDT 24 Aug 08 06:16:00 PM PDT 24 2643948163 ps
T3587 /workspace/coverage/default/1.usbdev_freq_loclk_max.163674305 Aug 08 06:13:29 PM PDT 24 Aug 08 06:16:15 PM PDT 24 109075186819 ps
T3588 /workspace/coverage/default/41.usbdev_data_toggle_clear.3198974595 Aug 08 06:20:02 PM PDT 24 Aug 08 06:20:04 PM PDT 24 407802753 ps
T3589 /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.678454294 Aug 08 06:15:59 PM PDT 24 Aug 08 06:16:38 PM PDT 24 1411037430 ps
T3590 /workspace/coverage/default/22.usbdev_smoke.73851792 Aug 08 06:17:12 PM PDT 24 Aug 08 06:17:13 PM PDT 24 186411203 ps
T3591 /workspace/coverage/default/462.usbdev_tx_rx_disruption.54094603 Aug 08 06:22:35 PM PDT 24 Aug 08 06:22:37 PM PDT 24 524727129 ps
T3592 /workspace/coverage/default/347.usbdev_tx_rx_disruption.4028046075 Aug 08 06:22:24 PM PDT 24 Aug 08 06:22:28 PM PDT 24 491624314 ps
T3593 /workspace/coverage/default/118.usbdev_tx_rx_disruption.2586062012 Aug 08 06:21:24 PM PDT 24 Aug 08 06:21:26 PM PDT 24 542443937 ps
T3594 /workspace/coverage/default/29.usbdev_pending_in_trans.1244068533 Aug 08 06:18:15 PM PDT 24 Aug 08 06:18:16 PM PDT 24 165541208 ps
T3595 /workspace/coverage/default/33.usbdev_enable.793934520 Aug 08 06:18:47 PM PDT 24 Aug 08 06:18:48 PM PDT 24 71761101 ps
T3596 /workspace/coverage/default/1.usbdev_setup_priority.216310655 Aug 08 06:13:28 PM PDT 24 Aug 08 06:13:29 PM PDT 24 412714985 ps
T3597 /workspace/coverage/default/10.usbdev_phy_config_pinflip.1426054434 Aug 08 06:15:37 PM PDT 24 Aug 08 06:15:38 PM PDT 24 224483166 ps
T3598 /workspace/coverage/default/94.usbdev_endpoint_types.1557684125 Aug 08 06:21:13 PM PDT 24 Aug 08 06:21:15 PM PDT 24 842003861 ps
T3599 /workspace/coverage/default/142.usbdev_tx_rx_disruption.1242455673 Aug 08 06:21:26 PM PDT 24 Aug 08 06:21:28 PM PDT 24 533356610 ps
T3600 /workspace/coverage/default/15.usbdev_resume_link_active.67547446 Aug 08 06:16:02 PM PDT 24 Aug 08 06:16:25 PM PDT 24 20156706079 ps
T3601 /workspace/coverage/default/23.usbdev_alert_test.2994205512 Aug 08 06:17:28 PM PDT 24 Aug 08 06:17:29 PM PDT 24 35481265 ps
T3602 /workspace/coverage/default/35.usbdev_min_length_in_transaction.644223273 Aug 08 06:19:03 PM PDT 24 Aug 08 06:19:04 PM PDT 24 151946114 ps
T3603 /workspace/coverage/default/46.usbdev_in_trans.2106129378 Aug 08 06:20:51 PM PDT 24 Aug 08 06:20:52 PM PDT 24 190936998 ps
T3604 /workspace/coverage/default/400.usbdev_tx_rx_disruption.673960704 Aug 08 06:22:35 PM PDT 24 Aug 08 06:22:37 PM PDT 24 467769806 ps
T3605 /workspace/coverage/default/20.usbdev_smoke.1625026326 Aug 08 06:16:57 PM PDT 24 Aug 08 06:16:58 PM PDT 24 207390591 ps
T3606 /workspace/coverage/default/13.usbdev_pending_in_trans.2560704514 Aug 08 06:15:48 PM PDT 24 Aug 08 06:15:49 PM PDT 24 151531861 ps
T3607 /workspace/coverage/default/385.usbdev_tx_rx_disruption.3206952189 Aug 08 06:22:26 PM PDT 24 Aug 08 06:22:28 PM PDT 24 630058929 ps
T3608 /workspace/coverage/default/19.usbdev_pkt_received.1266215678 Aug 08 06:17:01 PM PDT 24 Aug 08 06:17:02 PM PDT 24 155636419 ps
T3609 /workspace/coverage/default/147.usbdev_tx_rx_disruption.335390637 Aug 08 06:21:43 PM PDT 24 Aug 08 06:21:45 PM PDT 24 544376947 ps
T3610 /workspace/coverage/default/40.usbdev_setup_trans_ignored.3733798933 Aug 08 06:19:54 PM PDT 24 Aug 08 06:19:55 PM PDT 24 172512036 ps
T3611 /workspace/coverage/default/32.usbdev_out_stall.3221942821 Aug 08 06:18:43 PM PDT 24 Aug 08 06:18:44 PM PDT 24 165297347 ps
T3612 /workspace/coverage/default/14.usbdev_low_speed_traffic.588070150 Aug 08 06:16:00 PM PDT 24 Aug 08 06:17:36 PM PDT 24 3459987910 ps
T3613 /workspace/coverage/default/12.usbdev_random_length_out_transaction.2452920876 Aug 08 06:15:50 PM PDT 24 Aug 08 06:15:52 PM PDT 24 172650299 ps
T3614 /workspace/coverage/default/49.usbdev_max_length_in_transaction.2874274674 Aug 08 06:20:55 PM PDT 24 Aug 08 06:20:56 PM PDT 24 236962657 ps
T3615 /workspace/coverage/default/31.usbdev_phy_config_pinflip.3658728522 Aug 08 06:18:24 PM PDT 24 Aug 08 06:18:25 PM PDT 24 222544713 ps
T3616 /workspace/coverage/default/453.usbdev_tx_rx_disruption.3385125781 Aug 08 06:22:37 PM PDT 24 Aug 08 06:22:39 PM PDT 24 663431858 ps
T3617 /workspace/coverage/default/28.usbdev_data_toggle_clear.4102280686 Aug 08 06:17:55 PM PDT 24 Aug 08 06:17:57 PM PDT 24 522356871 ps
T3618 /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3960074346 Aug 08 06:14:14 PM PDT 24 Aug 08 06:16:07 PM PDT 24 7205754277 ps
T3619 /workspace/coverage/default/2.usbdev_random_length_in_transaction.1443415701 Aug 08 06:13:45 PM PDT 24 Aug 08 06:13:46 PM PDT 24 233223970 ps
T3620 /workspace/coverage/default/34.usbdev_stream_len_max.915999797 Aug 08 06:19:04 PM PDT 24 Aug 08 06:19:07 PM PDT 24 1300060560 ps
T3621 /workspace/coverage/default/167.usbdev_endpoint_types.467690170 Aug 08 06:21:36 PM PDT 24 Aug 08 06:21:38 PM PDT 24 493014234 ps
T3622 /workspace/coverage/default/2.usbdev_setup_stage.3116450276 Aug 08 06:13:42 PM PDT 24 Aug 08 06:13:43 PM PDT 24 180202106 ps
T3623 /workspace/coverage/default/28.usbdev_iso_retraction.3611514657 Aug 08 06:18:00 PM PDT 24 Aug 08 06:18:45 PM PDT 24 3626925687 ps
T3624 /workspace/coverage/default/15.usbdev_random_length_in_transaction.688021286 Aug 08 06:16:04 PM PDT 24 Aug 08 06:16:05 PM PDT 24 208985921 ps
T3625 /workspace/coverage/default/27.usbdev_out_stall.1773460284 Aug 08 06:17:51 PM PDT 24 Aug 08 06:17:52 PM PDT 24 163589778 ps
T3626 /workspace/coverage/default/46.usbdev_av_buffer.3445510996 Aug 08 06:20:31 PM PDT 24 Aug 08 06:20:32 PM PDT 24 143497095 ps
T3627 /workspace/coverage/default/187.usbdev_tx_rx_disruption.3285869003 Aug 08 06:21:48 PM PDT 24 Aug 08 06:21:50 PM PDT 24 574241313 ps
T3628 /workspace/coverage/default/113.usbdev_endpoint_types.16066361 Aug 08 06:21:28 PM PDT 24 Aug 08 06:21:30 PM PDT 24 460021850 ps
T3629 /workspace/coverage/default/16.usbdev_rx_full.2998307819 Aug 08 06:16:22 PM PDT 24 Aug 08 06:16:23 PM PDT 24 273839458 ps
T3630 /workspace/coverage/default/8.usbdev_resume_link_active.1702153085 Aug 08 06:14:49 PM PDT 24 Aug 08 06:15:16 PM PDT 24 20247499274 ps
T3631 /workspace/coverage/default/363.usbdev_tx_rx_disruption.3865579813 Aug 08 06:22:20 PM PDT 24 Aug 08 06:22:21 PM PDT 24 512733076 ps
T3632 /workspace/coverage/default/38.usbdev_setup_trans_ignored.4291940378 Aug 08 06:19:37 PM PDT 24 Aug 08 06:19:38 PM PDT 24 149399575 ps
T3633 /workspace/coverage/default/2.usbdev_rand_bus_disconnects.399745877 Aug 08 06:13:46 PM PDT 24 Aug 08 06:14:09 PM PDT 24 6262846365 ps
T260 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2198304665 Aug 08 05:39:03 PM PDT 24 Aug 08 05:39:04 PM PDT 24 131879106 ps
T277 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3241848817 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:19 PM PDT 24 72507799 ps
T261 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.533317916 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 52063235 ps
T215 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2532961340 Aug 08 05:38:10 PM PDT 24 Aug 08 05:38:14 PM PDT 24 493253152 ps
T216 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.734646481 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:20 PM PDT 24 214801990 ps
T312 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2159858807 Aug 08 05:38:26 PM PDT 24 Aug 08 05:38:27 PM PDT 24 104508349 ps
T299 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3318505732 Aug 08 05:38:29 PM PDT 24 Aug 08 05:38:38 PM PDT 24 1853666504 ps
T217 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.738256391 Aug 08 05:39:14 PM PDT 24 Aug 08 05:39:16 PM PDT 24 481143579 ps
T223 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3877316841 Aug 08 05:39:22 PM PDT 24 Aug 08 05:39:23 PM PDT 24 34793942 ps
T313 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.565958109 Aug 08 05:39:15 PM PDT 24 Aug 08 05:39:16 PM PDT 24 204899662 ps
T300 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.508990157 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:50 PM PDT 24 77132680 ps
T259 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4017373617 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:03 PM PDT 24 980511402 ps
T226 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2485821317 Aug 08 05:38:31 PM PDT 24 Aug 08 05:38:31 PM PDT 24 36989806 ps
T224 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2840314226 Aug 08 05:39:19 PM PDT 24 Aug 08 05:39:20 PM PDT 24 55625708 ps
T225 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.915250379 Aug 08 05:39:23 PM PDT 24 Aug 08 05:39:23 PM PDT 24 53181295 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2397472359 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:22 PM PDT 24 107311859 ps
T227 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1150995778 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 54999352 ps
T258 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2564422774 Aug 08 05:38:59 PM PDT 24 Aug 08 05:39:00 PM PDT 24 76486217 ps
T3634 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3710498249 Aug 08 05:38:26 PM PDT 24 Aug 08 05:38:35 PM PDT 24 1015834518 ps
T265 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2210236930 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:20 PM PDT 24 174993333 ps
T319 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3064481790 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 43671435 ps
T314 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1597351062 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:50 PM PDT 24 117556090 ps
T340 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3406332921 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:21 PM PDT 24 48658909 ps
T264 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2873561553 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:44 PM PDT 24 1339253335 ps
T342 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.577850080 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:50 PM PDT 24 45037164 ps
T320 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2966448390 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 48022598 ps
T301 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2841395439 Aug 08 05:38:28 PM PDT 24 Aug 08 05:38:30 PM PDT 24 100548733 ps
T302 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3690040509 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 126662015 ps
T341 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.914346098 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 64233358 ps
T343 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4105169834 Aug 08 05:39:10 PM PDT 24 Aug 08 05:39:11 PM PDT 24 40400635 ps
T345 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1441716174 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 48550132 ps
T3635 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3176733561 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:22 PM PDT 24 118361133 ps
T278 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1652209574 Aug 08 05:38:52 PM PDT 24 Aug 08 05:38:54 PM PDT 24 262719937 ps
T281 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2579035600 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:17 PM PDT 24 2047637567 ps
T346 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2420624713 Aug 08 05:39:22 PM PDT 24 Aug 08 05:39:23 PM PDT 24 52220065 ps
T282 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.709403174 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:17 PM PDT 24 1369939590 ps
T3636 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2392991183 Aug 08 05:38:51 PM PDT 24 Aug 08 05:38:51 PM PDT 24 32280241 ps
T283 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3256936281 Aug 08 05:38:54 PM PDT 24 Aug 08 05:38:59 PM PDT 24 728583006 ps
T315 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1954767950 Aug 08 05:38:57 PM PDT 24 Aug 08 05:38:59 PM PDT 24 218201100 ps
T344 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3006333501 Aug 08 05:39:20 PM PDT 24 Aug 08 05:39:21 PM PDT 24 98422780 ps
T284 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.551232169 Aug 08 05:38:54 PM PDT 24 Aug 08 05:38:58 PM PDT 24 499231404 ps
T3637 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2566807473 Aug 08 05:38:33 PM PDT 24 Aug 08 05:38:35 PM PDT 24 102672685 ps
T316 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2461794858 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:41 PM PDT 24 138528394 ps
T3638 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2566107906 Aug 08 05:39:19 PM PDT 24 Aug 08 05:39:20 PM PDT 24 41068361 ps
T3639 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.358150906 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 232643003 ps
T309 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1450655093 Aug 08 05:38:29 PM PDT 24 Aug 08 05:38:30 PM PDT 24 93121524 ps
T273 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2520212406 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:01 PM PDT 24 122543610 ps
T3640 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.845087425 Aug 08 05:38:50 PM PDT 24 Aug 08 05:38:51 PM PDT 24 52604298 ps
T3641 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1883789944 Aug 08 05:38:25 PM PDT 24 Aug 08 05:38:26 PM PDT 24 93501276 ps
T3642 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1967973214 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:39 PM PDT 24 48808423 ps
T3643 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1739916686 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 117295262 ps
T3644 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4031576480 Aug 08 05:38:33 PM PDT 24 Aug 08 05:38:35 PM PDT 24 191692464 ps
T303 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1894086238 Aug 08 05:38:10 PM PDT 24 Aug 08 05:38:11 PM PDT 24 78810579 ps
T304 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1554752115 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:42 PM PDT 24 334325799 ps
T3645 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2591908064 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:21 PM PDT 24 70970980 ps
T285 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3662377367 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 90733382 ps
T305 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.530573520 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:40 PM PDT 24 90305717 ps
T3646 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4201849119 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 33267749 ps
T3647 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.528453495 Aug 08 05:38:26 PM PDT 24 Aug 08 05:38:27 PM PDT 24 46998689 ps
T3648 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2933610474 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 58097225 ps
T3649 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4270741528 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 42769485 ps
T3650 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1303049591 Aug 08 05:39:20 PM PDT 24 Aug 08 05:39:21 PM PDT 24 77990902 ps
T3651 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3656768108 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 46062312 ps
T3652 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.886314268 Aug 08 05:39:19 PM PDT 24 Aug 08 05:39:20 PM PDT 24 39135802 ps
T496 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3183322045 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:54 PM PDT 24 1539156206 ps
T3653 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2352332860 Aug 08 05:39:22 PM PDT 24 Aug 08 05:39:23 PM PDT 24 84835504 ps
T3654 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2949659619 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:42 PM PDT 24 401572481 ps
T306 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3125040387 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:21 PM PDT 24 210470803 ps
T3655 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1124351954 Aug 08 05:38:57 PM PDT 24 Aug 08 05:38:58 PM PDT 24 59897235 ps
T271 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2728459358 Aug 08 05:38:50 PM PDT 24 Aug 08 05:38:52 PM PDT 24 65073014 ps
T3656 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1893834834 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:13 PM PDT 24 51966113 ps
T3657 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1310075704 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:40 PM PDT 24 199957085 ps
T3658 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1319330162 Aug 08 05:38:48 PM PDT 24 Aug 08 05:38:50 PM PDT 24 64766690 ps
T266 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2088950711 Aug 08 05:38:57 PM PDT 24 Aug 08 05:39:00 PM PDT 24 102042768 ps
T3659 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3764796683 Aug 08 05:39:03 PM PDT 24 Aug 08 05:39:05 PM PDT 24 149450357 ps
T267 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.522711910 Aug 08 05:39:10 PM PDT 24 Aug 08 05:39:13 PM PDT 24 243812363 ps
T274 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1953161730 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:51 PM PDT 24 204623188 ps
T3660 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3783231980 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:50 PM PDT 24 184249493 ps
T272 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4266241083 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:15 PM PDT 24 296597097 ps
T3661 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2666573754 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 159133396 ps
T307 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.730756869 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 56751534 ps
T3662 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2219816074 Aug 08 05:39:20 PM PDT 24 Aug 08 05:39:21 PM PDT 24 51981164 ps
T279 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2483421005 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:01 PM PDT 24 107949814 ps
T280 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3799381467 Aug 08 05:39:13 PM PDT 24 Aug 08 05:39:15 PM PDT 24 93009505 ps
T3663 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3711775426 Aug 08 05:39:26 PM PDT 24 Aug 08 05:39:27 PM PDT 24 46805011 ps
T3664 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1167439540 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:39 PM PDT 24 45740873 ps
T3665 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2947134694 Aug 08 05:38:57 PM PDT 24 Aug 08 05:38:58 PM PDT 24 146042097 ps
T308 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3222515480 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:21 PM PDT 24 397601612 ps
T3666 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3416776992 Aug 08 05:39:23 PM PDT 24 Aug 08 05:39:23 PM PDT 24 50209903 ps
T3667 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2938459965 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 55457809 ps
T275 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1967744063 Aug 08 05:38:29 PM PDT 24 Aug 08 05:38:32 PM PDT 24 303163202 ps
T3668 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1785699844 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:13 PM PDT 24 43072200 ps
T3669 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2846100158 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:40 PM PDT 24 97911407 ps
T3670 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3758143622 Aug 08 05:38:09 PM PDT 24 Aug 08 05:38:10 PM PDT 24 111766904 ps
T3671 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1434022615 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:00 PM PDT 24 249712014 ps
T3672 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1250646827 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 73434080 ps
T3673 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2024025290 Aug 08 05:38:51 PM PDT 24 Aug 08 05:38:52 PM PDT 24 110688387 ps
T349 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3638223270 Aug 08 05:38:54 PM PDT 24 Aug 08 05:39:00 PM PDT 24 1135933447 ps
T3674 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3438018178 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:13 PM PDT 24 43600755 ps
T3675 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1305651964 Aug 08 05:39:03 PM PDT 24 Aug 08 05:39:05 PM PDT 24 137898195 ps
T3676 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3841824540 Aug 08 05:38:53 PM PDT 24 Aug 08 05:38:54 PM PDT 24 73610898 ps
T3677 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1676030460 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 289942135 ps
T3678 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1436945279 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 106760690 ps
T310 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2897205015 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:20 PM PDT 24 158091079 ps
T3679 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4271338184 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:00 PM PDT 24 71277897 ps
T276 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1504593595 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:19 PM PDT 24 48117024 ps
T311 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1496724005 Aug 08 05:38:40 PM PDT 24 Aug 08 05:38:42 PM PDT 24 104362264 ps
T3680 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.673813116 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 52007215 ps
T3681 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1727742427 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 40674639 ps
T352 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.468426969 Aug 08 05:38:58 PM PDT 24 Aug 08 05:39:03 PM PDT 24 892508395 ps
T3682 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2122143935 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 105256892 ps
T3683 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.234231480 Aug 08 05:38:31 PM PDT 24 Aug 08 05:38:34 PM PDT 24 101041713 ps
T3684 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2307131221 Aug 08 05:38:28 PM PDT 24 Aug 08 05:38:29 PM PDT 24 183262637 ps
T3685 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3516696734 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:12 PM PDT 24 161033700 ps
T350 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.896292214 Aug 08 05:39:22 PM PDT 24 Aug 08 05:39:25 PM PDT 24 733774701 ps
T3686 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2731145077 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:24 PM PDT 24 845591965 ps
T3687 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.689495784 Aug 08 05:39:13 PM PDT 24 Aug 08 05:39:14 PM PDT 24 183449083 ps
T3688 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2812167933 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:15 PM PDT 24 231724434 ps
T3689 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3836414812 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:13 PM PDT 24 87781490 ps
T351 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1648228700 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:42 PM PDT 24 712334778 ps
T3690 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3314049995 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:40 PM PDT 24 78516752 ps
T3691 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4117192415 Aug 08 05:38:53 PM PDT 24 Aug 08 05:38:54 PM PDT 24 85301993 ps
T497 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4281566908 Aug 08 05:38:28 PM PDT 24 Aug 08 05:38:31 PM PDT 24 462064019 ps
T3692 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3963277033 Aug 08 05:38:10 PM PDT 24 Aug 08 05:38:13 PM PDT 24 243520338 ps
T3693 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4045180591 Aug 08 05:39:19 PM PDT 24 Aug 08 05:39:20 PM PDT 24 46269338 ps
T3694 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3410335442 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 54991246 ps
T498 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3926711299 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:25 PM PDT 24 2158339951 ps
T3695 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1828967205 Aug 08 05:38:11 PM PDT 24 Aug 08 05:38:13 PM PDT 24 152615945 ps
T3696 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1941894551 Aug 08 05:38:54 PM PDT 24 Aug 08 05:38:56 PM PDT 24 139010060 ps
T3697 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2190760902 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 77911251 ps
T3698 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.675414433 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 38003719 ps
T3699 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1699614923 Aug 08 05:38:10 PM PDT 24 Aug 08 05:38:12 PM PDT 24 137325220 ps
T3700 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1209428629 Aug 08 05:39:19 PM PDT 24 Aug 08 05:39:19 PM PDT 24 46101310 ps
T3701 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1242168989 Aug 08 05:38:29 PM PDT 24 Aug 08 05:38:30 PM PDT 24 59009531 ps
T3702 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2775973152 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:40 PM PDT 24 95620860 ps
T3703 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3407727645 Aug 08 05:39:13 PM PDT 24 Aug 08 05:39:15 PM PDT 24 168576155 ps
T3704 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.164379203 Aug 08 05:38:25 PM PDT 24 Aug 08 05:38:27 PM PDT 24 93098037 ps
T3705 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3620662437 Aug 08 05:39:13 PM PDT 24 Aug 08 05:39:15 PM PDT 24 95027449 ps
T3706 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2676841227 Aug 08 05:38:50 PM PDT 24 Aug 08 05:38:51 PM PDT 24 81936935 ps
T3707 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3150778315 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 55601358 ps
T3708 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1686467330 Aug 08 05:38:50 PM PDT 24 Aug 08 05:38:52 PM PDT 24 273956629 ps
T347 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3452241039 Aug 08 05:38:18 PM PDT 24 Aug 08 05:38:24 PM PDT 24 962175924 ps
T3709 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2553212009 Aug 08 05:39:10 PM PDT 24 Aug 08 05:39:12 PM PDT 24 83825422 ps
T348 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3927895261 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:18 PM PDT 24 1184662267 ps
T3710 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1267745810 Aug 08 05:39:20 PM PDT 24 Aug 08 05:39:21 PM PDT 24 47829675 ps
T3711 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3517287003 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:20 PM PDT 24 103284886 ps
T3712 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2075143845 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 53088405 ps
T3713 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2217127066 Aug 08 05:39:02 PM PDT 24 Aug 08 05:39:07 PM PDT 24 528814688 ps
T3714 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3919824494 Aug 08 05:39:23 PM PDT 24 Aug 08 05:39:24 PM PDT 24 36870589 ps
T3715 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1807066779 Aug 08 05:38:59 PM PDT 24 Aug 08 05:39:00 PM PDT 24 30765987 ps
T3716 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3199371657 Aug 08 05:38:29 PM PDT 24 Aug 08 05:38:31 PM PDT 24 233448787 ps
T3717 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4196222326 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:50 PM PDT 24 156133376 ps
T3718 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3483505566 Aug 08 05:38:51 PM PDT 24 Aug 08 05:38:53 PM PDT 24 109164019 ps
T3719 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3727785974 Aug 08 05:38:39 PM PDT 24 Aug 08 05:38:44 PM PDT 24 633120228 ps
T3720 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2574467155 Aug 08 05:39:10 PM PDT 24 Aug 08 05:39:16 PM PDT 24 730299177 ps
T3721 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1515030256 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:23 PM PDT 24 189766776 ps
T3722 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4278172377 Aug 08 05:38:58 PM PDT 24 Aug 08 05:38:59 PM PDT 24 70193552 ps
T3723 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.989914420 Aug 08 05:38:28 PM PDT 24 Aug 08 05:38:29 PM PDT 24 64600188 ps
T3724 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3957522880 Aug 08 05:39:10 PM PDT 24 Aug 08 05:39:11 PM PDT 24 40234036 ps
T3725 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2436524727 Aug 08 05:38:59 PM PDT 24 Aug 08 05:39:00 PM PDT 24 205048389 ps
T3726 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2588818815 Aug 08 05:39:23 PM PDT 24 Aug 08 05:39:24 PM PDT 24 86900040 ps
T3727 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1880157411 Aug 08 05:38:59 PM PDT 24 Aug 08 05:39:04 PM PDT 24 524328679 ps
T3728 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2793730718 Aug 08 05:38:40 PM PDT 24 Aug 08 05:38:41 PM PDT 24 70817315 ps
T3729 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.167773207 Aug 08 05:38:49 PM PDT 24 Aug 08 05:38:52 PM PDT 24 136638751 ps
T3730 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3970827039 Aug 08 05:38:11 PM PDT 24 Aug 08 05:38:12 PM PDT 24 50982975 ps
T3731 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3711626943 Aug 08 05:39:11 PM PDT 24 Aug 08 05:39:14 PM PDT 24 185415743 ps
T3732 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3031542680 Aug 08 05:38:33 PM PDT 24 Aug 08 05:38:38 PM PDT 24 450684635 ps
T3733 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3101911017 Aug 08 05:38:19 PM PDT 24 Aug 08 05:38:20 PM PDT 24 71123970 ps
T3734 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.653500522 Aug 08 05:39:09 PM PDT 24 Aug 08 05:39:10 PM PDT 24 47633047 ps
T3735 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1208506120 Aug 08 05:39:23 PM PDT 24 Aug 08 05:39:24 PM PDT 24 37057749 ps
T3736 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2136332042 Aug 08 05:38:38 PM PDT 24 Aug 08 05:38:40 PM PDT 24 90806263 ps
T3737 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2886222767 Aug 08 05:39:21 PM PDT 24 Aug 08 05:39:22 PM PDT 24 46823450 ps
T3738 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3184900125 Aug 08 05:39:12 PM PDT 24 Aug 08 05:39:13 PM PDT 24 38668491 ps
T3739 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.115045134 Aug 08 05:38:40 PM PDT 24 Aug 08 05:38:42 PM PDT 24 90202166 ps
T3740 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2866919173 Aug 08 05:38:26 PM PDT 24 Aug 08 05:38:28 PM PDT 24 194020760 ps

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.3146988289
Short name T31
Test name
Test status
Simulation time 616646621 ps
CPU time 1.62 seconds
Started Aug 08 06:22:19 PM PDT 24
Finished Aug 08 06:22:21 PM PDT 24
Peak memory 207584 kb
Host smart-67b19400-f18a-4ece-9da0-891a5a165ab5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146988289 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.3146988289
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2943666077
Short name T70
Test name
Test status
Simulation time 7431224382 ps
CPU time 182.87 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 218608 kb
Host smart-cdae40a3-8840-4d4c-8b43-6c0866419a73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2943666077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2943666077
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2454925395
Short name T7
Test name
Test status
Simulation time 29627871185 ps
CPU time 36.45 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207816 kb
Host smart-b89d8a76-03db-4817-8732-f697bd811178
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454925395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.2454925395
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.577850080
Short name T342
Test name
Test status
Simulation time 45037164 ps
CPU time 0.75 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 207024 kb
Host smart-4f9bffbf-51c0-4e77-940e-a290ec40bdff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=577850080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.577850080
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.2589002192
Short name T39
Test name
Test status
Simulation time 498924093 ps
CPU time 1.4 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207508 kb
Host smart-05307332-ee71-4e25-8164-3d8743215778
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2589002192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.2589002192
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1166311356
Short name T268
Test name
Test status
Simulation time 17947049897 ps
CPU time 44.66 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 216064 kb
Host smart-a8ccaa27-f99b-4142-ba83-a9bb0c4b7aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
11356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1166311356
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.734646481
Short name T216
Test name
Test status
Simulation time 214801990 ps
CPU time 1.85 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:20 PM PDT 24
Peak memory 215460 kb
Host smart-2b703856-722d-4c0d-8d30-39c2d42d2bed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734646481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.734646481
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3683873863
Short name T104
Test name
Test status
Simulation time 9176739800 ps
CPU time 11.21 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 216016 kb
Host smart-5d38e190-6700-4de8-a6de-3cdc910be999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
73863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3683873863
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1733759655
Short name T246
Test name
Test status
Simulation time 2412266321 ps
CPU time 66.35 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:15:34 PM PDT 24
Peak memory 224388 kb
Host smart-ad0f8d28-c8a8-4554-a808-fd6fa09a701e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1733759655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1733759655
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2829735867
Short name T115
Test name
Test status
Simulation time 52265746042 ps
CPU time 97.28 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207824 kb
Host smart-2531e902-b915-4935-8bc9-953f062b5c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
35867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2829735867
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.735150320
Short name T119
Test name
Test status
Simulation time 847653109 ps
CPU time 5.26 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207680 kb
Host smart-234f5cb2-984d-4627-ad62-fd364d951cb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735150320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.735150320
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2227082238
Short name T197
Test name
Test status
Simulation time 306945828 ps
CPU time 1.09 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:13:12 PM PDT 24
Peak memory 207480 kb
Host smart-6d2c3c7e-6e2b-4ea7-af6b-85b046c03f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
82238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2227082238
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2820837507
Short name T27
Test name
Test status
Simulation time 44736030 ps
CPU time 0.67 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 207480 kb
Host smart-98e97ec4-1ba9-431d-a2a7-169ef9c7c685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
37507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2820837507
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.2407402400
Short name T199
Test name
Test status
Simulation time 525073821 ps
CPU time 1.55 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207572 kb
Host smart-4f918eb9-2777-4360-b835-d84ac7347400
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407402400 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.2407402400
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.915250379
Short name T225
Test name
Test status
Simulation time 53181295 ps
CPU time 0.74 seconds
Started Aug 08 05:39:23 PM PDT 24
Finished Aug 08 05:39:23 PM PDT 24
Peak memory 207008 kb
Host smart-9cdb9d9a-3d76-45f7-8541-65dfdc264cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=915250379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.915250379
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2579035600
Short name T281
Test name
Test status
Simulation time 2047637567 ps
CPU time 6.02 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:17 PM PDT 24
Peak memory 207280 kb
Host smart-53ca702d-23b8-4d67-8569-80cff94044e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2579035600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2579035600
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.573222999
Short name T67
Test name
Test status
Simulation time 216353051 ps
CPU time 0.91 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207556 kb
Host smart-99e5854e-6d96-4aa1-bfb3-72f8222c9dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57322
2999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.573222999
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.4240242866
Short name T12
Test name
Test status
Simulation time 19430376629 ps
CPU time 23.46 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207768 kb
Host smart-44d93e6b-a74a-4673-b994-c4b26988f93b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240242866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.4240242866
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1959796920
Short name T874
Test name
Test status
Simulation time 3823198182 ps
CPU time 6.2 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 216000 kb
Host smart-bade3961-3fa7-4073-91c4-9810bde63c29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959796920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.1959796920
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2986589518
Short name T229
Test name
Test status
Simulation time 1009469097 ps
CPU time 2.05 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 224556 kb
Host smart-a7bbe408-843d-481f-b9d2-123a88970b15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2986589518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2986589518
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.885959594
Short name T995
Test name
Test status
Simulation time 59132682 ps
CPU time 0.71 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207600 kb
Host smart-7425ad51-ca55-44e6-b016-c0eb07aefd7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=885959594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.885959594
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.4232924615
Short name T1764
Test name
Test status
Simulation time 628089025 ps
CPU time 1.72 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207592 kb
Host smart-61779348-c28d-4963-835d-cc564bae3fab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232924615 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.4232924615
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.3713868577
Short name T249
Test name
Test status
Simulation time 541902572 ps
CPU time 1.71 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:04 PM PDT 24
Peak memory 207636 kb
Host smart-f8a247b7-c175-4d18-ab07-512c54423470
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713868577 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.3713868577
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3035047366
Short name T604
Test name
Test status
Simulation time 881977723 ps
CPU time 2.34 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207728 kb
Host smart-ff41c03c-d540-4fad-84a1-90c250c95d7a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3035047366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3035047366
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2590567249
Short name T76
Test name
Test status
Simulation time 156136913 ps
CPU time 0.87 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207524 kb
Host smart-9229ceba-d404-4318-b941-e9e9ba5d68c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905
67249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2590567249
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3318505732
Short name T299
Test name
Test status
Simulation time 1853666504 ps
CPU time 8.61 seconds
Started Aug 08 05:38:29 PM PDT 24
Finished Aug 08 05:38:38 PM PDT 24
Peak memory 207368 kb
Host smart-f87e4d6f-7c03-49c2-b820-17846b34548d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3318505732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3318505732
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.3122931022
Short name T52
Test name
Test status
Simulation time 256717760 ps
CPU time 1.1 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207572 kb
Host smart-2573fdab-cda9-445a-acb1-80ebbb5fcec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31229
31022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.3122931022
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2190858722
Short name T80
Test name
Test status
Simulation time 3934312724 ps
CPU time 103.82 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:15:11 PM PDT 24
Peak memory 218668 kb
Host smart-bd607d66-15bd-491e-a899-db9ce4f3be83
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190858722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2190858722
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.2562870625
Short name T2585
Test name
Test status
Simulation time 665761298 ps
CPU time 1.67 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207512 kb
Host smart-f389da6c-3635-404f-8436-d1ab2ab57998
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2562870625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.2562870625
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.2710124753
Short name T380
Test name
Test status
Simulation time 711009146 ps
CPU time 1.59 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207540 kb
Host smart-42439a11-2be4-44cd-917f-5950136f06ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2710124753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.2710124753
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2397472359
Short name T257
Test name
Test status
Simulation time 107311859 ps
CPU time 2.58 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:22 PM PDT 24
Peak memory 215612 kb
Host smart-e02ceb2b-cce5-496a-bf9e-dd25024b5f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397472359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2397472359
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.1682331599
Short name T366
Test name
Test status
Simulation time 983005294 ps
CPU time 2 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:17:37 PM PDT 24
Peak memory 207476 kb
Host smart-d78277be-8e07-45b2-abf7-68635503514a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1682331599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.1682331599
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_device_address.125949736
Short name T405
Test name
Test status
Simulation time 28534460940 ps
CPU time 50.91 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:20:43 PM PDT 24
Peak memory 207900 kb
Host smart-36933270-c888-43c2-8859-b87f48e35805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
9736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.125949736
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2102138299
Short name T116
Test name
Test status
Simulation time 36105071700 ps
CPU time 54.26 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207792 kb
Host smart-c9a3e3ac-57a8-4b4b-8e51-4f46a3e1cb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21021
38299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2102138299
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2420624713
Short name T346
Test name
Test status
Simulation time 52220065 ps
CPU time 0.73 seconds
Started Aug 08 05:39:22 PM PDT 24
Finished Aug 08 05:39:23 PM PDT 24
Peak memory 206928 kb
Host smart-9069a176-73a9-4e0e-ac09-6142db65e1e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2420624713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2420624713
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.2233734540
Short name T386
Test name
Test status
Simulation time 776434832 ps
CPU time 1.8 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207488 kb
Host smart-e37c3e07-7394-461c-bf09-9d2530d16e07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2233734540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.2233734540
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.2180704101
Short name T219
Test name
Test status
Simulation time 539662595 ps
CPU time 1.67 seconds
Started Aug 08 06:21:05 PM PDT 24
Finished Aug 08 06:21:06 PM PDT 24
Peak memory 207520 kb
Host smart-f03f38a8-59c2-4916-b1ca-62ad697bd032
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180704101 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.2180704101
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1231773724
Short name T1012
Test name
Test status
Simulation time 156391580 ps
CPU time 0.85 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207488 kb
Host smart-bf573644-509b-4f0d-aa26-943f383e8327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12317
73724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1231773724
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.743962082
Short name T160
Test name
Test status
Simulation time 529797334 ps
CPU time 1.53 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207548 kb
Host smart-7ef17af3-f3d6-41c3-92fd-e51d9f41457a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743962082 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.743962082
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.322216437
Short name T3208
Test name
Test status
Simulation time 724717345 ps
CPU time 1.77 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207532 kb
Host smart-c4ffca22-6740-4a81-8367-b1ed77f13cc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=322216437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.322216437
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.766788390
Short name T411
Test name
Test status
Simulation time 783924355 ps
CPU time 1.85 seconds
Started Aug 08 06:21:37 PM PDT 24
Finished Aug 08 06:21:39 PM PDT 24
Peak memory 207564 kb
Host smart-3c6f40a2-b4ba-40df-98ab-64656bf29aaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=766788390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.766788390
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.3406733696
Short name T481
Test name
Test status
Simulation time 841401720 ps
CPU time 2.03 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207508 kb
Host smart-b9fd36e3-f655-424f-979c-6cebd72156a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3406733696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.3406733696
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3694404530
Short name T11
Test name
Test status
Simulation time 14191034464 ps
CPU time 16.21 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 216008 kb
Host smart-64c49ae4-6962-4e29-ab9a-75dfc456cb77
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694404530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3694404530
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.2710947986
Short name T247
Test name
Test status
Simulation time 698962880 ps
CPU time 1.7 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207520 kb
Host smart-149aeec6-854c-4cfd-919b-21b91feba2f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2710947986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.2710947986
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.1892859656
Short name T415
Test name
Test status
Simulation time 532745696 ps
CPU time 1.47 seconds
Started Aug 08 06:21:56 PM PDT 24
Finished Aug 08 06:21:57 PM PDT 24
Peak memory 207592 kb
Host smart-f57f2bc3-b1c4-414c-b15c-744910777681
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1892859656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1892859656
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.2213717185
Short name T388
Test name
Test status
Simulation time 647086229 ps
CPU time 1.58 seconds
Started Aug 08 06:13:36 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 207480 kb
Host smart-a3c31944-45da-475e-8cf3-067252a12903
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2213717185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.2213717185
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.187442541
Short name T446
Test name
Test status
Simulation time 673662864 ps
CPU time 1.81 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207508 kb
Host smart-800e570f-ab2b-47c1-9f9a-740e28d5ffdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=187442541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.187442541
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.1651397235
Short name T436
Test name
Test status
Simulation time 360857328 ps
CPU time 1.21 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207468 kb
Host smart-6e012b16-c215-492d-b92d-6e47380365fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1651397235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.1651397235
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.2538125201
Short name T422
Test name
Test status
Simulation time 724217856 ps
CPU time 1.69 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:02 PM PDT 24
Peak memory 207500 kb
Host smart-1cec024e-6fa3-4a5a-b4d1-46315fcc8b13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2538125201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.2538125201
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.103989895
Short name T745
Test name
Test status
Simulation time 4546291979 ps
CPU time 42.3 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 216184 kb
Host smart-a680da00-ba5b-4f61-afa0-5307858e8a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
9895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.103989895
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.611547567
Short name T59
Test name
Test status
Simulation time 394470779 ps
CPU time 1.44 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207524 kb
Host smart-deaab806-d6bb-42d6-90e0-f21ad976afae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61154
7567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.611547567
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.94657854
Short name T3281
Test name
Test status
Simulation time 460164253 ps
CPU time 1.31 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207552 kb
Host smart-63144412-98e1-4bd1-bdbc-868b5c4abeac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=94657854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.94657854
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.4212916156
Short name T402
Test name
Test status
Simulation time 654539181 ps
CPU time 1.65 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207512 kb
Host smart-2d2a17b0-4b9a-4b52-a493-8064089b3265
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4212916156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.4212916156
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.3247779730
Short name T398
Test name
Test status
Simulation time 656116577 ps
CPU time 1.45 seconds
Started Aug 08 06:19:41 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207564 kb
Host smart-283e096c-fab3-49c3-aa84-2992f283c426
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3247779730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.3247779730
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3001855079
Short name T129
Test name
Test status
Simulation time 223600385 ps
CPU time 0.89 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207512 kb
Host smart-7f309122-3b47-46a6-9f10-69dd259f5ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30018
55079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3001855079
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.184170870
Short name T94
Test name
Test status
Simulation time 655695894 ps
CPU time 1.73 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207564 kb
Host smart-fd2772c3-8736-45b7-8df3-c3b5eb7fd497
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184170870 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.184170870
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2911812753
Short name T95
Test name
Test status
Simulation time 191049676 ps
CPU time 0.87 seconds
Started Aug 08 06:17:08 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207556 kb
Host smart-2220f095-a67a-4ba4-9a96-df9787b951b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118
12753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2911812753
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.709403174
Short name T282
Test name
Test status
Simulation time 1369939590 ps
CPU time 5.46 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:17 PM PDT 24
Peak memory 207188 kb
Host smart-6a1c8d88-ed91-4160-a41b-2de95bc08bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=709403174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.709403174
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.3546867149
Short name T456
Test name
Test status
Simulation time 764625539 ps
CPU time 1.94 seconds
Started Aug 08 06:21:35 PM PDT 24
Finished Aug 08 06:21:37 PM PDT 24
Peak memory 207500 kb
Host smart-c08aca92-a5c6-479e-bb3b-59ae4ef6fefa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3546867149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.3546867149
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.2910437225
Short name T338
Test name
Test status
Simulation time 572569426 ps
CPU time 1.58 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207448 kb
Host smart-de32ea26-74ed-49b9-a480-c44c0107eff6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2910437225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.2910437225
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3669475449
Short name T511
Test name
Test status
Simulation time 3519945208 ps
CPU time 34.71 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 224288 kb
Host smart-385a163f-f1d5-4404-8bc5-7c4c6f2ab0ca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3669475449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3669475449
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.1253479746
Short name T461
Test name
Test status
Simulation time 844450678 ps
CPU time 1.95 seconds
Started Aug 08 06:21:34 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 207556 kb
Host smart-2fb76cd1-950c-4bd6-9b21-56f13d426fc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1253479746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.1253479746
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.513467431
Short name T353
Test name
Test status
Simulation time 167083802 ps
CPU time 0.95 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207512 kb
Host smart-5dc4bf5e-54d2-4a0c-a150-d8fea17e1d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51346
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.513467431
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.467690170
Short name T3621
Test name
Test status
Simulation time 493014234 ps
CPU time 1.47 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207508 kb
Host smart-6d9ea30d-98d9-485f-a543-593beb232e9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=467690170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.467690170
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2159858807
Short name T312
Test name
Test status
Simulation time 104508349 ps
CPU time 1.06 seconds
Started Aug 08 05:38:26 PM PDT 24
Finished Aug 08 05:38:27 PM PDT 24
Peak memory 207304 kb
Host smart-6714b2fa-f183-4b17-8d10-b76c0f5e1539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2159858807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2159858807
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.184363598
Short name T97
Test name
Test status
Simulation time 146362323 ps
CPU time 0.88 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 207496 kb
Host smart-ed2a68ef-c3a1-4f7a-b4ba-691381b256f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
3598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.184363598
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4105169834
Short name T343
Test name
Test status
Simulation time 40400635 ps
CPU time 0.72 seconds
Started Aug 08 05:39:10 PM PDT 24
Finished Aug 08 05:39:11 PM PDT 24
Peak memory 206884 kb
Host smart-9a1c19d2-1c2d-47c8-893a-74ac7621ead3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4105169834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4105169834
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2076146705
Short name T522
Test name
Test status
Simulation time 5108480508 ps
CPU time 50.09 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207908 kb
Host smart-48aff261-7308-4886-ab77-62771d5f4c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20761
46705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2076146705
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.446997868
Short name T459
Test name
Test status
Simulation time 716838901 ps
CPU time 1.59 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207516 kb
Host smart-a97e4985-963c-40c4-86b9-c8d2fdca4010
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=446997868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.446997868
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.798947255
Short name T449
Test name
Test status
Simulation time 822198679 ps
CPU time 1.76 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207552 kb
Host smart-4da7c571-34b0-409e-8ce7-94d5f7c2e83a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=798947255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.798947255
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.1964891699
Short name T362
Test name
Test status
Simulation time 355656581 ps
CPU time 1.11 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207508 kb
Host smart-bc60f351-2807-4262-bc06-fa47a7821d50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1964891699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.1964891699
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.2689451582
Short name T485
Test name
Test status
Simulation time 415629662 ps
CPU time 1.29 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207540 kb
Host smart-b0ce6c66-fd23-4372-94ba-389319f85382
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2689451582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.2689451582
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.1369645349
Short name T2123
Test name
Test status
Simulation time 594324591 ps
CPU time 1.57 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207536 kb
Host smart-524a315f-8ff8-4388-a3df-986d7bb0627a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1369645349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.1369645349
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.900811141
Short name T462
Test name
Test status
Simulation time 318215148 ps
CPU time 1.1 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207560 kb
Host smart-eb2056db-7ee3-430d-9610-1b0fcb9cecf7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=900811141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.900811141
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3526747144
Short name T170
Test name
Test status
Simulation time 6237462617 ps
CPU time 34.46 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:46 PM PDT 24
Peak memory 219232 kb
Host smart-be3496ba-9ecf-4ced-85fc-c075d3b02e71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3526747144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3526747144
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.522711910
Short name T267
Test name
Test status
Simulation time 243812363 ps
CPU time 3.13 seconds
Started Aug 08 05:39:10 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 220016 kb
Host smart-b5d42628-f500-4507-a82a-cd3e15190a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=522711910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.522711910
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2347311233
Short name T161
Test name
Test status
Simulation time 5001462830 ps
CPU time 48.51 seconds
Started Aug 08 06:13:31 PM PDT 24
Finished Aug 08 06:14:19 PM PDT 24
Peak memory 224236 kb
Host smart-19d52d8d-40d9-4907-9b75-358dd1db35f0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2347311233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2347311233
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.916675890
Short name T329
Test name
Test status
Simulation time 175895976 ps
CPU time 0.88 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:13:12 PM PDT 24
Peak memory 207548 kb
Host smart-f3160d97-2b7b-45b3-bce7-fea5c918a0dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=916675890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.916675890
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3125368960
Short name T1943
Test name
Test status
Simulation time 41430841240 ps
CPU time 65.43 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207864 kb
Host smart-08953c91-b3c7-4b90-a956-f92237ea243f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
68960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3125368960
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_address.1244917942
Short name T994
Test name
Test status
Simulation time 55393635477 ps
CPU time 89.64 seconds
Started Aug 08 06:21:07 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207816 kb
Host smart-696741a7-683e-4973-82d7-d6b0ce042b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12449
17942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.1244917942
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.468426969
Short name T352
Test name
Test status
Simulation time 892508395 ps
CPU time 4.67 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:03 PM PDT 24
Peak memory 207260 kb
Host smart-e817bbcf-1fd3-47b9-87bf-94475be5af72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=468426969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.468426969
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.551232169
Short name T284
Test name
Test status
Simulation time 499231404 ps
CPU time 3.8 seconds
Started Aug 08 05:38:54 PM PDT 24
Finished Aug 08 05:38:58 PM PDT 24
Peak memory 207328 kb
Host smart-fd16b9bc-fa10-4cc0-af2a-d079ec3e71bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=551232169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.551232169
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2947447771
Short name T525
Test name
Test status
Simulation time 119108450284 ps
CPU time 200.6 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207792 kb
Host smart-75ca4f56-63fa-4dc2-ae39-6cd04ee63b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
47771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2947447771
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2702812286
Short name T323
Test name
Test status
Simulation time 257490857 ps
CPU time 1.12 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 207588 kb
Host smart-dec95908-11b0-44ed-9f13-af6c28b816ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27028
12286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2702812286
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.2106376286
Short name T443
Test name
Test status
Simulation time 218919151 ps
CPU time 1.01 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207436 kb
Host smart-60ce6d74-5aab-49e0-afc2-17a9736d3bb3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2106376286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.2106376286
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.257973998
Short name T518
Test name
Test status
Simulation time 109097363920 ps
CPU time 196.9 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:16:47 PM PDT 24
Peak memory 207828 kb
Host smart-3d6a5c3b-bf9e-453f-beb8-37e0c6c0a214
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=257973998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.257973998
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1582212931
Short name T3269
Test name
Test status
Simulation time 4305489162 ps
CPU time 126.15 seconds
Started Aug 08 06:15:36 PM PDT 24
Finished Aug 08 06:17:42 PM PDT 24
Peak memory 217480 kb
Host smart-29de1c24-db04-440a-88d9-ca78577b9b17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1582212931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1582212931
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.2321647230
Short name T339
Test name
Test status
Simulation time 697881959 ps
CPU time 1.63 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 207528 kb
Host smart-4f233983-c192-496a-acea-ab9cb29c5c1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2321647230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.2321647230
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.1944790829
Short name T326
Test name
Test status
Simulation time 314470782 ps
CPU time 1.22 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207536 kb
Host smart-a0510b6d-5abb-4773-b40c-52bd8f1c0136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
90829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1944790829
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.3597595248
Short name T425
Test name
Test status
Simulation time 619793208 ps
CPU time 1.61 seconds
Started Aug 08 06:21:20 PM PDT 24
Finished Aug 08 06:21:22 PM PDT 24
Peak memory 207564 kb
Host smart-7d959369-53df-4c5c-bf33-4da3ce0b2e11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3597595248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.3597595248
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.416426908
Short name T2089
Test name
Test status
Simulation time 610091333 ps
CPU time 1.52 seconds
Started Aug 08 06:21:22 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207564 kb
Host smart-a0ed7ac8-62f9-420a-82e5-b0ccc2b37e59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=416426908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.416426908
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.1837380822
Short name T372
Test name
Test status
Simulation time 1140528264 ps
CPU time 2.52 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207484 kb
Host smart-bbf99874-8d80-4915-b885-726217193046
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1837380822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.1837380822
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.3063316675
Short name T435
Test name
Test status
Simulation time 363807923 ps
CPU time 1.24 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207552 kb
Host smart-7b962ce4-d9e5-416a-8206-14de1f133941
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3063316675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.3063316675
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.466646963
Short name T430
Test name
Test status
Simulation time 439809647 ps
CPU time 1.33 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207564 kb
Host smart-d68874b8-35d1-4f41-85d3-a8e1bd114d66
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=466646963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.466646963
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.1936320695
Short name T379
Test name
Test status
Simulation time 721606873 ps
CPU time 1.88 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 207500 kb
Host smart-240e1b9b-ff7d-4ca3-8ef8-02fa990439d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1936320695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.1936320695
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.3283863633
Short name T440
Test name
Test status
Simulation time 281761510 ps
CPU time 1.08 seconds
Started Aug 08 06:16:13 PM PDT 24
Finished Aug 08 06:16:14 PM PDT 24
Peak memory 207748 kb
Host smart-da7522ba-ce42-44f0-b6fa-647e7e6f8452
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3283863633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3283863633
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.2092408050
Short name T383
Test name
Test status
Simulation time 511444266 ps
CPU time 1.56 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207480 kb
Host smart-8f231457-1e04-4ab9-918c-cc9930d1f03b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2092408050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.2092408050
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.1103444715
Short name T483
Test name
Test status
Simulation time 285620902 ps
CPU time 1.15 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207552 kb
Host smart-b18cc0d8-2cd9-4c4c-aa53-e988cd5b5f99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1103444715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.1103444715
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.511518316
Short name T410
Test name
Test status
Simulation time 596112230 ps
CPU time 1.61 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207504 kb
Host smart-18dce6a7-fb29-4bc2-a998-7c2afa56492e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=511518316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.511518316
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2015792856
Short name T1001
Test name
Test status
Simulation time 182608605 ps
CPU time 0.91 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207552 kb
Host smart-7948a8dd-c957-4360-9856-30a6ee7b7a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20157
92856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2015792856
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3639882875
Short name T1804
Test name
Test status
Simulation time 21229208115 ps
CPU time 24 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:27 PM PDT 24
Peak memory 207876 kb
Host smart-37e1acaa-b828-4ed2-93fd-8c9223910c92
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639882875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3639882875
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.542493605
Short name T250
Test name
Test status
Simulation time 577489074 ps
CPU time 1.6 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207516 kb
Host smart-c8cf39d4-9db9-419f-81eb-532d9274ea96
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542493605 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.542493605
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2720423115
Short name T66
Test name
Test status
Simulation time 153391652 ps
CPU time 0.87 seconds
Started Aug 08 06:13:16 PM PDT 24
Finished Aug 08 06:13:17 PM PDT 24
Peak memory 207548 kb
Host smart-a74df02c-e317-46c3-a7fd-c76c4e1c9521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27204
23115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2720423115
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1129076186
Short name T88
Test name
Test status
Simulation time 7795598571 ps
CPU time 45.39 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 220020 kb
Host smart-20c255cb-b7ba-4959-bab7-151d2c9bb584
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129076186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1129076186
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.2256172698
Short name T118
Test name
Test status
Simulation time 645618013 ps
CPU time 1.8 seconds
Started Aug 08 06:22:34 PM PDT 24
Finished Aug 08 06:22:36 PM PDT 24
Peak memory 207580 kb
Host smart-dc506e35-c3af-4ba0-bb0d-676ff8a761bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256172698 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.2256172698
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3266522492
Short name T44
Test name
Test status
Simulation time 55982628 ps
CPU time 0.77 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 207500 kb
Host smart-a471a37b-c23e-4a04-8a38-78dfd7246825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32665
22492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3266522492
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1879825191
Short name T49
Test name
Test status
Simulation time 151356356 ps
CPU time 0.92 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 207560 kb
Host smart-e6a06400-0c48-4720-be37-f9d3e8dd0434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
25191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1879825191
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1227880923
Short name T71
Test name
Test status
Simulation time 4155881171 ps
CPU time 9.96 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:13:17 PM PDT 24
Peak memory 207812 kb
Host smart-34ab2568-4f58-48cb-bc3b-8d771194df28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12278
80923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1227880923
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2331859452
Short name T75
Test name
Test status
Simulation time 545148231 ps
CPU time 1.62 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207580 kb
Host smart-e56ba346-0875-467f-ae67-4da11d017539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
59452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2331859452
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1752869632
Short name T72
Test name
Test status
Simulation time 171860025 ps
CPU time 0.9 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 206328 kb
Host smart-b52d6a13-ea29-4d6b-b5bc-034ce873e83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
69632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1752869632
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3079455423
Short name T83
Test name
Test status
Simulation time 163635457 ps
CPU time 0.9 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207540 kb
Host smart-55a6056f-aa58-430e-a943-c890138e5eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30794
55423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3079455423
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1697080921
Short name T60
Test name
Test status
Simulation time 176489440 ps
CPU time 0.98 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207576 kb
Host smart-69770488-e3f1-4917-a766-d287dd0a373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16970
80921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1697080921
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.740494796
Short name T2368
Test name
Test status
Simulation time 3692317672 ps
CPU time 27.99 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:57 PM PDT 24
Peak memory 217980 kb
Host smart-12ccd7de-4d3f-4334-b04c-2ee455cb5e9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=740494796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.740494796
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1434022615
Short name T3671
Test name
Test status
Simulation time 249712014 ps
CPU time 2.8 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 207216 kb
Host smart-e8d7dc74-b7f4-4a76-a2c3-2195a631910e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434022615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1434022615
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1556952477
Short name T1005
Test name
Test status
Simulation time 377456714 ps
CPU time 2.6 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 207676 kb
Host smart-572f22e8-87b3-4ba8-bf7b-cee30e2c6cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
52477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1556952477
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.961790338
Short name T291
Test name
Test status
Simulation time 17955940706 ps
CPU time 47.61 seconds
Started Aug 08 06:13:09 PM PDT 24
Finished Aug 08 06:13:57 PM PDT 24
Peak memory 216156 kb
Host smart-48c81024-62ac-48bc-bf72-5eb84d8aa99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96179
0338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.961790338
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1719552318
Short name T154
Test name
Test status
Simulation time 209021917 ps
CPU time 0.91 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207568 kb
Host smart-4556f8ea-886d-4ab5-abe6-cf57434379af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195
52318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1719552318
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2934087131
Short name T1911
Test name
Test status
Simulation time 216469897 ps
CPU time 1 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207528 kb
Host smart-bd967408-f639-4db3-922d-14cb5cbf00de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
87131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2934087131
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1823141929
Short name T146
Test name
Test status
Simulation time 206035347 ps
CPU time 0.94 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-c080a45e-32bf-4cad-8dfd-82eda2f82f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18231
41929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1823141929
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3210283719
Short name T132
Test name
Test status
Simulation time 239155411 ps
CPU time 0.97 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207532 kb
Host smart-867f6f5c-c709-4d57-bd17-0cfe2456993f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32102
83719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3210283719
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3286007296
Short name T152
Test name
Test status
Simulation time 204634329 ps
CPU time 0.94 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207504 kb
Host smart-73d4e990-777a-48cd-acfa-2ceb42f59b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32860
07296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3286007296
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3661040863
Short name T134
Test name
Test status
Simulation time 247571176 ps
CPU time 1.01 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207544 kb
Host smart-918b4e38-15bd-427b-bd47-469898a4b702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36610
40863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3661040863
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.670724632
Short name T136
Test name
Test status
Simulation time 168999678 ps
CPU time 0.9 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:20 PM PDT 24
Peak memory 207536 kb
Host smart-187b8042-6c0d-455a-9b7e-335f984a18c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67072
4632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.670724632
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1433079465
Short name T150
Test name
Test status
Simulation time 212465368 ps
CPU time 0.98 seconds
Started Aug 08 06:18:11 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 207600 kb
Host smart-1e261f4f-0a65-40f9-889a-07bc837d440b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
79465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1433079465
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.211325566
Short name T143
Test name
Test status
Simulation time 223735413 ps
CPU time 0.97 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207500 kb
Host smart-ebf3dbf3-ca5f-4251-b38b-8f0c6390f9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.211325566
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1211225202
Short name T139
Test name
Test status
Simulation time 205821588 ps
CPU time 0.96 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207488 kb
Host smart-6f592554-d726-413d-9298-05d8b5204243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12112
25202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1211225202
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3680059268
Short name T158
Test name
Test status
Simulation time 191331307 ps
CPU time 0.93 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207620 kb
Host smart-4c181e5d-daa6-47f0-bb46-09c6667c9525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
59268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3680059268
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3222515480
Short name T308
Test name
Test status
Simulation time 397601612 ps
CPU time 3.64 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:21 PM PDT 24
Peak memory 207268 kb
Host smart-0313e711-1ff5-48fe-9fba-f7353ac25c6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3222515480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3222515480
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3710498249
Short name T3634
Test name
Test status
Simulation time 1015834518 ps
CPU time 9.49 seconds
Started Aug 08 05:38:26 PM PDT 24
Finished Aug 08 05:38:35 PM PDT 24
Peak memory 207308 kb
Host smart-730dfbf8-2b49-4c34-bacc-1e794efeb10c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3710498249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3710498249
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3758143622
Short name T3670
Test name
Test status
Simulation time 111766904 ps
CPU time 0.98 seconds
Started Aug 08 05:38:09 PM PDT 24
Finished Aug 08 05:38:10 PM PDT 24
Peak memory 207176 kb
Host smart-f4104033-334f-4b43-94b5-530b8a619713
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3758143622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3758143622
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1894086238
Short name T303
Test name
Test status
Simulation time 78810579 ps
CPU time 0.99 seconds
Started Aug 08 05:38:10 PM PDT 24
Finished Aug 08 05:38:11 PM PDT 24
Peak memory 207048 kb
Host smart-630081ea-f276-4ac6-b1ad-4d8994e58530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1894086238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1894086238
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3970827039
Short name T3730
Test name
Test status
Simulation time 50982975 ps
CPU time 0.77 seconds
Started Aug 08 05:38:11 PM PDT 24
Finished Aug 08 05:38:12 PM PDT 24
Peak memory 206880 kb
Host smart-b9ad5cd2-fa6a-46c9-a76c-04bada09992b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3970827039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3970827039
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1828967205
Short name T3695
Test name
Test status
Simulation time 152615945 ps
CPU time 1.52 seconds
Started Aug 08 05:38:11 PM PDT 24
Finished Aug 08 05:38:13 PM PDT 24
Peak memory 207216 kb
Host smart-26f7e805-9e97-4055-9dbe-efa8d541ecd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1828967205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1828967205
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1699614923
Short name T3699
Test name
Test status
Simulation time 137325220 ps
CPU time 2.4 seconds
Started Aug 08 05:38:10 PM PDT 24
Finished Aug 08 05:38:12 PM PDT 24
Peak memory 207208 kb
Host smart-77e27dba-69d4-4dbe-b6c9-1fb3f5ff8d0d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1699614923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1699614923
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3963277033
Short name T3692
Test name
Test status
Simulation time 243520338 ps
CPU time 2.42 seconds
Started Aug 08 05:38:10 PM PDT 24
Finished Aug 08 05:38:13 PM PDT 24
Peak memory 207216 kb
Host smart-9b7a013d-6a15-4b3b-a75b-4c4d37e10860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3963277033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3963277033
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2532961340
Short name T215
Test name
Test status
Simulation time 493253152 ps
CPU time 3.07 seconds
Started Aug 08 05:38:10 PM PDT 24
Finished Aug 08 05:38:14 PM PDT 24
Peak memory 207232 kb
Host smart-2f990d08-d128-4b35-b8b3-4f2b52beded4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2532961340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2532961340
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3176733561
Short name T3635
Test name
Test status
Simulation time 118361133 ps
CPU time 3.22 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:22 PM PDT 24
Peak memory 207316 kb
Host smart-25bfc02f-2fbd-4063-ae5d-2629d05db900
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3176733561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3176733561
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2731145077
Short name T3686
Test name
Test status
Simulation time 845591965 ps
CPU time 4.93 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:24 PM PDT 24
Peak memory 207292 kb
Host smart-76520181-a9df-4d9b-ae32-eded69516722
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2731145077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2731145077
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.989914420
Short name T3723
Test name
Test status
Simulation time 64600188 ps
CPU time 0.79 seconds
Started Aug 08 05:38:28 PM PDT 24
Finished Aug 08 05:38:29 PM PDT 24
Peak memory 207052 kb
Host smart-54f90cd8-ef7c-4f87-acc0-e352b8e70a34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=989914420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.989914420
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2210236930
Short name T265
Test name
Test status
Simulation time 174993333 ps
CPU time 1.96 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:20 PM PDT 24
Peak memory 215560 kb
Host smart-8c2dc61a-ca72-42e5-820e-3031ee7165a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210236930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2210236930
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3517287003
Short name T3711
Test name
Test status
Simulation time 103284886 ps
CPU time 1.03 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:20 PM PDT 24
Peak memory 207084 kb
Host smart-39620417-bf46-4ddf-b976-ca78e538d91b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3517287003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3517287003
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3101911017
Short name T3733
Test name
Test status
Simulation time 71123970 ps
CPU time 0.71 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:20 PM PDT 24
Peak memory 206964 kb
Host smart-7b66c59c-7c05-45f2-9867-fd8d72bf0937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3101911017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3101911017
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2897205015
Short name T310
Test name
Test status
Simulation time 158091079 ps
CPU time 1.48 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:20 PM PDT 24
Peak memory 207188 kb
Host smart-8f026e44-8bdf-4388-bb51-c1343ad2baa4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2897205015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2897205015
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.164379203
Short name T3704
Test name
Test status
Simulation time 93098037 ps
CPU time 2.43 seconds
Started Aug 08 05:38:25 PM PDT 24
Finished Aug 08 05:38:27 PM PDT 24
Peak memory 207244 kb
Host smart-2be351ef-8783-4e95-b5b7-3752cb1bf65c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=164379203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.164379203
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2866919173
Short name T3740
Test name
Test status
Simulation time 194020760 ps
CPU time 1.59 seconds
Started Aug 08 05:38:26 PM PDT 24
Finished Aug 08 05:38:28 PM PDT 24
Peak memory 207256 kb
Host smart-26344b2e-b216-4601-8370-0f67bba19e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2866919173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2866919173
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3926711299
Short name T498
Test name
Test status
Simulation time 2158339951 ps
CPU time 6.24 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:25 PM PDT 24
Peak memory 207492 kb
Host smart-76feab23-8ede-4516-a398-ff1923fc5c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3926711299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3926711299
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1305651964
Short name T3675
Test name
Test status
Simulation time 137898195 ps
CPU time 1.67 seconds
Started Aug 08 05:39:03 PM PDT 24
Finished Aug 08 05:39:05 PM PDT 24
Peak memory 215612 kb
Host smart-4373f6c3-3703-4497-bd57-ebea7e7da2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305651964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1305651964
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.533317916
Short name T261
Test name
Test status
Simulation time 52063235 ps
CPU time 0.99 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207072 kb
Host smart-2372bbc2-a728-4d86-9e78-26667f2b6511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=533317916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.533317916
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1727742427
Short name T3681
Test name
Test status
Simulation time 40674639 ps
CPU time 0.78 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 206984 kb
Host smart-b8f49f79-f47f-4b78-a4da-4cd5d85ad13d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1727742427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1727742427
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1954767950
Short name T315
Test name
Test status
Simulation time 218201100 ps
CPU time 1.79 seconds
Started Aug 08 05:38:57 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207300 kb
Host smart-1c646c2e-63e1-4bd6-9ce5-31fcfa6c0fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1954767950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1954767950
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2483421005
Short name T279
Test name
Test status
Simulation time 107949814 ps
CPU time 2.58 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:01 PM PDT 24
Peak memory 220844 kb
Host smart-ec28abab-a196-4bc5-ba96-04e5805aefd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483421005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2483421005
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2217127066
Short name T3713
Test name
Test status
Simulation time 528814688 ps
CPU time 4.44 seconds
Started Aug 08 05:39:02 PM PDT 24
Finished Aug 08 05:39:07 PM PDT 24
Peak memory 207352 kb
Host smart-1ee33dcc-e9dd-4f12-96e3-9fec5b2b19cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2217127066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2217127066
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2564422774
Short name T258
Test name
Test status
Simulation time 76486217 ps
CPU time 1.34 seconds
Started Aug 08 05:38:59 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 215608 kb
Host smart-347f1eb0-8d25-439b-a8c8-2a79936a095a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564422774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2564422774
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4278172377
Short name T3722
Test name
Test status
Simulation time 70193552 ps
CPU time 0.94 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207152 kb
Host smart-c4eddfd5-5021-4476-9cc7-eefcddd6d989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4278172377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4278172377
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1150995778
Short name T227
Test name
Test status
Simulation time 54999352 ps
CPU time 0.72 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 206984 kb
Host smart-f13dd6ed-4365-4c70-aec7-398043548e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150995778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1150995778
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2198304665
Short name T260
Test name
Test status
Simulation time 131879106 ps
CPU time 1.14 seconds
Started Aug 08 05:39:03 PM PDT 24
Finished Aug 08 05:39:04 PM PDT 24
Peak memory 207352 kb
Host smart-0c5b1e08-fc00-48da-94ba-ad5f45a28948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2198304665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2198304665
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1880157411
Short name T3727
Test name
Test status
Simulation time 524328679 ps
CPU time 4.29 seconds
Started Aug 08 05:38:59 PM PDT 24
Finished Aug 08 05:39:04 PM PDT 24
Peak memory 207344 kb
Host smart-239a45f8-1a8f-4893-aab6-d87216a85b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1880157411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1880157411
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3764796683
Short name T3659
Test name
Test status
Simulation time 149450357 ps
CPU time 2.14 seconds
Started Aug 08 05:39:03 PM PDT 24
Finished Aug 08 05:39:05 PM PDT 24
Peak memory 215584 kb
Host smart-414d4aee-78be-40af-876d-8646505b42f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764796683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3764796683
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1436945279
Short name T3678
Test name
Test status
Simulation time 106760690 ps
CPU time 1.14 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207100 kb
Host smart-cd7451fe-fafa-40a9-8ac2-1c6d10083555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1436945279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1436945279
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1807066779
Short name T3715
Test name
Test status
Simulation time 30765987 ps
CPU time 0.71 seconds
Started Aug 08 05:38:59 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 206964 kb
Host smart-dee52ed3-26cf-4ed1-9937-5c65d676f3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1807066779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1807066779
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2436524727
Short name T3725
Test name
Test status
Simulation time 205048389 ps
CPU time 1.42 seconds
Started Aug 08 05:38:59 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 207168 kb
Host smart-b5fa987c-e689-40b9-b273-529f4cfdd749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2436524727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2436524727
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2088950711
Short name T266
Test name
Test status
Simulation time 102042768 ps
CPU time 3.09 seconds
Started Aug 08 05:38:57 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 207300 kb
Host smart-5cb786a5-81d8-4fce-9f8d-37762e1155bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088950711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2088950711
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4017373617
Short name T259
Test name
Test status
Simulation time 980511402 ps
CPU time 5.13 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:03 PM PDT 24
Peak memory 207224 kb
Host smart-2aae8e2f-f411-4b05-8bbe-c39aa972b799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4017373617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4017373617
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3836414812
Short name T3689
Test name
Test status
Simulation time 87781490 ps
CPU time 2.43 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 215672 kb
Host smart-719f32ce-8eec-4e11-86b8-40e08f31dc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836414812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3836414812
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.730756869
Short name T307
Test name
Test status
Simulation time 56751534 ps
CPU time 1.01 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 207068 kb
Host smart-24e49ef1-032b-48d1-ac4f-39c0a6ae29ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=730756869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.730756869
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1124351954
Short name T3655
Test name
Test status
Simulation time 59897235 ps
CPU time 0.71 seconds
Started Aug 08 05:38:57 PM PDT 24
Finished Aug 08 05:38:58 PM PDT 24
Peak memory 206944 kb
Host smart-23703d4b-a5e8-480e-a19a-f77ec84608b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124351954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1124351954
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.358150906
Short name T3639
Test name
Test status
Simulation time 232643003 ps
CPU time 1.13 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207072 kb
Host smart-11151abb-0a50-49ad-af82-fc2c6a856d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=358150906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.358150906
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4271338184
Short name T3679
Test name
Test status
Simulation time 71277897 ps
CPU time 2.25 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 207288 kb
Host smart-11905d35-04e1-4383-ac98-0823bf3986e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4271338184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4271338184
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2553212009
Short name T3709
Test name
Test status
Simulation time 83825422 ps
CPU time 1.25 seconds
Started Aug 08 05:39:10 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 215404 kb
Host smart-d99ac538-a77e-402f-9750-43167d593932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553212009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2553212009
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.653500522
Short name T3734
Test name
Test status
Simulation time 47633047 ps
CPU time 0.77 seconds
Started Aug 08 05:39:09 PM PDT 24
Finished Aug 08 05:39:10 PM PDT 24
Peak memory 207060 kb
Host smart-7f91f13e-e5db-491b-ba64-24baa72afb38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=653500522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.653500522
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3184900125
Short name T3738
Test name
Test status
Simulation time 38668491 ps
CPU time 0.73 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207016 kb
Host smart-703e2787-0c4d-4b02-b78a-5cb3d2bc3d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3184900125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3184900125
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2666573754
Short name T3661
Test name
Test status
Simulation time 159133396 ps
CPU time 1.54 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207296 kb
Host smart-fc7f2160-82ec-414a-9fac-8d6175c3ed57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2666573754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2666573754
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3799381467
Short name T280
Test name
Test status
Simulation time 93009505 ps
CPU time 1.76 seconds
Started Aug 08 05:39:13 PM PDT 24
Finished Aug 08 05:39:15 PM PDT 24
Peak memory 223576 kb
Host smart-bf475feb-e8e0-4e89-b876-3cd0d80b412c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3799381467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3799381467
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2574467155
Short name T3720
Test name
Test status
Simulation time 730299177 ps
CPU time 5.2 seconds
Started Aug 08 05:39:10 PM PDT 24
Finished Aug 08 05:39:16 PM PDT 24
Peak memory 207316 kb
Host smart-742be12e-c98a-4a9b-baba-2df10f2a6a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2574467155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2574467155
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3662377367
Short name T285
Test name
Test status
Simulation time 90733382 ps
CPU time 1.37 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 215464 kb
Host smart-0868fadb-9524-4618-8eae-aab41cd7628c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662377367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3662377367
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3690040509
Short name T302
Test name
Test status
Simulation time 126662015 ps
CPU time 1.05 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 207040 kb
Host smart-7a7b6c57-9c45-46f6-ad67-87c6a5994625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3690040509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3690040509
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1893834834
Short name T3656
Test name
Test status
Simulation time 51966113 ps
CPU time 0.72 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 206892 kb
Host smart-acfd0d27-76b1-4bbe-91af-72b8c9d72d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1893834834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1893834834
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3516696734
Short name T3685
Test name
Test status
Simulation time 161033700 ps
CPU time 1.23 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 207300 kb
Host smart-033f6f4e-c52a-45e7-a5a8-6da7f3108d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3516696734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3516696734
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.738256391
Short name T217
Test name
Test status
Simulation time 481143579 ps
CPU time 2.71 seconds
Started Aug 08 05:39:14 PM PDT 24
Finished Aug 08 05:39:16 PM PDT 24
Peak memory 207260 kb
Host smart-91d0b7cd-8b61-4c61-a7bd-2bfcae7b6027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=738256391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.738256391
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1739916686
Short name T3643
Test name
Test status
Simulation time 117295262 ps
CPU time 1.29 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 223132 kb
Host smart-92cd8ebb-fc9a-438a-a4c9-89956e412219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739916686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1739916686
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3438018178
Short name T3674
Test name
Test status
Simulation time 43600755 ps
CPU time 0.89 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207076 kb
Host smart-fa365e22-6376-40c0-8bfd-ff3f4a7b690e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3438018178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3438018178
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.673813116
Short name T3680
Test name
Test status
Simulation time 52007215 ps
CPU time 0.75 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 207008 kb
Host smart-8c481fae-5ddf-4232-aba2-aa1c6466b723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=673813116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.673813116
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1676030460
Short name T3677
Test name
Test status
Simulation time 289942135 ps
CPU time 1.61 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207380 kb
Host smart-cddb9c93-b811-4188-912a-5e056effb4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1676030460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1676030460
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2812167933
Short name T3688
Test name
Test status
Simulation time 231724434 ps
CPU time 3.04 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:15 PM PDT 24
Peak memory 207340 kb
Host smart-5ff2d812-20f5-4f35-8ba9-f048f4859a44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2812167933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2812167933
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3927895261
Short name T348
Test name
Test status
Simulation time 1184662267 ps
CPU time 5.64 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:18 PM PDT 24
Peak memory 207360 kb
Host smart-ebb74ee3-3a0e-4cbf-a572-9da82fa5985c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3927895261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3927895261
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3407727645
Short name T3703
Test name
Test status
Simulation time 168576155 ps
CPU time 1.82 seconds
Started Aug 08 05:39:13 PM PDT 24
Finished Aug 08 05:39:15 PM PDT 24
Peak memory 215492 kb
Host smart-fb3cd2b4-bc54-4d31-a4c3-6bbf2bde4680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407727645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3407727645
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1785699844
Short name T3668
Test name
Test status
Simulation time 43072200 ps
CPU time 0.81 seconds
Started Aug 08 05:39:12 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 207056 kb
Host smart-5265ef7e-ca1b-40a7-9cf6-655250a9ee7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1785699844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1785699844
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2938459965
Short name T3667
Test name
Test status
Simulation time 55457809 ps
CPU time 0.73 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:12 PM PDT 24
Peak memory 206924 kb
Host smart-d6d5b39c-7b62-40b3-a871-deffeb234ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938459965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2938459965
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.689495784
Short name T3687
Test name
Test status
Simulation time 183449083 ps
CPU time 1.18 seconds
Started Aug 08 05:39:13 PM PDT 24
Finished Aug 08 05:39:14 PM PDT 24
Peak memory 207232 kb
Host smart-2eb8b12a-5455-43a3-9622-9bc93120dadf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=689495784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.689495784
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4266241083
Short name T272
Test name
Test status
Simulation time 296597097 ps
CPU time 3.13 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:15 PM PDT 24
Peak memory 220000 kb
Host smart-2e3e3bb5-700c-4150-9675-63d4bb709c30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4266241083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4266241083
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1250646827
Short name T3672
Test name
Test status
Simulation time 73434080 ps
CPU time 1.68 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:13 PM PDT 24
Peak memory 215476 kb
Host smart-62101fcd-a729-4b80-aef5-6462f00245e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250646827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1250646827
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3957522880
Short name T3724
Test name
Test status
Simulation time 40234036 ps
CPU time 0.76 seconds
Started Aug 08 05:39:10 PM PDT 24
Finished Aug 08 05:39:11 PM PDT 24
Peak memory 206996 kb
Host smart-e81e7fca-f8a5-47cf-8fea-1ae4930cece9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3957522880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3957522880
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.565958109
Short name T313
Test name
Test status
Simulation time 204899662 ps
CPU time 1.78 seconds
Started Aug 08 05:39:15 PM PDT 24
Finished Aug 08 05:39:16 PM PDT 24
Peak memory 207292 kb
Host smart-196a335b-f9a8-4f96-b2a9-856be1ca0b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=565958109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.565958109
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3711626943
Short name T3731
Test name
Test status
Simulation time 185415743 ps
CPU time 2.29 seconds
Started Aug 08 05:39:11 PM PDT 24
Finished Aug 08 05:39:14 PM PDT 24
Peak memory 207400 kb
Host smart-c4a7a356-5fd4-459c-aa11-52d5e6d889b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3711626943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3711626943
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2190760902
Short name T3697
Test name
Test status
Simulation time 77911251 ps
CPU time 1.24 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 215468 kb
Host smart-51eec183-50ac-46aa-8e7a-c1cc6f3a1088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190760902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2190760902
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2219816074
Short name T3662
Test name
Test status
Simulation time 51981164 ps
CPU time 0.8 seconds
Started Aug 08 05:39:20 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 207096 kb
Host smart-fddb610c-325d-4011-890e-d62c17421fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2219816074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2219816074
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3006333501
Short name T344
Test name
Test status
Simulation time 98422780 ps
CPU time 0.79 seconds
Started Aug 08 05:39:20 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 206924 kb
Host smart-d9238c52-c760-4256-8432-e59a9372012c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3006333501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3006333501
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2075143845
Short name T3712
Test name
Test status
Simulation time 53088405 ps
CPU time 1.09 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 207380 kb
Host smart-4eba1983-fdf0-4e89-a1d7-28166c115fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2075143845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2075143845
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3620662437
Short name T3705
Test name
Test status
Simulation time 95027449 ps
CPU time 1.95 seconds
Started Aug 08 05:39:13 PM PDT 24
Finished Aug 08 05:39:15 PM PDT 24
Peak memory 207252 kb
Host smart-f67c3a7f-8dfb-499f-9a58-2da6b42edb46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3620662437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3620662437
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.896292214
Short name T350
Test name
Test status
Simulation time 733774701 ps
CPU time 3.04 seconds
Started Aug 08 05:39:22 PM PDT 24
Finished Aug 08 05:39:25 PM PDT 24
Peak memory 207532 kb
Host smart-5a771c7a-e94c-462c-b17b-d6cf6e4af2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=896292214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.896292214
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4031576480
Short name T3644
Test name
Test status
Simulation time 191692464 ps
CPU time 2.12 seconds
Started Aug 08 05:38:33 PM PDT 24
Finished Aug 08 05:38:35 PM PDT 24
Peak memory 207308 kb
Host smart-ae17e637-911b-4527-8ea0-41316267da4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4031576480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4031576480
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3031542680
Short name T3732
Test name
Test status
Simulation time 450684635 ps
CPU time 4.79 seconds
Started Aug 08 05:38:33 PM PDT 24
Finished Aug 08 05:38:38 PM PDT 24
Peak memory 207376 kb
Host smart-b66c38be-d391-4112-bbee-9e9498410e79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3031542680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3031542680
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1883789944
Short name T3641
Test name
Test status
Simulation time 93501276 ps
CPU time 0.92 seconds
Started Aug 08 05:38:25 PM PDT 24
Finished Aug 08 05:38:26 PM PDT 24
Peak memory 207152 kb
Host smart-d697edda-0238-4dcf-81a7-6fe4a2816b8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1883789944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1883789944
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.234231480
Short name T3683
Test name
Test status
Simulation time 101041713 ps
CPU time 2.95 seconds
Started Aug 08 05:38:31 PM PDT 24
Finished Aug 08 05:38:34 PM PDT 24
Peak memory 215116 kb
Host smart-5f074ed0-c61f-4ad8-9dce-4527e3a6fc1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234231480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.234231480
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3241848817
Short name T277
Test name
Test status
Simulation time 72507799 ps
CPU time 1.03 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:19 PM PDT 24
Peak memory 207164 kb
Host smart-07e01b3a-35c3-443e-bfdc-b70399be1794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3241848817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3241848817
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.528453495
Short name T3647
Test name
Test status
Simulation time 46998689 ps
CPU time 0.75 seconds
Started Aug 08 05:38:26 PM PDT 24
Finished Aug 08 05:38:27 PM PDT 24
Peak memory 206872 kb
Host smart-9f5b4ab5-3ec4-422e-b7e8-1a60d043132d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=528453495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.528453495
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3125040387
Short name T306
Test name
Test status
Simulation time 210470803 ps
CPU time 2.4 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:21 PM PDT 24
Peak memory 215516 kb
Host smart-e7f3f49c-4379-4ed2-853d-62040acbb6bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3125040387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3125040387
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1515030256
Short name T3721
Test name
Test status
Simulation time 189766776 ps
CPU time 3.75 seconds
Started Aug 08 05:38:19 PM PDT 24
Finished Aug 08 05:38:23 PM PDT 24
Peak memory 207128 kb
Host smart-21b14490-ae75-466e-99cf-5f1139b9d848
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1515030256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1515030256
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3199371657
Short name T3716
Test name
Test status
Simulation time 233448787 ps
CPU time 1.69 seconds
Started Aug 08 05:38:29 PM PDT 24
Finished Aug 08 05:38:31 PM PDT 24
Peak memory 207268 kb
Host smart-f1ba5033-8b2d-47c0-af11-3a60729ae69a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3199371657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3199371657
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1504593595
Short name T276
Test name
Test status
Simulation time 48117024 ps
CPU time 1.21 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:19 PM PDT 24
Peak memory 207336 kb
Host smart-ca6ebb20-0b25-4765-a603-0b477bfd4677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1504593595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1504593595
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3452241039
Short name T347
Test name
Test status
Simulation time 962175924 ps
CPU time 5.38 seconds
Started Aug 08 05:38:18 PM PDT 24
Finished Aug 08 05:38:24 PM PDT 24
Peak memory 207332 kb
Host smart-b35f2ce7-2777-4f16-95a0-b2d6eea498d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3452241039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3452241039
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2122143935
Short name T3682
Test name
Test status
Simulation time 105256892 ps
CPU time 0.78 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206988 kb
Host smart-b1c09189-1277-4b53-85f0-f50748ce9e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2122143935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2122143935
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3406332921
Short name T340
Test name
Test status
Simulation time 48658909 ps
CPU time 0.76 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 207008 kb
Host smart-a5b1137a-7d2e-44d3-b6d1-b3da4766ce83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3406332921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3406332921
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4201849119
Short name T3646
Test name
Test status
Simulation time 33267749 ps
CPU time 0.69 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206936 kb
Host smart-29f9cbc8-425b-4ddb-bb64-212fc78d0a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201849119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4201849119
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.914346098
Short name T341
Test name
Test status
Simulation time 64233358 ps
CPU time 0.77 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206904 kb
Host smart-90de7cfb-5a9b-471b-ba29-643c99a22e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914346098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.914346098
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1441716174
Short name T345
Test name
Test status
Simulation time 48550132 ps
CPU time 0.74 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206928 kb
Host smart-d2dbdab0-fff7-441e-9916-b0002bdd15b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1441716174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1441716174
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2591908064
Short name T3645
Test name
Test status
Simulation time 70970980 ps
CPU time 0.78 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 206928 kb
Host smart-ef7d1cde-d7c5-4ff7-b6e7-6b6a214e22f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2591908064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2591908064
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2966448390
Short name T320
Test name
Test status
Simulation time 48022598 ps
CPU time 0.75 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 207016 kb
Host smart-7c29e396-05d1-45d6-b200-5d81281d7e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2966448390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2966448390
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3919824494
Short name T3714
Test name
Test status
Simulation time 36870589 ps
CPU time 0.75 seconds
Started Aug 08 05:39:23 PM PDT 24
Finished Aug 08 05:39:24 PM PDT 24
Peak memory 207212 kb
Host smart-3fdd2879-c4ee-448d-ade8-50f5a8f969d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3919824494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3919824494
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2840314226
Short name T224
Test name
Test status
Simulation time 55625708 ps
CPU time 0.76 seconds
Started Aug 08 05:39:19 PM PDT 24
Finished Aug 08 05:39:20 PM PDT 24
Peak memory 206888 kb
Host smart-63a2c468-c78f-458a-848a-44880738b44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840314226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2840314226
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2841395439
Short name T301
Test name
Test status
Simulation time 100548733 ps
CPU time 1.91 seconds
Started Aug 08 05:38:28 PM PDT 24
Finished Aug 08 05:38:30 PM PDT 24
Peak memory 207292 kb
Host smart-485f3a65-864f-4ea6-ba71-7a0c9277e065
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2841395439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2841395439
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2307131221
Short name T3684
Test name
Test status
Simulation time 183262637 ps
CPU time 1.01 seconds
Started Aug 08 05:38:28 PM PDT 24
Finished Aug 08 05:38:29 PM PDT 24
Peak memory 207144 kb
Host smart-272a50c3-6c2a-41fa-a916-4dcb8cfb2496
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2307131221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2307131221
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2136332042
Short name T3736
Test name
Test status
Simulation time 90806263 ps
CPU time 1.36 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 215480 kb
Host smart-933b71a5-8eca-4cc4-a641-c53be91fcd47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136332042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2136332042
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1450655093
Short name T309
Test name
Test status
Simulation time 93121524 ps
CPU time 0.88 seconds
Started Aug 08 05:38:29 PM PDT 24
Finished Aug 08 05:38:30 PM PDT 24
Peak memory 207184 kb
Host smart-9a3feb3f-f1f8-4518-ad4b-19f18af5c609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1450655093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1450655093
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2485821317
Short name T226
Test name
Test status
Simulation time 36989806 ps
CPU time 0.69 seconds
Started Aug 08 05:38:31 PM PDT 24
Finished Aug 08 05:38:31 PM PDT 24
Peak memory 206660 kb
Host smart-97a90740-4700-4ef9-bdce-5651b5b9d905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2485821317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2485821317
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1242168989
Short name T3701
Test name
Test status
Simulation time 59009531 ps
CPU time 1.34 seconds
Started Aug 08 05:38:29 PM PDT 24
Finished Aug 08 05:38:30 PM PDT 24
Peak memory 215504 kb
Host smart-a9c4cff7-d1a3-4cd1-bc6c-bcc0bf822c85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1242168989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1242168989
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2566807473
Short name T3637
Test name
Test status
Simulation time 102672685 ps
CPU time 2.36 seconds
Started Aug 08 05:38:33 PM PDT 24
Finished Aug 08 05:38:35 PM PDT 24
Peak memory 207240 kb
Host smart-037c4203-448b-43cf-96f4-09c0bb741676
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2566807473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2566807473
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2461794858
Short name T316
Test name
Test status
Simulation time 138528394 ps
CPU time 1.21 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:41 PM PDT 24
Peak memory 207368 kb
Host smart-48a0c0aa-7fd0-4315-ba14-ea4460398c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2461794858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2461794858
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1967744063
Short name T275
Test name
Test status
Simulation time 303163202 ps
CPU time 3.3 seconds
Started Aug 08 05:38:29 PM PDT 24
Finished Aug 08 05:38:32 PM PDT 24
Peak memory 215552 kb
Host smart-33291112-11a1-458b-89d8-5d8afd66ce1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1967744063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1967744063
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4281566908
Short name T497
Test name
Test status
Simulation time 462064019 ps
CPU time 2.69 seconds
Started Aug 08 05:38:28 PM PDT 24
Finished Aug 08 05:38:31 PM PDT 24
Peak memory 207260 kb
Host smart-faace062-3397-439b-9312-8164c3ffdb74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4281566908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4281566908
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4270741528
Short name T3649
Test name
Test status
Simulation time 42769485 ps
CPU time 0.72 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206888 kb
Host smart-1a42e53b-9050-4a85-9af9-078bd2a3d628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4270741528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4270741528
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3416776992
Short name T3666
Test name
Test status
Simulation time 50209903 ps
CPU time 0.72 seconds
Started Aug 08 05:39:23 PM PDT 24
Finished Aug 08 05:39:23 PM PDT 24
Peak memory 206964 kb
Host smart-b7911efc-423b-4fc3-b8bb-7e7fc0576b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416776992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3416776992
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2588818815
Short name T3726
Test name
Test status
Simulation time 86900040 ps
CPU time 0.79 seconds
Started Aug 08 05:39:23 PM PDT 24
Finished Aug 08 05:39:24 PM PDT 24
Peak memory 206928 kb
Host smart-d6403d86-f56a-421e-9292-c11d5fb526da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2588818815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2588818815
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.886314268
Short name T3652
Test name
Test status
Simulation time 39135802 ps
CPU time 0.7 seconds
Started Aug 08 05:39:19 PM PDT 24
Finished Aug 08 05:39:20 PM PDT 24
Peak memory 206952 kb
Host smart-826a5677-b567-43d8-83ac-2aa54b39ec5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886314268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.886314268
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2566107906
Short name T3638
Test name
Test status
Simulation time 41068361 ps
CPU time 0.68 seconds
Started Aug 08 05:39:19 PM PDT 24
Finished Aug 08 05:39:20 PM PDT 24
Peak memory 206896 kb
Host smart-3fa795ff-efb8-45ad-aa56-16d8392af9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2566107906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2566107906
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1208506120
Short name T3735
Test name
Test status
Simulation time 37057749 ps
CPU time 0.74 seconds
Started Aug 08 05:39:23 PM PDT 24
Finished Aug 08 05:39:24 PM PDT 24
Peak memory 207016 kb
Host smart-f1b853c5-fafd-4ffe-900a-66eb09de90d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1208506120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1208506120
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2886222767
Short name T3737
Test name
Test status
Simulation time 46823450 ps
CPU time 0.72 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206916 kb
Host smart-450b3ea6-2be0-47a2-91d0-0792b6781d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886222767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2886222767
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1303049591
Short name T3650
Test name
Test status
Simulation time 77990902 ps
CPU time 0.8 seconds
Started Aug 08 05:39:20 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 207040 kb
Host smart-09f3800c-a499-4e42-9def-90a7456b6cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1303049591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1303049591
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3064481790
Short name T319
Test name
Test status
Simulation time 43671435 ps
CPU time 0.71 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206924 kb
Host smart-99943eab-7509-479d-87cf-ab3350f6fb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3064481790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3064481790
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.675414433
Short name T3698
Test name
Test status
Simulation time 38003719 ps
CPU time 0.73 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206964 kb
Host smart-c0defea1-cada-4baf-ae13-53d79a01d349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=675414433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.675414433
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1554752115
Short name T304
Test name
Test status
Simulation time 334325799 ps
CPU time 3.81 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:42 PM PDT 24
Peak memory 207256 kb
Host smart-d4f61828-19dd-468a-92bd-d571e9573e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1554752115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1554752115
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3727785974
Short name T3719
Test name
Test status
Simulation time 633120228 ps
CPU time 5.12 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:44 PM PDT 24
Peak memory 207208 kb
Host smart-38bf802c-6a21-4c47-8b7a-47ddc649874d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3727785974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3727785974
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.530573520
Short name T305
Test name
Test status
Simulation time 90305717 ps
CPU time 0.83 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 206984 kb
Host smart-dc41a90c-eee7-4713-8f86-2338b19764e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=530573520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.530573520
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2775973152
Short name T3702
Test name
Test status
Simulation time 95620860 ps
CPU time 1.21 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 215404 kb
Host smart-ab805f97-71ee-4810-96df-8258718f9d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775973152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2775973152
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2793730718
Short name T3728
Test name
Test status
Simulation time 70817315 ps
CPU time 0.98 seconds
Started Aug 08 05:38:40 PM PDT 24
Finished Aug 08 05:38:41 PM PDT 24
Peak memory 207012 kb
Host smart-6d6ca121-4e90-4dcd-a408-e70a163567af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2793730718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2793730718
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1167439540
Short name T3664
Test name
Test status
Simulation time 45740873 ps
CPU time 0.71 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:39 PM PDT 24
Peak memory 207032 kb
Host smart-7fcfcce3-22de-4473-bed1-2d5f027b8051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1167439540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1167439540
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1496724005
Short name T311
Test name
Test status
Simulation time 104362264 ps
CPU time 2.22 seconds
Started Aug 08 05:38:40 PM PDT 24
Finished Aug 08 05:38:42 PM PDT 24
Peak memory 207216 kb
Host smart-68cee9fa-b24d-4f8d-869c-fc63c7b509ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1496724005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1496724005
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2949659619
Short name T3654
Test name
Test status
Simulation time 401572481 ps
CPU time 2.73 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:42 PM PDT 24
Peak memory 207220 kb
Host smart-34541722-6563-4fbc-a1fb-a65f07f8de93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2949659619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2949659619
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1310075704
Short name T3657
Test name
Test status
Simulation time 199957085 ps
CPU time 1.68 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 207248 kb
Host smart-b5759eba-8306-4500-8f0e-194f9465954a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1310075704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1310075704
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2846100158
Short name T3669
Test name
Test status
Simulation time 97911407 ps
CPU time 1.88 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 223588 kb
Host smart-910937b7-3e00-4077-83de-343720af7834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846100158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2846100158
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1648228700
Short name T351
Test name
Test status
Simulation time 712334778 ps
CPU time 2.69 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:42 PM PDT 24
Peak memory 207312 kb
Host smart-601083c9-7188-4121-a260-5399b1fe77d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1648228700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1648228700
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3410335442
Short name T3694
Test name
Test status
Simulation time 54991246 ps
CPU time 0.73 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206988 kb
Host smart-93a903c0-59dc-4bee-a39d-55a948a54274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3410335442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3410335442
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3877316841
Short name T223
Test name
Test status
Simulation time 34793942 ps
CPU time 0.71 seconds
Started Aug 08 05:39:22 PM PDT 24
Finished Aug 08 05:39:23 PM PDT 24
Peak memory 207008 kb
Host smart-abd5397b-68ab-4fa2-88ee-3ef3baec1b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877316841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3877316841
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1267745810
Short name T3710
Test name
Test status
Simulation time 47829675 ps
CPU time 0.71 seconds
Started Aug 08 05:39:20 PM PDT 24
Finished Aug 08 05:39:21 PM PDT 24
Peak memory 206992 kb
Host smart-8aa863e2-6c89-4ef4-aafe-1227f6fbd21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1267745810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1267745810
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3711775426
Short name T3663
Test name
Test status
Simulation time 46805011 ps
CPU time 0.72 seconds
Started Aug 08 05:39:26 PM PDT 24
Finished Aug 08 05:39:27 PM PDT 24
Peak memory 207012 kb
Host smart-7f86e334-7752-40bf-84ba-893aa807b01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3711775426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3711775426
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.4045180591
Short name T3693
Test name
Test status
Simulation time 46269338 ps
CPU time 0.7 seconds
Started Aug 08 05:39:19 PM PDT 24
Finished Aug 08 05:39:20 PM PDT 24
Peak memory 206876 kb
Host smart-7ec5f01a-fe9d-4430-a058-15d83a4b46d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4045180591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4045180591
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3656768108
Short name T3651
Test name
Test status
Simulation time 46062312 ps
CPU time 0.69 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206916 kb
Host smart-6ccad1a1-d5c0-4a14-bbbf-1fafbcf6ac0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656768108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3656768108
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2933610474
Short name T3648
Test name
Test status
Simulation time 58097225 ps
CPU time 0.74 seconds
Started Aug 08 05:39:21 PM PDT 24
Finished Aug 08 05:39:22 PM PDT 24
Peak memory 206984 kb
Host smart-9b13ede6-9e8a-40f5-b47a-00cef5b8bcc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2933610474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2933610474
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2352332860
Short name T3653
Test name
Test status
Simulation time 84835504 ps
CPU time 0.77 seconds
Started Aug 08 05:39:22 PM PDT 24
Finished Aug 08 05:39:23 PM PDT 24
Peak memory 207212 kb
Host smart-2c41f741-eefa-4202-8645-69934b187184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352332860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2352332860
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1209428629
Short name T3700
Test name
Test status
Simulation time 46101310 ps
CPU time 0.73 seconds
Started Aug 08 05:39:19 PM PDT 24
Finished Aug 08 05:39:19 PM PDT 24
Peak memory 206884 kb
Host smart-e490521b-3411-45b2-9bdf-d4977aed591b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209428629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1209428629
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1941894551
Short name T3696
Test name
Test status
Simulation time 139010060 ps
CPU time 1.85 seconds
Started Aug 08 05:38:54 PM PDT 24
Finished Aug 08 05:38:56 PM PDT 24
Peak memory 215636 kb
Host smart-685462fe-7633-4006-8243-7e5bac05d4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941894551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1941894551
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3314049995
Short name T3690
Test name
Test status
Simulation time 78516752 ps
CPU time 1.03 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:40 PM PDT 24
Peak memory 206940 kb
Host smart-2d18598a-2b37-41b3-8815-71fab915b59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3314049995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3314049995
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1967973214
Short name T3642
Test name
Test status
Simulation time 48808423 ps
CPU time 0.7 seconds
Started Aug 08 05:38:38 PM PDT 24
Finished Aug 08 05:38:39 PM PDT 24
Peak memory 207016 kb
Host smart-706d9261-8044-4828-81fe-19d71acebab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1967973214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1967973214
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4196222326
Short name T3717
Test name
Test status
Simulation time 156133376 ps
CPU time 1.25 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 207392 kb
Host smart-80f381ab-f05f-4a7b-9a7c-492af4f58715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4196222326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4196222326
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.115045134
Short name T3739
Test name
Test status
Simulation time 90202166 ps
CPU time 1.87 seconds
Started Aug 08 05:38:40 PM PDT 24
Finished Aug 08 05:38:42 PM PDT 24
Peak memory 220980 kb
Host smart-2c733889-ccf6-41e0-b72f-bd7b8c746fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115045134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.115045134
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2873561553
Short name T264
Test name
Test status
Simulation time 1339253335 ps
CPU time 4.93 seconds
Started Aug 08 05:38:39 PM PDT 24
Finished Aug 08 05:38:44 PM PDT 24
Peak memory 207292 kb
Host smart-8dedd908-9205-420b-b65a-1b480f8aeaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2873561553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2873561553
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1319330162
Short name T3658
Test name
Test status
Simulation time 64766690 ps
CPU time 1.12 seconds
Started Aug 08 05:38:48 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 215340 kb
Host smart-8c0635e6-0d56-4b4b-90d5-edf214d1760f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319330162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1319330162
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.508990157
Short name T300
Test name
Test status
Simulation time 77132680 ps
CPU time 1.02 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 207100 kb
Host smart-0180d73e-054c-4cf5-917f-c45e8c09cda9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=508990157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.508990157
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2392991183
Short name T3636
Test name
Test status
Simulation time 32280241 ps
CPU time 0.7 seconds
Started Aug 08 05:38:51 PM PDT 24
Finished Aug 08 05:38:51 PM PDT 24
Peak memory 206880 kb
Host smart-0fa28c61-2b05-4c8c-9599-04957b7db068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392991183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2392991183
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1686467330
Short name T3708
Test name
Test status
Simulation time 273956629 ps
CPU time 1.7 seconds
Started Aug 08 05:38:50 PM PDT 24
Finished Aug 08 05:38:52 PM PDT 24
Peak memory 207216 kb
Host smart-fd2438f9-6304-47c1-b7ed-ecfe105f5c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1686467330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1686467330
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3483505566
Short name T3718
Test name
Test status
Simulation time 109164019 ps
CPU time 1.66 seconds
Started Aug 08 05:38:51 PM PDT 24
Finished Aug 08 05:38:53 PM PDT 24
Peak memory 207340 kb
Host smart-7e3f5bb3-cc66-4e61-9283-3382aaea0747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3483505566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3483505566
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3638223270
Short name T349
Test name
Test status
Simulation time 1135933447 ps
CPU time 5.93 seconds
Started Aug 08 05:38:54 PM PDT 24
Finished Aug 08 05:39:00 PM PDT 24
Peak memory 207352 kb
Host smart-33189ae7-3c62-407d-aa03-ab6e2eb6d99e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3638223270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3638223270
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2024025290
Short name T3673
Test name
Test status
Simulation time 110688387 ps
CPU time 1.21 seconds
Started Aug 08 05:38:51 PM PDT 24
Finished Aug 08 05:38:52 PM PDT 24
Peak memory 215356 kb
Host smart-cad3f1b7-05a7-4159-bc04-3d82bbacdd23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024025290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2024025290
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.845087425
Short name T3640
Test name
Test status
Simulation time 52604298 ps
CPU time 0.95 seconds
Started Aug 08 05:38:50 PM PDT 24
Finished Aug 08 05:38:51 PM PDT 24
Peak memory 206896 kb
Host smart-9070d4e5-a523-4f27-a6cd-c900c1fd837f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=845087425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.845087425
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2676841227
Short name T3706
Test name
Test status
Simulation time 81936935 ps
CPU time 0.75 seconds
Started Aug 08 05:38:50 PM PDT 24
Finished Aug 08 05:38:51 PM PDT 24
Peak memory 206952 kb
Host smart-5d8395f3-5702-48d4-b0cd-6363981f1097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2676841227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2676841227
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4117192415
Short name T3691
Test name
Test status
Simulation time 85301993 ps
CPU time 1.52 seconds
Started Aug 08 05:38:53 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 207280 kb
Host smart-ba2f489d-b6b2-44e3-b215-0b5266ff2ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4117192415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4117192415
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2728459358
Short name T271
Test name
Test status
Simulation time 65073014 ps
CPU time 1.72 seconds
Started Aug 08 05:38:50 PM PDT 24
Finished Aug 08 05:38:52 PM PDT 24
Peak memory 207356 kb
Host smart-2ce26236-3a26-40be-ab5d-51f07ec4cd0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728459358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2728459358
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3256936281
Short name T283
Test name
Test status
Simulation time 728583006 ps
CPU time 5.43 seconds
Started Aug 08 05:38:54 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207380 kb
Host smart-775b39a4-4480-4bd0-88a9-025b0c7b596b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3256936281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3256936281
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1652209574
Short name T278
Test name
Test status
Simulation time 262719937 ps
CPU time 2.14 seconds
Started Aug 08 05:38:52 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 215492 kb
Host smart-9913bd62-453d-4a37-8dac-b5a4fb635dd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652209574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1652209574
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1597351062
Short name T314
Test name
Test status
Simulation time 117556090 ps
CPU time 1.07 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 207128 kb
Host smart-036b6ab5-61e8-4a32-8d55-cbfa0a924e41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1597351062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1597351062
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3841824540
Short name T3676
Test name
Test status
Simulation time 73610898 ps
CPU time 0.77 seconds
Started Aug 08 05:38:53 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 206928 kb
Host smart-b5a1b3ca-0870-444b-97e3-25335631ed06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3841824540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3841824540
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3783231980
Short name T3660
Test name
Test status
Simulation time 184249493 ps
CPU time 1.71 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:50 PM PDT 24
Peak memory 207332 kb
Host smart-f1805e76-313e-44e4-9a2b-8ce0a91ef64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783231980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3783231980
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.167773207
Short name T3729
Test name
Test status
Simulation time 136638751 ps
CPU time 3.04 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:52 PM PDT 24
Peak memory 222952 kb
Host smart-fb187255-49e0-4e28-8d88-fb13d7e9e05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=167773207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.167773207
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2520212406
Short name T273
Test name
Test status
Simulation time 122543610 ps
CPU time 3.06 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:39:01 PM PDT 24
Peak memory 215516 kb
Host smart-0b32a037-1ee6-46af-a338-b2d1fd30058e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520212406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2520212406
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3150778315
Short name T3707
Test name
Test status
Simulation time 55601358 ps
CPU time 0.98 seconds
Started Aug 08 05:38:58 PM PDT 24
Finished Aug 08 05:38:59 PM PDT 24
Peak memory 207036 kb
Host smart-7bb70972-199d-4da6-aa9b-fc8d81774c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3150778315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3150778315
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2947134694
Short name T3665
Test name
Test status
Simulation time 146042097 ps
CPU time 1.12 seconds
Started Aug 08 05:38:57 PM PDT 24
Finished Aug 08 05:38:58 PM PDT 24
Peak memory 207304 kb
Host smart-6bfde0d9-d478-42a0-9d75-0681003bd1c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2947134694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2947134694
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1953161730
Short name T274
Test name
Test status
Simulation time 204623188 ps
CPU time 2.18 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:51 PM PDT 24
Peak memory 207280 kb
Host smart-ee348bbc-b080-49ee-89b9-63e6c400d366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1953161730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1953161730
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3183322045
Short name T496
Test name
Test status
Simulation time 1539156206 ps
CPU time 5.24 seconds
Started Aug 08 05:38:49 PM PDT 24
Finished Aug 08 05:38:54 PM PDT 24
Peak memory 207316 kb
Host smart-3918a481-75aa-424f-8027-def2be9c3b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3183322045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3183322045
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2032928935
Short name T2551
Test name
Test status
Simulation time 41176946 ps
CPU time 0.66 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207620 kb
Host smart-21c834da-8cec-49fa-b651-9d3ce4fa917d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2032928935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2032928935
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2917685631
Short name T1273
Test name
Test status
Simulation time 4338040553 ps
CPU time 6.44 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:09 PM PDT 24
Peak memory 215932 kb
Host smart-18261c08-7a7b-4197-a8e4-15ce341c66c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917685631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.2917685631
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1780340742
Short name T1372
Test name
Test status
Simulation time 25485701277 ps
CPU time 38.83 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 216024 kb
Host smart-505dd1f5-10c7-4e7d-9b41-3c53e2fc7a47
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780340742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1780340742
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3287353804
Short name T1545
Test name
Test status
Simulation time 157501894 ps
CPU time 0.86 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 207532 kb
Host smart-448a1f5e-8176-4812-850e-d1519a095cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873
53804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3287353804
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2358957306
Short name T1393
Test name
Test status
Simulation time 179784087 ps
CPU time 0.9 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:04 PM PDT 24
Peak memory 207580 kb
Host smart-c23c9543-313b-4202-b0dc-a8a4145512f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
57306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2358957306
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1078361133
Short name T1665
Test name
Test status
Simulation time 227824812 ps
CPU time 1.1 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:02 PM PDT 24
Peak memory 207620 kb
Host smart-eb9cff22-52bf-4e96-9e94-5fa5ac7379fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10783
61133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1078361133
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3732008578
Short name T3046
Test name
Test status
Simulation time 711541100 ps
CPU time 2.05 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 207548 kb
Host smart-0fd7f1a0-04f1-4491-ae0f-6cee2104cf0f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3732008578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3732008578
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3750469383
Short name T1650
Test name
Test status
Simulation time 61897864894 ps
CPU time 101.74 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:14:43 PM PDT 24
Peak memory 207868 kb
Host smart-71afdd0f-b9b9-4730-9113-cfa6db75e390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37504
69383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3750469383
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.3453806648
Short name T2150
Test name
Test status
Simulation time 5668035752 ps
CPU time 38.09 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207872 kb
Host smart-d555567f-032d-4220-b750-2d1b97e4eeff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453806648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3453806648
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.1072589775
Short name T2863
Test name
Test status
Simulation time 970925653 ps
CPU time 2.22 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207556 kb
Host smart-326d4952-f346-4a7f-8639-42440dd08e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10725
89775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.1072589775
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.691900484
Short name T1671
Test name
Test status
Simulation time 165542157 ps
CPU time 0.89 seconds
Started Aug 08 06:13:06 PM PDT 24
Finished Aug 08 06:13:07 PM PDT 24
Peak memory 207544 kb
Host smart-3bfd6c2b-d47f-4ed4-b125-950d2596b38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69190
0484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.691900484
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.128853552
Short name T1993
Test name
Test status
Simulation time 52431782 ps
CPU time 0.72 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 206328 kb
Host smart-bda53baa-221d-4f5b-a823-bf5553e29a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12885
3552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.128853552
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2349980964
Short name T3105
Test name
Test status
Simulation time 1064253278 ps
CPU time 2.71 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207720 kb
Host smart-747cb0c2-c949-466a-8f7e-1ba76fa0b84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
80964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2349980964
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1303738764
Short name T3520
Test name
Test status
Simulation time 116199705631 ps
CPU time 182.03 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:16:09 PM PDT 24
Peak memory 207784 kb
Host smart-b365d3da-fb2a-4267-929b-07daf618b08b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1303738764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1303738764
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.1258018764
Short name T3309
Test name
Test status
Simulation time 92096558054 ps
CPU time 143.15 seconds
Started Aug 08 06:13:04 PM PDT 24
Finished Aug 08 06:15:27 PM PDT 24
Peak memory 207800 kb
Host smart-b0f35db0-c70e-4c5f-8849-1aaf67b45649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258018764 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1258018764
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.1052740014
Short name T1452
Test name
Test status
Simulation time 121082688428 ps
CPU time 217.22 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:16:40 PM PDT 24
Peak memory 207864 kb
Host smart-df7177d6-eb3b-4409-b917-57b85bcbffd7
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1052740014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.1052740014
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1425170407
Short name T1917
Test name
Test status
Simulation time 85199932511 ps
CPU time 127.52 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:15:10 PM PDT 24
Peak memory 207792 kb
Host smart-1c2b0001-e4ed-4b34-b147-d07f50c0c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425170407 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1425170407
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3316283269
Short name T3527
Test name
Test status
Simulation time 253011113 ps
CPU time 1.2 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 216912 kb
Host smart-2f0b7e10-c659-4c8b-8ce9-372d5b963d2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3316283269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3316283269
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2906241070
Short name T2516
Test name
Test status
Simulation time 202047143 ps
CPU time 0.96 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:02 PM PDT 24
Peak memory 207524 kb
Host smart-92a76d0c-b31f-4871-a699-a62e0fa66f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062
41070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2906241070
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2218624750
Short name T880
Test name
Test status
Simulation time 234024410 ps
CPU time 1.02 seconds
Started Aug 08 06:13:04 PM PDT 24
Finished Aug 08 06:13:05 PM PDT 24
Peak memory 207604 kb
Host smart-6107970a-ce30-46c6-b4ed-a1e761b5abbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
24750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2218624750
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1358156173
Short name T2553
Test name
Test status
Simulation time 3686029992 ps
CPU time 104.77 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 218444 kb
Host smart-76ab6962-4bf4-4784-9cf2-ab5c5755fead
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1358156173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1358156173
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2814389536
Short name T637
Test name
Test status
Simulation time 11661737550 ps
CPU time 148.77 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:15:31 PM PDT 24
Peak memory 207824 kb
Host smart-3e0432ee-aea0-4470-911f-0bf6fea72f62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2814389536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2814389536
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1519298964
Short name T3332
Test name
Test status
Simulation time 213645836 ps
CPU time 0.94 seconds
Started Aug 08 06:13:02 PM PDT 24
Finished Aug 08 06:13:03 PM PDT 24
Peak memory 207524 kb
Host smart-a222dbfb-5ed3-4c8e-952a-212ed62c1af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
98964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1519298964
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2849661234
Short name T73
Test name
Test status
Simulation time 454026665 ps
CPU time 1.37 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 207440 kb
Host smart-25831822-5c20-48a8-918e-03cd15df6f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
61234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2849661234
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2257478792
Short name T1913
Test name
Test status
Simulation time 28260533702 ps
CPU time 45.99 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 207840 kb
Host smart-eb9e753d-f529-4622-a6d2-d94adcd81c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
78792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2257478792
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3247719693
Short name T1014
Test name
Test status
Simulation time 5880902815 ps
CPU time 8.25 seconds
Started Aug 08 06:13:00 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 216380 kb
Host smart-0da77b4e-56c6-4d66-8784-fa75ea010b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32477
19693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3247719693
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.29035518
Short name T2966
Test name
Test status
Simulation time 4911827082 ps
CPU time 130.94 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:15:14 PM PDT 24
Peak memory 218704 kb
Host smart-33048d61-761d-4473-9b20-8ca71d1b5b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.29035518
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.432964288
Short name T3379
Test name
Test status
Simulation time 3448904684 ps
CPU time 100.29 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:14:47 PM PDT 24
Peak memory 216040 kb
Host smart-b156d38a-b943-4828-ba04-bc35d60126fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=432964288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.432964288
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3983100195
Short name T1584
Test name
Test status
Simulation time 246012590 ps
CPU time 1.01 seconds
Started Aug 08 06:13:01 PM PDT 24
Finished Aug 08 06:13:02 PM PDT 24
Peak memory 207608 kb
Host smart-47fcd66d-c40c-4ac3-be6d-47a8e505b9b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3983100195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3983100195
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.176842178
Short name T2754
Test name
Test status
Simulation time 189463324 ps
CPU time 0.96 seconds
Started Aug 08 06:13:07 PM PDT 24
Finished Aug 08 06:13:08 PM PDT 24
Peak memory 207408 kb
Host smart-1c5544cf-2ca5-40c4-b645-db213080418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
2178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.176842178
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.422609788
Short name T3221
Test name
Test status
Simulation time 1834897367 ps
CPU time 13.34 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207760 kb
Host smart-7243dd1b-24da-4082-bf64-3b8a505a5a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
9788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.422609788
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1316346581
Short name T1690
Test name
Test status
Simulation time 3014213922 ps
CPU time 35.05 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:50 PM PDT 24
Peak memory 216148 kb
Host smart-a74720b3-4767-4d94-836d-e0da098904c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1316346581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1316346581
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.645054138
Short name T2684
Test name
Test status
Simulation time 3099288107 ps
CPU time 33.03 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:47 PM PDT 24
Peak memory 217376 kb
Host smart-134d2d5e-f99d-4875-bae6-1b2c070207e9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=645054138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.645054138
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2532468145
Short name T528
Test name
Test status
Simulation time 147553602 ps
CPU time 0.86 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207588 kb
Host smart-a14cd5b7-6690-4849-89c0-be7d05d85787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25324
68145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2532468145
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3500385741
Short name T74
Test name
Test status
Simulation time 494179313 ps
CPU time 1.64 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207460 kb
Host smart-c598907a-739d-4832-b8f2-75725df6661b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
85741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3500385741
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1844589389
Short name T1426
Test name
Test status
Simulation time 181273196 ps
CPU time 0.91 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207592 kb
Host smart-1769fdc5-7f1c-49df-8a60-9a19301bbbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18445
89389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1844589389
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3371369481
Short name T2277
Test name
Test status
Simulation time 221700512 ps
CPU time 1.03 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207544 kb
Host smart-51b67000-1a34-4e83-844b-b9e5fc9732e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
69481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3371369481
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2137977442
Short name T673
Test name
Test status
Simulation time 204115633 ps
CPU time 0.89 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 207548 kb
Host smart-fef056ee-f57b-4e4b-93f9-532dbfbd440e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
77442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2137977442
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.95611818
Short name T252
Test name
Test status
Simulation time 209579388 ps
CPU time 0.96 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207528 kb
Host smart-f2e7957d-b84b-4514-a57b-bdfb6ef44fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95611
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.95611818
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2567247252
Short name T185
Test name
Test status
Simulation time 182925704 ps
CPU time 0.85 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207504 kb
Host smart-8c292c66-979b-4cb4-8b87-ee8ced364022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
47252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2567247252
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.52048160
Short name T1492
Test name
Test status
Simulation time 189153111 ps
CPU time 0.93 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 207520 kb
Host smart-f0b7cfb6-3026-486b-a542-4531b9e84edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52048
160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.52048160
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1933283563
Short name T1127
Test name
Test status
Simulation time 202459278 ps
CPU time 1 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 207580 kb
Host smart-6644457e-90c5-488c-9556-d0ab9a518ed9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1933283563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1933283563
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2515968295
Short name T2833
Test name
Test status
Simulation time 233751434 ps
CPU time 1 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207596 kb
Host smart-e070084c-ae13-4002-9e35-3af049aaf7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25159
68295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2515968295
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.2343897671
Short name T1800
Test name
Test status
Simulation time 217852013 ps
CPU time 1 seconds
Started Aug 08 06:13:16 PM PDT 24
Finished Aug 08 06:13:18 PM PDT 24
Peak memory 207620 kb
Host smart-383f1ce7-f89e-477f-9a44-9cff43e48f2d
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2343897671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2343897671
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.497306487
Short name T2347
Test name
Test status
Simulation time 209302908 ps
CPU time 0.98 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207484 kb
Host smart-a4fc0768-be23-4736-a255-0421d8b7932b
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=497306487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.497306487
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2045842843
Short name T3233
Test name
Test status
Simulation time 175563751 ps
CPU time 0.88 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207540 kb
Host smart-142365b2-f1c0-4412-a072-9394f874e145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20458
42843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2045842843
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.674554882
Short name T3109
Test name
Test status
Simulation time 86672434 ps
CPU time 0.76 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:13 PM PDT 24
Peak memory 207532 kb
Host smart-db78f70d-68fc-4a7e-82f3-0ebcc1af7d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67455
4882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.674554882
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1238537012
Short name T2046
Test name
Test status
Simulation time 154069667 ps
CPU time 0.86 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207568 kb
Host smart-3650bef4-9b5c-492e-b895-dff8b41c3783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
37012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1238537012
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1893948435
Short name T2067
Test name
Test status
Simulation time 181252424 ps
CPU time 0.89 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207616 kb
Host smart-a50eb1fc-fcb6-40bf-af1b-72a821b16e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
48435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1893948435
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2552017038
Short name T2463
Test name
Test status
Simulation time 6531783522 ps
CPU time 34.68 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:48 PM PDT 24
Peak memory 219472 kb
Host smart-4480e4ab-69be-4dec-925e-3479f59b63fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552017038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2552017038
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.405643968
Short name T2448
Test name
Test status
Simulation time 6351820215 ps
CPU time 34.19 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:49 PM PDT 24
Peak memory 219956 kb
Host smart-323276d9-ede2-409c-9ef2-b84d9cb7af5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=405643968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.405643968
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2395088711
Short name T1659
Test name
Test status
Simulation time 183168557 ps
CPU time 0.93 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207596 kb
Host smart-8a9684d7-2c43-4ca8-9f7f-0224e748c494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
88711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2395088711
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.537726603
Short name T2650
Test name
Test status
Simulation time 191992937 ps
CPU time 0.95 seconds
Started Aug 08 06:13:16 PM PDT 24
Finished Aug 08 06:13:18 PM PDT 24
Peak memory 207620 kb
Host smart-3320f499-99e5-4620-87bd-989ad442b557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53772
6603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.537726603
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.632721629
Short name T1069
Test name
Test status
Simulation time 20155654622 ps
CPU time 25.44 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 207644 kb
Host smart-d696f052-c9be-443f-8c70-3c7f2924b3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63272
1629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.632721629
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.873354681
Short name T503
Test name
Test status
Simulation time 157096203 ps
CPU time 0.86 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:13:12 PM PDT 24
Peak memory 207612 kb
Host smart-bdf1b632-36ee-41fd-8103-3635098ff9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87335
4681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.873354681
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2309866113
Short name T1270
Test name
Test status
Simulation time 177392467 ps
CPU time 0.92 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207568 kb
Host smart-084ae8bc-a164-4cdd-b585-d60cc84d797c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
66113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2309866113
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1672874105
Short name T1195
Test name
Test status
Simulation time 168595117 ps
CPU time 0.87 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207532 kb
Host smart-372b6208-db0e-4969-b9c5-86ac122b1b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
74105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1672874105
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.644001991
Short name T2358
Test name
Test status
Simulation time 155013895 ps
CPU time 0.87 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:12 PM PDT 24
Peak memory 207592 kb
Host smart-c5eb30a2-1877-45b7-a272-fa4346c1cb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64400
1991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.644001991
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1399552423
Short name T2159
Test name
Test status
Simulation time 222120588 ps
CPU time 1 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:14 PM PDT 24
Peak memory 207604 kb
Host smart-dc4d952a-53c0-49db-ae26-4938e154ccaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
52423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1399552423
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1681112631
Short name T2180
Test name
Test status
Simulation time 1933484887 ps
CPU time 14.75 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 217820 kb
Host smart-4e1c836f-47a1-473a-b4e8-36bd8564b171
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1681112631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1681112631
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.390721201
Short name T1089
Test name
Test status
Simulation time 159766551 ps
CPU time 0.9 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207536 kb
Host smart-3611c0f2-f92b-48a5-84ed-3e315b5e3366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
1201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.390721201
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3392378706
Short name T2386
Test name
Test status
Simulation time 187812874 ps
CPU time 0.94 seconds
Started Aug 08 06:13:15 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207548 kb
Host smart-f0b9b24e-bc03-4bc6-8707-a8fbf7ed23d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33923
78706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3392378706
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1617186671
Short name T2974
Test name
Test status
Simulation time 690926976 ps
CPU time 1.94 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:16 PM PDT 24
Peak memory 207504 kb
Host smart-69f5dcc1-5cda-410d-9bfd-9e15a9aba947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171
86671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1617186671
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.162652932
Short name T2439
Test name
Test status
Simulation time 2179578342 ps
CPU time 21.55 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 216148 kb
Host smart-8e1560cf-fd8c-4078-bfb3-da13ceb1218c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265
2932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.162652932
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2983208723
Short name T89
Test name
Test status
Simulation time 7323621755 ps
CPU time 102.35 seconds
Started Aug 08 06:13:11 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 216044 kb
Host smart-d097b0bd-3a66-4830-83d3-3f35c5eb6ae6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983208723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2983208723
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.3830910911
Short name T3163
Test name
Test status
Simulation time 2019344457 ps
CPU time 16.41 seconds
Started Aug 08 06:13:03 PM PDT 24
Finished Aug 08 06:13:19 PM PDT 24
Peak memory 207784 kb
Host smart-811559f8-24af-4772-a2c9-29b273defd77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830910911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.3830910911
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.1491567713
Short name T1509
Test name
Test status
Simulation time 562979314 ps
CPU time 1.82 seconds
Started Aug 08 06:13:16 PM PDT 24
Finished Aug 08 06:13:18 PM PDT 24
Peak memory 207516 kb
Host smart-babb2944-5082-4c77-a03f-ef90245ea056
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491567713 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.1491567713
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.356643296
Short name T1696
Test name
Test status
Simulation time 90348126 ps
CPU time 0.71 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207604 kb
Host smart-0291fc65-3546-4127-b349-f81cd675eba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=356643296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.356643296
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2060086353
Short name T2616
Test name
Test status
Simulation time 4982918615 ps
CPU time 7.81 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:22 PM PDT 24
Peak memory 216028 kb
Host smart-8eff3cf0-7b9e-4550-8864-57bdd24f6f6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060086353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.2060086353
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3202875375
Short name T2210
Test name
Test status
Simulation time 14501855301 ps
CPU time 15.79 seconds
Started Aug 08 06:13:12 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 216016 kb
Host smart-2a61c9be-8684-47ea-9cd0-fb27977ec1ba
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202875375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3202875375
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2715748604
Short name T3413
Test name
Test status
Simulation time 24931880867 ps
CPU time 28.84 seconds
Started Aug 08 06:13:13 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 216276 kb
Host smart-cd22c139-02ce-4a2e-8f65-8c0d1149034a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715748604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.2715748604
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.991795662
Short name T1731
Test name
Test status
Simulation time 186001534 ps
CPU time 0.94 seconds
Started Aug 08 06:13:14 PM PDT 24
Finished Aug 08 06:13:15 PM PDT 24
Peak memory 207588 kb
Host smart-4bbee369-18dc-4d36-b6ef-b9d0d1062188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99179
5662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.991795662
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2716381869
Short name T3354
Test name
Test status
Simulation time 174034842 ps
CPU time 0.91 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207596 kb
Host smart-1ac25f49-026d-49b2-a528-1a634335355d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27163
81869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2716381869
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3885202204
Short name T2498
Test name
Test status
Simulation time 1157792238 ps
CPU time 3.14 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207696 kb
Host smart-7f95cff4-710a-4a6d-af1c-7b12f1894080
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3885202204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3885202204
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2589848031
Short name T499
Test name
Test status
Simulation time 40298086162 ps
CPU time 61.58 seconds
Started Aug 08 06:13:31 PM PDT 24
Finished Aug 08 06:14:33 PM PDT 24
Peak memory 207880 kb
Host smart-8e6d0e63-7041-41a0-ae93-1675c8d6c6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25898
48031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2589848031
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.2493970767
Short name T3407
Test name
Test status
Simulation time 2207138147 ps
CPU time 14.56 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207860 kb
Host smart-497197f6-30c4-4c60-a6c3-1143797c953f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493970767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.2493970767
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.4049149228
Short name T3138
Test name
Test status
Simulation time 921358871 ps
CPU time 2.07 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207568 kb
Host smart-18043316-157a-495c-9972-001704e71504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
49228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.4049149228
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1502779308
Short name T2669
Test name
Test status
Simulation time 160464562 ps
CPU time 0.9 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207540 kb
Host smart-651ac4b2-a13b-4467-8f49-4ffc60bc7629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15027
79308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1502779308
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3930146129
Short name T1414
Test name
Test status
Simulation time 63151871 ps
CPU time 0.73 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207560 kb
Host smart-c26d9a28-4844-4fff-9cc4-c6120dbd8bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
46129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3930146129
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3193287084
Short name T2975
Test name
Test status
Simulation time 811308033 ps
CPU time 2.55 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:32 PM PDT 24
Peak memory 207644 kb
Host smart-d5ea32f0-f062-4680-b904-828a11d11c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
87084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3193287084
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1181025861
Short name T2376
Test name
Test status
Simulation time 239230978 ps
CPU time 2.24 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207680 kb
Host smart-1c0cfb08-2137-4303-851f-54974df295f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11810
25861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1181025861
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3533315673
Short name T2765
Test name
Test status
Simulation time 83215177874 ps
CPU time 131.59 seconds
Started Aug 08 06:13:26 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207860 kb
Host smart-d0fa2647-2e26-44fe-9e0f-e20c6bfa5524
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3533315673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3533315673
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2859176012
Short name T2997
Test name
Test status
Simulation time 109046231294 ps
CPU time 174.52 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 207844 kb
Host smart-f3dd2e30-abee-4d8e-a173-b53b647e0523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859176012 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2859176012
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.163674305
Short name T3587
Test name
Test status
Simulation time 109075186819 ps
CPU time 165.64 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:16:15 PM PDT 24
Peak memory 207844 kb
Host smart-8ee6fbe0-02d4-49b5-bd01-52abab438641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163674305 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.163674305
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.295013286
Short name T1422
Test name
Test status
Simulation time 84158147820 ps
CPU time 123.04 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:15:31 PM PDT 24
Peak memory 207828 kb
Host smart-c38ed081-aa12-4fca-a531-a7a557ced2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.295013286
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3102587648
Short name T2480
Test name
Test status
Simulation time 214940627 ps
CPU time 1.18 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 215916 kb
Host smart-19b3ba9c-25df-4b8c-a959-fece7ceaf21e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3102587648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3102587648
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3436266402
Short name T529
Test name
Test status
Simulation time 143756729 ps
CPU time 0.85 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207440 kb
Host smart-fab4ec96-eacf-45d0-8007-1f712507081f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362
66402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3436266402
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1260432301
Short name T2834
Test name
Test status
Simulation time 250005448 ps
CPU time 1.01 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207520 kb
Host smart-01c91b21-11f5-409d-a92f-f403057ad3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12604
32301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1260432301
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1087500964
Short name T1139
Test name
Test status
Simulation time 8031215690 ps
CPU time 108.24 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:15:18 PM PDT 24
Peak memory 207808 kb
Host smart-2368daff-08c3-42d9-8c08-35b8e4154f9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1087500964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1087500964
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.4143658649
Short name T3153
Test name
Test status
Simulation time 231899107 ps
CPU time 1.1 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207540 kb
Host smart-8290ed22-4a7c-4a42-aa92-ff0ce56a6a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41436
58649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.4143658649
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1543941587
Short name T1591
Test name
Test status
Simulation time 9236376278 ps
CPU time 14.44 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207824 kb
Host smart-05077c4b-32c0-4508-a676-e0cbd1410d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15439
41587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1543941587
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1473426881
Short name T2160
Test name
Test status
Simulation time 3692852352 ps
CPU time 5.33 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 207720 kb
Host smart-939573e4-e834-4dda-b56d-7d255e81919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14734
26881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1473426881
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.782751185
Short name T3334
Test name
Test status
Simulation time 4787305795 ps
CPU time 134.19 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 216120 kb
Host smart-aa6cb285-8067-4384-85ed-aa30a661113b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78275
1185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.782751185
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.88585196
Short name T548
Test name
Test status
Simulation time 1518384021 ps
CPU time 42.14 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:14:12 PM PDT 24
Peak memory 215912 kb
Host smart-d7cf9ecf-3241-4fd8-a582-18bd084f469d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=88585196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.88585196
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1213938128
Short name T2631
Test name
Test status
Simulation time 264406188 ps
CPU time 1.06 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207436 kb
Host smart-53e44724-1714-4531-909c-66bc776820bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1213938128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1213938128
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2662466468
Short name T776
Test name
Test status
Simulation time 216149789 ps
CPU time 0.94 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207536 kb
Host smart-a772bdd6-4ff4-4412-87e3-7cd2714aa265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
66468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2662466468
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.1929923774
Short name T2404
Test name
Test status
Simulation time 2712762198 ps
CPU time 78.33 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 217568 kb
Host smart-61c8968c-18bf-4e5b-929b-17769a62ba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
23774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.1929923774
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.559000555
Short name T2514
Test name
Test status
Simulation time 3072130162 ps
CPU time 25.18 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 216060 kb
Host smart-d4ff3898-bb15-4cbf-be36-5b9ca4ca36d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=559000555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.559000555
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2999685646
Short name T3360
Test name
Test status
Simulation time 2267439060 ps
CPU time 60.52 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 216160 kb
Host smart-9ee59e38-91f9-4786-a607-a1f69b08733d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2999685646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2999685646
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.4151873091
Short name T22
Test name
Test status
Simulation time 151423095 ps
CPU time 0.84 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207592 kb
Host smart-a08aaac5-ac37-49ac-9f19-60e1a25bb96d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4151873091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.4151873091
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1230983764
Short name T1811
Test name
Test status
Simulation time 146478250 ps
CPU time 0.9 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207564 kb
Host smart-a1197adb-f5eb-4ee1-94ea-16209028581b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12309
83764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1230983764
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.155787842
Short name T2151
Test name
Test status
Simulation time 189135600 ps
CPU time 0.94 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207524 kb
Host smart-986021df-3e54-4d64-b360-5ad547163f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578
7842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.155787842
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.74800601
Short name T1329
Test name
Test status
Simulation time 192496469 ps
CPU time 0.9 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207560 kb
Host smart-84532946-2d26-48a1-91e6-c722476909fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74800
601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.74800601
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1481900706
Short name T3528
Test name
Test status
Simulation time 204358491 ps
CPU time 0.92 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207560 kb
Host smart-4579b51e-1a7e-41de-a464-b0341cf74973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
00706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1481900706
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.613454125
Short name T1730
Test name
Test status
Simulation time 153297776 ps
CPU time 0.84 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207588 kb
Host smart-869121b8-a2a6-4285-a848-2ef62c0d54ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61345
4125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.613454125
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4147558528
Short name T2287
Test name
Test status
Simulation time 255267274 ps
CPU time 1.09 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207660 kb
Host smart-7d0d9f4b-40f1-4125-89e4-a9d9b898ba65
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4147558528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4147558528
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2289368505
Short name T2294
Test name
Test status
Simulation time 282270366 ps
CPU time 1.05 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207432 kb
Host smart-26824e97-d50a-451b-9a8b-eeb0e2c9d7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
68505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2289368505
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1515991157
Short name T3159
Test name
Test status
Simulation time 148218684 ps
CPU time 0.92 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207480 kb
Host smart-23566f9e-2c8d-487c-bb07-5d16f1df3565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
91157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1515991157
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.205532566
Short name T28
Test name
Test status
Simulation time 26290749 ps
CPU time 0.67 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207540 kb
Host smart-d060518e-d340-43b2-94b1-69eea6bee440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20553
2566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.205532566
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4107433526
Short name T293
Test name
Test status
Simulation time 11277704694 ps
CPU time 28.22 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 216108 kb
Host smart-76d09d74-0e0f-430e-a9d3-4efa1a0d619e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41074
33526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4107433526
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.65676471
Short name T1661
Test name
Test status
Simulation time 154445711 ps
CPU time 0.89 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207528 kb
Host smart-535a07db-48c7-46ef-80db-0b87574833f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65676
471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.65676471
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.583136062
Short name T2973
Test name
Test status
Simulation time 188154120 ps
CPU time 0.92 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207544 kb
Host smart-892bafef-5789-448d-b835-d05091aa2023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58313
6062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.583136062
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3945019937
Short name T1202
Test name
Test status
Simulation time 7634867576 ps
CPU time 201.13 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:16:50 PM PDT 24
Peak memory 218340 kb
Host smart-75465f75-811f-49be-9888-46f924968f7a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945019937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3945019937
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3982295668
Short name T2195
Test name
Test status
Simulation time 9789086588 ps
CPU time 172.14 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:16:21 PM PDT 24
Peak memory 224340 kb
Host smart-22d27032-bb2a-4491-bf65-5e3b540a7830
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982295668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3982295668
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3108164931
Short name T3489
Test name
Test status
Simulation time 173628873 ps
CPU time 0.9 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207492 kb
Host smart-a114c1cf-aaf8-4cbc-953a-dd5a8f915d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
64931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3108164931
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.635752196
Short name T1218
Test name
Test status
Simulation time 170555621 ps
CPU time 0.85 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207588 kb
Host smart-3a791ab6-5214-436d-bb49-75197c307e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63575
2196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.635752196
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.380011175
Short name T3296
Test name
Test status
Simulation time 20167382313 ps
CPU time 27.67 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 207632 kb
Host smart-2ae0099b-a6c0-4124-af0d-135186611a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
1175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.380011175
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.505425833
Short name T2266
Test name
Test status
Simulation time 182164323 ps
CPU time 0.89 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207576 kb
Host smart-afc42cd7-4de7-461c-ab37-13c3bc91829b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50542
5833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.505425833
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.1005376180
Short name T3455
Test name
Test status
Simulation time 253928818 ps
CPU time 1.15 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207524 kb
Host smart-5668ba58-f9e5-4128-8f77-00e8ba947fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053
76180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.1005376180
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1448847654
Short name T3179
Test name
Test status
Simulation time 267034462 ps
CPU time 0.99 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207640 kb
Host smart-4cc07c85-5c09-4140-9b9b-eb3549e35032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
47654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1448847654
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3089317164
Short name T230
Test name
Test status
Simulation time 1127317509 ps
CPU time 1.94 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 224476 kb
Host smart-fb1cbc73-59c7-477f-b048-f917afaf4141
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3089317164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3089317164
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.216310655
Short name T3596
Test name
Test status
Simulation time 412714985 ps
CPU time 1.46 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207544 kb
Host smart-31b8ec50-c05d-4598-94f1-0513f8baf292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
0655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.216310655
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.392340489
Short name T1587
Test name
Test status
Simulation time 230164022 ps
CPU time 0.97 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207540 kb
Host smart-bbcb949b-a2b8-4979-9078-fd8dbac5288d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
0489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.392340489
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.189759574
Short name T777
Test name
Test status
Simulation time 150186875 ps
CPU time 0.87 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207584 kb
Host smart-b537a4b6-58fe-4185-9ecf-5f9c9e684c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.189759574
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.858278358
Short name T2668
Test name
Test status
Simulation time 178372729 ps
CPU time 0.92 seconds
Started Aug 08 06:13:27 PM PDT 24
Finished Aug 08 06:13:28 PM PDT 24
Peak memory 207612 kb
Host smart-3bb33752-a1ee-41d0-8a64-95f845dc67fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85827
8358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.858278358
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.63876759
Short name T1296
Test name
Test status
Simulation time 239292965 ps
CPU time 1.15 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:13:30 PM PDT 24
Peak memory 207508 kb
Host smart-b0872887-4e19-4461-a782-2d3d624ccbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63876
759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.63876759
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.364775705
Short name T1241
Test name
Test status
Simulation time 1810577882 ps
CPU time 50.47 seconds
Started Aug 08 06:13:29 PM PDT 24
Finished Aug 08 06:14:20 PM PDT 24
Peak memory 217464 kb
Host smart-c19da7b6-adf7-4a1d-8822-9cc03e635b28
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=364775705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.364775705
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2954030451
Short name T2441
Test name
Test status
Simulation time 181342202 ps
CPU time 0.88 seconds
Started Aug 08 06:13:28 PM PDT 24
Finished Aug 08 06:13:29 PM PDT 24
Peak memory 207564 kb
Host smart-f153fd73-8709-4292-9fa9-d2e0f56856a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
30451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2954030451
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1154973819
Short name T1910
Test name
Test status
Simulation time 198581301 ps
CPU time 0.93 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:31 PM PDT 24
Peak memory 207584 kb
Host smart-349441f8-39cb-4403-8f31-305db7f52291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11549
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1154973819
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1147098566
Short name T2076
Test name
Test status
Simulation time 1276008820 ps
CPU time 2.8 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207688 kb
Host smart-fd3b36e7-8962-4a2b-8954-62873ad10949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11470
98566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1147098566
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4183648002
Short name T1433
Test name
Test status
Simulation time 2605874664 ps
CPU time 18.92 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:13:49 PM PDT 24
Peak memory 224140 kb
Host smart-13e07a53-16f9-4059-99f9-c4d3eee244e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41836
48002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4183648002
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.2016947069
Short name T964
Test name
Test status
Simulation time 5664945949 ps
CPU time 38.33 seconds
Started Aug 08 06:13:30 PM PDT 24
Finished Aug 08 06:14:09 PM PDT 24
Peak memory 207812 kb
Host smart-1c035576-71ca-4fa4-a43d-d96132053fbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016947069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.2016947069
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.3192314174
Short name T550
Test name
Test status
Simulation time 643691557 ps
CPU time 1.77 seconds
Started Aug 08 06:13:31 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207812 kb
Host smart-ac1c6624-910e-4557-a0ba-f64aa5057ab5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192314174 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.3192314174
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.1980400305
Short name T1400
Test name
Test status
Simulation time 101631317 ps
CPU time 0.72 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 207568 kb
Host smart-99a061a6-d551-484d-85c4-da314d3ce064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1980400305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1980400305
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2413758112
Short name T3571
Test name
Test status
Simulation time 5860122088 ps
CPU time 7.83 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:10 PM PDT 24
Peak memory 215988 kb
Host smart-50f92d4d-db7c-4469-9d82-158e53e962a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413758112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.2413758112
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1368084912
Short name T3005
Test name
Test status
Simulation time 15819026790 ps
CPU time 18.94 seconds
Started Aug 08 06:15:05 PM PDT 24
Finished Aug 08 06:15:24 PM PDT 24
Peak memory 215980 kb
Host smart-92861f90-7348-4a92-ad0b-7e4620d13db2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368084912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1368084912
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1633947555
Short name T1813
Test name
Test status
Simulation time 24542498526 ps
CPU time 29.74 seconds
Started Aug 08 06:15:04 PM PDT 24
Finished Aug 08 06:15:33 PM PDT 24
Peak memory 215992 kb
Host smart-ab21fa6c-a0af-4b6c-b329-2e9a3c4af779
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633947555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.1633947555
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.58699543
Short name T1497
Test name
Test status
Simulation time 193286881 ps
CPU time 0.92 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:15:04 PM PDT 24
Peak memory 207524 kb
Host smart-86145dd7-8313-489a-91b0-977fc301c453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58699
543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.58699543
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1056151623
Short name T912
Test name
Test status
Simulation time 149438115 ps
CPU time 0.81 seconds
Started Aug 08 06:15:04 PM PDT 24
Finished Aug 08 06:15:05 PM PDT 24
Peak memory 207532 kb
Host smart-88a2e279-5f9a-48d9-bfdf-6c5940f5b8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
51623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1056151623
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.4237779783
Short name T3003
Test name
Test status
Simulation time 182078454 ps
CPU time 0.88 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207560 kb
Host smart-2e2a8d4c-ab6f-4a12-9fef-948db0b2f6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377
79783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.4237779783
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3969862345
Short name T3122
Test name
Test status
Simulation time 301861301 ps
CPU time 1.06 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207596 kb
Host smart-6f0353ce-a8cd-4fcb-8820-ae7feb25739c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3969862345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3969862345
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.157733205
Short name T1979
Test name
Test status
Simulation time 49404325412 ps
CPU time 88.82 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:17:10 PM PDT 24
Peak memory 207888 kb
Host smart-790e7ef9-830b-4231-b68d-264daf3524c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.157733205
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3972550739
Short name T2214
Test name
Test status
Simulation time 2064294815 ps
CPU time 17.04 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207804 kb
Host smart-9eb95b74-42bf-4837-844e-e908165be175
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972550739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3972550739
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3340658460
Short name T450
Test name
Test status
Simulation time 419323485 ps
CPU time 1.48 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207564 kb
Host smart-ca710827-fab0-4b76-a407-e302f942d2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33406
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3340658460
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3147231403
Short name T1217
Test name
Test status
Simulation time 150504144 ps
CPU time 0.85 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 207556 kb
Host smart-34206157-1d3e-4a71-a2b1-7db00d85210e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
31403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3147231403
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3241507689
Short name T3295
Test name
Test status
Simulation time 58284240 ps
CPU time 0.69 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 207464 kb
Host smart-389e030a-f6b0-4c1a-9ecc-a526bc3551ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
07689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3241507689
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2740195901
Short name T708
Test name
Test status
Simulation time 817119057 ps
CPU time 2.26 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 207756 kb
Host smart-cba72b2b-eb06-4a81-8e22-718fc7ed4ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
95901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2740195901
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.953615640
Short name T2112
Test name
Test status
Simulation time 375816896 ps
CPU time 1.35 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207536 kb
Host smart-cbcc0db7-a865-48b7-bb61-eb656107b966
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=953615640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.953615640
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2682119701
Short name T2917
Test name
Test status
Simulation time 196127387 ps
CPU time 2.28 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207788 kb
Host smart-dcd406c6-7c8d-40f2-8f6f-2117041fad98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821
19701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2682119701
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3715443569
Short name T1021
Test name
Test status
Simulation time 208619681 ps
CPU time 1.07 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 216000 kb
Host smart-1a3ec596-ca06-4b74-84cb-4b50e2184224
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3715443569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3715443569
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.811078469
Short name T2912
Test name
Test status
Simulation time 140202844 ps
CPU time 0.81 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 207480 kb
Host smart-f2e7c1d7-64f4-466d-94b7-b38207bf0d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81107
8469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.811078469
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2739533036
Short name T980
Test name
Test status
Simulation time 186329462 ps
CPU time 0.94 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207576 kb
Host smart-0a665ad6-6b87-41d1-8520-54daeaae0391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27395
33036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2739533036
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2058939657
Short name T2360
Test name
Test status
Simulation time 3711573730 ps
CPU time 110.39 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 216156 kb
Host smart-b5a6035e-7579-4f27-b9b6-64e60f93ce7c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2058939657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2058939657
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.2912777517
Short name T2687
Test name
Test status
Simulation time 4038088630 ps
CPU time 25.81 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 207884 kb
Host smart-c23990b9-dd51-43c7-b5d1-b2d11b032090
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2912777517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.2912777517
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3678636185
Short name T2534
Test name
Test status
Simulation time 241079803 ps
CPU time 0.97 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207520 kb
Host smart-02fbbfed-e244-4a4c-8edd-e77a36a7d0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786
36185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3678636185
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3930739221
Short name T2639
Test name
Test status
Simulation time 25805508122 ps
CPU time 38.65 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 216164 kb
Host smart-a38ce063-ad78-4e87-8633-ec726152252b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
39221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3930739221
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3167862635
Short name T1938
Test name
Test status
Simulation time 8438667514 ps
CPU time 11.4 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207860 kb
Host smart-30c72540-8aef-4475-bb1c-0d48c89249fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
62635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3167862635
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3015191947
Short name T191
Test name
Test status
Simulation time 4679402307 ps
CPU time 37.81 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:16:19 PM PDT 24
Peak memory 218660 kb
Host smart-e01d0317-8f09-4f4b-8c09-fc9ba63d41a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30151
91947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3015191947
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1452626316
Short name T1803
Test name
Test status
Simulation time 3320825906 ps
CPU time 32.5 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:16:10 PM PDT 24
Peak memory 217900 kb
Host smart-644635ad-4a66-4dbb-b9e6-d5f41008a1ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1452626316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1452626316
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1539289474
Short name T1724
Test name
Test status
Simulation time 239044605 ps
CPU time 1.04 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207568 kb
Host smart-5f5cbe10-d423-4bbb-bc2f-ab96695887d9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1539289474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1539289474
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2246459051
Short name T1612
Test name
Test status
Simulation time 189777069 ps
CPU time 0.96 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207588 kb
Host smart-826a5c7e-5fa3-4051-b2bd-922a0037f735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464
59051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2246459051
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.3236455149
Short name T235
Test name
Test status
Simulation time 2803056181 ps
CPU time 27.46 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:16:09 PM PDT 24
Peak memory 224292 kb
Host smart-ebe45434-b9bb-49f9-8fa0-5b77467516fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364
55149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.3236455149
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.664711189
Short name T2523
Test name
Test status
Simulation time 3237016111 ps
CPU time 27.6 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 218696 kb
Host smart-10221444-a786-4c8a-9342-2c582ad7d7a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=664711189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.664711189
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1254457015
Short name T2206
Test name
Test status
Simulation time 156981291 ps
CPU time 0.91 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207620 kb
Host smart-5a51e0c0-527d-49b0-891d-9ed514477c7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254457015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1254457015
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2947856855
Short name T2921
Test name
Test status
Simulation time 176911659 ps
CPU time 0.89 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207596 kb
Host smart-87ea5090-4ac5-4d9a-b157-988c1ab35cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
56855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2947856855
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3746284708
Short name T156
Test name
Test status
Simulation time 238992176 ps
CPU time 1.03 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207592 kb
Host smart-f35dca4b-1737-46ec-bbc9-c2f90081aa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37462
84708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3746284708
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3400521648
Short name T1035
Test name
Test status
Simulation time 171193661 ps
CPU time 0.95 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 207604 kb
Host smart-465bc804-80ba-4d46-9c11-aa911eba1463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34005
21648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3400521648
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2937732394
Short name T652
Test name
Test status
Simulation time 190457999 ps
CPU time 0.9 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207592 kb
Host smart-c2ecde51-2a54-48dc-b0f6-8ceeaa65b4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29377
32394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2937732394
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2522716091
Short name T768
Test name
Test status
Simulation time 167922080 ps
CPU time 0.91 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 207560 kb
Host smart-c2b5f57a-b54d-4a75-a00c-ef9d1ba44ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25227
16091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2522716091
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1315538018
Short name T1531
Test name
Test status
Simulation time 160430665 ps
CPU time 0.9 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207544 kb
Host smart-d97070ad-e64d-4991-88b2-23c0a222e19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13155
38018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1315538018
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1426054434
Short name T3597
Test name
Test status
Simulation time 224483166 ps
CPU time 1.04 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207620 kb
Host smart-8eed893a-744b-4d49-ac3a-ed66dbf0c9b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1426054434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1426054434
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2334428608
Short name T41
Test name
Test status
Simulation time 43427870 ps
CPU time 0.72 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207532 kb
Host smart-f3e28abc-c936-4873-bede-50c7cca0b0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
28608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2334428608
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1408582328
Short name T1303
Test name
Test status
Simulation time 10356233337 ps
CPU time 25.25 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 220308 kb
Host smart-37df86ce-6587-4982-b3a7-603097c881f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
82328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1408582328
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4008882313
Short name T1593
Test name
Test status
Simulation time 177386176 ps
CPU time 0.93 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207780 kb
Host smart-91b4eade-68a5-48f7-9c65-ac12822543f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40088
82313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4008882313
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.549376032
Short name T236
Test name
Test status
Simulation time 239954211 ps
CPU time 0.99 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207556 kb
Host smart-b0084a78-4554-4d94-a981-244737571b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54937
6032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.549376032
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.846878613
Short name T2885
Test name
Test status
Simulation time 223646542 ps
CPU time 0.93 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207648 kb
Host smart-59c9b3b0-f370-4a32-a9d5-a612b3e07b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84687
8613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.846878613
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3499440774
Short name T3217
Test name
Test status
Simulation time 196494375 ps
CPU time 0.9 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207620 kb
Host smart-c2acb498-f721-4b7f-8050-5e54fc94466d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34994
40774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3499440774
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.77334667
Short name T1557
Test name
Test status
Simulation time 20195580823 ps
CPU time 25.44 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:16:10 PM PDT 24
Peak memory 207620 kb
Host smart-d507d246-f31d-4790-be23-15ebee545df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77334
667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.77334667
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1634173548
Short name T1728
Test name
Test status
Simulation time 183643646 ps
CPU time 0.88 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207560 kb
Host smart-a846c186-be72-4685-9fa2-9d2e9e5dcc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
73548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1634173548
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.3592426590
Short name T949
Test name
Test status
Simulation time 284569721 ps
CPU time 1.15 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207548 kb
Host smart-a66f13ef-89f3-4d55-8c24-ed454c0dcc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
26590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.3592426590
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.277830934
Short name T2989
Test name
Test status
Simulation time 160178219 ps
CPU time 0.85 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207532 kb
Host smart-e512a1cb-f55d-44ff-b7ae-440123580b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
0934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.277830934
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2777158417
Short name T1482
Test name
Test status
Simulation time 148900282 ps
CPU time 0.86 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 207600 kb
Host smart-96d12087-5d89-42c6-b2cc-0e9e687288f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
58417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2777158417
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2808970873
Short name T526
Test name
Test status
Simulation time 244620814 ps
CPU time 1.04 seconds
Started Aug 08 06:15:37 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 207548 kb
Host smart-7f018d0a-b54c-4eb9-accd-94cfeaf93809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28089
70873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2808970873
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3402718264
Short name T3133
Test name
Test status
Simulation time 3018537526 ps
CPU time 29.79 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:16:15 PM PDT 24
Peak memory 224252 kb
Host smart-adb72fb7-1e12-4142-bb7f-3be819ca0cfa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3402718264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3402718264
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.101370661
Short name T2678
Test name
Test status
Simulation time 180473405 ps
CPU time 0.92 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207564 kb
Host smart-7851f657-0025-4d51-8eb6-b9df4bf78963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
0661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.101370661
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3131100768
Short name T724
Test name
Test status
Simulation time 175661357 ps
CPU time 0.87 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207784 kb
Host smart-72789f93-4cf7-4886-96a9-8058988244f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31311
00768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3131100768
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1385455805
Short name T2540
Test name
Test status
Simulation time 443849034 ps
CPU time 1.37 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207536 kb
Host smart-b0ca79ce-e15a-4bde-8e13-ddebac5a74b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
55805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1385455805
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.811411612
Short name T2218
Test name
Test status
Simulation time 2730466934 ps
CPU time 78.38 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 217552 kb
Host smart-7848fd8e-0d65-40cb-91fb-c0f2d5eae9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81141
1612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.811411612
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.70083023
Short name T2541
Test name
Test status
Simulation time 1120351701 ps
CPU time 25.66 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207748 kb
Host smart-f97217eb-d5e5-4eaf-8a67-b3852bbadf5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70083023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_host_
handshake.70083023
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.698172142
Short name T2752
Test name
Test status
Simulation time 644212438 ps
CPU time 1.67 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 207612 kb
Host smart-4460e1c6-7837-472e-baf2-b767e9f05ec6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698172142 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.698172142
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.3209029721
Short name T387
Test name
Test status
Simulation time 720183682 ps
CPU time 1.72 seconds
Started Aug 08 06:21:14 PM PDT 24
Finished Aug 08 06:21:16 PM PDT 24
Peak memory 207540 kb
Host smart-c493bb89-eb30-46f2-bdf6-56b7b0b1a717
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3209029721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.3209029721
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.60411450
Short name T1801
Test name
Test status
Simulation time 403672404 ps
CPU time 1.34 seconds
Started Aug 08 06:21:18 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207512 kb
Host smart-669bf921-fd6b-47d9-aaf0-d3404f861e1f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60411450 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.60411450
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.1141095881
Short name T409
Test name
Test status
Simulation time 278896775 ps
CPU time 1.06 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207620 kb
Host smart-2474c2db-6f7a-4334-84b7-3bdd04505eb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1141095881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.1141095881
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.1972466905
Short name T810
Test name
Test status
Simulation time 565549602 ps
CPU time 1.83 seconds
Started Aug 08 06:21:34 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 207572 kb
Host smart-a18fbe5d-e178-420a-81b3-112530b98553
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972466905 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.1972466905
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.1899632591
Short name T553
Test name
Test status
Simulation time 644434368 ps
CPU time 1.76 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 207496 kb
Host smart-65c22c2a-c43a-4114-9167-57f633e970f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899632591 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.1899632591
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.1535696557
Short name T407
Test name
Test status
Simulation time 528309201 ps
CPU time 1.34 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207536 kb
Host smart-ad0ff2b1-15ad-47a0-b5aa-40e21cc46cb6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1535696557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1535696557
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.540358647
Short name T869
Test name
Test status
Simulation time 483485614 ps
CPU time 1.48 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207552 kb
Host smart-f4f583a7-3375-49fc-8c0a-77cc7d9c7c56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540358647 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.540358647
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.1134478027
Short name T360
Test name
Test status
Simulation time 911589843 ps
CPU time 1.9 seconds
Started Aug 08 06:21:38 PM PDT 24
Finished Aug 08 06:21:40 PM PDT 24
Peak memory 207540 kb
Host smart-255062c8-f191-4a2b-a82e-11126818b87a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1134478027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.1134478027
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.2413012864
Short name T833
Test name
Test status
Simulation time 548616779 ps
CPU time 1.59 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207600 kb
Host smart-b599a442-f066-475f-9733-586aae6c9313
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413012864 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.2413012864
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.1602270691
Short name T2879
Test name
Test status
Simulation time 496810221 ps
CPU time 1.4 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207520 kb
Host smart-e2355c1f-d542-4ce0-bd1c-523969c9ec49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1602270691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.1602270691
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.533598801
Short name T2513
Test name
Test status
Simulation time 642978920 ps
CPU time 1.72 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207552 kb
Host smart-28ec6306-293d-484b-be12-0ec0d711d709
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533598801 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.533598801
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.1995175818
Short name T1870
Test name
Test status
Simulation time 270507933 ps
CPU time 1.04 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207556 kb
Host smart-7575b5fe-b6d7-464a-a2f4-4345b578c3ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1995175818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1995175818
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.3676356785
Short name T2526
Test name
Test status
Simulation time 511792607 ps
CPU time 1.53 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207576 kb
Host smart-5fbeadfc-5d5b-4e78-85f5-69ae0fad1d3d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676356785 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.3676356785
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.3097949311
Short name T1360
Test name
Test status
Simulation time 528015843 ps
CPU time 1.44 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207516 kb
Host smart-8113ed2e-1a87-4302-a905-934f4e0c971d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097949311 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.3097949311
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.1926235251
Short name T492
Test name
Test status
Simulation time 230724568 ps
CPU time 1 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207396 kb
Host smart-27dcf309-91b2-4915-a143-7d88e246ac12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1926235251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.1926235251
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.1982589117
Short name T2871
Test name
Test status
Simulation time 517061491 ps
CPU time 1.52 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207492 kb
Host smart-bd9dedd3-136e-4017-91fa-4bb8cb916594
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982589117 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.1982589117
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3639390206
Short name T209
Test name
Test status
Simulation time 9790729168 ps
CPU time 13.31 seconds
Started Aug 08 06:15:39 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207836 kb
Host smart-51666745-9791-4a47-86b7-23f0a63752df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639390206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.3639390206
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.604570829
Short name T3559
Test name
Test status
Simulation time 19821326922 ps
CPU time 22.51 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207860 kb
Host smart-d454e90f-b046-49d4-8660-8f25f1a76b74
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=604570829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.604570829
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1328468851
Short name T1893
Test name
Test status
Simulation time 31291321546 ps
CPU time 43.72 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207888 kb
Host smart-e2a3d650-d73f-4dc9-97fa-277b8735b7c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328468851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.1328468851
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2485565735
Short name T3070
Test name
Test status
Simulation time 196950212 ps
CPU time 0.99 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 207584 kb
Host smart-04972a5a-9aa3-4b5b-b0b9-d7ce5663a529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
65735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2485565735
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2541675878
Short name T2520
Test name
Test status
Simulation time 159430496 ps
CPU time 0.85 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 207564 kb
Host smart-d6882b27-6a78-4753-be5a-78e40ab79225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25416
75878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2541675878
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.703728734
Short name T2685
Test name
Test status
Simulation time 545468317 ps
CPU time 1.93 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207584 kb
Host smart-dc16879e-83b4-41aa-8893-2aae07dffa00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70372
8734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.703728734
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3757078463
Short name T1188
Test name
Test status
Simulation time 1026086936 ps
CPU time 2.71 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207748 kb
Host smart-b7f3eebf-c287-4838-af0a-666e06014a06
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3757078463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3757078463
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3937559618
Short name T502
Test name
Test status
Simulation time 17584376637 ps
CPU time 29.91 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 207844 kb
Host smart-3977b6e6-9175-4d2b-a6d3-135761fcec12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375
59618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3937559618
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.4190460394
Short name T813
Test name
Test status
Simulation time 2205986877 ps
CPU time 13.99 seconds
Started Aug 08 06:15:38 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207812 kb
Host smart-e27f0ed8-9c04-4ca1-be0c-ea1b1d0658fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190460394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.4190460394
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3314915681
Short name T3513
Test name
Test status
Simulation time 814026425 ps
CPU time 1.91 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207568 kb
Host smart-06082021-d404-445b-9e61-a68075fd0021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33149
15681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3314915681
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.227172456
Short name T1162
Test name
Test status
Simulation time 139797092 ps
CPU time 0.8 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207560 kb
Host smart-6bb1a719-090f-4775-9e16-15c06cbb3bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
2456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.227172456
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1033539067
Short name T2925
Test name
Test status
Simulation time 63257712 ps
CPU time 0.7 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207556 kb
Host smart-98e540f6-5204-4b16-816e-cba51d3972d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10335
39067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1033539067
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3841573348
Short name T1233
Test name
Test status
Simulation time 706918516 ps
CPU time 1.94 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207812 kb
Host smart-59ae7d47-4ab0-4eac-adf4-e3db42743761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38415
73348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3841573348
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3777900540
Short name T3158
Test name
Test status
Simulation time 361908074 ps
CPU time 2.35 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 207732 kb
Host smart-f6a80b41-218c-4e8b-a4e9-26785a1401a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
00540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3777900540
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.325650488
Short name T2069
Test name
Test status
Simulation time 227562999 ps
CPU time 1.21 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 216616 kb
Host smart-1083ae8c-5ee5-4710-97fb-c5313118686e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=325650488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.325650488
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3817823286
Short name T1465
Test name
Test status
Simulation time 154666195 ps
CPU time 0.82 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207544 kb
Host smart-282e1e4d-1967-4d46-a229-ce9140505397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
23286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3817823286
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2960033437
Short name T2598
Test name
Test status
Simulation time 160301928 ps
CPU time 0.84 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207588 kb
Host smart-b88076c0-ae50-4a7a-9d82-35481f0dafeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29600
33437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2960033437
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1529357873
Short name T3488
Test name
Test status
Simulation time 4359608406 ps
CPU time 36.36 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 218080 kb
Host smart-3eab0727-2ff7-486a-acd1-b02115fa2fa6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1529357873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1529357873
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2805807917
Short name T2820
Test name
Test status
Simulation time 10897513901 ps
CPU time 74.73 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207852 kb
Host smart-001cf485-f99c-4833-b5a0-f5e1b95e8264
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2805807917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2805807917
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.419320550
Short name T2387
Test name
Test status
Simulation time 208942043 ps
CPU time 0.99 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207644 kb
Host smart-6a79e453-68f9-4207-9b7a-819f1df80369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
0550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.419320550
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2479515748
Short name T1604
Test name
Test status
Simulation time 5489920746 ps
CPU time 8.19 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 217064 kb
Host smart-73c04037-86ed-4add-b76f-eb3594e5a668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
15748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2479515748
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.190844762
Short name T2162
Test name
Test status
Simulation time 3603128966 ps
CPU time 99.63 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:17:26 PM PDT 24
Peak memory 217528 kb
Host smart-0cae91df-1480-45e2-8532-683b2d4c818d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=190844762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.190844762
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1370775836
Short name T861
Test name
Test status
Simulation time 241546576 ps
CPU time 1.08 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 207592 kb
Host smart-89db32f4-4b22-4ba3-be68-7e45afdf2868
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1370775836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1370775836
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4260884381
Short name T540
Test name
Test status
Simulation time 191407765 ps
CPU time 0.96 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207572 kb
Host smart-2a98b6ea-93f4-4f09-a15c-fecb9380bb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
84381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4260884381
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.702101983
Short name T2257
Test name
Test status
Simulation time 2839457791 ps
CPU time 28.74 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 218112 kb
Host smart-d9228655-1eb5-49f3-a62c-87c1552d0a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70210
1983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.702101983
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3123862568
Short name T3264
Test name
Test status
Simulation time 1992294804 ps
CPU time 15.98 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:58 PM PDT 24
Peak memory 216092 kb
Host smart-8035850d-7af7-48b5-991e-1a9b1ee8e562
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3123862568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3123862568
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1162201359
Short name T2776
Test name
Test status
Simulation time 2123314516 ps
CPU time 15.99 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 216932 kb
Host smart-afac7289-94e7-497e-b65b-2322f6ef3cf5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1162201359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1162201359
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2504361346
Short name T1212
Test name
Test status
Simulation time 175213485 ps
CPU time 0.88 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207564 kb
Host smart-739f369a-19f4-4751-b37a-d27685467cc8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2504361346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2504361346
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4041022277
Short name T2867
Test name
Test status
Simulation time 141605148 ps
CPU time 0.84 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207616 kb
Host smart-2ea62cf5-2db3-4f68-b6cb-e1a0e26d6f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40410
22277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4041022277
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.211240334
Short name T575
Test name
Test status
Simulation time 155422524 ps
CPU time 0.86 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207560 kb
Host smart-d4555cbb-9ba2-43fa-bbee-eee95063ea64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.211240334
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1421269146
Short name T3304
Test name
Test status
Simulation time 182925182 ps
CPU time 0.93 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 207536 kb
Host smart-291d8793-9887-4168-ad10-ff23ac100879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14212
69146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1421269146
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2328702894
Short name T1186
Test name
Test status
Simulation time 213833829 ps
CPU time 0.91 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207568 kb
Host smart-3c9211ee-749c-4313-8e79-d7f74bb89a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
02894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2328702894
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1719517777
Short name T2115
Test name
Test status
Simulation time 152045349 ps
CPU time 0.86 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207564 kb
Host smart-5ac4ca53-b16c-48e2-a948-b03ec0696302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195
17777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1719517777
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1368285545
Short name T3430
Test name
Test status
Simulation time 223614753 ps
CPU time 1.02 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207516 kb
Host smart-60c5ab6f-553e-485f-9980-70a0d1603756
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1368285545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1368285545
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4243125083
Short name T2993
Test name
Test status
Simulation time 143682700 ps
CPU time 0.83 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207500 kb
Host smart-db9904c2-05f0-4533-b965-54b2a15ff3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42431
25083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4243125083
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.786782049
Short name T921
Test name
Test status
Simulation time 51385386 ps
CPU time 0.75 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 207516 kb
Host smart-bd7be196-77fe-4205-ba88-709dcf3edaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78678
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.786782049
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3605922150
Short name T2936
Test name
Test status
Simulation time 15115189963 ps
CPU time 39.11 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 216084 kb
Host smart-9c4a836c-769d-4290-8ad7-6e2441de4609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36059
22150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3605922150
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1846999052
Short name T3392
Test name
Test status
Simulation time 179771028 ps
CPU time 0.84 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207504 kb
Host smart-c4798bde-7b6a-46a8-a33c-f7634d18d21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
99052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1846999052
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.364039060
Short name T1081
Test name
Test status
Simulation time 214376040 ps
CPU time 1.07 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207340 kb
Host smart-0871dc92-a5ec-44ef-adfd-8ed98c56071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.364039060
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.180868692
Short name T780
Test name
Test status
Simulation time 242508297 ps
CPU time 1.03 seconds
Started Aug 08 06:15:41 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 207612 kb
Host smart-33633175-3f09-4653-9db2-1df955be07ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18086
8692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.180868692
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.674707391
Short name T2747
Test name
Test status
Simulation time 149635942 ps
CPU time 0.85 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207520 kb
Host smart-ce3e745d-a13d-4422-a494-3b5748204f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67470
7391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.674707391
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.1676315730
Short name T2940
Test name
Test status
Simulation time 20171125981 ps
CPU time 23.83 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:10 PM PDT 24
Peak memory 207596 kb
Host smart-a4a2d584-cda9-49c8-baf7-c6f584d13719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
15730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.1676315730
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2392838300
Short name T2509
Test name
Test status
Simulation time 178961892 ps
CPU time 0.88 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207496 kb
Host smart-9681ff4f-aced-4bd8-a8df-99aba2cc5653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23928
38300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2392838300
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.921727440
Short name T1674
Test name
Test status
Simulation time 246311509 ps
CPU time 1.11 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207564 kb
Host smart-46bedde4-13de-47d5-8db7-9344aa56ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92172
7440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.921727440
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.853516282
Short name T1370
Test name
Test status
Simulation time 156343592 ps
CPU time 0.81 seconds
Started Aug 08 06:15:42 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 207516 kb
Host smart-d5e00b81-a096-4997-9998-16607cb8b3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85351
6282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.853516282
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2614157555
Short name T2155
Test name
Test status
Simulation time 188567410 ps
CPU time 1 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207572 kb
Host smart-e380d519-012e-4505-8e6d-f4118610dddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141
57555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2614157555
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3887916534
Short name T2518
Test name
Test status
Simulation time 242119940 ps
CPU time 1.09 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207564 kb
Host smart-5412a872-33fb-4c4a-bd01-b9351cf200b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879
16534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3887916534
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3550833724
Short name T1094
Test name
Test status
Simulation time 2153620014 ps
CPU time 60.51 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:47 PM PDT 24
Peak memory 216000 kb
Host smart-b0d1e683-ede0-4c62-ae42-f5163c085f34
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3550833724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3550833724
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.774580570
Short name T937
Test name
Test status
Simulation time 201533199 ps
CPU time 0.92 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207568 kb
Host smart-32af85cd-6c98-4856-bf3d-b5e2c7102d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77458
0570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.774580570
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.193602343
Short name T2601
Test name
Test status
Simulation time 208412068 ps
CPU time 0.92 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207532 kb
Host smart-0803b748-a1a3-4a9c-b52f-ec7bc6334a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19360
2343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.193602343
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.18743101
Short name T2743
Test name
Test status
Simulation time 1298362615 ps
CPU time 3.04 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207696 kb
Host smart-8ba17494-7946-4199-92f8-3c289252d278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18743
101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.18743101
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.4145370519
Short name T1783
Test name
Test status
Simulation time 2260957867 ps
CPU time 22.62 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 217424 kb
Host smart-3d59d1f1-87dc-4ba5-9c5a-45342f42737e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41453
70519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.4145370519
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.3818246859
Short name T1972
Test name
Test status
Simulation time 1488572422 ps
CPU time 13.53 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207764 kb
Host smart-156b3f6e-a189-4f65-9aa0-313fb589e5f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818246859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.3818246859
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.718540636
Short name T2361
Test name
Test status
Simulation time 455111827 ps
CPU time 1.42 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-d082b086-de50-4cfa-87f8-52e1b709b6df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718540636 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.718540636
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.2800651801
Short name T2963
Test name
Test status
Simulation time 276426670 ps
CPU time 1.01 seconds
Started Aug 08 06:21:21 PM PDT 24
Finished Aug 08 06:21:22 PM PDT 24
Peak memory 207528 kb
Host smart-87061b58-1f60-4b94-87b9-e97a327e94ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2800651801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.2800651801
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.3688834420
Short name T2084
Test name
Test status
Simulation time 571016009 ps
CPU time 1.6 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207560 kb
Host smart-626fdcc9-24df-4fda-ab65-f0a5cdbb5e46
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688834420 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.3688834420
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.3990912346
Short name T1552
Test name
Test status
Simulation time 595385126 ps
CPU time 1.62 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207552 kb
Host smart-0054db71-d4ee-4e84-9cc0-df8f4fd848e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990912346 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.3990912346
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.4076073976
Short name T378
Test name
Test status
Simulation time 450834070 ps
CPU time 1.21 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207592 kb
Host smart-693c044f-1ab8-4789-bfff-210b9db18e8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4076073976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.4076073976
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.332573570
Short name T173
Test name
Test status
Simulation time 441923150 ps
CPU time 1.35 seconds
Started Aug 08 06:21:21 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 207584 kb
Host smart-aa3cf9cb-48c7-462f-a9a9-7ae365f7f55c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332573570 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.332573570
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.16066361
Short name T3628
Test name
Test status
Simulation time 460021850 ps
CPU time 1.32 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207552 kb
Host smart-61fe0123-4d86-4256-b6c7-b9ba3500afbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=16066361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.16066361
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.4043831911
Short name T2323
Test name
Test status
Simulation time 548522053 ps
CPU time 1.59 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207600 kb
Host smart-591fe013-c9f5-4342-aa49-6e2fe68ab94e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043831911 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.4043831911
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.3150347097
Short name T3061
Test name
Test status
Simulation time 221157433 ps
CPU time 0.94 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207504 kb
Host smart-9eba392f-4d5e-49ac-816b-b3abb6b1fdfb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3150347097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.3150347097
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.841535821
Short name T687
Test name
Test status
Simulation time 643082104 ps
CPU time 1.64 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207572 kb
Host smart-cba04e58-8fac-43ad-9f05-f64ff5a605d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841535821 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.841535821
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.2174891696
Short name T1934
Test name
Test status
Simulation time 429680867 ps
CPU time 1.29 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207500 kb
Host smart-d24bdf67-bcd5-40fa-a2f1-c9f19bd3317d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2174891696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.2174891696
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.2287941955
Short name T2666
Test name
Test status
Simulation time 556217348 ps
CPU time 1.51 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207500 kb
Host smart-5fdddc16-c852-4e8f-9f66-e5db6bda7bfb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287941955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.2287941955
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.1013974681
Short name T2774
Test name
Test status
Simulation time 602880187 ps
CPU time 1.56 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207500 kb
Host smart-ce4f7f7a-1947-488a-80e3-a5d841530dba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1013974681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.1013974681
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.235527850
Short name T3318
Test name
Test status
Simulation time 483582190 ps
CPU time 1.64 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207548 kb
Host smart-02755cf7-8d12-43dc-ab71-8a5d533bc1ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235527850 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.235527850
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.977919219
Short name T721
Test name
Test status
Simulation time 419378628 ps
CPU time 1.36 seconds
Started Aug 08 06:21:35 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 207488 kb
Host smart-f4c2ec16-a8b6-46a9-baaa-4639edcfa6c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977919219 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.977919219
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.2586062012
Short name T3593
Test name
Test status
Simulation time 542443937 ps
CPU time 1.56 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207588 kb
Host smart-a672224d-3e4b-41a2-9df3-8ff99fdedde4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586062012 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.2586062012
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.3387712012
Short name T381
Test name
Test status
Simulation time 546834051 ps
CPU time 1.55 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207504 kb
Host smart-330ab6a0-0751-4812-8f36-a9b4a0738b2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3387712012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.3387712012
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.1115970013
Short name T1756
Test name
Test status
Simulation time 536203559 ps
CPU time 1.77 seconds
Started Aug 08 06:21:21 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 207540 kb
Host smart-26c1e214-04c2-45cd-b34e-29ead99f46be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115970013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.1115970013
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.984865011
Short name T1644
Test name
Test status
Simulation time 73704011 ps
CPU time 0.68 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207584 kb
Host smart-bb0c3264-b479-4853-9dc5-c47de487f37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=984865011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.984865011
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.698927489
Short name T2769
Test name
Test status
Simulation time 11105906639 ps
CPU time 15.93 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207824 kb
Host smart-8614de40-3e8c-4c89-9613-5366222be52a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698927489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_disconnect.698927489
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2376849174
Short name T1281
Test name
Test status
Simulation time 20507862607 ps
CPU time 24.56 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 207768 kb
Host smart-1930c71f-761f-4d72-88ac-ea06f11cae9d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376849174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2376849174
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.4092049283
Short name T760
Test name
Test status
Simulation time 26243214759 ps
CPU time 38.05 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 215968 kb
Host smart-75f12db9-e41b-4407-a65f-6761920c0008
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092049283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.4092049283
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1589683395
Short name T3267
Test name
Test status
Simulation time 176931022 ps
CPU time 0.88 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207460 kb
Host smart-8a3106de-2473-4cd9-b49f-c413a27050e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
83395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1589683395
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1030281294
Short name T2977
Test name
Test status
Simulation time 164181308 ps
CPU time 0.89 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207516 kb
Host smart-5b14b0b7-0ae4-4da3-8966-558872722fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10302
81294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1030281294
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2371484748
Short name T1075
Test name
Test status
Simulation time 345478940 ps
CPU time 1.29 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207548 kb
Host smart-ca2a6a4c-9e12-4742-be86-fe06159d149e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714
84748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2371484748
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3624579953
Short name T3394
Test name
Test status
Simulation time 322322575 ps
CPU time 1.17 seconds
Started Aug 08 06:15:43 PM PDT 24
Finished Aug 08 06:15:44 PM PDT 24
Peak memory 207528 kb
Host smart-5ccfe1d0-ae5c-4f41-be53-41eb5e68961d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3624579953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3624579953
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.711014387
Short name T393
Test name
Test status
Simulation time 17296685613 ps
CPU time 27.16 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:15 PM PDT 24
Peak memory 207812 kb
Host smart-911e8fb9-fc32-4bb9-a375-9db4b767a791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71101
4387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.711014387
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3245213817
Short name T1983
Test name
Test status
Simulation time 746367421 ps
CPU time 14.25 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207668 kb
Host smart-8814b71d-bc83-4ec1-b340-552b44a119c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245213817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3245213817
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.352820477
Short name T2020
Test name
Test status
Simulation time 1078498537 ps
CPU time 2.44 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207436 kb
Host smart-9f27394d-507b-4960-8999-17a02316def7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35282
0477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.352820477
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.820991314
Short name T2840
Test name
Test status
Simulation time 169695582 ps
CPU time 0.87 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207548 kb
Host smart-02edf140-9dec-41a0-bdde-f6720646fe16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82099
1314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.820991314
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1596737185
Short name T667
Test name
Test status
Simulation time 53515118 ps
CPU time 0.77 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207548 kb
Host smart-43d279b8-16fa-476a-9ae5-12985c104c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
37185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1596737185
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2231140561
Short name T2280
Test name
Test status
Simulation time 912342484 ps
CPU time 2.63 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207748 kb
Host smart-f857e367-6800-46b0-a88b-8083bc367338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
40561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2231140561
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.469656092
Short name T1016
Test name
Test status
Simulation time 350731696 ps
CPU time 2.67 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:54 PM PDT 24
Peak memory 207680 kb
Host smart-cd9c6800-e5aa-4710-9d21-386c53d7fdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46965
6092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.469656092
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3772222196
Short name T2390
Test name
Test status
Simulation time 230214861 ps
CPU time 1.15 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 215912 kb
Host smart-91929b5b-ab5a-4fba-be89-93f0578706aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3772222196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3772222196
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2446087660
Short name T959
Test name
Test status
Simulation time 145895935 ps
CPU time 0.81 seconds
Started Aug 08 06:15:45 PM PDT 24
Finished Aug 08 06:15:46 PM PDT 24
Peak memory 207472 kb
Host smart-7c53b9e7-e07f-4638-ace3-74492dc992b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24460
87660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2446087660
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3538769764
Short name T1771
Test name
Test status
Simulation time 225386320 ps
CPU time 0.99 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207468 kb
Host smart-6464abaa-08b7-4cf5-ab0d-ee0e0aed0a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
69764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3538769764
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1085525786
Short name T1549
Test name
Test status
Simulation time 3778801950 ps
CPU time 28.86 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:15 PM PDT 24
Peak memory 224232 kb
Host smart-f2d6ac23-31d6-4767-8ca8-91e5e81a48ea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1085525786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1085525786
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1429961408
Short name T1260
Test name
Test status
Simulation time 7631887605 ps
CPU time 60.43 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:16:46 PM PDT 24
Peak memory 207860 kb
Host smart-b93eead8-8a76-4003-9b79-fa9c9c2ed5b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1429961408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1429961408
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2019295811
Short name T2230
Test name
Test status
Simulation time 264630421 ps
CPU time 1.04 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207544 kb
Host smart-5bdc7760-a2c2-4290-8778-ba9aa27d4a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
95811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2019295811
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2627327666
Short name T1435
Test name
Test status
Simulation time 8318748131 ps
CPU time 12.08 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 216084 kb
Host smart-d08355cf-b507-48c8-817b-8c82c257b6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26273
27666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2627327666
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3060354748
Short name T1466
Test name
Test status
Simulation time 9481238487 ps
CPU time 11.41 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207852 kb
Host smart-88ae8960-9cda-4b13-8c3e-299d42e301c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30603
54748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3060354748
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2351822271
Short name T966
Test name
Test status
Simulation time 3716891299 ps
CPU time 34.25 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 217764 kb
Host smart-58c8a785-ba41-4c3d-96c9-b6b3425a9a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23518
22271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2351822271
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2697517637
Short name T2524
Test name
Test status
Simulation time 1905718135 ps
CPU time 17.97 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 216712 kb
Host smart-662f0e14-c009-4d06-a557-f21e310762e7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2697517637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2697517637
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.321633005
Short name T1933
Test name
Test status
Simulation time 250258935 ps
CPU time 0.95 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 207540 kb
Host smart-d1c02882-6f50-4240-9bfd-527f4d88884a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=321633005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.321633005
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.316146413
Short name T2428
Test name
Test status
Simulation time 210408559 ps
CPU time 0.95 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207568 kb
Host smart-8e47e832-d546-45f9-9498-abfdb89349be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.316146413
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.3258411264
Short name T1000
Test name
Test status
Simulation time 3396395018 ps
CPU time 33.43 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 224316 kb
Host smart-1aabec23-b6b4-4ee0-93f3-9e9b6521b992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32584
11264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.3258411264
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4093147146
Short name T186
Test name
Test status
Simulation time 1796451126 ps
CPU time 17.75 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 224168 kb
Host smart-7a0867b9-9882-47d5-9704-13d5afba4a30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4093147146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4093147146
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.7858834
Short name T1194
Test name
Test status
Simulation time 2257964952 ps
CPU time 64.05 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 217068 kb
Host smart-6693b7a8-6a48-4618-b7df-8b23eb6def56
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=7858834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.7858834
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.203272553
Short name T3131
Test name
Test status
Simulation time 158106888 ps
CPU time 0.87 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207600 kb
Host smart-658f7f0d-a1f0-443e-adf1-e61cd9d47167
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=203272553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.203272553
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.882091496
Short name T2853
Test name
Test status
Simulation time 142752533 ps
CPU time 0.84 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207512 kb
Host smart-3541189f-e663-4765-8da1-a1627cd2f7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88209
1496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.882091496
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.747303268
Short name T2998
Test name
Test status
Simulation time 184562476 ps
CPU time 0.92 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207520 kb
Host smart-eed72da9-048c-41b7-aa5b-bd7710759e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74730
3268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.747303268
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.568550727
Short name T2972
Test name
Test status
Simulation time 189950195 ps
CPU time 0.94 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207536 kb
Host smart-2749439d-5f8c-4381-9568-01a161087716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56855
0727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.568550727
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.409931233
Short name T1575
Test name
Test status
Simulation time 179013491 ps
CPU time 0.85 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207516 kb
Host smart-d8943920-3d56-4d89-a757-7aadbc84dc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
1233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.409931233
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.842316122
Short name T1559
Test name
Test status
Simulation time 210658668 ps
CPU time 0.97 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207548 kb
Host smart-3b62d549-b9c1-48ba-826d-3c032ea50408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84231
6122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.842316122
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3655417237
Short name T3364
Test name
Test status
Simulation time 167062438 ps
CPU time 0.92 seconds
Started Aug 08 06:15:44 PM PDT 24
Finished Aug 08 06:15:45 PM PDT 24
Peak memory 207576 kb
Host smart-c93e69c7-e993-43dc-8437-5d3b8e553c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36554
17237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3655417237
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3601129330
Short name T2808
Test name
Test status
Simulation time 200411822 ps
CPU time 0.97 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207532 kb
Host smart-f126293c-4056-4f82-9e8d-36a289107d98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3601129330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3601129330
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2160045884
Short name T2407
Test name
Test status
Simulation time 145387246 ps
CPU time 0.9 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207172 kb
Host smart-7ac39a1b-2165-4a6b-8cab-59f85143dafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
45884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2160045884
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.49898564
Short name T2628
Test name
Test status
Simulation time 35068558 ps
CPU time 0.69 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207536 kb
Host smart-df7c22ad-8589-4828-b3c9-f42f98951248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49898
564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.49898564
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3644117718
Short name T298
Test name
Test status
Simulation time 14641824815 ps
CPU time 35.53 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:16:26 PM PDT 24
Peak memory 216104 kb
Host smart-e1605ce5-812f-451d-9e62-29ec9ce01ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
17718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3644117718
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3379626938
Short name T3238
Test name
Test status
Simulation time 186705611 ps
CPU time 0.93 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207560 kb
Host smart-11e41935-ad1f-4de2-af06-aa5fafd71f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
26938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3379626938
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2715985306
Short name T3065
Test name
Test status
Simulation time 225878041 ps
CPU time 0.93 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207564 kb
Host smart-153f8ec2-d3f2-4faa-9077-33c6363b5f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
85306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2715985306
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.799033779
Short name T2256
Test name
Test status
Simulation time 264138733 ps
CPU time 1.06 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207124 kb
Host smart-cdf8487c-23fe-4ffb-88aa-29771b4bbbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79903
3779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.799033779
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2452920876
Short name T3613
Test name
Test status
Simulation time 172650299 ps
CPU time 0.97 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207576 kb
Host smart-e0f96d6e-4ddd-4650-bdd6-63d2e4e3650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
20876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2452920876
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.3806160459
Short name T3218
Test name
Test status
Simulation time 20150698662 ps
CPU time 23.28 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 207560 kb
Host smart-69369fb8-20be-4f9a-9023-f9fcbc58b1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38061
60459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.3806160459
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2917578974
Short name T1821
Test name
Test status
Simulation time 176454504 ps
CPU time 0.81 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207572 kb
Host smart-164bd5b4-e670-4429-9a92-441b5ac6c466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
78974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2917578974
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3131481094
Short name T2822
Test name
Test status
Simulation time 176455376 ps
CPU time 0.89 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207556 kb
Host smart-f35e5fad-0893-441b-8b73-b8ad937ac924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
81094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3131481094
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2232364289
Short name T3316
Test name
Test status
Simulation time 191902865 ps
CPU time 0.9 seconds
Started Aug 08 06:15:46 PM PDT 24
Finished Aug 08 06:15:47 PM PDT 24
Peak memory 207592 kb
Host smart-dc0a816f-beca-44f1-a428-7403063e4f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
64289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2232364289
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2253463213
Short name T1622
Test name
Test status
Simulation time 219809595 ps
CPU time 0.97 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207476 kb
Host smart-9e0e70b0-cb8f-4dd6-b457-2d9a94b27588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534
63213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2253463213
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2908653065
Short name T1317
Test name
Test status
Simulation time 1857897626 ps
CPU time 13.7 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 217572 kb
Host smart-e0196e53-55e8-4c38-a5d9-8bbf56885ead
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2908653065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2908653065
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3689805583
Short name T2181
Test name
Test status
Simulation time 167714457 ps
CPU time 0.89 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207516 kb
Host smart-d448674d-0af5-4c82-a844-62d9d1e4b7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36898
05583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3689805583
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2676095734
Short name T1086
Test name
Test status
Simulation time 176249872 ps
CPU time 0.86 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207388 kb
Host smart-45bda376-22b3-43eb-a650-ea0672693061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26760
95734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2676095734
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.1486718439
Short name T2026
Test name
Test status
Simulation time 1181970154 ps
CPU time 2.99 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207688 kb
Host smart-c2686c25-3585-49ef-b0dd-ee2364436086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
18439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.1486718439
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.252783268
Short name T2656
Test name
Test status
Simulation time 2787504412 ps
CPU time 26.47 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:15 PM PDT 24
Peak memory 217424 kb
Host smart-0b3c50be-fd80-43ca-854e-e4ddb2a855db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278
3268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.252783268
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.1705231927
Short name T3186
Test name
Test status
Simulation time 647863054 ps
CPU time 5.06 seconds
Started Aug 08 06:15:47 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207748 kb
Host smart-35bab087-ab0f-4e41-a747-2d23ce6aebb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705231927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.1705231927
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.2047347194
Short name T106
Test name
Test status
Simulation time 472249640 ps
CPU time 1.42 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207296 kb
Host smart-16b51d20-b3bf-4d73-a677-ae979d337fec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047347194 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.2047347194
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.1463633039
Short name T3091
Test name
Test status
Simulation time 258233277 ps
CPU time 0.98 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207492 kb
Host smart-18eb5e9b-ff3d-4713-bfdf-23f8b0aca76c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1463633039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.1463633039
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.1559317163
Short name T2645
Test name
Test status
Simulation time 573873971 ps
CPU time 1.51 seconds
Started Aug 08 06:21:37 PM PDT 24
Finished Aug 08 06:21:39 PM PDT 24
Peak memory 207552 kb
Host smart-7994e4e0-1ca8-4c71-9598-88a11f4b8334
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559317163 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.1559317163
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.224752554
Short name T3014
Test name
Test status
Simulation time 508040938 ps
CPU time 1.55 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207572 kb
Host smart-aa26d60b-1180-490c-b806-70600543a25b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224752554 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.224752554
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.2472731546
Short name T468
Test name
Test status
Simulation time 301321982 ps
CPU time 1.09 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207576 kb
Host smart-67a0e6db-b2d9-4057-bf20-5a78859f005c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2472731546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.2472731546
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.2433107842
Short name T2352
Test name
Test status
Simulation time 522963337 ps
CPU time 1.49 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207600 kb
Host smart-33c5a330-1bda-4e2b-8583-6eded37853c8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433107842 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.2433107842
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.862397632
Short name T3156
Test name
Test status
Simulation time 357711715 ps
CPU time 1.17 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207548 kb
Host smart-49d33ec5-5e96-467b-a3ff-3a018268558e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=862397632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.862397632
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.1167998601
Short name T2642
Test name
Test status
Simulation time 477229570 ps
CPU time 1.51 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207544 kb
Host smart-5672d38d-f2ac-40eb-8158-bfe55e7f1cf5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167998601 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.1167998601
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.1887769881
Short name T376
Test name
Test status
Simulation time 724395611 ps
CPU time 1.57 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207556 kb
Host smart-e1734635-11d1-4b25-b8d5-75764629a165
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1887769881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.1887769881
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.755963413
Short name T1391
Test name
Test status
Simulation time 671800106 ps
CPU time 1.83 seconds
Started Aug 08 06:21:22 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207568 kb
Host smart-d7b31229-6a1b-4162-977a-1884ec705cdc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755963413 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.755963413
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.1477499221
Short name T20
Test name
Test status
Simulation time 550766197 ps
CPU time 1.56 seconds
Started Aug 08 06:21:20 PM PDT 24
Finished Aug 08 06:21:22 PM PDT 24
Peak memory 207496 kb
Host smart-91ae4688-fa08-43e2-b94e-b77494ae762e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477499221 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.1477499221
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.1590434553
Short name T733
Test name
Test status
Simulation time 615212232 ps
CPU time 1.65 seconds
Started Aug 08 06:21:35 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 206376 kb
Host smart-3cba62c8-2794-407c-8e17-7054874a5f30
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590434553 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.1590434553
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.1351887672
Short name T482
Test name
Test status
Simulation time 449487785 ps
CPU time 1.35 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207588 kb
Host smart-ee3d2cff-13db-4e81-95b3-9b1b43d99900
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1351887672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.1351887672
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.2306709901
Short name T3548
Test name
Test status
Simulation time 557394066 ps
CPU time 1.69 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207616 kb
Host smart-d3a1a1ad-af30-4675-8ff8-c401dfd51438
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306709901 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.2306709901
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.4071284368
Short name T3336
Test name
Test status
Simulation time 238421837 ps
CPU time 1.09 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207492 kb
Host smart-8a88f331-e938-4c9c-86ae-1211b9bcd33f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4071284368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.4071284368
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.525433116
Short name T3049
Test name
Test status
Simulation time 497399299 ps
CPU time 1.64 seconds
Started Aug 08 06:21:20 PM PDT 24
Finished Aug 08 06:21:22 PM PDT 24
Peak memory 207600 kb
Host smart-897159d6-0272-4436-8e67-41dd770ba355
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525433116 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.525433116
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.1400064044
Short name T404
Test name
Test status
Simulation time 693939231 ps
CPU time 1.81 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207492 kb
Host smart-3ca8dab6-29ac-4127-888b-2e74e1d49194
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1400064044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.1400064044
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.4057267543
Short name T3292
Test name
Test status
Simulation time 579783750 ps
CPU time 1.6 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 206312 kb
Host smart-50e387ad-8cfa-4d69-a181-c8fae9217297
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057267543 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.4057267543
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1469848017
Short name T2070
Test name
Test status
Simulation time 110298046 ps
CPU time 0.72 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207552 kb
Host smart-390d432b-8c12-4551-9682-de72cb5b8d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1469848017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1469848017
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3335407598
Short name T1849
Test name
Test status
Simulation time 10623063591 ps
CPU time 14.81 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207828 kb
Host smart-7982e401-ebe0-4856-a142-3781d784d95f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335407598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3335407598
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3914006768
Short name T1219
Test name
Test status
Simulation time 21243096203 ps
CPU time 24.32 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:13 PM PDT 24
Peak memory 207812 kb
Host smart-9912618b-e7a6-4043-8410-0940cba8713e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914006768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3914006768
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.4219314451
Short name T1970
Test name
Test status
Simulation time 23553671369 ps
CPU time 29.1 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:18 PM PDT 24
Peak memory 215940 kb
Host smart-164184be-ba31-41fe-8f39-b8f39154048b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219314451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.4219314451
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1743114834
Short name T875
Test name
Test status
Simulation time 187780618 ps
CPU time 0.91 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207544 kb
Host smart-027e3e13-aedd-4fb1-b100-dee00102be3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
14834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1743114834
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1226999424
Short name T2562
Test name
Test status
Simulation time 183569563 ps
CPU time 0.85 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207516 kb
Host smart-db6304a4-0cf8-4109-be11-68d3306e6b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
99424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1226999424
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1283916296
Short name T764
Test name
Test status
Simulation time 409387757 ps
CPU time 1.32 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207520 kb
Host smart-6ffd9ce2-57c1-443e-b763-21dbc05e5874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12839
16296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1283916296
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1725838681
Short name T1654
Test name
Test status
Simulation time 347700814 ps
CPU time 1.19 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207532 kb
Host smart-3d190351-4665-47a4-956f-f4dfea139cad
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1725838681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1725838681
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1341426921
Short name T2783
Test name
Test status
Simulation time 52202879838 ps
CPU time 72.01 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207808 kb
Host smart-41bdcb6e-7267-439f-b7e3-2cb150c81506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
26921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1341426921
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.1934869575
Short name T1830
Test name
Test status
Simulation time 2512304733 ps
CPU time 22.69 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 207876 kb
Host smart-cefc6153-8360-4c3e-a4a9-8144210b0631
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934869575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.1934869575
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2279598897
Short name T2354
Test name
Test status
Simulation time 1176219368 ps
CPU time 2.58 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 207480 kb
Host smart-5d0da391-ca0e-4bc7-8469-f7f259dc3559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22795
98897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2279598897
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.759026639
Short name T2981
Test name
Test status
Simulation time 159678672 ps
CPU time 0.83 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207500 kb
Host smart-3d30ef5e-859d-4fcc-8a80-5f8985425434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75902
6639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.759026639
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2332390160
Short name T1745
Test name
Test status
Simulation time 32605679 ps
CPU time 0.69 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207492 kb
Host smart-fdc7e411-5f77-495a-a44f-623f3459d884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323
90160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2332390160
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.164621992
Short name T2956
Test name
Test status
Simulation time 927715497 ps
CPU time 2.65 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 207724 kb
Host smart-1514b2dd-3d98-44a6-821d-e494b31bb694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16462
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.164621992
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.921970802
Short name T624
Test name
Test status
Simulation time 197893435 ps
CPU time 1.38 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207688 kb
Host smart-af4f26c7-11b0-4ad8-9a27-dddd4205b8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92197
0802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.921970802
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3798526672
Short name T2969
Test name
Test status
Simulation time 166741996 ps
CPU time 0.91 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207508 kb
Host smart-bbe60284-a458-45a4-99fd-f0deb933eded
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3798526672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3798526672
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.4253491866
Short name T2273
Test name
Test status
Simulation time 173093866 ps
CPU time 0.87 seconds
Started Aug 08 06:15:40 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 207572 kb
Host smart-d30662ef-1c1b-4400-a7b2-337437d452bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
91866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4253491866
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.566770276
Short name T2538
Test name
Test status
Simulation time 161749062 ps
CPU time 0.88 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207576 kb
Host smart-83867bc4-e886-4949-9bdb-aab77d22548f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56677
0276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.566770276
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.4273879742
Short name T1044
Test name
Test status
Simulation time 11457450558 ps
CPU time 73.72 seconds
Started Aug 08 06:15:50 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 207816 kb
Host smart-dff645cc-e5fb-41ef-be00-ee5dba22005b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4273879742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.4273879742
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.800675953
Short name T2029
Test name
Test status
Simulation time 168737616 ps
CPU time 0.86 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207548 kb
Host smart-9dc5d2db-5a77-4414-bcea-a833ad6dc26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80067
5953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.800675953
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3446024150
Short name T714
Test name
Test status
Simulation time 32032839019 ps
CPU time 47.29 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207832 kb
Host smart-ed423062-7143-4803-913d-de5846d82718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34460
24150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3446024150
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3471232232
Short name T3333
Test name
Test status
Simulation time 5879666603 ps
CPU time 8.96 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:16:08 PM PDT 24
Peak memory 207824 kb
Host smart-06b96d76-fd3d-4ad4-be1a-e4921f7cb6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34712
32232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3471232232
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3614599568
Short name T755
Test name
Test status
Simulation time 3375503927 ps
CPU time 92.37 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 224232 kb
Host smart-4b68051c-d4f0-41c8-8984-416b24e4b9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36145
99568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3614599568
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3038588850
Short name T2455
Test name
Test status
Simulation time 1771530040 ps
CPU time 13.3 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 215952 kb
Host smart-72c85651-0814-428b-9a75-62e440cc4659
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3038588850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3038588850
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.507161545
Short name T2416
Test name
Test status
Simulation time 242850668 ps
CPU time 0.99 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207564 kb
Host smart-a304dfea-e8a4-4dee-a37c-249a585134cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=507161545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.507161545
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2040105214
Short name T2357
Test name
Test status
Simulation time 184664697 ps
CPU time 1.01 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207656 kb
Host smart-7ab83b86-f0c5-4be5-a4a7-090f5873eecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
05214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2040105214
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.678454294
Short name T3589
Test name
Test status
Simulation time 1411037430 ps
CPU time 38.65 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 215984 kb
Host smart-855950fa-8a1b-4c41-80b9-5cf5b50dc717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67845
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.678454294
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1136589687
Short name T2649
Test name
Test status
Simulation time 3136939512 ps
CPU time 23.84 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 217728 kb
Host smart-472f34b0-302e-4bfa-bb22-21b3a50f9b90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1136589687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1136589687
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.147648061
Short name T3519
Test name
Test status
Simulation time 2360411487 ps
CPU time 63.71 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 216096 kb
Host smart-21c69595-9272-4588-abc9-eb10a96562d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=147648061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.147648061
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.781807528
Short name T3252
Test name
Test status
Simulation time 180375768 ps
CPU time 0.88 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207580 kb
Host smart-3ad7ec75-b946-4af8-bd48-c6ab3d2b5cb8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=781807528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.781807528
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2781637650
Short name T569
Test name
Test status
Simulation time 140939640 ps
CPU time 0.87 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207596 kb
Host smart-cfdb644c-e134-4e27-a98a-6624d4d083c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27816
37650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2781637650
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3677481969
Short name T587
Test name
Test status
Simulation time 236439049 ps
CPU time 0.93 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 207576 kb
Host smart-bbee0b1d-f8f9-4b92-aae6-797b7eb096d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36774
81969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3677481969
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.4020369493
Short name T1307
Test name
Test status
Simulation time 191676447 ps
CPU time 0.89 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207544 kb
Host smart-bd93b671-af02-4b2c-bc9e-c7ad5a45f09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
69493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.4020369493
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2909649383
Short name T3035
Test name
Test status
Simulation time 177674270 ps
CPU time 0.86 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207560 kb
Host smart-6c448f70-ebcf-4c76-94d2-e1d557f65af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
49383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2909649383
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2560704514
Short name T3606
Test name
Test status
Simulation time 151531861 ps
CPU time 0.88 seconds
Started Aug 08 06:15:48 PM PDT 24
Finished Aug 08 06:15:49 PM PDT 24
Peak memory 207556 kb
Host smart-7c797aa8-8354-467c-9bf4-6ab5ac45bcac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
04514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2560704514
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.373956248
Short name T2693
Test name
Test status
Simulation time 264429423 ps
CPU time 0.99 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207628 kb
Host smart-06192e4c-5cca-4b71-8dce-1eca0885fa0d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=373956248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.373956248
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2316889015
Short name T3137
Test name
Test status
Simulation time 144753634 ps
CPU time 0.8 seconds
Started Aug 08 06:15:55 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 207608 kb
Host smart-0207dddf-7ab4-4e16-a1f5-fd660f8843a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23168
89015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2316889015
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2151560147
Short name T1555
Test name
Test status
Simulation time 36018141 ps
CPU time 0.69 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207308 kb
Host smart-ea9081ca-7254-4172-a1ac-5148345908e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
60147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2151560147
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.410440440
Short name T318
Test name
Test status
Simulation time 23492999229 ps
CPU time 61.04 seconds
Started Aug 08 06:15:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 216096 kb
Host smart-976a7e83-0e30-422e-a218-5b136fe55249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
0440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.410440440
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.200951590
Short name T2467
Test name
Test status
Simulation time 188243254 ps
CPU time 0.93 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:53 PM PDT 24
Peak memory 207600 kb
Host smart-a1c440c7-e330-4cf3-a37d-6b1c2df22915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20095
1590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.200951590
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1745045001
Short name T1748
Test name
Test status
Simulation time 225482927 ps
CPU time 1.02 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207240 kb
Host smart-25bbc6bb-f3a1-4eb2-b3b7-9c2c10830a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17450
45001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1745045001
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2625034484
Short name T2008
Test name
Test status
Simulation time 184461300 ps
CPU time 0.94 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207536 kb
Host smart-d82300fa-e041-44bb-9e2b-a485ecde9fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26250
34484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2625034484
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.123836348
Short name T1663
Test name
Test status
Simulation time 182822104 ps
CPU time 0.91 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207624 kb
Host smart-67e58495-3b04-4aa1-9cf3-6636a34fb47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12383
6348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.123836348
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.2035310894
Short name T3447
Test name
Test status
Simulation time 20171023210 ps
CPU time 24.74 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 207644 kb
Host smart-5baa4c40-3616-43f9-ad60-e11c21ab08ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20353
10894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.2035310894
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3718936574
Short name T1438
Test name
Test status
Simulation time 194506659 ps
CPU time 0.88 seconds
Started Aug 08 06:15:58 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207596 kb
Host smart-4e3a2e5e-abe2-421f-93e2-ddc08c5a26bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189
36574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3718936574
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.3800789001
Short name T1760
Test name
Test status
Simulation time 286434179 ps
CPU time 1.18 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:58 PM PDT 24
Peak memory 207564 kb
Host smart-b3dd56a8-3e5d-49be-826f-90c33d53f056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
89001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.3800789001
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.92601447
Short name T2223
Test name
Test status
Simulation time 152371837 ps
CPU time 0.83 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207504 kb
Host smart-6d2fbb5a-d1fc-49a9-9f96-672081203abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92601
447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.92601447
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2673974841
Short name T1160
Test name
Test status
Simulation time 183959810 ps
CPU time 0.91 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207536 kb
Host smart-c1001d9e-0339-436e-8cb7-522255ecf2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26739
74841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2673974841
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.61148961
Short name T3197
Test name
Test status
Simulation time 196197924 ps
CPU time 1.01 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207556 kb
Host smart-8a9380a5-9579-497a-9be4-3181e673c7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61148
961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.61148961
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3511275728
Short name T951
Test name
Test status
Simulation time 2969539952 ps
CPU time 31.25 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:32 PM PDT 24
Peak memory 216144 kb
Host smart-f3efc8ac-1ded-400c-ac29-ac1640926faa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3511275728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3511275728
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1206810759
Short name T797
Test name
Test status
Simulation time 167623961 ps
CPU time 0.83 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207600 kb
Host smart-755d9186-7c8c-4392-8006-4468c195ccff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12068
10759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1206810759
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2694530298
Short name T1815
Test name
Test status
Simulation time 188315892 ps
CPU time 0.91 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207572 kb
Host smart-ab47e471-7b00-447e-b6c9-58b088e097ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
30298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2694530298
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.3024250366
Short name T836
Test name
Test status
Simulation time 885634570 ps
CPU time 2.27 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207668 kb
Host smart-a292fa82-b199-46b6-bd7a-1b567af782f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30242
50366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.3024250366
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3427012706
Short name T2114
Test name
Test status
Simulation time 3003768653 ps
CPU time 28.33 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:28 PM PDT 24
Peak memory 217160 kb
Host smart-8a827a93-83a3-45fe-b1a5-94749ff7919e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34270
12706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3427012706
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1508730746
Short name T727
Test name
Test status
Simulation time 727519939 ps
CPU time 14.64 seconds
Started Aug 08 06:15:49 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207696 kb
Host smart-092f057a-b84d-4269-8cea-e23cec12b077
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508730746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1508730746
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.762073585
Short name T3263
Test name
Test status
Simulation time 491772117 ps
CPU time 1.51 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207580 kb
Host smart-cd990057-e161-4523-903e-e706fe903ca7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762073585 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.762073585
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.3688739876
Short name T2898
Test name
Test status
Simulation time 372898581 ps
CPU time 1.16 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207532 kb
Host smart-ca848b42-c9c7-4845-9810-5afca4f87f5a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688739876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.3688739876
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.696920413
Short name T201
Test name
Test status
Simulation time 550624163 ps
CPU time 1.66 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207540 kb
Host smart-b2d9d9a4-33f9-4d21-b39e-90d46ed6f771
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696920413 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.696920413
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.273210264
Short name T453
Test name
Test status
Simulation time 927944410 ps
CPU time 1.81 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207524 kb
Host smart-2f674692-bc9f-47c1-8341-0282b14c9932
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=273210264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.273210264
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.3159262121
Short name T2435
Test name
Test status
Simulation time 678947630 ps
CPU time 1.78 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207544 kb
Host smart-611376eb-51cc-4f25-a14c-3718f1ee8b4f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159262121 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.3159262121
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.4106469536
Short name T985
Test name
Test status
Simulation time 494543476 ps
CPU time 1.43 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207544 kb
Host smart-93f0536b-4c40-4689-950e-e24a3ace6e8f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106469536 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.4106469536
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.2632050549
Short name T375
Test name
Test status
Simulation time 442202525 ps
CPU time 1.41 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207472 kb
Host smart-771e40d4-0416-4acd-bcfd-2d6ec1f3484c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2632050549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2632050549
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.3531796336
Short name T2965
Test name
Test status
Simulation time 678459530 ps
CPU time 2.05 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207604 kb
Host smart-cbdb4cdb-173e-4e6f-bd36-e3560b6af7a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531796336 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.3531796336
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.4236943929
Short name T426
Test name
Test status
Simulation time 512357941 ps
CPU time 1.44 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207588 kb
Host smart-87e5fd9a-7c15-4bb6-aaca-4c36527f8750
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4236943929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.4236943929
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.2556479487
Short name T882
Test name
Test status
Simulation time 603808907 ps
CPU time 1.93 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207552 kb
Host smart-732e1b64-bfc4-4c06-832d-bfc004374aca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556479487 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.2556479487
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.3186416603
Short name T401
Test name
Test status
Simulation time 661273403 ps
CPU time 1.48 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207516 kb
Host smart-ca93991e-07b7-47cc-9067-b474feed082a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3186416603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.3186416603
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.2551320114
Short name T3514
Test name
Test status
Simulation time 594852569 ps
CPU time 1.74 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207572 kb
Host smart-c1aa0f41-312e-424a-a889-d0e7f2cc2182
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551320114 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.2551320114
Directory /workspace/135.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.2278699172
Short name T792
Test name
Test status
Simulation time 609522958 ps
CPU time 1.6 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207584 kb
Host smart-7e226fd4-2650-4ee5-b7e6-52bdc9fdd978
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278699172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.2278699172
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.1434636478
Short name T2615
Test name
Test status
Simulation time 625601618 ps
CPU time 1.73 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207564 kb
Host smart-e2ae8d72-6fce-43e2-9936-b71f3608789f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434636478 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.1434636478
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.3132751580
Short name T3504
Test name
Test status
Simulation time 531610104 ps
CPU time 1.44 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207532 kb
Host smart-51b9f2bf-cdb6-4db2-8de1-089fc5a9c627
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3132751580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.3132751580
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.4221991390
Short name T962
Test name
Test status
Simulation time 522931338 ps
CPU time 1.54 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207572 kb
Host smart-a44ed78e-148f-4f68-a026-e950eb4220ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221991390 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.4221991390
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.946796712
Short name T2558
Test name
Test status
Simulation time 470765108 ps
CPU time 1.55 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207580 kb
Host smart-f8049475-6ac7-4979-b75e-a06253f51bc4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946796712 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.946796712
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.3081610708
Short name T2740
Test name
Test status
Simulation time 65926856 ps
CPU time 0.7 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207580 kb
Host smart-693ddef4-dd45-45ce-aac0-c81fa499f00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3081610708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.3081610708
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3669012322
Short name T679
Test name
Test status
Simulation time 4223181746 ps
CPU time 6.62 seconds
Started Aug 08 06:15:58 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 216100 kb
Host smart-a08ab545-77f8-4282-a40e-ac2497ba2a06
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669012322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.3669012322
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3408953173
Short name T996
Test name
Test status
Simulation time 15258977988 ps
CPU time 19.17 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 216008 kb
Host smart-2fb14197-caac-4a57-b55e-bb7f14bd9a81
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408953173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3408953173
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2789573069
Short name T8
Test name
Test status
Simulation time 25827078755 ps
CPU time 32.55 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:32 PM PDT 24
Peak memory 215968 kb
Host smart-f01666d4-435b-472c-9c2f-c736bb231a01
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789573069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.2789573069
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3256769833
Short name T3308
Test name
Test status
Simulation time 209372902 ps
CPU time 0.89 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207508 kb
Host smart-9228e070-9f22-439a-bea2-5edddd6745c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
69833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3256769833
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3241943540
Short name T2217
Test name
Test status
Simulation time 148951600 ps
CPU time 0.84 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207604 kb
Host smart-6aa9e5d4-8e86-4e8b-bdfa-38a18c673a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32419
43540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3241943540
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.442676175
Short name T2127
Test name
Test status
Simulation time 364460262 ps
CPU time 1.33 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207544 kb
Host smart-30d49ada-3a3e-4566-84ea-d8b154f77142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44267
6175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.442676175
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1154847670
Short name T2023
Test name
Test status
Simulation time 589897213 ps
CPU time 1.74 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207544 kb
Host smart-6b73aa23-c15c-4ff0-aa35-bfdbe51a4f0e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1154847670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1154847670
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2338779944
Short name T2843
Test name
Test status
Simulation time 39873381445 ps
CPU time 61.92 seconds
Started Aug 08 06:15:57 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207908 kb
Host smart-0ad68dcf-7868-43fa-a0de-18a702170d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
79944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2338779944
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.2258024162
Short name T2260
Test name
Test status
Simulation time 684532039 ps
CPU time 5.09 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207732 kb
Host smart-25139a4c-bd55-4f41-9449-da5946f0f635
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258024162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2258024162
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.4238539380
Short name T2243
Test name
Test status
Simulation time 923469569 ps
CPU time 1.99 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207496 kb
Host smart-51d48ebc-0629-407c-aa83-bf501b445957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42385
39380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.4238539380
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2619979824
Short name T1306
Test name
Test status
Simulation time 187987418 ps
CPU time 0.86 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 207576 kb
Host smart-80e8f906-a74d-497a-b568-2935812795ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26199
79824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2619979824
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3935665468
Short name T1953
Test name
Test status
Simulation time 32249095 ps
CPU time 0.7 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207500 kb
Host smart-2d59feb2-1b23-49de-8155-35997ad49b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
65468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3935665468
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1246476307
Short name T3375
Test name
Test status
Simulation time 812377565 ps
CPU time 2.37 seconds
Started Aug 08 06:15:56 PM PDT 24
Finished Aug 08 06:15:59 PM PDT 24
Peak memory 207720 kb
Host smart-775a3673-9332-4655-acca-48fb51829ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
76307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1246476307
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3154202320
Short name T3213
Test name
Test status
Simulation time 369549282 ps
CPU time 2.58 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207720 kb
Host smart-5c05f443-bab5-46ba-b10c-d983a02bbbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
02320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3154202320
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.547580635
Short name T2531
Test name
Test status
Simulation time 224598634 ps
CPU time 1.23 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 224016 kb
Host smart-c960e58a-7d2a-4382-91ef-204eb74b5e8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=547580635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.547580635
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2518214127
Short name T1641
Test name
Test status
Simulation time 165136037 ps
CPU time 0.87 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207540 kb
Host smart-142462ac-bf94-42da-8aa8-95b1c10b1e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25182
14127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2518214127
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2308273169
Short name T2481
Test name
Test status
Simulation time 229216262 ps
CPU time 0.93 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207576 kb
Host smart-36bea157-6eda-4338-879c-d7c778995230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
73169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2308273169
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.668773008
Short name T771
Test name
Test status
Simulation time 4724735398 ps
CPU time 46.63 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:47 PM PDT 24
Peak memory 217920 kb
Host smart-12135d2b-7ae7-48b9-bb4c-9a799fa3cbe3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=668773008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.668773008
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.448270947
Short name T3305
Test name
Test status
Simulation time 13213943336 ps
CPU time 169.07 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207788 kb
Host smart-b37b226b-0a5a-4638-a4c1-a6cf7e5889a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=448270947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.448270947
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1063940933
Short name T3017
Test name
Test status
Simulation time 238830037 ps
CPU time 1.03 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207388 kb
Host smart-45a137e4-a122-4c1e-8b11-de1466e12cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
40933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1063940933
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.681490193
Short name T1437
Test name
Test status
Simulation time 27850611125 ps
CPU time 42.16 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:42 PM PDT 24
Peak memory 207840 kb
Host smart-71d7f0ca-9661-4838-9824-2caa93eb021f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68149
0193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.681490193
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2062844038
Short name T1
Test name
Test status
Simulation time 3619876460 ps
CPU time 5.63 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 215620 kb
Host smart-3e372269-7090-4a90-b66e-fa40a8732d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
44038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2062844038
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.588070150
Short name T3612
Test name
Test status
Simulation time 3459987910 ps
CPU time 95.59 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 216048 kb
Host smart-f6fe2170-efc7-49a1-a225-99431109c6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58807
0150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.588070150
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1748618519
Short name T2713
Test name
Test status
Simulation time 3486035137 ps
CPU time 99.93 seconds
Started Aug 08 06:15:58 PM PDT 24
Finished Aug 08 06:17:38 PM PDT 24
Peak memory 216180 kb
Host smart-a3d7a746-937d-4f6d-932d-a2b8a8251944
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1748618519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1748618519
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2231531205
Short name T1884
Test name
Test status
Simulation time 234732965 ps
CPU time 1 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207620 kb
Host smart-b1a06baf-8542-48f1-95ec-bdda1a66262b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2231531205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2231531205
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1972047008
Short name T2929
Test name
Test status
Simulation time 202146229 ps
CPU time 0.93 seconds
Started Aug 08 06:15:58 PM PDT 24
Finished Aug 08 06:15:59 PM PDT 24
Peak memory 207564 kb
Host smart-feeb21a0-8d5e-4ed7-bef7-ea1ccac140cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19720
47008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1972047008
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.199031493
Short name T1971
Test name
Test status
Simulation time 1937180504 ps
CPU time 15.02 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:14 PM PDT 24
Peak memory 224128 kb
Host smart-0e2cfc23-ab54-4e68-8f9d-ed1e6fced8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19903
1493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.199031493
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2889305312
Short name T1653
Test name
Test status
Simulation time 2193018629 ps
CPU time 64.03 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 217924 kb
Host smart-0ffdfab9-6fd4-413d-9404-76819aabaccb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2889305312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2889305312
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3730066696
Short name T1758
Test name
Test status
Simulation time 3072475619 ps
CPU time 93.79 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 217476 kb
Host smart-accdc4a6-afb2-45f8-8332-aee56e4a1894
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3730066696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3730066696
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1495842926
Short name T1101
Test name
Test status
Simulation time 164776424 ps
CPU time 0.91 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207512 kb
Host smart-63ac5098-9755-4ab9-ba09-8df8f4f9012a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1495842926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1495842926
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.677865091
Short name T1631
Test name
Test status
Simulation time 178926205 ps
CPU time 0.9 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207496 kb
Host smart-865d7425-a686-40c0-9e42-cbdbf5b3fdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67786
5091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.677865091
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1816020589
Short name T3545
Test name
Test status
Simulation time 181887527 ps
CPU time 0.95 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207512 kb
Host smart-84064b44-6c41-4a01-92c2-b3cf549ad7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
20589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1816020589
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.872387937
Short name T544
Test name
Test status
Simulation time 170882620 ps
CPU time 0.84 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207512 kb
Host smart-e4df8353-3cb6-4570-a280-b1b3ae68237d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87238
7937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.872387937
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.32567766
Short name T2134
Test name
Test status
Simulation time 154614179 ps
CPU time 0.87 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207180 kb
Host smart-d490188a-df00-41eb-b0c4-43acc9d2adee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.32567766
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3866901717
Short name T1768
Test name
Test status
Simulation time 151348688 ps
CPU time 0.85 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207128 kb
Host smart-5eb11eec-b305-4200-abdb-7aef08cecd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
01717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3866901717
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.457841351
Short name T2611
Test name
Test status
Simulation time 213657506 ps
CPU time 0.96 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207512 kb
Host smart-ddaabca3-105c-4178-b3b6-7f0d9eaf9a13
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=457841351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.457841351
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1577605016
Short name T1084
Test name
Test status
Simulation time 152450539 ps
CPU time 0.88 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207540 kb
Host smart-fb695538-70ec-4b55-9e65-8b542d26754b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15776
05016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1577605016
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1452154094
Short name T2292
Test name
Test status
Simulation time 33897681 ps
CPU time 0.71 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207532 kb
Host smart-6c6d6ed5-de44-4848-a2cd-b33c6b985c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14521
54094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1452154094
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2875513630
Short name T1897
Test name
Test status
Simulation time 19740725371 ps
CPU time 45.87 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:45 PM PDT 24
Peak memory 216052 kb
Host smart-95105908-d04d-48b6-b77a-890dbc5c2180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
13630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2875513630
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3502456026
Short name T555
Test name
Test status
Simulation time 179354642 ps
CPU time 0.87 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:15:55 PM PDT 24
Peak memory 206360 kb
Host smart-fff99a9a-1a66-4f81-a3ae-c09615403c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024
56026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3502456026
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.4060653184
Short name T3443
Test name
Test status
Simulation time 264345644 ps
CPU time 1.05 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207568 kb
Host smart-aaea9dd0-f11a-4404-be09-3f613d4aadea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
53184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.4060653184
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2814720090
Short name T25
Test name
Test status
Simulation time 174855993 ps
CPU time 0.86 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207580 kb
Host smart-a1cfab44-df79-4684-bb24-ccf5f12ee7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28147
20090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2814720090
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.2742136780
Short name T3183
Test name
Test status
Simulation time 20160261479 ps
CPU time 25.74 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207632 kb
Host smart-66d70edc-2b94-4611-bf5d-c45dc4674e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
36780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.2742136780
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4226432144
Short name T77
Test name
Test status
Simulation time 144644840 ps
CPU time 0.91 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207528 kb
Host smart-f8b4159f-3e53-465a-a3c5-596efc6ee426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42264
32144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4226432144
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.3430635193
Short name T2263
Test name
Test status
Simulation time 257625983 ps
CPU time 1.12 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207524 kb
Host smart-518e6c5b-269f-4d4a-9c2a-4d867d7c2253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34306
35193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.3430635193
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.431172956
Short name T3368
Test name
Test status
Simulation time 152036877 ps
CPU time 0.86 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:15:55 PM PDT 24
Peak memory 207560 kb
Host smart-373533da-8628-4fa3-b47d-3cf5d32b7ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43117
2956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.431172956
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2425183225
Short name T1995
Test name
Test status
Simulation time 148294398 ps
CPU time 0.83 seconds
Started Aug 08 06:15:54 PM PDT 24
Finished Aug 08 06:15:55 PM PDT 24
Peak memory 206360 kb
Host smart-220d1e85-57bd-4a91-bd82-05ec310fbd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
83225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2425183225
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1689008600
Short name T1392
Test name
Test status
Simulation time 267088125 ps
CPU time 1.09 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207584 kb
Host smart-fac87108-5bb3-4326-8d9d-0c1dc2df1e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
08600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1689008600
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2432985872
Short name T3114
Test name
Test status
Simulation time 3370187744 ps
CPU time 34.29 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 217164 kb
Host smart-59239ef7-c036-4de5-80a8-85a31cf4abe0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2432985872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2432985872
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.689636456
Short name T2874
Test name
Test status
Simulation time 151585496 ps
CPU time 0.84 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207544 kb
Host smart-c1e9ba3e-de8a-481a-8e56-35d4a3f06bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68963
6456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.689636456
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.636701569
Short name T2478
Test name
Test status
Simulation time 178714227 ps
CPU time 0.9 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207560 kb
Host smart-82a460f6-5c6b-4040-892a-629407d39462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63670
1569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.636701569
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.1850009376
Short name T919
Test name
Test status
Simulation time 1323070791 ps
CPU time 3.27 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:07 PM PDT 24
Peak memory 207620 kb
Host smart-ef123cf7-ffcf-4f16-9f9a-3605021dec8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
09376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.1850009376
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2165510683
Short name T3298
Test name
Test status
Simulation time 2711353481 ps
CPU time 75.42 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:17:08 PM PDT 24
Peak memory 216096 kb
Host smart-08976d0b-1925-4611-b4ef-2b11dc7e0369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
10683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2165510683
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.3353826891
Short name T3476
Test name
Test status
Simulation time 1170078527 ps
CPU time 26.18 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:27 PM PDT 24
Peak memory 207728 kb
Host smart-38b65b92-8a61-47c6-9285-2ad35a555907
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353826891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.3353826891
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.3743729813
Short name T1569
Test name
Test status
Simulation time 598725229 ps
CPU time 1.82 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207552 kb
Host smart-68c7fd47-ea44-4cd1-a3f9-28466c6bd239
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743729813 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.3743729813
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.411661763
Short name T2667
Test name
Test status
Simulation time 270119887 ps
CPU time 0.99 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207564 kb
Host smart-e6ed870d-e5b5-4fbc-8562-079f6b33e50e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=411661763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.411661763
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.1179070600
Short name T200
Test name
Test status
Simulation time 486978925 ps
CPU time 1.46 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207548 kb
Host smart-cf4c2927-f24a-4500-b72e-ca46258ed613
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179070600 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.1179070600
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.4154032774
Short name T363
Test name
Test status
Simulation time 680566860 ps
CPU time 1.89 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207464 kb
Host smart-af3b317d-0bf7-4cba-b5d8-726e457faa76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4154032774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.4154032774
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.1852044448
Short name T3104
Test name
Test status
Simulation time 515229518 ps
CPU time 1.71 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207548 kb
Host smart-db0bb286-067d-437b-84ca-5b8d42e33d8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852044448 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.1852044448
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.3965489394
Short name T457
Test name
Test status
Simulation time 356276146 ps
CPU time 1.19 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207532 kb
Host smart-172f8364-4305-40fd-9724-efc06f15d5f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3965489394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.3965489394
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.1242455673
Short name T3599
Test name
Test status
Simulation time 533356610 ps
CPU time 1.58 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207512 kb
Host smart-2539b312-a0df-42ba-9f23-e89cbc02a7cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242455673 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.1242455673
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.2187339495
Short name T494
Test name
Test status
Simulation time 148975751 ps
CPU time 0.84 seconds
Started Aug 08 06:21:37 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207528 kb
Host smart-20578ca4-b8a8-40cb-a85b-eb79c366c113
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2187339495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.2187339495
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.1426027236
Short name T3262
Test name
Test status
Simulation time 491732990 ps
CPU time 1.47 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207512 kb
Host smart-120edcd2-49f2-431e-8fe0-c12e306ebd24
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426027236 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.1426027236
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.2743567713
Short name T420
Test name
Test status
Simulation time 476834485 ps
CPU time 1.37 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207496 kb
Host smart-badcb287-e487-4205-9d25-3fb8b4ef1f86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2743567713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.2743567713
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.351518281
Short name T2446
Test name
Test status
Simulation time 562538569 ps
CPU time 1.62 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207568 kb
Host smart-3b4ba5b6-1775-4954-8783-5bd43fb6705b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351518281 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.351518281
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.3837809429
Short name T445
Test name
Test status
Simulation time 245941528 ps
CPU time 0.99 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207516 kb
Host smart-696173f3-635a-464e-8a8c-0767ba30d09a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3837809429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3837809429
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.2985911958
Short name T894
Test name
Test status
Simulation time 469896937 ps
CPU time 1.47 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207520 kb
Host smart-776d1b37-c1c6-42a3-b012-477f817d224f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985911958 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.2985911958
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.2072817774
Short name T3176
Test name
Test status
Simulation time 409854746 ps
CPU time 1.2 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207448 kb
Host smart-413e0ec3-9890-4ab9-a855-6478d7eadfb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2072817774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2072817774
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.1190430571
Short name T2556
Test name
Test status
Simulation time 564624982 ps
CPU time 1.68 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207564 kb
Host smart-baf872cb-7b0b-4922-951b-ac97b25967a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190430571 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.1190430571
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.252551778
Short name T391
Test name
Test status
Simulation time 545239671 ps
CPU time 1.43 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207448 kb
Host smart-f597c1fb-a81b-40bd-86fa-99caf8646175
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=252551778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.252551778
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.335390637
Short name T3609
Test name
Test status
Simulation time 544376947 ps
CPU time 1.56 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207640 kb
Host smart-4a96b576-e5d4-4d9f-bde0-c4c9f77b5004
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335390637 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.335390637
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.120340222
Short name T1215
Test name
Test status
Simulation time 304400520 ps
CPU time 1.07 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207484 kb
Host smart-a674f170-256d-4fe4-858a-c1dc95022ca8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=120340222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.120340222
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.2546768119
Short name T2968
Test name
Test status
Simulation time 485309996 ps
CPU time 1.58 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207516 kb
Host smart-a1a8f961-c03e-4059-acff-3d6bff77b3ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546768119 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.2546768119
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.436938013
Short name T335
Test name
Test status
Simulation time 522558888 ps
CPU time 1.66 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207544 kb
Host smart-5b006e95-c912-44d6-9d57-d727de6aa228
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=436938013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.436938013
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.261569020
Short name T2400
Test name
Test status
Simulation time 575316034 ps
CPU time 1.77 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207744 kb
Host smart-5b28d714-83fd-421e-bac8-47a3dad77e17
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261569020 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.261569020
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2708738749
Short name T715
Test name
Test status
Simulation time 50842341 ps
CPU time 0.75 seconds
Started Aug 08 06:16:23 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207608 kb
Host smart-f60c9426-c884-4961-8523-1fbb7103274a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2708738749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2708738749
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3247858739
Short name T2582
Test name
Test status
Simulation time 6728349384 ps
CPU time 9.23 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 215988 kb
Host smart-9a9e62b6-71f0-4660-a20d-710e23fc261f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247858739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3247858739
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.273945423
Short name T2856
Test name
Test status
Simulation time 16086136197 ps
CPU time 18.67 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 215960 kb
Host smart-1d0e74a8-4291-4fea-b297-49f3d4505bb0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=273945423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.273945423
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1480477126
Short name T1318
Test name
Test status
Simulation time 25525306792 ps
CPU time 30.68 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:32 PM PDT 24
Peak memory 216004 kb
Host smart-8565a11e-9bd4-4577-80b2-09a89c120e54
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480477126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.1480477126
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3076383323
Short name T863
Test name
Test status
Simulation time 160153155 ps
CPU time 0.91 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207524 kb
Host smart-e2875082-4dc9-4bab-a844-1392956688d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
83323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3076383323
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3084039428
Short name T976
Test name
Test status
Simulation time 210199906 ps
CPU time 0.98 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207492 kb
Host smart-da9f20ae-3fe5-4470-ad34-f4257096abf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840
39428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3084039428
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.431144848
Short name T1002
Test name
Test status
Simulation time 448198848 ps
CPU time 1.61 seconds
Started Aug 08 06:15:53 PM PDT 24
Finished Aug 08 06:15:55 PM PDT 24
Peak memory 206368 kb
Host smart-efbeb326-bb4c-44be-8c17-a6a0c844097c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43114
4848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.431144848
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3742089328
Short name T1610
Test name
Test status
Simulation time 774936474 ps
CPU time 2.42 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207724 kb
Host smart-c6ebcdaa-7dd2-4f7a-888d-f64185f34939
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3742089328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3742089328
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2177510537
Short name T2573
Test name
Test status
Simulation time 1992146525 ps
CPU time 17.23 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:21 PM PDT 24
Peak memory 207664 kb
Host smart-2cf45699-4f61-4934-a7ea-689b200b59ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177510537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2177510537
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.824296107
Short name T3266
Test name
Test status
Simulation time 1028545203 ps
CPU time 2.21 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:15:54 PM PDT 24
Peak memory 207528 kb
Host smart-1137a540-1753-42b4-ac17-7fd06da2f6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82429
6107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.824296107
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.924393231
Short name T523
Test name
Test status
Simulation time 164621457 ps
CPU time 0.84 seconds
Started Aug 08 06:15:51 PM PDT 24
Finished Aug 08 06:15:52 PM PDT 24
Peak memory 207576 kb
Host smart-e83688c2-c0e2-40fc-a6b5-8e139f8c6015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92439
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.924393231
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3105064279
Short name T820
Test name
Test status
Simulation time 32463996 ps
CPU time 0.68 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207368 kb
Host smart-bd1399f3-252b-4456-a612-17bb5cda2339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31050
64279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3105064279
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3229500504
Short name T1922
Test name
Test status
Simulation time 889193483 ps
CPU time 2.5 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207748 kb
Host smart-db8d65f8-22e5-4970-800a-ec3ed92d4830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
00504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3229500504
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.207960665
Short name T394
Test name
Test status
Simulation time 462988700 ps
CPU time 1.34 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207516 kb
Host smart-df26bbc2-2f89-4592-b366-989864e870ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=207960665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.207960665
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3518166192
Short name T3120
Test name
Test status
Simulation time 265606968 ps
CPU time 2.24 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207684 kb
Host smart-7250861c-0960-45a6-ae27-81d79d48f5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35181
66192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3518166192
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1858485813
Short name T1964
Test name
Test status
Simulation time 162687947 ps
CPU time 0.94 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207524 kb
Host smart-feff749c-2774-4fd5-a09c-e3f6f915f4b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1858485813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1858485813
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4287551944
Short name T1522
Test name
Test status
Simulation time 203487821 ps
CPU time 0.86 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207492 kb
Host smart-9e9429d2-bbdb-4ce1-92ac-91a3a100a0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
51944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4287551944
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.940921541
Short name T1289
Test name
Test status
Simulation time 165972638 ps
CPU time 0.89 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207584 kb
Host smart-cef97932-f78b-46d1-becc-3bc2312a6f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94092
1541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.940921541
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1497412447
Short name T1298
Test name
Test status
Simulation time 2662951854 ps
CPU time 19.9 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 218172 kb
Host smart-90f05bb3-c87d-4d91-8be0-66c59947283a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1497412447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1497412447
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2850363343
Short name T2471
Test name
Test status
Simulation time 8177356812 ps
CPU time 54.58 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207800 kb
Host smart-f8985d5e-f72e-4af6-859d-d4bc09961977
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2850363343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2850363343
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1310306443
Short name T1954
Test name
Test status
Simulation time 204849696 ps
CPU time 0.88 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207544 kb
Host smart-5dd43764-419b-4ec8-a8c8-2e4c27714ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13103
06443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1310306443
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1350563595
Short name T3485
Test name
Test status
Simulation time 24851079638 ps
CPU time 38.34 seconds
Started Aug 08 06:15:52 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 216852 kb
Host smart-078b8a86-1381-4670-9201-a89c24e0cf77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
63595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1350563595
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2113431587
Short name T1646
Test name
Test status
Simulation time 8778658511 ps
CPU time 11.2 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:14 PM PDT 24
Peak memory 207824 kb
Host smart-87c91576-b34b-416f-b674-84f3f741fedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21134
31587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2113431587
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2489836373
Short name T1316
Test name
Test status
Simulation time 5635890744 ps
CPU time 161.72 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 218440 kb
Host smart-932174d3-3f0d-43c3-b303-7cda4e2982e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24898
36373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2489836373
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.4021526508
Short name T743
Test name
Test status
Simulation time 2612422762 ps
CPU time 18.95 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 216136 kb
Host smart-ed5fb060-8462-4237-9681-e3670098d12d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4021526508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.4021526508
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1322865050
Short name T2044
Test name
Test status
Simulation time 248687369 ps
CPU time 0.98 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207544 kb
Host smart-30328b32-1aaf-4a05-8b6f-cea4c127a801
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1322865050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1322865050
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.4129250383
Short name T961
Test name
Test status
Simulation time 189241272 ps
CPU time 0.92 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207504 kb
Host smart-b5cf7ab4-9a8d-439f-a3f6-1e452be7f17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41292
50383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4129250383
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.1524045679
Short name T982
Test name
Test status
Simulation time 2042105480 ps
CPU time 20.45 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 217908 kb
Host smart-c6f3d22c-853b-4623-9657-bfab31d5e114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
45679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.1524045679
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1510007091
Short name T853
Test name
Test status
Simulation time 2092129175 ps
CPU time 59.52 seconds
Started Aug 08 06:16:01 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 217252 kb
Host smart-0192503d-ea1b-4b06-9b8a-596a67d6f2e5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1510007091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1510007091
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3101790423
Short name T649
Test name
Test status
Simulation time 178077281 ps
CPU time 0.84 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207524 kb
Host smart-fbb61b97-b004-4a7b-91e4-3e4f791264c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3101790423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3101790423
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2402984009
Short name T748
Test name
Test status
Simulation time 151334875 ps
CPU time 0.84 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207592 kb
Host smart-16060947-3d5e-4a8f-b0d4-f4ee7ebd71ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
84009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2402984009
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4214050196
Short name T3145
Test name
Test status
Simulation time 245723518 ps
CPU time 0.94 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207536 kb
Host smart-ad9e8968-0efe-4dc6-8a02-5734f1c385fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42140
50196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4214050196
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2738367005
Short name T680
Test name
Test status
Simulation time 225284799 ps
CPU time 0.93 seconds
Started Aug 08 06:15:58 PM PDT 24
Finished Aug 08 06:15:59 PM PDT 24
Peak memory 207612 kb
Host smart-9a36b90c-08d5-4bb7-a0c5-d3b60f3c73e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27383
67005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2738367005
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1523385874
Short name T1721
Test name
Test status
Simulation time 163435855 ps
CPU time 0.86 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207504 kb
Host smart-7f6a4c5e-5842-4756-90e4-12cca38e3b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
85874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1523385874
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1746965979
Short name T2658
Test name
Test status
Simulation time 180915109 ps
CPU time 0.88 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207604 kb
Host smart-08f248b3-1e96-482c-a84a-cff81bac6481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17469
65979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1746965979
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3677528290
Short name T2006
Test name
Test status
Simulation time 160014824 ps
CPU time 0.87 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207572 kb
Host smart-c2c4d247-02b1-4a94-add7-ec65136bda0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36775
28290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3677528290
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1078352872
Short name T1534
Test name
Test status
Simulation time 229485849 ps
CPU time 1.08 seconds
Started Aug 08 06:15:59 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207588 kb
Host smart-a2a2b7da-13db-47bc-8f9a-87a68dbb4517
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1078352872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1078352872
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3163260340
Short name T3301
Test name
Test status
Simulation time 177092797 ps
CPU time 0.82 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207560 kb
Host smart-bcf7b935-378d-4ef6-88c0-6da0ef410ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
60340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3163260340
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1615408556
Short name T1919
Test name
Test status
Simulation time 28787231 ps
CPU time 0.68 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207528 kb
Host smart-91973a9c-537e-4405-b710-2ba7f53da0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16154
08556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1615408556
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1143745349
Short name T1561
Test name
Test status
Simulation time 11765687204 ps
CPU time 28.77 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 216076 kb
Host smart-63891d18-19bf-4377-9b5a-244c44e782d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
45349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1143745349
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1855435493
Short name T2802
Test name
Test status
Simulation time 188895681 ps
CPU time 0.94 seconds
Started Aug 08 06:16:06 PM PDT 24
Finished Aug 08 06:16:07 PM PDT 24
Peak memory 207564 kb
Host smart-9295fc2e-ea0e-4af7-99af-6e804dca0b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
35493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1855435493
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2744090654
Short name T30
Test name
Test status
Simulation time 174884099 ps
CPU time 0.91 seconds
Started Aug 08 06:16:05 PM PDT 24
Finished Aug 08 06:16:07 PM PDT 24
Peak memory 207524 kb
Host smart-6fa8e531-2280-460b-bb46-e3aefd354d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27440
90654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2744090654
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.688021286
Short name T3624
Test name
Test status
Simulation time 208985921 ps
CPU time 0.9 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207592 kb
Host smart-fe3a4551-d0a7-42fa-b127-37906ac07c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68802
1286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.688021286
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.42917653
Short name T1152
Test name
Test status
Simulation time 177605170 ps
CPU time 0.88 seconds
Started Aug 08 06:16:05 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207528 kb
Host smart-73433fbe-940c-4bfe-beec-6618a771addc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917
653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.42917653
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.67547446
Short name T3600
Test name
Test status
Simulation time 20156706079 ps
CPU time 22.17 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 207624 kb
Host smart-4350d2ef-ca8f-4261-aba9-e7de48f92368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67547
446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.67547446
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3638852845
Short name T1310
Test name
Test status
Simulation time 156135961 ps
CPU time 0.91 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207496 kb
Host smart-b1e2a59d-29d9-4ec0-84b2-73a9613d4eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
52845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3638852845
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.2773022535
Short name T1087
Test name
Test status
Simulation time 288061232 ps
CPU time 1.12 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207552 kb
Host smart-1f7aa801-d367-450f-815f-d62aa6bab747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27730
22535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.2773022535
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2481429037
Short name T471
Test name
Test status
Simulation time 218277418 ps
CPU time 1 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207464 kb
Host smart-a470ae0b-b3a1-45ef-b4a1-d7da35bee8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24814
29037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2481429037
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.589499170
Short name T3555
Test name
Test status
Simulation time 151217230 ps
CPU time 0.86 seconds
Started Aug 08 06:16:07 PM PDT 24
Finished Aug 08 06:16:08 PM PDT 24
Peak memory 207564 kb
Host smart-5b56d845-f692-4fb4-b4e7-f850979879a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58949
9170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.589499170
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1112752038
Short name T3326
Test name
Test status
Simulation time 234691510 ps
CPU time 1.28 seconds
Started Aug 08 06:16:00 PM PDT 24
Finished Aug 08 06:16:02 PM PDT 24
Peak memory 207788 kb
Host smart-98946761-89f5-4068-b301-067a8652089e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11127
52038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1112752038
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.828023681
Short name T563
Test name
Test status
Simulation time 2152010561 ps
CPU time 16.45 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:19 PM PDT 24
Peak memory 207836 kb
Host smart-eb9ba1ba-8a03-4d45-960b-98a80cbccac3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=828023681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.828023681
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1877712663
Short name T3554
Test name
Test status
Simulation time 227103248 ps
CPU time 0.93 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:03 PM PDT 24
Peak memory 207548 kb
Host smart-ffdebaa5-9832-42a8-b7ef-cd6dc3601bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
12663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1877712663
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1011948165
Short name T2121
Test name
Test status
Simulation time 168575554 ps
CPU time 0.94 seconds
Started Aug 08 06:16:04 PM PDT 24
Finished Aug 08 06:16:05 PM PDT 24
Peak memory 207492 kb
Host smart-73fa9a29-b24c-45eb-a2ae-91753687e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
48165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1011948165
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1029449227
Short name T1214
Test name
Test status
Simulation time 1024060169 ps
CPU time 2.44 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 207680 kb
Host smart-761414d4-8f10-4480-b939-8bbab1a40eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294
49227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1029449227
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.280937228
Short name T1003
Test name
Test status
Simulation time 3139221443 ps
CPU time 23.99 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:26 PM PDT 24
Peak memory 217724 kb
Host smart-23749209-ac36-4fb6-9e01-28532368de83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
7228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.280937228
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.915010188
Short name T795
Test name
Test status
Simulation time 899754195 ps
CPU time 19.29 seconds
Started Aug 08 06:16:03 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 207696 kb
Host smart-fadd3141-5612-4881-9c58-86f81b5f7385
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915010188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host
_handshake.915010188
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.466040574
Short name T2027
Test name
Test status
Simulation time 486026462 ps
CPU time 1.57 seconds
Started Aug 08 06:16:02 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207564 kb
Host smart-12e65617-5b91-4925-9159-2e759a6e36a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466040574 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.466040574
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.2883989326
Short name T108
Test name
Test status
Simulation time 825142975 ps
CPU time 1.83 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207556 kb
Host smart-03c49dfa-0783-4945-8f25-4f7bdc5330b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2883989326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2883989326
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.4274771941
Short name T1510
Test name
Test status
Simulation time 508113768 ps
CPU time 1.59 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207636 kb
Host smart-54733bd2-4e6b-424d-b87d-891c898828b2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274771941 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.4274771941
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.1664249547
Short name T2392
Test name
Test status
Simulation time 581485926 ps
CPU time 1.72 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207616 kb
Host smart-4076d248-4cd6-4add-9007-610c89de3077
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664249547 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.1664249547
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.688078459
Short name T429
Test name
Test status
Simulation time 485922849 ps
CPU time 1.52 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207552 kb
Host smart-b22bec5e-c268-4c94-a016-e892a13a60d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=688078459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.688078459
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.3587913395
Short name T1697
Test name
Test status
Simulation time 513945388 ps
CPU time 1.55 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207564 kb
Host smart-cb79f695-27c4-4e8f-9d46-1a5e36f0a713
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587913395 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.3587913395
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.2184501892
Short name T419
Test name
Test status
Simulation time 237342927 ps
CPU time 0.97 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207496 kb
Host smart-064192ab-3930-4331-a9ad-5197207da418
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2184501892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.2184501892
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.1537302744
Short name T1213
Test name
Test status
Simulation time 659609723 ps
CPU time 1.79 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207540 kb
Host smart-51235e2b-2da7-4ef8-bd7b-f756d4be1ad3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537302744 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.1537302744
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.2873241205
Short name T906
Test name
Test status
Simulation time 589183346 ps
CPU time 1.51 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207536 kb
Host smart-d75ba0c7-984c-49d8-8128-f132f0085ed8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873241205 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.2873241205
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.1250327128
Short name T452
Test name
Test status
Simulation time 347348642 ps
CPU time 1.31 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207528 kb
Host smart-1819be49-36c1-462f-bc8f-277bd1d61f79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1250327128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.1250327128
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.3358153134
Short name T1088
Test name
Test status
Simulation time 447100700 ps
CPU time 1.57 seconds
Started Aug 08 06:21:38 PM PDT 24
Finished Aug 08 06:21:40 PM PDT 24
Peak memory 207584 kb
Host smart-f3bd9d7a-9d36-4cbc-84fe-4af85e26c1a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358153134 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.3358153134
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.3216984144
Short name T1633
Test name
Test status
Simulation time 397052031 ps
CPU time 1.22 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207516 kb
Host smart-8d263635-6150-4757-95be-21647d069e1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3216984144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.3216984144
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.608791527
Short name T84
Test name
Test status
Simulation time 595017804 ps
CPU time 1.76 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207608 kb
Host smart-25ab3f37-e1d4-4f23-bbaf-45f9f3c384e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608791527 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.608791527
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.2258785195
Short name T3483
Test name
Test status
Simulation time 637932661 ps
CPU time 1.7 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207624 kb
Host smart-4e826c5b-0b59-4784-a33a-e606b1faeffe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258785195 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.2258785195
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.2168397890
Short name T408
Test name
Test status
Simulation time 355235742 ps
CPU time 1.15 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207540 kb
Host smart-3d485e8d-859b-4316-9000-aef79f213652
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2168397890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.2168397890
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.3705680938
Short name T2179
Test name
Test status
Simulation time 637041432 ps
CPU time 1.65 seconds
Started Aug 08 06:21:33 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207788 kb
Host smart-5fe38c75-6c46-4fc9-9d06-74cbb49fedb6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705680938 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.3705680938
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.3856635523
Short name T120
Test name
Test status
Simulation time 519520374 ps
CPU time 1.48 seconds
Started Aug 08 06:21:29 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207540 kb
Host smart-d88caf27-f290-48d4-8b2e-02a33deae97a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3856635523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.3856635523
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.2669115867
Short name T2146
Test name
Test status
Simulation time 595548741 ps
CPU time 1.77 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207552 kb
Host smart-8979c26f-41cf-4c1d-ba97-4fd9efd8ec3c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669115867 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.2669115867
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1778614214
Short name T3427
Test name
Test status
Simulation time 32301988 ps
CPU time 0.69 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207580 kb
Host smart-99e593f2-5f01-4cfd-9e08-d476772c972e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1778614214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1778614214
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.131883835
Short name T3033
Test name
Test status
Simulation time 12050260776 ps
CPU time 16.96 seconds
Started Aug 08 06:16:13 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 207860 kb
Host smart-1046f5fe-925e-4325-b138-71e41c7093eb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131883835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_disconnect.131883835
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.318708968
Short name T2768
Test name
Test status
Simulation time 13499871140 ps
CPU time 17.24 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:46 PM PDT 24
Peak memory 216020 kb
Host smart-7d102c3a-ccee-4ec5-9ecf-225641b56862
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=318708968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.318708968
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3095421086
Short name T3503
Test name
Test status
Simulation time 30290079771 ps
CPU time 36.22 seconds
Started Aug 08 06:16:15 PM PDT 24
Finished Aug 08 06:16:52 PM PDT 24
Peak memory 207808 kb
Host smart-24f7cb4a-4c6c-4174-b020-1766fbb407b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095421086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.3095421086
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3358962117
Short name T1279
Test name
Test status
Simulation time 152740242 ps
CPU time 0.87 seconds
Started Aug 08 06:16:16 PM PDT 24
Finished Aug 08 06:16:17 PM PDT 24
Peak memory 207560 kb
Host smart-bb553103-831e-4931-ad76-1c2608631559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
62117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3358962117
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3853788450
Short name T2839
Test name
Test status
Simulation time 176440907 ps
CPU time 0.83 seconds
Started Aug 08 06:16:23 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207484 kb
Host smart-4de99a80-118b-4edb-85c5-9f56b66651a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537
88450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3853788450
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2060739969
Short name T605
Test name
Test status
Simulation time 544673100 ps
CPU time 1.73 seconds
Started Aug 08 06:16:16 PM PDT 24
Finished Aug 08 06:16:17 PM PDT 24
Peak memory 207572 kb
Host smart-12dc08b8-c7aa-458d-ab15-a3afd3f0e577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20607
39969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2060739969
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1943665418
Short name T1797
Test name
Test status
Simulation time 715127225 ps
CPU time 1.93 seconds
Started Aug 08 06:16:17 PM PDT 24
Finished Aug 08 06:16:19 PM PDT 24
Peak memory 207488 kb
Host smart-5a353b78-8588-4551-aa43-231f99d2bbc7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1943665418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1943665418
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3810093548
Short name T491
Test name
Test status
Simulation time 20382156696 ps
CPU time 37.61 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207796 kb
Host smart-df8370af-5242-4ffc-9d28-a937033d1537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
93548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3810093548
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1316168069
Short name T2503
Test name
Test status
Simulation time 897797858 ps
CPU time 19.59 seconds
Started Aug 08 06:16:13 PM PDT 24
Finished Aug 08 06:16:33 PM PDT 24
Peak memory 207964 kb
Host smart-83bcb3bb-ac9c-464b-8769-591e68a88b2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316168069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1316168069
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.362432889
Short name T1525
Test name
Test status
Simulation time 839343382 ps
CPU time 1.7 seconds
Started Aug 08 06:16:25 PM PDT 24
Finished Aug 08 06:16:26 PM PDT 24
Peak memory 207540 kb
Host smart-7e64e509-088c-4ddf-b535-5fe0de017327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.362432889
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3355691465
Short name T2422
Test name
Test status
Simulation time 159467561 ps
CPU time 0.85 seconds
Started Aug 08 06:16:15 PM PDT 24
Finished Aug 08 06:16:16 PM PDT 24
Peak memory 207488 kb
Host smart-9af15317-4c76-4fb5-b57d-9d1dd3189414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33556
91465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3355691465
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3642320952
Short name T1234
Test name
Test status
Simulation time 38215602 ps
CPU time 0.72 seconds
Started Aug 08 06:16:09 PM PDT 24
Finished Aug 08 06:16:10 PM PDT 24
Peak memory 207572 kb
Host smart-8dfbe0ec-cf98-44fd-9ff4-ba20007450aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
20952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3642320952
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2301655358
Short name T1173
Test name
Test status
Simulation time 855159290 ps
CPU time 2.22 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207692 kb
Host smart-467db69c-4632-4d23-ab68-b992a46ef78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23016
55358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2301655358
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2135821803
Short name T1605
Test name
Test status
Simulation time 226823785 ps
CPU time 1.7 seconds
Started Aug 08 06:16:19 PM PDT 24
Finished Aug 08 06:16:21 PM PDT 24
Peak memory 207712 kb
Host smart-20872bea-e7fc-409e-ab74-93a81f4a09e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
21803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2135821803
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1874688588
Short name T2948
Test name
Test status
Simulation time 241589554 ps
CPU time 1.16 seconds
Started Aug 08 06:16:11 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 215884 kb
Host smart-bc702696-534e-4b9d-b0d1-818971013b1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1874688588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1874688588
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.437544718
Short name T1565
Test name
Test status
Simulation time 149029423 ps
CPU time 0.84 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 207508 kb
Host smart-1236b329-6af8-480a-8344-6ffc4e23c0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43754
4718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.437544718
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2722646464
Short name T845
Test name
Test status
Simulation time 269671244 ps
CPU time 1.11 seconds
Started Aug 08 06:16:10 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 207584 kb
Host smart-82a010b0-82cd-48ee-bca3-1dc6b137a880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27226
46464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2722646464
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.612965432
Short name T1205
Test name
Test status
Simulation time 3230290786 ps
CPU time 92.79 seconds
Started Aug 08 06:16:09 PM PDT 24
Finished Aug 08 06:17:42 PM PDT 24
Peak memory 218464 kb
Host smart-f2f6f46d-0c9a-49f6-8aff-28871b94002e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=612965432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.612965432
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3041517594
Short name T98
Test name
Test status
Simulation time 11916985557 ps
CPU time 135.87 seconds
Started Aug 08 06:16:08 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207888 kb
Host smart-0a1efafd-2031-4221-bfac-746c6622481e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3041517594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3041517594
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3669107742
Short name T1918
Test name
Test status
Simulation time 187604432 ps
CPU time 0.98 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207496 kb
Host smart-4edba2bf-dbad-4585-8298-c8d10e0c1c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691
07742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3669107742
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3915363433
Short name T1662
Test name
Test status
Simulation time 29086789303 ps
CPU time 47.33 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207856 kb
Host smart-cd64593c-c093-4713-b795-b6110c2523ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39153
63433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3915363433
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2159753375
Short name T698
Test name
Test status
Simulation time 6165934914 ps
CPU time 8.35 seconds
Started Aug 08 06:16:20 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 216164 kb
Host smart-65fca47e-81fa-489c-8eb2-e282811e40d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
53375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2159753375
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3272417368
Short name T2438
Test name
Test status
Simulation time 4230070323 ps
CPU time 40.63 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 216172 kb
Host smart-2aa4060e-a23a-4ca9-aa8a-dd037f808157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32724
17368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3272417368
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1526706908
Short name T3273
Test name
Test status
Simulation time 1824842454 ps
CPU time 18.18 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:41 PM PDT 24
Peak memory 224060 kb
Host smart-b0eb8b82-531a-46d4-81df-0d39073bc139
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1526706908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1526706908
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.569289656
Short name T2613
Test name
Test status
Simulation time 259119924 ps
CPU time 1.09 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207532 kb
Host smart-9538fb21-d1ad-4acc-85de-1780e2474eec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=569289656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.569289656
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.838384032
Short name T3044
Test name
Test status
Simulation time 189238955 ps
CPU time 0.89 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207620 kb
Host smart-90bfe06e-e183-41af-b77f-df63c32fd42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83838
4032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.838384032
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.3376562909
Short name T979
Test name
Test status
Simulation time 2098473088 ps
CPU time 16.72 seconds
Started Aug 08 06:16:27 PM PDT 24
Finished Aug 08 06:16:44 PM PDT 24
Peak memory 215944 kb
Host smart-bfa8bdaa-faff-43bc-9c2d-c84753b5f46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33765
62909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.3376562909
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1982368585
Short name T2596
Test name
Test status
Simulation time 3915976065 ps
CPU time 39.67 seconds
Started Aug 08 06:16:24 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 218056 kb
Host smart-4b298d83-9677-49c3-9fa0-2b5922fca8b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1982368585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1982368585
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1531529483
Short name T3435
Test name
Test status
Simulation time 163357190 ps
CPU time 0.91 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207576 kb
Host smart-ae6d281f-26c7-4123-8a6d-39dc88bed723
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1531529483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1531529483
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2248805455
Short name T2108
Test name
Test status
Simulation time 156578108 ps
CPU time 0.85 seconds
Started Aug 08 06:16:30 PM PDT 24
Finished Aug 08 06:16:31 PM PDT 24
Peak memory 207536 kb
Host smart-afdf11c2-3eeb-46b4-856d-2f08d97bd84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22488
05455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2248805455
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1449577400
Short name T142
Test name
Test status
Simulation time 181608910 ps
CPU time 0.87 seconds
Started Aug 08 06:16:26 PM PDT 24
Finished Aug 08 06:16:27 PM PDT 24
Peak memory 207576 kb
Host smart-63b8becd-08a6-45c5-8909-8db8d4339af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14495
77400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1449577400
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2957011350
Short name T3068
Test name
Test status
Simulation time 170936691 ps
CPU time 1 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207560 kb
Host smart-e4ebf333-16bc-483c-aec8-77ca49e020d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570
11350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2957011350
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.347737491
Short name T2274
Test name
Test status
Simulation time 177688863 ps
CPU time 0.85 seconds
Started Aug 08 06:16:32 PM PDT 24
Finished Aug 08 06:16:32 PM PDT 24
Peak memory 207592 kb
Host smart-0d6a8856-6f55-4209-b7b3-8e321adc62e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.347737491
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1677812840
Short name T3256
Test name
Test status
Simulation time 247737725 ps
CPU time 0.97 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207544 kb
Host smart-60f09ffe-a269-4da1-a851-e3bc5c95383c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
12840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1677812840
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3900652681
Short name T2077
Test name
Test status
Simulation time 196597395 ps
CPU time 0.9 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 207544 kb
Host smart-2f378549-2f84-4432-a073-0f0b68684694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
52681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3900652681
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1992202119
Short name T2363
Test name
Test status
Simulation time 283310642 ps
CPU time 1.06 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207620 kb
Host smart-482cbf38-f8cf-4a25-922d-8cb4f1ce2d68
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1992202119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1992202119
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2320480904
Short name T1812
Test name
Test status
Simulation time 140899227 ps
CPU time 0.82 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 207556 kb
Host smart-52166229-f1d1-435d-b285-9aa2810699bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
80904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2320480904
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2727078815
Short name T1339
Test name
Test status
Simulation time 34384460 ps
CPU time 0.67 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207468 kb
Host smart-f6fa1c45-840e-4091-8132-ed94f64bc918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27270
78815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2727078815
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3009037418
Short name T2158
Test name
Test status
Simulation time 12957602863 ps
CPU time 32.92 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 220208 kb
Host smart-e6640f87-4882-4f05-9976-f48b51c7fe3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
37418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3009037418
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1115095648
Short name T2647
Test name
Test status
Simulation time 196135865 ps
CPU time 0.92 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:30 PM PDT 24
Peak memory 207528 kb
Host smart-02c4bb60-3e50-4152-939d-a9b11f83b174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11150
95648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1115095648
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2427626341
Short name T2326
Test name
Test status
Simulation time 183740340 ps
CPU time 0.91 seconds
Started Aug 08 06:16:25 PM PDT 24
Finished Aug 08 06:16:26 PM PDT 24
Peak memory 207580 kb
Host smart-f8ede789-4c12-4f12-9a5d-0eed86fa0fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
26341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2427626341
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.506070683
Short name T1571
Test name
Test status
Simulation time 203417823 ps
CPU time 0.91 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207584 kb
Host smart-16a11da1-e280-4c98-b674-1e67ca2448e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50607
0683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.506070683
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1352183719
Short name T900
Test name
Test status
Simulation time 172865996 ps
CPU time 0.87 seconds
Started Aug 08 06:16:26 PM PDT 24
Finished Aug 08 06:16:27 PM PDT 24
Peak memory 207540 kb
Host smart-3d929e06-9910-46b2-86a5-25629c804747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
83719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1352183719
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.68793130
Short name T103
Test name
Test status
Simulation time 20165708155 ps
CPU time 23.18 seconds
Started Aug 08 06:16:30 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207696 kb
Host smart-f1c75ad8-8219-4f3a-aa02-832c20b27832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68793
130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.68793130
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4072717581
Short name T2005
Test name
Test status
Simulation time 172256753 ps
CPU time 0.9 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:22 PM PDT 24
Peak memory 207228 kb
Host smart-b900e4fd-fd6b-4ec1-8735-62875786c8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40727
17581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4072717581
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.2998307819
Short name T3629
Test name
Test status
Simulation time 273839458 ps
CPU time 1.08 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 207580 kb
Host smart-3090ee06-73ef-463e-b4b3-63f122bd843a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
07819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.2998307819
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.4166600345
Short name T1336
Test name
Test status
Simulation time 192336584 ps
CPU time 0.86 seconds
Started Aug 08 06:16:27 PM PDT 24
Finished Aug 08 06:16:28 PM PDT 24
Peak memory 207436 kb
Host smart-0199d813-8b4e-44ad-9436-60209f3f6bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
00345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.4166600345
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.4203018673
Short name T1832
Test name
Test status
Simulation time 165387822 ps
CPU time 0.9 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207596 kb
Host smart-05a5c569-7057-4743-b915-739f30daffd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
18673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.4203018673
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1425459281
Short name T1942
Test name
Test status
Simulation time 239734342 ps
CPU time 1.02 seconds
Started Aug 08 06:16:24 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 207788 kb
Host smart-cfd85dae-4117-4205-8d50-75799d202d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
59281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1425459281
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.140161464
Short name T2804
Test name
Test status
Simulation time 1903886870 ps
CPU time 14.5 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 216028 kb
Host smart-66d3a726-46e6-4482-83bd-1b006fb499ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=140161464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.140161464
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.4184095664
Short name T2163
Test name
Test status
Simulation time 194863950 ps
CPU time 0.91 seconds
Started Aug 08 06:16:26 PM PDT 24
Finished Aug 08 06:16:27 PM PDT 24
Peak memory 207620 kb
Host smart-e878ef57-69f7-4fbd-a357-2a001196b5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41840
95664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.4184095664
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2426879862
Short name T1131
Test name
Test status
Simulation time 177196166 ps
CPU time 0.88 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207488 kb
Host smart-398a5e08-b12a-446a-93e9-5ba5d4a73baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24268
79862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2426879862
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.714803915
Short name T737
Test name
Test status
Simulation time 571642467 ps
CPU time 1.65 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 207228 kb
Host smart-fdb95307-73b8-4df4-9856-a6daca069b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71480
3915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.714803915
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.644058676
Short name T910
Test name
Test status
Simulation time 2928401306 ps
CPU time 81.05 seconds
Started Aug 08 06:16:26 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 216108 kb
Host smart-d16388e9-af8c-4034-9797-a7b5ab1918ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64405
8676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.644058676
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3794914716
Short name T1027
Test name
Test status
Simulation time 1016213597 ps
CPU time 22.41 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:44 PM PDT 24
Peak memory 207684 kb
Host smart-c000cd05-6a48-4768-b29b-2da9405e7a9c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794914716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3794914716
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.3630319082
Short name T1475
Test name
Test status
Simulation time 502146993 ps
CPU time 1.6 seconds
Started Aug 08 06:16:23 PM PDT 24
Finished Aug 08 06:16:25 PM PDT 24
Peak memory 207564 kb
Host smart-7a650c59-8ec5-48bb-b8b2-23a5e79670ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630319082 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.3630319082
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.3645093329
Short name T1327
Test name
Test status
Simulation time 317868422 ps
CPU time 1.04 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207472 kb
Host smart-a9b8bae3-ff15-4109-b189-0a79526d8130
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3645093329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.3645093329
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.2551219488
Short name T122
Test name
Test status
Simulation time 527493189 ps
CPU time 1.58 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 206304 kb
Host smart-457e6ec8-a9a4-4f7e-8b17-9d8ec906a944
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551219488 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.2551219488
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.1984664152
Short name T437
Test name
Test status
Simulation time 476974870 ps
CPU time 1.46 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207488 kb
Host smart-5aa227b1-10ff-4856-a8d9-3ae3059a19b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1984664152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.1984664152
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.3334059129
Short name T2449
Test name
Test status
Simulation time 513840304 ps
CPU time 1.79 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207596 kb
Host smart-50702f17-4464-4dd7-a889-682993ec9806
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334059129 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.3334059129
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.3908155094
Short name T397
Test name
Test status
Simulation time 581971773 ps
CPU time 1.53 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207504 kb
Host smart-509b87e1-1c4f-466e-a969-afd8d7ff33f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3908155094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.3908155094
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.1192932352
Short name T1312
Test name
Test status
Simulation time 572308066 ps
CPU time 1.52 seconds
Started Aug 08 06:21:35 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 206376 kb
Host smart-18fccc78-10fd-4e37-8581-ee3104eda5ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192932352 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.1192932352
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.1405436315
Short name T359
Test name
Test status
Simulation time 463191442 ps
CPU time 1.3 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207476 kb
Host smart-d5bbbccb-2756-4012-b88d-e2e40ba4eb9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1405436315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.1405436315
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.1287808220
Short name T1377
Test name
Test status
Simulation time 496320012 ps
CPU time 1.61 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207612 kb
Host smart-cf4e250b-ba93-4582-9016-85049953c5b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287808220 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.1287808220
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.865831885
Short name T358
Test name
Test status
Simulation time 418272634 ps
CPU time 1.18 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207484 kb
Host smart-33c99a9a-dd55-4276-ae55-80bd11d5e8c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=865831885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.865831885
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.2296643846
Short name T1384
Test name
Test status
Simulation time 429545122 ps
CPU time 1.4 seconds
Started Aug 08 06:21:52 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207524 kb
Host smart-e2aad360-6d37-4ae7-b4fb-eeced1218cb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296643846 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.2296643846
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.61568896
Short name T364
Test name
Test status
Simulation time 731318507 ps
CPU time 1.62 seconds
Started Aug 08 06:22:05 PM PDT 24
Finished Aug 08 06:22:07 PM PDT 24
Peak memory 207496 kb
Host smart-ae44322a-c8d3-4c53-bf55-b0551cd39e35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=61568896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.61568896
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.3043670847
Short name T2857
Test name
Test status
Simulation time 484568691 ps
CPU time 1.56 seconds
Started Aug 08 06:21:53 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207528 kb
Host smart-1b984e68-580b-47d2-9c93-0e7fd608a7eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043670847 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.3043670847
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.552909620
Short name T901
Test name
Test status
Simulation time 564502062 ps
CPU time 1.6 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207552 kb
Host smart-959b5a7b-8136-4800-a203-978b4c374657
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552909620 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.552909620
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.2717456278
Short name T189
Test name
Test status
Simulation time 528110166 ps
CPU time 1.66 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207644 kb
Host smart-d8a95526-92aa-4dc3-98a5-e4413bcb7ea9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717456278 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.2717456278
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.3705379851
Short name T2402
Test name
Test status
Simulation time 151293620 ps
CPU time 0.88 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:40 PM PDT 24
Peak memory 207508 kb
Host smart-9f2d2ff5-047d-4afa-bb23-47ca274d4a4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3705379851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.3705379851
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.1118244211
Short name T1847
Test name
Test status
Simulation time 593350132 ps
CPU time 1.7 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207520 kb
Host smart-839524ed-b1d1-4030-a9b3-2f0d8d7199e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118244211 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.1118244211
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.975627178
Short name T403
Test name
Test status
Simulation time 749277166 ps
CPU time 1.83 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207484 kb
Host smart-48b0f7c2-77b0-4e78-a20e-de9b94691c76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=975627178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.975627178
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.3952555676
Short name T1583
Test name
Test status
Simulation time 562233883 ps
CPU time 1.71 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207548 kb
Host smart-cde8a601-ef60-48ff-b342-bbb1eb4ff9ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952555676 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.3952555676
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3453569296
Short name T2887
Test name
Test status
Simulation time 53642183 ps
CPU time 0.68 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207604 kb
Host smart-e71d506a-e298-44f5-92bd-a057b13c4edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3453569296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3453569296
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.303530281
Short name T2894
Test name
Test status
Simulation time 6276021617 ps
CPU time 8.49 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 216072 kb
Host smart-d9090433-f366-4800-bb68-84c1e4fedbbc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303530281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_disconnect.303530281
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2941086410
Short name T1930
Test name
Test status
Simulation time 16351161584 ps
CPU time 19.47 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 215992 kb
Host smart-e675ce35-118b-42b5-9987-5c15c026063a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941086410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2941086410
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.935612479
Short name T2641
Test name
Test status
Simulation time 25266237941 ps
CPU time 30.65 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 216048 kb
Host smart-848a85da-86c7-408f-bd68-e02686880684
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935612479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_resume.935612479
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2014824456
Short name T1895
Test name
Test status
Simulation time 215102564 ps
CPU time 0.94 seconds
Started Aug 08 06:16:23 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207544 kb
Host smart-16e7c928-becd-43be-8c5b-56edb120048d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148
24456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2014824456
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1171447400
Short name T86
Test name
Test status
Simulation time 142429872 ps
CPU time 0.82 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:29 PM PDT 24
Peak memory 207588 kb
Host smart-24f965c7-0e5b-4dbe-903c-83bcedec54eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11714
47400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1171447400
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1735542082
Short name T1629
Test name
Test status
Simulation time 399980716 ps
CPU time 1.5 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207548 kb
Host smart-fecefd9a-6157-435b-b014-c326ba2ff5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
42082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1735542082
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3345193164
Short name T1921
Test name
Test status
Simulation time 1159435760 ps
CPU time 2.97 seconds
Started Aug 08 06:16:28 PM PDT 24
Finished Aug 08 06:16:31 PM PDT 24
Peak memory 207740 kb
Host smart-3f6a87e5-3f37-4848-9a6b-79d488570cdc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3345193164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3345193164
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3450648758
Short name T3214
Test name
Test status
Simulation time 24136662688 ps
CPU time 42.22 seconds
Started Aug 08 06:16:21 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207848 kb
Host smart-a8731d9f-46f4-44bc-b50e-7e9cc47d881e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34506
48758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3450648758
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.4014197153
Short name T2574
Test name
Test status
Simulation time 1558381357 ps
CPU time 13.24 seconds
Started Aug 08 06:16:22 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207780 kb
Host smart-0c1c4e24-b7bb-427a-899a-884cd2529d51
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014197153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.4014197153
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.3121725432
Short name T333
Test name
Test status
Simulation time 1161583526 ps
CPU time 2.32 seconds
Started Aug 08 06:16:29 PM PDT 24
Finished Aug 08 06:16:31 PM PDT 24
Peak memory 207508 kb
Host smart-39ff2da2-ecc9-4705-baca-083a756464af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31217
25432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.3121725432
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3006488896
Short name T1926
Test name
Test status
Simulation time 176106130 ps
CPU time 0.87 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207748 kb
Host smart-a305bea9-1b8f-4386-b0f1-dc651ff78f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30064
88896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3006488896
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.752162144
Short name T269
Test name
Test status
Simulation time 38360317 ps
CPU time 0.7 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207564 kb
Host smart-2dd2e401-0f61-411d-a6db-69edaa97ff5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75216
2144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.752162144
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3195991407
Short name T1615
Test name
Test status
Simulation time 741382139 ps
CPU time 2.31 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207724 kb
Host smart-1f82399b-7d82-48ed-8761-85a481e706ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
91407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3195991407
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.3946406325
Short name T2244
Test name
Test status
Simulation time 669474473 ps
CPU time 1.68 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207496 kb
Host smart-8504b3a5-4bf3-48ff-b80f-a725866ba009
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3946406325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.3946406325
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2125419356
Short name T2659
Test name
Test status
Simulation time 351047897 ps
CPU time 2.08 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207612 kb
Host smart-5d06ba5d-1e8b-4f4a-b1fa-7cf83f290e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21254
19356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2125419356
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2301817965
Short name T1846
Test name
Test status
Simulation time 145844361 ps
CPU time 0.84 seconds
Started Aug 08 06:16:32 PM PDT 24
Finished Aug 08 06:16:33 PM PDT 24
Peak memory 207564 kb
Host smart-3edfb7c4-dab6-4cdf-9acd-2d717e29dfe1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2301817965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2301817965
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2628323244
Short name T3470
Test name
Test status
Simulation time 153843516 ps
CPU time 0.86 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207516 kb
Host smart-bf32bc49-c76b-4bc9-b303-b8e23947a31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26283
23244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2628323244
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2319556343
Short name T2563
Test name
Test status
Simulation time 210316349 ps
CPU time 0.99 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207504 kb
Host smart-e9bbf240-5033-4bca-a5ba-8ec30b39d18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23195
56343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2319556343
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.919394050
Short name T1533
Test name
Test status
Simulation time 3610444744 ps
CPU time 36.25 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:17:10 PM PDT 24
Peak memory 217232 kb
Host smart-299d80f4-79ca-48b7-84fb-24d9a92784ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=919394050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.919394050
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2877823971
Short name T99
Test name
Test status
Simulation time 12621049598 ps
CPU time 95.66 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207812 kb
Host smart-fb23c17a-dfef-4790-b736-53da68388eb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2877823971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2877823971
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.984244622
Short name T2496
Test name
Test status
Simulation time 183288649 ps
CPU time 0.91 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207536 kb
Host smart-b1161611-c321-4d1a-842d-33608694f363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98424
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.984244622
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.762228207
Short name T46
Test name
Test status
Simulation time 28356294736 ps
CPU time 49.46 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:17:24 PM PDT 24
Peak memory 216188 kb
Host smart-a83c8528-cad6-438f-b879-2f43d8319cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76222
8207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.762228207
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.562070372
Short name T1240
Test name
Test status
Simulation time 5957484173 ps
CPU time 7.73 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:45 PM PDT 24
Peak memory 216244 kb
Host smart-85bac04d-15d9-4a79-aa07-2d2215b9797c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56207
0372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.562070372
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3953414559
Short name T2577
Test name
Test status
Simulation time 4166363694 ps
CPU time 114.51 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:18:29 PM PDT 24
Peak memory 218640 kb
Host smart-bc79d2b6-3bd0-41cc-9b52-319da6903428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
14559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3953414559
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2269529937
Short name T2003
Test name
Test status
Simulation time 2730271180 ps
CPU time 27.58 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 217800 kb
Host smart-b471e205-15c0-4c9b-91f4-913f101355c2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2269529937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2269529937
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.921456089
Short name T1108
Test name
Test status
Simulation time 252588318 ps
CPU time 1.06 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207556 kb
Host smart-050d9e78-1794-4f37-a257-cd95e8f5923d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=921456089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.921456089
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3907788768
Short name T1570
Test name
Test status
Simulation time 195639691 ps
CPU time 0.91 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207568 kb
Host smart-7385c707-0fda-4848-abe8-58594b2af6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39077
88768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3907788768
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.3106406502
Short name T2762
Test name
Test status
Simulation time 2756698864 ps
CPU time 80.44 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 216144 kb
Host smart-c1d7795f-1540-41e2-aee4-147ed79ef805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31064
06502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.3106406502
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3748441430
Short name T2453
Test name
Test status
Simulation time 2580065629 ps
CPU time 24.96 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 217320 kb
Host smart-05528f13-2045-4a68-ae1a-5940fafd4c27
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3748441430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3748441430
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1665551947
Short name T1122
Test name
Test status
Simulation time 158992701 ps
CPU time 0.84 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207596 kb
Host smart-4f551706-cbcd-467c-9985-f5845d7e03a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1665551947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1665551947
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.50477765
Short name T2283
Test name
Test status
Simulation time 139809009 ps
CPU time 0.83 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207540 kb
Host smart-56a7d0fe-0a16-4295-986d-e6d3afabe303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50477
765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.50477765
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1348917943
Short name T3582
Test name
Test status
Simulation time 170596347 ps
CPU time 0.95 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207608 kb
Host smart-966ed584-e78b-439b-b198-a4a067939001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
17943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1348917943
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.4151831978
Short name T251
Test name
Test status
Simulation time 180138790 ps
CPU time 0.88 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207528 kb
Host smart-d7e36997-8686-4ef4-9e9b-2c6a33212a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518
31978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.4151831978
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2690738830
Short name T747
Test name
Test status
Simulation time 174410737 ps
CPU time 0.87 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207520 kb
Host smart-73ff4111-d7d7-401c-b3fc-0bd7fbdbad2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
38830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2690738830
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1329339680
Short name T2290
Test name
Test status
Simulation time 167996221 ps
CPU time 0.83 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207592 kb
Host smart-2481c841-0f00-42b8-8054-24df1bb7659e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
39680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1329339680
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3503309551
Short name T2732
Test name
Test status
Simulation time 239301346 ps
CPU time 1.05 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207520 kb
Host smart-4076bfd0-74b5-4e11-a11b-64d4277c22d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3503309551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3503309551
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3699681932
Short name T1201
Test name
Test status
Simulation time 165381679 ps
CPU time 0.85 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207564 kb
Host smart-6f9807ef-2cf6-4ca8-9a74-df61d634a4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36996
81932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3699681932
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2773879257
Short name T1939
Test name
Test status
Simulation time 48211007 ps
CPU time 0.73 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207500 kb
Host smart-eee544db-3f18-4567-a60d-66ef0a401ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
79257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2773879257
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3907646699
Short name T2062
Test name
Test status
Simulation time 19767172517 ps
CPU time 49.32 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:17:23 PM PDT 24
Peak memory 216112 kb
Host smart-39068c5f-fe2c-49b6-9a90-5e055bba1bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39076
46699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3907646699
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3561837836
Short name T753
Test name
Test status
Simulation time 239945482 ps
CPU time 0.94 seconds
Started Aug 08 06:16:39 PM PDT 24
Finished Aug 08 06:16:41 PM PDT 24
Peak memory 207612 kb
Host smart-9af17dfc-64f5-4bc3-8f5d-2c0dba186de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35618
37836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3561837836
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.374472235
Short name T1860
Test name
Test status
Simulation time 231819379 ps
CPU time 1.01 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207500 kb
Host smart-e9640f0a-008b-4a75-a333-0efce2b53e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37447
2235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.374472235
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.481879362
Short name T2758
Test name
Test status
Simulation time 175837042 ps
CPU time 0.94 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207496 kb
Host smart-87d02265-5d26-427c-9fd7-e742ea505896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48187
9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.481879362
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1580127291
Short name T924
Test name
Test status
Simulation time 183515595 ps
CPU time 0.85 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207628 kb
Host smart-9929fe15-2ca9-463c-bed0-328b7b0e29fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15801
27291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1580127291
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.3704255037
Short name T1616
Test name
Test status
Simulation time 20176186703 ps
CPU time 27.06 seconds
Started Aug 08 06:16:31 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207580 kb
Host smart-57682d93-9fa0-4a32-b89f-ccd051b740b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042
55037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.3704255037
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1316220813
Short name T1582
Test name
Test status
Simulation time 145323977 ps
CPU time 0.84 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207440 kb
Host smart-e23507b6-60cc-4430-906f-98885145ceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13162
20813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1316220813
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.4098323725
Short name T3059
Test name
Test status
Simulation time 300482899 ps
CPU time 1.12 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207512 kb
Host smart-47b3b005-8a27-46bb-9d69-825d0ca818f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40983
23725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.4098323725
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2293024647
Short name T965
Test name
Test status
Simulation time 221656544 ps
CPU time 0.91 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207500 kb
Host smart-0d63557e-06e9-43c3-a681-df37ddfa9445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22930
24647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2293024647
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2463074939
Short name T460
Test name
Test status
Simulation time 168964342 ps
CPU time 0.87 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207664 kb
Host smart-0bbbcc8b-3b9a-4e3b-a2dc-ac3e18ffa78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
74939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2463074939
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4174878738
Short name T1049
Test name
Test status
Simulation time 200036842 ps
CPU time 0.98 seconds
Started Aug 08 06:16:41 PM PDT 24
Finished Aug 08 06:16:42 PM PDT 24
Peak memory 207508 kb
Host smart-59f4e686-f8c8-409f-b6b1-3a1f99447810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
78738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4174878738
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3752146585
Short name T3486
Test name
Test status
Simulation time 2281721095 ps
CPU time 18.24 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 218076 kb
Host smart-f313ddb5-12dc-4b45-a61e-6558eda1710d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3752146585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3752146585
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.583617963
Short name T3499
Test name
Test status
Simulation time 203677171 ps
CPU time 0.91 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207620 kb
Host smart-1964b711-e1af-4fe8-84d3-5b905725b49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58361
7963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.583617963
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3351448501
Short name T3084
Test name
Test status
Simulation time 186464704 ps
CPU time 0.92 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207592 kb
Host smart-a73bc850-0abe-4232-bf6f-55b908d49653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33514
48501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3351448501
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1952896983
Short name T2772
Test name
Test status
Simulation time 891013323 ps
CPU time 2.39 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:41 PM PDT 24
Peak memory 207780 kb
Host smart-b0f4c05f-039b-42b8-9f4a-2e6a816128a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
96983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1952896983
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2494737595
Short name T1387
Test name
Test status
Simulation time 1944975093 ps
CPU time 56.79 seconds
Started Aug 08 06:16:46 PM PDT 24
Finished Aug 08 06:17:43 PM PDT 24
Peak memory 215992 kb
Host smart-3a26e155-f8df-4aca-8e42-2e0eae5636ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
37595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2494737595
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.880156999
Short name T933
Test name
Test status
Simulation time 2000793514 ps
CPU time 17.29 seconds
Started Aug 08 06:16:25 PM PDT 24
Finished Aug 08 06:16:42 PM PDT 24
Peak memory 207756 kb
Host smart-210d8793-b1ba-4e57-a5ad-fe379e9433e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880156999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_host
_handshake.880156999
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.331355808
Short name T855
Test name
Test status
Simulation time 671855047 ps
CPU time 1.76 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207576 kb
Host smart-9f2376e7-e194-428c-9665-f55c23fe60e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331355808 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.331355808
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.2356191675
Short name T337
Test name
Test status
Simulation time 456919529 ps
CPU time 1.33 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207548 kb
Host smart-e20ef1ca-e33a-404d-86da-427847a67e0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2356191675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.2356191675
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.557893018
Short name T220
Test name
Test status
Simulation time 480780376 ps
CPU time 1.46 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207552 kb
Host smart-b565542b-fa9f-4f9e-bd6c-265175491791
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557893018 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.557893018
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.1659926984
Short name T427
Test name
Test status
Simulation time 427182470 ps
CPU time 1.27 seconds
Started Aug 08 06:21:34 PM PDT 24
Finished Aug 08 06:21:35 PM PDT 24
Peak memory 207516 kb
Host smart-f64144ce-61a0-4b1a-9f49-93cb312631cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1659926984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.1659926984
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.3410647013
Short name T1043
Test name
Test status
Simulation time 548743193 ps
CPU time 1.51 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207512 kb
Host smart-0fa978a7-41e6-4518-9ba0-474edbc2c2d5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410647013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.3410647013
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.1097833893
Short name T3400
Test name
Test status
Simulation time 962710309 ps
CPU time 2.04 seconds
Started Aug 08 06:21:55 PM PDT 24
Finished Aug 08 06:21:58 PM PDT 24
Peak memory 207496 kb
Host smart-415c7ae2-6eba-43d8-a704-33fa6906385f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1097833893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1097833893
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.512547077
Short name T1643
Test name
Test status
Simulation time 627504956 ps
CPU time 1.63 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207580 kb
Host smart-bc09822a-88d0-4651-a687-50905f10c678
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512547077 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.512547077
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.3743523750
Short name T373
Test name
Test status
Simulation time 617099136 ps
CPU time 1.69 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207488 kb
Host smart-841a7116-b635-47de-a293-156c8434b2c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3743523750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.3743523750
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.3208214131
Short name T164
Test name
Test status
Simulation time 532398954 ps
CPU time 1.54 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207528 kb
Host smart-c6de3891-e57c-43f3-8b6e-dbdd79d43b8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208214131 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.3208214131
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.3843298306
Short name T2908
Test name
Test status
Simulation time 248743531 ps
CPU time 1.05 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207620 kb
Host smart-eb7b647d-8dca-417e-b74d-23fcda73fda4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3843298306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.3843298306
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.3428498994
Short name T2372
Test name
Test status
Simulation time 620160625 ps
CPU time 1.61 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207572 kb
Host smart-63cb0cf2-2696-49d3-ac68-b8b9f53e2d5a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428498994 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.3428498994
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.81019001
Short name T466
Test name
Test status
Simulation time 191656053 ps
CPU time 0.91 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207608 kb
Host smart-5b0dc5c5-ba26-4d94-8652-3e0a6fd39cdb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=81019001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.81019001
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.997625859
Short name T2568
Test name
Test status
Simulation time 528287603 ps
CPU time 1.74 seconds
Started Aug 08 06:21:31 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207584 kb
Host smart-923765e2-94b0-44c0-a330-8c7515975317
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997625859 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.997625859
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.1123583291
Short name T2235
Test name
Test status
Simulation time 659821973 ps
CPU time 1.68 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207576 kb
Host smart-4fe3425a-9b94-435f-ba1d-c4d9aff853c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123583291 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.1123583291
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.2688131269
Short name T239
Test name
Test status
Simulation time 649525485 ps
CPU time 1.57 seconds
Started Aug 08 06:21:34 PM PDT 24
Finished Aug 08 06:21:36 PM PDT 24
Peak memory 207540 kb
Host smart-e75351c5-45a6-4c92-b557-b5ebb941565b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2688131269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.2688131269
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.3547478016
Short name T614
Test name
Test status
Simulation time 535584141 ps
CPU time 1.64 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207600 kb
Host smart-73894071-c1d8-4ada-b190-d4820302d381
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547478016 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.3547478016
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.3940396100
Short name T438
Test name
Test status
Simulation time 382355367 ps
CPU time 1.23 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207536 kb
Host smart-9028199e-e0f8-46dc-981a-6d843895adbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3940396100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.3940396100
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.3909249792
Short name T1004
Test name
Test status
Simulation time 588719883 ps
CPU time 1.66 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207572 kb
Host smart-0ca63879-d8c8-4c8a-8393-d43df52fc09b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909249792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.3909249792
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.844558
Short name T478
Test name
Test status
Simulation time 531859902 ps
CPU time 1.54 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207536 kb
Host smart-a2ef8a10-05c8-4051-9acd-4a3ea359c359
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=844558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.844558
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.235614873
Short name T3064
Test name
Test status
Simulation time 473447224 ps
CPU time 1.5 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207616 kb
Host smart-041ba047-f139-4713-b1cb-522165587ed2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235614873 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.235614873
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.692132378
Short name T3057
Test name
Test status
Simulation time 47833426 ps
CPU time 0.68 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207532 kb
Host smart-6fe790bf-07d9-44d3-aa7e-5c47ae21e0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=692132378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.692132378
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1740336838
Short name T3072
Test name
Test status
Simulation time 9799477966 ps
CPU time 13.37 seconds
Started Aug 08 06:16:43 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207804 kb
Host smart-0890590e-3005-4678-a6e0-4bd874e796cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740336838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.1740336838
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1547965893
Short name T218
Test name
Test status
Simulation time 20424290852 ps
CPU time 24.71 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207772 kb
Host smart-cc79375c-72c5-4108-9bcf-56764caf003e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547965893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1547965893
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.825796529
Short name T2485
Test name
Test status
Simulation time 30258346246 ps
CPU time 38.09 seconds
Started Aug 08 06:16:41 PM PDT 24
Finished Aug 08 06:17:19 PM PDT 24
Peak memory 207748 kb
Host smart-fa67da45-3346-4c18-a38e-237445e82cea
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825796529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_ao
n_wake_resume.825796529
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1958075050
Short name T1072
Test name
Test status
Simulation time 156424990 ps
CPU time 0.89 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207480 kb
Host smart-23ba9208-29ae-4c88-a5a4-a4186facc9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
75050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1958075050
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1555773023
Short name T2493
Test name
Test status
Simulation time 137991293 ps
CPU time 0.87 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207500 kb
Host smart-b786ac6e-9cf8-48b8-bd13-9e08c8e2db57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15557
73023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1555773023
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1240361531
Short name T3100
Test name
Test status
Simulation time 469523084 ps
CPU time 1.52 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207480 kb
Host smart-502ad141-602a-4780-a62c-9232b809f7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12403
61531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1240361531
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1437931861
Short name T504
Test name
Test status
Simulation time 744935337 ps
CPU time 2.27 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207748 kb
Host smart-30b2e8ad-5db2-40f7-a2a6-848d895d84dd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1437931861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1437931861
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.802710982
Short name T1245
Test name
Test status
Simulation time 27230424355 ps
CPU time 42.48 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207924 kb
Host smart-a689dc7d-ebc7-4490-bfce-bd9c21149845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80271
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.802710982
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.580114953
Short name T1244
Test name
Test status
Simulation time 413566770 ps
CPU time 7.63 seconds
Started Aug 08 06:16:42 PM PDT 24
Finished Aug 08 06:16:50 PM PDT 24
Peak memory 207664 kb
Host smart-9ee83896-6f56-463b-bfaa-6eedb42a0735
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580114953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.580114953
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.790846861
Short name T686
Test name
Test status
Simulation time 852331294 ps
CPU time 2.08 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207540 kb
Host smart-1f201401-b643-406c-b973-71d0ce19ce78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79084
6861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.790846861
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1395777999
Short name T3457
Test name
Test status
Simulation time 135877647 ps
CPU time 0.81 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207504 kb
Host smart-fa47a929-7aa4-48b2-93d5-ad31eea6fd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13957
77999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1395777999
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.617377010
Short name T2284
Test name
Test status
Simulation time 47439893 ps
CPU time 0.71 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207512 kb
Host smart-dbe60d33-c095-48df-b33a-a1382d691bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61737
7010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.617377010
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1879463335
Short name T2001
Test name
Test status
Simulation time 917894560 ps
CPU time 2.18 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207748 kb
Host smart-cc008f3b-7fdc-4ce2-9ef8-82691581b220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18794
63335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1879463335
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.3948146858
Short name T3286
Test name
Test status
Simulation time 457755976 ps
CPU time 1.36 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207588 kb
Host smart-c6469ef8-6a85-40e5-a703-6c8277a93607
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3948146858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.3948146858
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.269343925
Short name T2811
Test name
Test status
Simulation time 173635898 ps
CPU time 1.81 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207716 kb
Host smart-2534efb4-b890-4b22-af49-63fba9a9afde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
3925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.269343925
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.4031865445
Short name T3573
Test name
Test status
Simulation time 206280794 ps
CPU time 1.1 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 215964 kb
Host smart-77487408-ef9a-453a-a610-697ba1930709
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4031865445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.4031865445
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3173429415
Short name T1285
Test name
Test status
Simulation time 159341338 ps
CPU time 0.83 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207528 kb
Host smart-b90234e3-e5b7-485a-850d-ff1bbe12d09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734
29415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3173429415
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3912105042
Short name T1572
Test name
Test status
Simulation time 224491646 ps
CPU time 1.01 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207592 kb
Host smart-7440fbdd-3a96-4d48-a06f-1e60064efeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121
05042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3912105042
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.407325222
Short name T1879
Test name
Test status
Simulation time 4564387818 ps
CPU time 132.2 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 218024 kb
Host smart-5cbbac59-7cef-41d3-a08e-541cacd96ea1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=407325222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.407325222
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3391837622
Short name T975
Test name
Test status
Simulation time 8853928292 ps
CPU time 63.9 seconds
Started Aug 08 06:16:53 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207860 kb
Host smart-bac216ef-b215-477d-b74e-cd1447cdbaac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3391837622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3391837622
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2758858758
Short name T2675
Test name
Test status
Simulation time 243073281 ps
CPU time 1.07 seconds
Started Aug 08 06:16:48 PM PDT 24
Finished Aug 08 06:16:49 PM PDT 24
Peak memory 207592 kb
Host smart-f161e674-2d88-43d3-8037-b59a8ff90a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27588
58758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2758858758
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.857938442
Short name T2991
Test name
Test status
Simulation time 24977688292 ps
CPU time 31.79 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 216040 kb
Host smart-6d65323c-d89a-400a-b968-3639d33bd34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85793
8442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.857938442
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.16632698
Short name T2681
Test name
Test status
Simulation time 4003061564 ps
CPU time 6.51 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:43 PM PDT 24
Peak memory 207840 kb
Host smart-3723c594-fa5b-4f9a-aa08-39a4fa43bc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16632
698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.16632698
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1614242142
Short name T826
Test name
Test status
Simulation time 3102140037 ps
CPU time 24.28 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 217932 kb
Host smart-701449a2-e41d-4497-99eb-7e0b36aa916e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
42142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1614242142
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2775138514
Short name T1090
Test name
Test status
Simulation time 3132531594 ps
CPU time 91.68 seconds
Started Aug 08 06:16:41 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 217660 kb
Host smart-a9c55397-d119-4521-bf34-d15d833d91d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2775138514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2775138514
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3124688532
Short name T3094
Test name
Test status
Simulation time 274294323 ps
CPU time 1.12 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207588 kb
Host smart-f643d94e-b41d-44b7-8f9e-5c0729c81ee9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3124688532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3124688532
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1750282332
Short name T2983
Test name
Test status
Simulation time 193445224 ps
CPU time 0.91 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207596 kb
Host smart-2b0a3ec5-2015-45a3-8d92-e38314e444bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
82332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1750282332
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.3001941663
Short name T2680
Test name
Test status
Simulation time 3517901102 ps
CPU time 25.59 seconds
Started Aug 08 06:16:40 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207864 kb
Host smart-0070ab7b-7a7f-46e3-8a4b-3bd3cb5e457a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30019
41663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.3001941663
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3357355202
Short name T2031
Test name
Test status
Simulation time 4045371921 ps
CPU time 31.59 seconds
Started Aug 08 06:16:41 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 217764 kb
Host smart-9d495040-cb01-48fc-9fd5-6c8a316aee3a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3357355202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3357355202
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3379233460
Short name T576
Test name
Test status
Simulation time 164734909 ps
CPU time 0.9 seconds
Started Aug 08 06:16:53 PM PDT 24
Finished Aug 08 06:16:54 PM PDT 24
Peak memory 207564 kb
Host smart-f6f32012-c1df-432b-b793-d8a9486115f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3379233460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3379233460
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2957258361
Short name T286
Test name
Test status
Simulation time 159819815 ps
CPU time 0.84 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207544 kb
Host smart-37540f63-6a1e-4fba-92ad-2ce3660b136c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
58361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2957258361
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2803308160
Short name T1556
Test name
Test status
Simulation time 208355544 ps
CPU time 0.9 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207544 kb
Host smart-0dc3004e-d09a-48a9-9be7-274e288992c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
08160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2803308160
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.968646701
Short name T2910
Test name
Test status
Simulation time 167853240 ps
CPU time 0.9 seconds
Started Aug 08 06:16:42 PM PDT 24
Finished Aug 08 06:16:43 PM PDT 24
Peak memory 207604 kb
Host smart-1487d3c0-eefe-474a-ad30-8aad794df7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96864
6701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.968646701
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.530268612
Short name T2696
Test name
Test status
Simulation time 189401547 ps
CPU time 0.92 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207592 kb
Host smart-31c4db5f-2c61-4b3d-a2d3-6179f0e7f311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53026
8612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.530268612
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1873928791
Short name T1747
Test name
Test status
Simulation time 163803988 ps
CPU time 0.86 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207652 kb
Host smart-ceb700f5-2c1a-4414-b083-1281d61cd985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18739
28791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1873928791
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1696391064
Short name T1399
Test name
Test status
Simulation time 165937267 ps
CPU time 0.86 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207640 kb
Host smart-3a01d217-3f25-4586-8341-962743eb9101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16963
91064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1696391064
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.897739128
Short name T2032
Test name
Test status
Simulation time 245105486 ps
CPU time 1 seconds
Started Aug 08 06:16:42 PM PDT 24
Finished Aug 08 06:16:43 PM PDT 24
Peak memory 207580 kb
Host smart-5e3a9fa5-c8c6-41e8-bb6d-6e5a67b163ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=897739128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.897739128
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3634372324
Short name T212
Test name
Test status
Simulation time 141481475 ps
CPU time 0.85 seconds
Started Aug 08 06:16:47 PM PDT 24
Finished Aug 08 06:16:48 PM PDT 24
Peak memory 207480 kb
Host smart-b99f7d8e-7472-4a63-9b36-540cb8b2fbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36343
72324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3634372324
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.360453119
Short name T1981
Test name
Test status
Simulation time 55162877 ps
CPU time 0.71 seconds
Started Aug 08 06:16:41 PM PDT 24
Finished Aug 08 06:16:41 PM PDT 24
Peak memory 207492 kb
Host smart-568f320d-dd05-44fe-923a-c39cd384d959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
3119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.360453119
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.591870304
Short name T2409
Test name
Test status
Simulation time 7196509193 ps
CPU time 18.74 seconds
Started Aug 08 06:16:44 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 216072 kb
Host smart-2ce2d30f-da9a-4e5f-93f9-1588bf4ecac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59187
0304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.591870304
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.154926146
Short name T2695
Test name
Test status
Simulation time 192765172 ps
CPU time 0.93 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207516 kb
Host smart-f8eb55f8-ea57-4e0a-9db4-264670e0f315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
6146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.154926146
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.79612833
Short name T2272
Test name
Test status
Simulation time 213385993 ps
CPU time 1.06 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207600 kb
Host smart-dd0d7baa-4979-4145-971a-07f4587cd0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79612
833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.79612833
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2134577501
Short name T577
Test name
Test status
Simulation time 229460895 ps
CPU time 1.06 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207568 kb
Host smart-b2cf561a-0477-495e-b5ed-a76993f399fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345
77501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2134577501
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.781064364
Short name T3117
Test name
Test status
Simulation time 156780996 ps
CPU time 0.87 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207520 kb
Host smart-ade67dac-4a0a-4f65-baef-ec6888e5fcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78106
4364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.781064364
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.4146923024
Short name T2137
Test name
Test status
Simulation time 20175456046 ps
CPU time 23.88 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207652 kb
Host smart-b7051a0a-9a2c-47e0-bd14-bc0a1896f982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41469
23024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.4146923024
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2913437568
Short name T740
Test name
Test status
Simulation time 168418597 ps
CPU time 0.87 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207600 kb
Host smart-f684aade-e3d9-4c3a-b981-05d36fa6ea51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
37568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2913437568
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.2047081237
Short name T2241
Test name
Test status
Simulation time 264658475 ps
CPU time 1.09 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:35 PM PDT 24
Peak memory 207512 kb
Host smart-30f7c6a4-4b71-44a0-823b-cf10ee57ccd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470
81237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.2047081237
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4262479667
Short name T881
Test name
Test status
Simulation time 195956746 ps
CPU time 0.89 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:38 PM PDT 24
Peak memory 207512 kb
Host smart-df21cc96-7fe2-4b7e-a1d2-562fb15ff956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42624
79667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4262479667
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3173132688
Short name T2683
Test name
Test status
Simulation time 147799303 ps
CPU time 0.84 seconds
Started Aug 08 06:16:39 PM PDT 24
Finished Aug 08 06:16:40 PM PDT 24
Peak memory 207532 kb
Host smart-190bef0d-f3a4-48a9-a9ff-b6de8b1ed0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
32688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3173132688
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.7498924
Short name T2079
Test name
Test status
Simulation time 282339409 ps
CPU time 1.08 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:37 PM PDT 24
Peak memory 207592 kb
Host smart-df16c3bf-a764-47b3-8d6a-a57a2c058c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74989
24 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.7498924
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1014234543
Short name T2946
Test name
Test status
Simulation time 2703799728 ps
CPU time 75.72 seconds
Started Aug 08 06:16:40 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 216084 kb
Host smart-a51cedc4-9896-4cb8-9806-e3e320409bf1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1014234543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1014234543
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3700683618
Short name T3151
Test name
Test status
Simulation time 193419110 ps
CPU time 0.92 seconds
Started Aug 08 06:16:33 PM PDT 24
Finished Aug 08 06:16:34 PM PDT 24
Peak memory 207532 kb
Host smart-94391acc-f5b6-459b-8d79-e2806c3e2897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
83618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3700683618
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2054795400
Short name T3087
Test name
Test status
Simulation time 182195258 ps
CPU time 0.88 seconds
Started Aug 08 06:16:35 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207560 kb
Host smart-0eb48017-a46e-4a56-901d-012a8816cb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20547
95400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2054795400
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.206750510
Short name T531
Test name
Test status
Simulation time 793469148 ps
CPU time 2.04 seconds
Started Aug 08 06:16:45 PM PDT 24
Finished Aug 08 06:16:47 PM PDT 24
Peak memory 207500 kb
Host smart-b3ec7065-35e2-419c-a377-cb360204e652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675
0510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.206750510
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2932434584
Short name T1685
Test name
Test status
Simulation time 2983554213 ps
CPU time 82.1 seconds
Started Aug 08 06:16:39 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 217572 kb
Host smart-cf49304d-40e6-42c4-8b39-06ec1e862511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
34584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2932434584
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2800072899
Short name T2156
Test name
Test status
Simulation time 2042817625 ps
CPU time 17.84 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207720 kb
Host smart-7cbed086-26c2-436c-9b38-2f9c68d5ae62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800072899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.2800072899
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.3514360781
Short name T2403
Test name
Test status
Simulation time 491111647 ps
CPU time 1.71 seconds
Started Aug 08 06:16:34 PM PDT 24
Finished Aug 08 06:16:36 PM PDT 24
Peak memory 207636 kb
Host smart-854b6abb-51a1-4e87-a435-ee10c2235847
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514360781 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.3514360781
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.2080139241
Short name T416
Test name
Test status
Simulation time 722123930 ps
CPU time 1.73 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207504 kb
Host smart-3ef0993e-32a6-4de7-bbea-6fadff8810b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2080139241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.2080139241
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.9781754
Short name T1290
Test name
Test status
Simulation time 470556129 ps
CPU time 1.56 seconds
Started Aug 08 06:21:38 PM PDT 24
Finished Aug 08 06:21:40 PM PDT 24
Peak memory 207620 kb
Host smart-8ea7b91b-593f-46a1-b03e-6891c80a6495
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9781754 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.9781754
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.201523160
Short name T3006
Test name
Test status
Simulation time 245347232 ps
CPU time 1 seconds
Started Aug 08 06:21:52 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207484 kb
Host smart-c5bc3cc7-718e-49ee-ad4e-6ba7502bf7c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=201523160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.201523160
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.2626119182
Short name T2971
Test name
Test status
Simulation time 549399273 ps
CPU time 1.64 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207616 kb
Host smart-5cefc7b3-6d95-48d1-a533-0f4469523a3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626119182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.2626119182
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.307851233
Short name T2233
Test name
Test status
Simulation time 676711285 ps
CPU time 1.76 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207540 kb
Host smart-039a5f2e-5d35-467c-b06b-a77a319259e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307851233 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.307851233
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.2002233456
Short name T470
Test name
Test status
Simulation time 389744849 ps
CPU time 1.19 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207480 kb
Host smart-9eb71ba0-190f-4e63-b89e-c1c7901a688c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2002233456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.2002233456
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.582647990
Short name T659
Test name
Test status
Simulation time 500975528 ps
CPU time 1.53 seconds
Started Aug 08 06:21:52 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207524 kb
Host smart-f3a0d26f-e6d4-4f68-a0df-df970e188be1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582647990 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.582647990
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.694399369
Short name T424
Test name
Test status
Simulation time 441979747 ps
CPU time 1.26 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 207552 kb
Host smart-54a18a97-e870-4f35-aaa1-dced5fc60b02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=694399369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.694399369
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.1624352557
Short name T2105
Test name
Test status
Simulation time 607479452 ps
CPU time 1.64 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207528 kb
Host smart-04b478a6-20e7-4c0e-ac73-17948290b962
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624352557 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.1624352557
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.2600881493
Short name T442
Test name
Test status
Simulation time 270949735 ps
CPU time 1.02 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207592 kb
Host smart-0731ef76-6e0c-461b-9de2-2213f26b55ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2600881493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.2600881493
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.185694894
Short name T3477
Test name
Test status
Simulation time 585780244 ps
CPU time 1.64 seconds
Started Aug 08 06:21:36 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 207560 kb
Host smart-e3a952bc-4c50-4ff5-920f-36e2983b36d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185694894 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.185694894
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.2259095588
Short name T657
Test name
Test status
Simulation time 628534995 ps
CPU time 1.62 seconds
Started Aug 08 06:22:02 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 207628 kb
Host smart-210d5523-34ed-4c5f-ba9a-d7585021bfb6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259095588 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.2259095588
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.2675980663
Short name T3207
Test name
Test status
Simulation time 168925773 ps
CPU time 0.82 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:33 PM PDT 24
Peak memory 207484 kb
Host smart-544a65ed-39d1-4626-a707-75fccbaccff8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2675980663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2675980663
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.3285869003
Short name T3627
Test name
Test status
Simulation time 574241313 ps
CPU time 1.8 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207516 kb
Host smart-db52f4cd-fbf1-4f3c-95e4-d9f4c4ff9a6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285869003 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.3285869003
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.2174800374
Short name T336
Test name
Test status
Simulation time 295483181 ps
CPU time 1.07 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207592 kb
Host smart-fe32b715-a778-4b02-91b1-b3c4362c7ce1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2174800374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.2174800374
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.1411025895
Short name T2618
Test name
Test status
Simulation time 605986167 ps
CPU time 1.68 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207584 kb
Host smart-5274a012-b995-4d4d-bc2d-236f0a437b92
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411025895 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.1411025895
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.1504336223
Short name T428
Test name
Test status
Simulation time 364909620 ps
CPU time 1.23 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207592 kb
Host smart-c6a01c00-0ab7-4088-ad6f-58d5b831d6d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1504336223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.1504336223
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.3534752990
Short name T3399
Test name
Test status
Simulation time 681504696 ps
CPU time 1.84 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207620 kb
Host smart-836f47b1-0b79-4591-a44d-ee979d8e858d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534752990 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.3534752990
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1105696783
Short name T2047
Test name
Test status
Simulation time 85749044 ps
CPU time 0.76 seconds
Started Aug 08 06:16:50 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 207612 kb
Host smart-d54884c0-84d8-44fe-bff7-bc0717b25d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1105696783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1105696783
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1573263832
Short name T2958
Test name
Test status
Simulation time 4127920804 ps
CPU time 6.75 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:16:43 PM PDT 24
Peak memory 216028 kb
Host smart-31f6779b-5016-41e6-b073-ab45422ef912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573263832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1573263832
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2247525442
Short name T1077
Test name
Test status
Simulation time 18629263513 ps
CPU time 23.59 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207792 kb
Host smart-5ee54401-325e-41ab-9abb-2a7e56cdd7d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247525442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2247525442
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.440652089
Short name T2351
Test name
Test status
Simulation time 24604278435 ps
CPU time 31.99 seconds
Started Aug 08 06:16:36 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 216024 kb
Host smart-f37955bf-595b-4b70-96ff-2e46bb76eac1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440652089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.440652089
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.931284412
Short name T3192
Test name
Test status
Simulation time 251813322 ps
CPU time 1 seconds
Started Aug 08 06:16:37 PM PDT 24
Finished Aug 08 06:16:39 PM PDT 24
Peak memory 207488 kb
Host smart-f15d8686-d021-4e00-aae1-7ee6217d2888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93128
4412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.931284412
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3069348282
Short name T922
Test name
Test status
Simulation time 149573874 ps
CPU time 0.83 seconds
Started Aug 08 06:16:44 PM PDT 24
Finished Aug 08 06:16:45 PM PDT 24
Peak memory 207532 kb
Host smart-cd8bec3d-629d-46c4-a3ba-bf4da14c6073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
48282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3069348282
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.2514863621
Short name T2967
Test name
Test status
Simulation time 557346653 ps
CPU time 1.73 seconds
Started Aug 08 06:16:38 PM PDT 24
Finished Aug 08 06:16:40 PM PDT 24
Peak memory 207564 kb
Host smart-5715661a-0902-4651-ac0f-26217ac52d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25148
63621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.2514863621
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.381112816
Short name T601
Test name
Test status
Simulation time 1011042522 ps
CPU time 2.46 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207808 kb
Host smart-d5c742ea-7326-4429-9b94-03386824c438
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=381112816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.381112816
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3499214667
Short name T3199
Test name
Test status
Simulation time 50321523559 ps
CPU time 82.27 seconds
Started Aug 08 06:16:48 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207860 kb
Host smart-787d5b68-8bfa-4ab6-8d55-c84e88b21498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992
14667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3499214667
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1336029416
Short name T1416
Test name
Test status
Simulation time 2432074701 ps
CPU time 20.99 seconds
Started Aug 08 06:16:43 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207788 kb
Host smart-74352f6e-3842-47ab-b9d4-69a59686d675
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336029416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1336029416
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4217442160
Short name T931
Test name
Test status
Simulation time 1031675884 ps
CPU time 2.21 seconds
Started Aug 08 06:16:51 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207572 kb
Host smart-b1e88606-98b6-477e-9c59-d7442499e27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42174
42160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4217442160
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_enable.443154246
Short name T2237
Test name
Test status
Simulation time 32322469 ps
CPU time 0.71 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207484 kb
Host smart-0e4fceba-5ea6-4c46-ba4a-27d9777b05ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44315
4246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.443154246
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.769789597
Short name T757
Test name
Test status
Simulation time 1094835622 ps
CPU time 2.71 seconds
Started Aug 08 06:16:47 PM PDT 24
Finished Aug 08 06:16:50 PM PDT 24
Peak memory 207964 kb
Host smart-f1881509-4903-463d-a950-a34b41bdda08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76978
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.769789597
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.2349930174
Short name T434
Test name
Test status
Simulation time 513592840 ps
CPU time 1.38 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207512 kb
Host smart-cd065f8b-9e2a-4a54-b777-22dd56cc41ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2349930174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.2349930174
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.415346309
Short name T1907
Test name
Test status
Simulation time 229881575 ps
CPU time 1.96 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207680 kb
Host smart-80f23dee-b310-44eb-842b-80c254bb984f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
6309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.415346309
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3453225562
Short name T2844
Test name
Test status
Simulation time 249489789 ps
CPU time 1.2 seconds
Started Aug 08 06:16:50 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 215880 kb
Host smart-61350eb1-df7d-4675-8e35-6fc900ccbbca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3453225562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3453225562
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2115122696
Short name T700
Test name
Test status
Simulation time 140196897 ps
CPU time 0.89 seconds
Started Aug 08 06:16:48 PM PDT 24
Finished Aug 08 06:16:49 PM PDT 24
Peak memory 207516 kb
Host smart-b9b95461-41e6-40ba-bd71-7ce730c1c471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151
22696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2115122696
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.187020344
Short name T918
Test name
Test status
Simulation time 233827794 ps
CPU time 0.98 seconds
Started Aug 08 06:16:47 PM PDT 24
Finished Aug 08 06:16:48 PM PDT 24
Peak memory 207560 kb
Host smart-d2453753-8f0d-4b13-a2ae-146574ad638e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
0344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.187020344
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3087650961
Short name T2497
Test name
Test status
Simulation time 4949594716 ps
CPU time 39.31 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:40 PM PDT 24
Peak memory 218652 kb
Host smart-1b92fcb9-5a0e-4b4f-b550-271a968e1c1d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3087650961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3087650961
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3230095164
Short name T1854
Test name
Test status
Simulation time 5231843355 ps
CPU time 33.85 seconds
Started Aug 08 06:16:53 PM PDT 24
Finished Aug 08 06:17:27 PM PDT 24
Peak memory 207772 kb
Host smart-021330b1-d0c1-4db4-a5ff-69561e0e0871
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3230095164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3230095164
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2195660788
Short name T2829
Test name
Test status
Simulation time 206730619 ps
CPU time 0.93 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207604 kb
Host smart-96cdd15a-259f-4c6d-8304-f4f810b0de28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
60788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2195660788
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.2545663702
Short name T592
Test name
Test status
Simulation time 6130758408 ps
CPU time 10.23 seconds
Started Aug 08 06:16:59 PM PDT 24
Finished Aug 08 06:17:10 PM PDT 24
Peak memory 207868 kb
Host smart-ea6a965d-0999-472e-93db-3bdd31073d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25456
63702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.2545663702
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2786626961
Short name T1222
Test name
Test status
Simulation time 3561775115 ps
CPU time 5.33 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207792 kb
Host smart-c87804e4-0115-4b23-bd55-899f2c5260b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27866
26961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2786626961
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1776129744
Short name T1586
Test name
Test status
Simulation time 4610530361 ps
CPU time 130.19 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 218852 kb
Host smart-2bab4a6d-5887-4a13-a4d2-96fa089d9654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
29744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1776129744
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2190510664
Short name T3074
Test name
Test status
Simulation time 2067854086 ps
CPU time 56.02 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 216044 kb
Host smart-f83afa6a-fde6-4ee0-a9f1-64141b92de48
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2190510664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2190510664
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.961145203
Short name T2605
Test name
Test status
Simulation time 300136755 ps
CPU time 1.03 seconds
Started Aug 08 06:16:49 PM PDT 24
Finished Aug 08 06:16:50 PM PDT 24
Peak memory 207592 kb
Host smart-8185919c-f2d0-469a-a3bf-7ac534be0cec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=961145203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.961145203
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3847131793
Short name T241
Test name
Test status
Simulation time 188340704 ps
CPU time 0.99 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207528 kb
Host smart-0926286f-79f5-400f-8236-12b337754d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38471
31793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3847131793
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.2398776738
Short name T1712
Test name
Test status
Simulation time 1936333610 ps
CPU time 50.49 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 215948 kb
Host smart-76b00502-a0f5-4bc5-a4f6-47a9a82e6396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23987
76738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.2398776738
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2653134704
Short name T238
Test name
Test status
Simulation time 3255969004 ps
CPU time 97.14 seconds
Started Aug 08 06:16:44 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 216060 kb
Host smart-dd41a9e7-9646-4613-bb0a-7b1b25a13236
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2653134704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2653134704
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1161656626
Short name T3011
Test name
Test status
Simulation time 157554462 ps
CPU time 0.85 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207520 kb
Host smart-1dd4e120-ef00-46d2-a537-aa7c9aafad85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1161656626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1161656626
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1479296955
Short name T3526
Test name
Test status
Simulation time 139018477 ps
CPU time 0.83 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207520 kb
Host smart-ac3bcea5-1f14-43f5-bf0c-6d11d77f6053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
96955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1479296955
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1178801098
Short name T1873
Test name
Test status
Simulation time 193445139 ps
CPU time 0.95 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207508 kb
Host smart-b82b6702-dc78-4acb-9ba3-9a261e0aad40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788
01098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1178801098
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.863225819
Short name T3250
Test name
Test status
Simulation time 164765842 ps
CPU time 0.91 seconds
Started Aug 08 06:16:51 PM PDT 24
Finished Aug 08 06:16:52 PM PDT 24
Peak memory 207540 kb
Host smart-95e8b4e9-4cba-471e-80d2-d1cde0d27db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86322
5819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.863225819
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.329248617
Short name T971
Test name
Test status
Simulation time 171158802 ps
CPU time 0.92 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207540 kb
Host smart-d994b318-5dfa-45fa-b6a8-f5ce35f52bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32924
8617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.329248617
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.687325460
Short name T1458
Test name
Test status
Simulation time 183417846 ps
CPU time 0.91 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207472 kb
Host smart-070a99ec-70ef-40c8-9e4b-01a3420c6e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68732
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.687325460
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3227824218
Short name T2603
Test name
Test status
Simulation time 156283518 ps
CPU time 0.87 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207544 kb
Host smart-597dc620-d4eb-4247-8ce9-c0d4754d745c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278
24218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3227824218
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.504231787
Short name T2249
Test name
Test status
Simulation time 221935748 ps
CPU time 1 seconds
Started Aug 08 06:16:51 PM PDT 24
Finished Aug 08 06:16:52 PM PDT 24
Peak memory 207584 kb
Host smart-a16a3bec-b05e-4b48-9359-5f3ed2fad0d9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=504231787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.504231787
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.826780657
Short name T1765
Test name
Test status
Simulation time 149207364 ps
CPU time 0.83 seconds
Started Aug 08 06:16:43 PM PDT 24
Finished Aug 08 06:16:45 PM PDT 24
Peak memory 207440 kb
Host smart-53d7f2aa-a033-4a10-a390-060a34f3f6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82678
0657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.826780657
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3158247864
Short name T1805
Test name
Test status
Simulation time 42924648 ps
CPU time 0.7 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207528 kb
Host smart-ce06716b-53ed-4b59-8ac0-34f14e49cf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
47864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3158247864
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1830423392
Short name T1601
Test name
Test status
Simulation time 7753080110 ps
CPU time 18.74 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 216064 kb
Host smart-158b553c-97b2-4a79-b44b-fd0f242f4b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18304
23392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1830423392
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1266215678
Short name T3608
Test name
Test status
Simulation time 155636419 ps
CPU time 0.88 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207536 kb
Host smart-85890017-2608-4df0-b929-8b34c3472407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12662
15678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1266215678
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3596454170
Short name T1309
Test name
Test status
Simulation time 189114805 ps
CPU time 0.89 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207528 kb
Host smart-9c41f638-4b4a-4aaa-bcb6-381d4abd7e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964
54170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3596454170
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.4286934511
Short name T3259
Test name
Test status
Simulation time 219815806 ps
CPU time 1.01 seconds
Started Aug 08 06:16:50 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 207612 kb
Host smart-a945b459-ff00-4aa8-97d5-b0c8b6310f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42869
34511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.4286934511
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2126509624
Short name T1445
Test name
Test status
Simulation time 199928526 ps
CPU time 0.92 seconds
Started Aug 08 06:16:48 PM PDT 24
Finished Aug 08 06:16:50 PM PDT 24
Peak memory 207520 kb
Host smart-b710c175-05b1-4b31-baa2-002b167854c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
09624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2126509624
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.3558623020
Short name T1444
Test name
Test status
Simulation time 20168053316 ps
CPU time 29.2 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207640 kb
Host smart-50e5c539-0e44-4b20-a4fe-086e2cbcf224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35586
23020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.3558623020
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1981261477
Short name T2609
Test name
Test status
Simulation time 184545354 ps
CPU time 0.93 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207608 kb
Host smart-9e61045f-863a-4c23-999d-5eac90b8ca2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
61477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1981261477
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.2260546415
Short name T56
Test name
Test status
Simulation time 405478921 ps
CPU time 1.37 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207520 kb
Host smart-509b17c7-6696-453d-8277-4e7c4a9fcbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22605
46415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.2260546415
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1755687650
Short name T3018
Test name
Test status
Simulation time 170637678 ps
CPU time 0.93 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207512 kb
Host smart-d8f3f697-8d99-4bc9-81d8-a619e59dc91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17556
87650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1755687650
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2702876822
Short name T610
Test name
Test status
Simulation time 151704916 ps
CPU time 0.85 seconds
Started Aug 08 06:16:47 PM PDT 24
Finished Aug 08 06:16:48 PM PDT 24
Peak memory 207544 kb
Host smart-7007a364-11e1-4908-b9b2-5d21daa8f2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27028
76822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2702876822
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1854822996
Short name T3324
Test name
Test status
Simulation time 208470240 ps
CPU time 0.99 seconds
Started Aug 08 06:16:49 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 207628 kb
Host smart-b9d0f4c4-e138-49a2-886d-a8fe95583517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18548
22996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1854822996
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3168996697
Short name T2483
Test name
Test status
Simulation time 2018704024 ps
CPU time 14.43 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:17:11 PM PDT 24
Peak memory 215984 kb
Host smart-75b926ec-1431-4070-ad1b-4fa2bccc5345
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3168996697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3168996697
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.143286657
Short name T2733
Test name
Test status
Simulation time 175483074 ps
CPU time 0.88 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207508 kb
Host smart-b921bed1-3bad-4f50-9fb7-6061fca19ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14328
6657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.143286657
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3799645885
Short name T3346
Test name
Test status
Simulation time 184764380 ps
CPU time 0.86 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207564 kb
Host smart-d6cc34cd-7ee1-49c2-b2d1-a0de8f9ed8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
45885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3799645885
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.217964436
Short name T1687
Test name
Test status
Simulation time 739934248 ps
CPU time 1.97 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207516 kb
Host smart-65461265-09cc-4627-b18d-0c5ee205aa02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21796
4436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.217964436
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.2431877711
Short name T1115
Test name
Test status
Simulation time 3183966448 ps
CPU time 24.73 seconds
Started Aug 08 06:17:10 PM PDT 24
Finished Aug 08 06:17:35 PM PDT 24
Peak memory 216028 kb
Host smart-367b164c-c95a-45de-a9d9-1ad524d04884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24318
77711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2431877711
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.4111651121
Short name T685
Test name
Test status
Simulation time 1546979658 ps
CPU time 13.11 seconds
Started Aug 08 06:16:50 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207740 kb
Host smart-2af4d953-50d1-4e02-85fe-2a2066b0c086
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111651121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.4111651121
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.601045513
Short name T3373
Test name
Test status
Simulation time 512272828 ps
CPU time 1.51 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207564 kb
Host smart-cbfdd1d4-1e1f-4bff-83e6-c510c277803a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601045513 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.601045513
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.2907806274
Short name T2302
Test name
Test status
Simulation time 347265761 ps
CPU time 1.1 seconds
Started Aug 08 06:21:41 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207500 kb
Host smart-e5057794-41fc-4797-b31d-834890d31e3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2907806274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.2907806274
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.4013461361
Short name T2607
Test name
Test status
Simulation time 465088042 ps
CPU time 1.51 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207544 kb
Host smart-227c67fa-e798-4832-8175-6aedc9d763c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013461361 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.4013461361
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.1447725968
Short name T2464
Test name
Test status
Simulation time 259756706 ps
CPU time 1.08 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207556 kb
Host smart-daa45286-121b-45cf-a13c-205302db8fc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1447725968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.1447725968
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.2380425796
Short name T2961
Test name
Test status
Simulation time 533505260 ps
CPU time 1.53 seconds
Started Aug 08 06:22:03 PM PDT 24
Finished Aug 08 06:22:05 PM PDT 24
Peak memory 207624 kb
Host smart-d390a74f-89f3-4246-b710-1259a9f7edfd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380425796 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.2380425796
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.578832980
Short name T469
Test name
Test status
Simulation time 568326588 ps
CPU time 1.41 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207560 kb
Host smart-9eccf1eb-f94f-43ba-9561-c80eb571e79a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=578832980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.578832980
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.3063531930
Short name T2174
Test name
Test status
Simulation time 560700460 ps
CPU time 1.61 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207536 kb
Host smart-89ca18b8-8d88-4380-affa-0d103d2b8d83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063531930 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.3063531930
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.667432764
Short name T920
Test name
Test status
Simulation time 575173885 ps
CPU time 1.66 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207528 kb
Host smart-c021ab69-4490-4744-9692-9ea2f0d9d4d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667432764 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.667432764
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.2013905626
Short name T463
Test name
Test status
Simulation time 174288194 ps
CPU time 0.87 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207588 kb
Host smart-6dae05c5-71dc-4c05-9205-12ac0afb28e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2013905626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.2013905626
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.3056724230
Short name T1432
Test name
Test status
Simulation time 513277410 ps
CPU time 1.58 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207496 kb
Host smart-7fa6f884-28c8-4a89-a10d-db3e0983409c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056724230 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.3056724230
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.2245869100
Short name T270
Test name
Test status
Simulation time 297879911 ps
CPU time 1.01 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207556 kb
Host smart-1ace2b93-1058-45b7-9dfb-c1f5871b36aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2245869100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.2245869100
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.2726080180
Short name T194
Test name
Test status
Simulation time 437779302 ps
CPU time 1.41 seconds
Started Aug 08 06:22:08 PM PDT 24
Finished Aug 08 06:22:10 PM PDT 24
Peak memory 207616 kb
Host smart-1ec9b997-fdc8-43ff-ab74-d157918dc608
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726080180 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.2726080180
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.404825925
Short name T399
Test name
Test status
Simulation time 407165429 ps
CPU time 1.29 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207524 kb
Host smart-4339c513-592a-40ab-990d-bce89d4c7740
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=404825925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.404825925
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.3192294625
Short name T183
Test name
Test status
Simulation time 445291703 ps
CPU time 1.43 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207556 kb
Host smart-bf6bafea-e496-4ea0-b258-6cb648cd015d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192294625 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.3192294625
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.3768369293
Short name T433
Test name
Test status
Simulation time 376290915 ps
CPU time 1.23 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207632 kb
Host smart-02ba9070-a059-4a40-a153-415120bdf3d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3768369293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.3768369293
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.2590953343
Short name T2165
Test name
Test status
Simulation time 507898647 ps
CPU time 1.78 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207520 kb
Host smart-f7536149-92f2-441d-bb8f-ed8150e74ca3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590953343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.2590953343
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.1019141929
Short name T1343
Test name
Test status
Simulation time 269224082 ps
CPU time 1.01 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207528 kb
Host smart-facdd10d-462d-429d-a436-e28a3a899f4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1019141929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.1019141929
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.3168873576
Short name T1961
Test name
Test status
Simulation time 565361469 ps
CPU time 1.62 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207556 kb
Host smart-5aeeddff-a657-4347-ba26-86488c517a6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168873576 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.3168873576
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.1215619643
Short name T3010
Test name
Test status
Simulation time 141603840 ps
CPU time 0.85 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207632 kb
Host smart-11504706-71b6-493b-a451-8a7f80fa0c56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1215619643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.1215619643
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.1442816111
Short name T507
Test name
Test status
Simulation time 612364656 ps
CPU time 1.53 seconds
Started Aug 08 06:21:57 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207540 kb
Host smart-fcf0796b-c647-4bfd-b779-34660eb0cfb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442816111 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.1442816111
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2861228029
Short name T2527
Test name
Test status
Simulation time 40719210 ps
CPU time 0.69 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207556 kb
Host smart-acab6126-0fa2-40da-890c-5cfcf3d3cfad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2861228029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2861228029
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3950640463
Short name T2905
Test name
Test status
Simulation time 5635161914 ps
CPU time 7.39 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 216036 kb
Host smart-a08fa2b1-1c58-48a0-b916-4a9f4fcdf51b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950640463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.3950640463
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.154883231
Short name T2075
Test name
Test status
Simulation time 16364564703 ps
CPU time 19.79 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:52 PM PDT 24
Peak memory 215988 kb
Host smart-1da2f4b3-f506-4534-8624-3b18df2c999f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=154883231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.154883231
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.433486111
Short name T1865
Test name
Test status
Simulation time 24506924307 ps
CPU time 29.08 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 216084 kb
Host smart-22b648e1-caf6-4b11-8aba-b214d3fb50e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433486111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_resume.433486111
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.26761502
Short name T2591
Test name
Test status
Simulation time 157949219 ps
CPU time 0.89 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207592 kb
Host smart-bc8f36b8-5613-491a-8cc2-cf9a27aff788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26761
502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.26761502
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1392647859
Short name T61
Test name
Test status
Simulation time 182851044 ps
CPU time 0.9 seconds
Started Aug 08 06:13:33 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207524 kb
Host smart-5d59d1ab-d107-4c9c-8d39-df0f63c461c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13926
47859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1392647859
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1343120948
Short name T64
Test name
Test status
Simulation time 150009031 ps
CPU time 0.84 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207516 kb
Host smart-0aca236f-400c-4e7f-ac15-e68345cfffe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
20948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1343120948
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4106428892
Short name T87
Test name
Test status
Simulation time 151102737 ps
CPU time 0.82 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 207508 kb
Host smart-75754f2b-deaa-4ddd-858a-8359e5c58bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064
28892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4106428892
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.635977030
Short name T1773
Test name
Test status
Simulation time 307749520 ps
CPU time 1.27 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:13:40 PM PDT 24
Peak memory 207512 kb
Host smart-7d4107a5-836c-4f7a-9816-f96b76f8f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63597
7030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.635977030
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3697388839
Short name T2413
Test name
Test status
Simulation time 623431316 ps
CPU time 1.78 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 207528 kb
Host smart-f8cd4683-16f8-4752-a16b-0c4c08085487
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3697388839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3697388839
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1099881488
Short name T2922
Test name
Test status
Simulation time 51302835726 ps
CPU time 75.67 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 207920 kb
Host smart-41635176-1530-422a-8033-fdb9b602f3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
81488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1099881488
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.847358016
Short name T3297
Test name
Test status
Simulation time 1538834696 ps
CPU time 13.53 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207680 kb
Host smart-53987cf3-d545-42d5-82e7-d892abbe5cac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847358016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.847358016
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.191502364
Short name T2109
Test name
Test status
Simulation time 761016919 ps
CPU time 1.95 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:13:37 PM PDT 24
Peak memory 207524 kb
Host smart-35dfe313-ccdc-48a0-a8c1-ce9b8e8d9472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19150
2364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.191502364
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2937590702
Short name T2104
Test name
Test status
Simulation time 147892449 ps
CPU time 0.84 seconds
Started Aug 08 06:13:33 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207540 kb
Host smart-9f16c6ee-a0a3-4826-b79e-82c0be2a06d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
90702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2937590702
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.446725558
Short name T1036
Test name
Test status
Simulation time 60125468 ps
CPU time 0.79 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:13:36 PM PDT 24
Peak memory 207600 kb
Host smart-80d25be5-c681-45ea-9d24-176f0e8126cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44672
5558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.446725558
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2024599056
Short name T789
Test name
Test status
Simulation time 830901425 ps
CPU time 2.65 seconds
Started Aug 08 06:13:36 PM PDT 24
Finished Aug 08 06:13:39 PM PDT 24
Peak memory 207736 kb
Host smart-48a16703-6a2a-4a91-9569-db9548cc2993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
99056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2024599056
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.691404360
Short name T1754
Test name
Test status
Simulation time 396120293 ps
CPU time 2.73 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 207772 kb
Host smart-721bb2c9-fd15-4c01-91f4-bd150234e90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69140
4360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.691404360
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1121034906
Short name T3452
Test name
Test status
Simulation time 120244578889 ps
CPU time 214.09 seconds
Started Aug 08 06:13:38 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207808 kb
Host smart-27a03bec-ada5-47ca-8492-66b52cafde7f
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1121034906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1121034906
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.3210489451
Short name T2375
Test name
Test status
Simulation time 103355300370 ps
CPU time 168.74 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:16:23 PM PDT 24
Peak memory 207828 kb
Host smart-756e30c0-9b23-4960-98d2-87fb15a027b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210489451 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3210489451
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.3533788042
Short name T928
Test name
Test status
Simulation time 87108100403 ps
CPU time 160.78 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:16:16 PM PDT 24
Peak memory 207812 kb
Host smart-e9d24f06-fb82-4f33-9307-b82b7133387b
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3533788042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.3533788042
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1379694442
Short name T524
Test name
Test status
Simulation time 106967080186 ps
CPU time 153.07 seconds
Started Aug 08 06:13:38 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 207788 kb
Host smart-075664be-53da-454d-bf2f-0ba9f517e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379694442 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1379694442
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.573104064
Short name T1627
Test name
Test status
Simulation time 91150367896 ps
CPU time 131.78 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207784 kb
Host smart-1a1e9f22-15e0-4b2f-8c85-80c91c099c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57310
4064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.573104064
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.161922666
Short name T1787
Test name
Test status
Simulation time 214552115 ps
CPU time 1.04 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 215896 kb
Host smart-eeab2e08-2237-4b4b-a55a-3973c9802cf5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=161922666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.161922666
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.4087264797
Short name T1528
Test name
Test status
Simulation time 143556153 ps
CPU time 0.79 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 207500 kb
Host smart-ab0f9cb0-c4e2-4d09-9e11-5cd9b281b7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872
64797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.4087264797
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2794300494
Short name T1051
Test name
Test status
Simulation time 242153671 ps
CPU time 0.95 seconds
Started Aug 08 06:13:38 PM PDT 24
Finished Aug 08 06:13:39 PM PDT 24
Peak memory 207520 kb
Host smart-fa241f66-a354-46ea-8575-88f75338c670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
00494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2794300494
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.665752000
Short name T1778
Test name
Test status
Simulation time 3941106020 ps
CPU time 115.14 seconds
Started Aug 08 06:13:33 PM PDT 24
Finished Aug 08 06:15:29 PM PDT 24
Peak memory 216056 kb
Host smart-0d8333c1-449c-486f-8f5e-7d44c5ae867f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=665752000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.665752000
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.1905487405
Short name T3572
Test name
Test status
Simulation time 5035098966 ps
CPU time 35.96 seconds
Started Aug 08 06:13:35 PM PDT 24
Finished Aug 08 06:14:11 PM PDT 24
Peak memory 207776 kb
Host smart-429c5f08-4d3c-4e25-8f59-9a10dbb65616
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1905487405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1905487405
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2683107207
Short name T578
Test name
Test status
Simulation time 188614629 ps
CPU time 0.92 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 207556 kb
Host smart-2237e5fb-c620-4530-8897-0dc0fad2e8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26831
07207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2683107207
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1444720827
Short name T1356
Test name
Test status
Simulation time 28350538905 ps
CPU time 52.65 seconds
Started Aug 08 06:13:36 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207852 kb
Host smart-e6f36747-c69a-48f6-8855-9d6fff9d125c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
20827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1444720827
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3109440669
Short name T804
Test name
Test status
Simulation time 9822981854 ps
CPU time 11.6 seconds
Started Aug 08 06:13:38 PM PDT 24
Finished Aug 08 06:13:50 PM PDT 24
Peak memory 207844 kb
Host smart-736bbd4d-4429-46d4-820a-5d062a92c531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
40669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3109440669
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3751707866
Short name T2002
Test name
Test status
Simulation time 2423193092 ps
CPU time 21.95 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:57 PM PDT 24
Peak memory 217128 kb
Host smart-cfa54732-d136-4a1d-adc5-abd4a0d92027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37517
07866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3751707866
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3311336770
Short name T1542
Test name
Test status
Simulation time 4080975761 ps
CPU time 118.56 seconds
Started Aug 08 06:13:33 PM PDT 24
Finished Aug 08 06:15:32 PM PDT 24
Peak memory 216124 kb
Host smart-59c8c930-8e4c-45bc-b4c4-f1ae11179985
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3311336770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3311336770
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3450598104
Short name T1092
Test name
Test status
Simulation time 234441461 ps
CPU time 0.99 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:33 PM PDT 24
Peak memory 207520 kb
Host smart-cf51f100-b803-4b72-a2f7-c3db988f385d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3450598104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3450598104
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.295231889
Short name T1642
Test name
Test status
Simulation time 192515666 ps
CPU time 0.97 seconds
Started Aug 08 06:13:31 PM PDT 24
Finished Aug 08 06:13:32 PM PDT 24
Peak memory 207552 kb
Host smart-e4bac375-515e-49df-b191-b9f4bd299584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
1889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.295231889
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.1886629888
Short name T3390
Test name
Test status
Simulation time 2333858185 ps
CPU time 65.56 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 217704 kb
Host smart-c3c5d524-6b24-4188-b5eb-b2f24d5ddf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
29888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.1886629888
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.918083580
Short name T1511
Test name
Test status
Simulation time 2074033154 ps
CPU time 59.25 seconds
Started Aug 08 06:13:38 PM PDT 24
Finished Aug 08 06:14:37 PM PDT 24
Peak memory 217752 kb
Host smart-01585e28-1289-47f3-b58f-74e90531bf6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=918083580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.918083580
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1620925530
Short name T3124
Test name
Test status
Simulation time 2641018631 ps
CPU time 26.06 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:14:00 PM PDT 24
Peak memory 217640 kb
Host smart-8373a139-cb4e-4c06-9a72-d4ef976fc3d2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1620925530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1620925530
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.2547339838
Short name T1274
Test name
Test status
Simulation time 200261137 ps
CPU time 0.88 seconds
Started Aug 08 06:13:34 PM PDT 24
Finished Aug 08 06:13:35 PM PDT 24
Peak memory 207552 kb
Host smart-e30c3a53-49ab-4f8c-b2bf-38376e566c37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2547339838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.2547339838
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1843396966
Short name T2011
Test name
Test status
Simulation time 139927628 ps
CPU time 0.84 seconds
Started Aug 08 06:13:36 PM PDT 24
Finished Aug 08 06:13:37 PM PDT 24
Peak memory 207496 kb
Host smart-8c1a6772-1c77-4c25-b8ed-aab73d30d7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433
96966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1843396966
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.424243101
Short name T147
Test name
Test status
Simulation time 199943956 ps
CPU time 0.94 seconds
Started Aug 08 06:13:39 PM PDT 24
Finished Aug 08 06:13:40 PM PDT 24
Peak memory 207516 kb
Host smart-ffa918d3-f023-4227-bfb9-a7ab8d6692a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424
3101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.424243101
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1144008249
Short name T2979
Test name
Test status
Simulation time 225698024 ps
CPU time 0.94 seconds
Started Aug 08 06:13:31 PM PDT 24
Finished Aug 08 06:13:32 PM PDT 24
Peak memory 207568 kb
Host smart-6a1ccc7f-c723-4ce7-803d-e304f606c251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11440
08249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1144008249
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3110401887
Short name T2220
Test name
Test status
Simulation time 145268998 ps
CPU time 0.85 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207576 kb
Host smart-b8785f3d-ab82-4dec-a08c-796e8aa91f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
01887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3110401887
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.203130256
Short name T580
Test name
Test status
Simulation time 168149088 ps
CPU time 0.86 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207592 kb
Host smart-be80908c-a295-4a7b-aa85-4770d32cbb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
0256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.203130256
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2767579883
Short name T993
Test name
Test status
Simulation time 163807746 ps
CPU time 0.87 seconds
Started Aug 08 06:13:37 PM PDT 24
Finished Aug 08 06:13:38 PM PDT 24
Peak memory 207516 kb
Host smart-77a975a6-f3a0-4137-a4ea-39ece6d5cc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
79883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2767579883
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.612507368
Short name T1055
Test name
Test status
Simulation time 259326348 ps
CPU time 1.06 seconds
Started Aug 08 06:13:32 PM PDT 24
Finished Aug 08 06:13:34 PM PDT 24
Peak memory 207552 kb
Host smart-53ea6dbe-10c6-4ffc-be6b-e0248ea8eb0c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=612507368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.612507368
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3093762999
Short name T542
Test name
Test status
Simulation time 225962399 ps
CPU time 1.01 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207584 kb
Host smart-e760de9b-82bd-45c2-84ca-8cb5465b2f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
62999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3093762999
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.677911172
Short name T2321
Test name
Test status
Simulation time 141901294 ps
CPU time 0.82 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:44 PM PDT 24
Peak memory 207560 kb
Host smart-6d397e91-22d8-433b-a662-c5129ad4b3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67791
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.677911172
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1361553834
Short name T42
Test name
Test status
Simulation time 37207013 ps
CPU time 0.68 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207552 kb
Host smart-e8e1f8d3-d272-4784-a143-42cebeea4661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
53834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1361553834
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2905882733
Short name T2830
Test name
Test status
Simulation time 9215707114 ps
CPU time 23.18 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 216068 kb
Host smart-da5ad6c2-f7ee-4b02-8a63-2fe2bdb4e991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
82733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2905882733
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.477734971
Short name T3075
Test name
Test status
Simulation time 162934704 ps
CPU time 0.85 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207568 kb
Host smart-a9b1b45c-8036-495e-acb5-359f4dd9b4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47773
4971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.477734971
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3139586850
Short name T589
Test name
Test status
Simulation time 215182552 ps
CPU time 0.94 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207512 kb
Host smart-68ce0af1-0da3-4bfe-a448-56cfd6ac35b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31395
86850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3139586850
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.399745877
Short name T3633
Test name
Test status
Simulation time 6262846365 ps
CPU time 22.21 seconds
Started Aug 08 06:13:46 PM PDT 24
Finished Aug 08 06:14:09 PM PDT 24
Peak memory 224308 kb
Host smart-1927fac4-8e9f-4de3-96a6-4df9dd571eb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=399745877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.399745877
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3632807636
Short name T1499
Test name
Test status
Simulation time 3707511064 ps
CPU time 24 seconds
Started Aug 08 06:13:40 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 224332 kb
Host smart-0d6d1f2a-7af7-4751-a44e-8c701e07174b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3632807636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3632807636
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2080419282
Short name T3090
Test name
Test status
Simulation time 14583900826 ps
CPU time 313.67 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:18:56 PM PDT 24
Peak memory 218828 kb
Host smart-c782ffc8-948d-4b9b-870e-c8786ed7a79c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080419282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2080419282
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1443415701
Short name T3619
Test name
Test status
Simulation time 233223970 ps
CPU time 1.02 seconds
Started Aug 08 06:13:45 PM PDT 24
Finished Aug 08 06:13:46 PM PDT 24
Peak memory 207564 kb
Host smart-223b59c1-bcf5-4d11-acee-c1844cfa7341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
15701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1443415701
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.865688547
Short name T1613
Test name
Test status
Simulation time 164613491 ps
CPU time 0.93 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207604 kb
Host smart-ed18d153-0b56-4fcb-a9de-20f01deb620a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86568
8547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.865688547
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.1768555394
Short name T1401
Test name
Test status
Simulation time 20166486925 ps
CPU time 24.32 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 207624 kb
Host smart-dfe7ae1b-c36a-43b5-8360-018384729ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17685
55394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.1768555394
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1610246558
Short name T509
Test name
Test status
Simulation time 181216801 ps
CPU time 0.89 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207512 kb
Host smart-508d5703-9162-433f-b6d6-e3743cca652c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16102
46558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1610246558
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.91421336
Short name T1927
Test name
Test status
Simulation time 252650771 ps
CPU time 1.06 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207532 kb
Host smart-3f87edcc-2ea8-43bc-9304-233c3044291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91421
336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.91421336
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3827316096
Short name T79
Test name
Test status
Simulation time 162883636 ps
CPU time 0.86 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207592 kb
Host smart-881a744a-a992-4dc0-b4bb-0a2808bf02ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
16096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3827316096
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3146031738
Short name T231
Test name
Test status
Simulation time 537843529 ps
CPU time 1.44 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 224684 kb
Host smart-454bbd35-5f9f-48a2-bb23-7b2aa908045c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3146031738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3146031738
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1601494354
Short name T58
Test name
Test status
Simulation time 352586344 ps
CPU time 1.3 seconds
Started Aug 08 06:13:40 PM PDT 24
Finished Aug 08 06:13:41 PM PDT 24
Peak memory 207564 kb
Host smart-5cd4266a-146d-459f-ae50-c6ab86148558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
94354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1601494354
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1111524450
Short name T2932
Test name
Test status
Simulation time 319996993 ps
CPU time 1.08 seconds
Started Aug 08 06:13:45 PM PDT 24
Finished Aug 08 06:13:46 PM PDT 24
Peak memory 207560 kb
Host smart-14eef067-47cb-4a5a-b5a1-cc109114aa4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11115
24450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1111524450
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3116450276
Short name T3622
Test name
Test status
Simulation time 180202106 ps
CPU time 0.84 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207492 kb
Host smart-deae7a89-86af-451c-9ed3-cdfe8e64d22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
50276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3116450276
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3760187552
Short name T2345
Test name
Test status
Simulation time 189700830 ps
CPU time 0.87 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:44 PM PDT 24
Peak memory 207656 kb
Host smart-e3af799d-ef7b-43f5-a579-b6dfbaf8a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37601
87552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3760187552
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4050334743
Short name T1467
Test name
Test status
Simulation time 187636806 ps
CPU time 0.96 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207540 kb
Host smart-e6e2fa98-b6a0-4c58-9142-5fdd53c7d271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
34743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4050334743
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3300234887
Short name T3558
Test name
Test status
Simulation time 2961406431 ps
CPU time 29.82 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:14:12 PM PDT 24
Peak memory 218180 kb
Host smart-5ae73d7e-c984-4b9f-9355-f807bd82c253
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3300234887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3300234887
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.578847897
Short name T1704
Test name
Test status
Simulation time 192860220 ps
CPU time 0.92 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:44 PM PDT 24
Peak memory 207564 kb
Host smart-d3bb7799-a449-4844-b840-1a5273fd537b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57884
7897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.578847897
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1515440051
Short name T2570
Test name
Test status
Simulation time 197268061 ps
CPU time 0.88 seconds
Started Aug 08 06:13:44 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207564 kb
Host smart-08577c5b-27b1-444b-ab85-96bf05b0c02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154
40051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1515440051
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.4258811653
Short name T981
Test name
Test status
Simulation time 1131902163 ps
CPU time 2.63 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:46 PM PDT 24
Peak memory 207688 kb
Host smart-5a5a6b12-c82c-483a-b89f-ac5174939a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42588
11653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.4258811653
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3462478594
Short name T840
Test name
Test status
Simulation time 2323396170 ps
CPU time 67.47 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 224260 kb
Host smart-2ba0a57c-81c8-40d9-aaf8-1e81b1c921fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
78594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3462478594
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2788304743
Short name T110
Test name
Test status
Simulation time 8232025630 ps
CPU time 48.05 seconds
Started Aug 08 06:13:46 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 219888 kb
Host smart-421ab216-2e6d-4d49-adf7-f26d2fc0d85e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788304743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2788304743
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.122274370
Short name T1976
Test name
Test status
Simulation time 482806605 ps
CPU time 1.46 seconds
Started Aug 08 06:13:44 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207544 kb
Host smart-ee844097-8b9c-416b-b609-1eff52fa9cbd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122274370 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.122274370
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1645031916
Short name T2488
Test name
Test status
Simulation time 36828675 ps
CPU time 0.65 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207492 kb
Host smart-f188b054-ac17-47f1-811c-cd3e4724322f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1645031916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1645031916
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.351733262
Short name T3149
Test name
Test status
Simulation time 6541552757 ps
CPU time 10.23 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 216004 kb
Host smart-e0b33b2a-229e-414c-ac16-51b27f350243
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351733262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.351733262
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3142866105
Short name T735
Test name
Test status
Simulation time 14072252011 ps
CPU time 16.88 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 216044 kb
Host smart-c3baa2fe-c1cb-49f2-93fc-23fe983fb099
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142866105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3142866105
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.4262444211
Short name T1822
Test name
Test status
Simulation time 29684687366 ps
CPU time 37.74 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207080 kb
Host smart-31e900e7-11b8-4d22-ac6a-dd91432dae83
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262444211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.4262444211
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1214774136
Short name T746
Test name
Test status
Simulation time 149691549 ps
CPU time 0.85 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207556 kb
Host smart-f80d7e92-677c-4382-ae27-8d6a3fc7a73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
74136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1214774136
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.4016236182
Short name T3220
Test name
Test status
Simulation time 172653461 ps
CPU time 0.88 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207476 kb
Host smart-9df5c94a-274c-42d1-8e7b-8b36d76da9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40162
36182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.4016236182
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3513041574
Short name T677
Test name
Test status
Simulation time 454710379 ps
CPU time 1.62 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207524 kb
Host smart-8f649ddf-71d9-4847-9a7c-dbdd12e51bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35130
41574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3513041574
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2473337618
Short name T114
Test name
Test status
Simulation time 764869259 ps
CPU time 2.06 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207544 kb
Host smart-df0c76b2-9196-4fa3-8f23-14e77bbd7493
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2473337618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2473337618
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1871265599
Short name T3141
Test name
Test status
Simulation time 49188440974 ps
CPU time 71.69 seconds
Started Aug 08 06:16:53 PM PDT 24
Finished Aug 08 06:18:05 PM PDT 24
Peak memory 207808 kb
Host smart-91fee683-09c1-4082-b1ea-cb0e9da8d35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18712
65599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1871265599
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.967417904
Short name T3293
Test name
Test status
Simulation time 1127196743 ps
CPU time 24.97 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207724 kb
Host smart-2b8040b0-7afe-4a55-be1c-4f58199378d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967417904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.967417904
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1101016633
Short name T2308
Test name
Test status
Simulation time 948150707 ps
CPU time 2.13 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207548 kb
Host smart-7671d9da-e514-4e91-a2dd-c9e91f9ba86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11010
16633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1101016633
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2838229998
Short name T2692
Test name
Test status
Simulation time 132455412 ps
CPU time 0.78 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207516 kb
Host smart-a62aea6e-f058-4d0d-8849-e73102ba5490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28382
29998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2838229998
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.505977375
Short name T1351
Test name
Test status
Simulation time 43452494 ps
CPU time 0.71 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207504 kb
Host smart-97c84c35-6a6e-4468-bc67-7e5b71f75d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50597
7375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.505977375
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.839557545
Short name T2657
Test name
Test status
Simulation time 897007877 ps
CPU time 2.32 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207780 kb
Host smart-9567ff82-380e-4b31-bab6-71f9a44803d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83955
7545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.839557545
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.3212686819
Short name T431
Test name
Test status
Simulation time 293731802 ps
CPU time 1.2 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207496 kb
Host smart-69a15cce-eeaf-47b1-987b-0ffba2458f26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3212686819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.3212686819
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2278464963
Short name T91
Test name
Test status
Simulation time 263053235 ps
CPU time 1.83 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207324 kb
Host smart-d1e35d77-9da4-4bbe-826f-d4240c102b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22784
64963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2278464963
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2759506170
Short name T3201
Test name
Test status
Simulation time 207306332 ps
CPU time 0.99 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 215956 kb
Host smart-659b586c-92b6-46c9-a4f0-b193c67e9d99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2759506170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2759506170
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4007155937
Short name T761
Test name
Test status
Simulation time 145636863 ps
CPU time 0.78 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207556 kb
Host smart-f4cc10e9-2428-4ad6-8a65-d82672a86449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40071
55937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4007155937
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3919224336
Short name T1707
Test name
Test status
Simulation time 222040072 ps
CPU time 1 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207508 kb
Host smart-58c851b5-3a3b-4d55-a653-23b086086753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39192
24336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3919224336
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2656161008
Short name T1008
Test name
Test status
Simulation time 4064790372 ps
CPU time 33.22 seconds
Started Aug 08 06:16:49 PM PDT 24
Finished Aug 08 06:17:23 PM PDT 24
Peak memory 218448 kb
Host smart-042b11e7-15be-4d9a-98f5-3a50d3d163e7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2656161008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2656161008
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2598718915
Short name T3185
Test name
Test status
Simulation time 6501477246 ps
CPU time 47.48 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207792 kb
Host smart-fed23f88-35ca-42fa-81e5-a3a864307352
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2598718915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2598718915
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1278592893
Short name T1825
Test name
Test status
Simulation time 268796636 ps
CPU time 1.05 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207536 kb
Host smart-5b7fcc76-169b-400f-84de-b724041f98b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12785
92893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1278592893
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.455691424
Short name T2242
Test name
Test status
Simulation time 32145348414 ps
CPU time 49.22 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 207856 kb
Host smart-8157d6e3-0dde-4d19-8da2-e8001d11b412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45569
1424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.455691424
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3498355325
Short name T1042
Test name
Test status
Simulation time 3528462588 ps
CPU time 5.48 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207740 kb
Host smart-1a6cb52f-08a6-45ad-bea4-aefe932a3480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34983
55325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3498355325
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1975279508
Short name T3567
Test name
Test status
Simulation time 3563476496 ps
CPU time 99.4 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 223784 kb
Host smart-a1cb100e-b82e-40ab-90fd-74ac60625dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19752
79508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1975279508
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.4088514798
Short name T1449
Test name
Test status
Simulation time 2835963599 ps
CPU time 26.7 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:27 PM PDT 24
Peak memory 217812 kb
Host smart-fd3ce05a-419c-44c8-9116-63772677ef6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4088514798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.4088514798
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1088574819
Short name T1065
Test name
Test status
Simulation time 234882175 ps
CPU time 0.98 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207560 kb
Host smart-bf06f755-269c-486b-82e0-d28dc489af11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1088574819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1088574819
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2944205359
Short name T3215
Test name
Test status
Simulation time 189626053 ps
CPU time 0.96 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207544 kb
Host smart-d726ecf0-c9d4-44d1-8bbe-e8f418c2eea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
05359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2944205359
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.3076604509
Short name T2876
Test name
Test status
Simulation time 2572927154 ps
CPU time 69.39 seconds
Started Aug 08 06:16:59 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 217880 kb
Host smart-6c93d18b-6e4f-4f8a-9935-52cfbb67f3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
04509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.3076604509
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1472546946
Short name T1523
Test name
Test status
Simulation time 2520795102 ps
CPU time 24.36 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:24 PM PDT 24
Peak memory 217928 kb
Host smart-ebf8202c-7731-4519-9b67-4a24fbfdac58
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1472546946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1472546946
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.317619167
Short name T1547
Test name
Test status
Simulation time 149383388 ps
CPU time 0.84 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207596 kb
Host smart-2e39ac98-4029-45c1-97a9-d2406ba56f3c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=317619167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.317619167
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.589964653
Short name T643
Test name
Test status
Simulation time 214297041 ps
CPU time 0.89 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 206888 kb
Host smart-90b989ba-f9be-469e-98c4-d57d84db8eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58996
4653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.589964653
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2115121016
Short name T141
Test name
Test status
Simulation time 179023534 ps
CPU time 0.87 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:56 PM PDT 24
Peak memory 207516 kb
Host smart-a63e118a-1247-4995-84ad-d0c1b2730946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151
21016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2115121016
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.826917333
Short name T3047
Test name
Test status
Simulation time 150573922 ps
CPU time 0.86 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207648 kb
Host smart-a601c729-b63e-4980-b0aa-fed7a8754bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82691
7333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.826917333
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.185405053
Short name T3030
Test name
Test status
Simulation time 163995827 ps
CPU time 0.84 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:16:53 PM PDT 24
Peak memory 207516 kb
Host smart-c16ee190-97af-4152-9263-66e547b93c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
5053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.185405053
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1583167424
Short name T1295
Test name
Test status
Simulation time 157285799 ps
CPU time 0.82 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207508 kb
Host smart-643b0eb9-5e2c-40bd-94ea-31b95efefa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15831
67424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1583167424
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2212629811
Short name T3317
Test name
Test status
Simulation time 176005561 ps
CPU time 0.87 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207512 kb
Host smart-d7703fc3-77a4-43c3-b052-96cbf1edef6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
29811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2212629811
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.881061921
Short name T1602
Test name
Test status
Simulation time 271725744 ps
CPU time 1 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207588 kb
Host smart-52bc4428-7429-451d-b344-1992f0790c44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=881061921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.881061921
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.307824923
Short name T1532
Test name
Test status
Simulation time 142445146 ps
CPU time 0.85 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207468 kb
Host smart-87bdc1cc-3dcb-4b4c-a30e-a6155bcb0b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
4923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.307824923
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.236228970
Short name T3574
Test name
Test status
Simulation time 55283239 ps
CPU time 0.73 seconds
Started Aug 08 06:16:56 PM PDT 24
Finished Aug 08 06:16:57 PM PDT 24
Peak memory 207564 kb
Host smart-fd77a3e5-8894-4e54-a32f-092e387a77ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23622
8970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.236228970
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1332261442
Short name T1782
Test name
Test status
Simulation time 9333766809 ps
CPU time 25.35 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 216020 kb
Host smart-b9b47aca-9ce1-4bfe-93d1-725674d20501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
61442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1332261442
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.685095566
Short name T1313
Test name
Test status
Simulation time 163978960 ps
CPU time 0.91 seconds
Started Aug 08 06:16:59 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207500 kb
Host smart-9689b591-df75-41a3-b9e8-a5242701c839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68509
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.685095566
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2412314755
Short name T1102
Test name
Test status
Simulation time 170801339 ps
CPU time 0.89 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:16:59 PM PDT 24
Peak memory 207644 kb
Host smart-98709fcb-5763-4c4c-8194-adc38d815020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24123
14755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2412314755
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.2209530719
Short name T233
Test name
Test status
Simulation time 240045282 ps
CPU time 1 seconds
Started Aug 08 06:17:05 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207512 kb
Host smart-24f1cbd6-233b-4e29-89f6-bf25d3a43e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095
30719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.2209530719
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.852804978
Short name T2951
Test name
Test status
Simulation time 245971134 ps
CPU time 1.02 seconds
Started Aug 08 06:16:52 PM PDT 24
Finished Aug 08 06:16:54 PM PDT 24
Peak memory 207620 kb
Host smart-5fc7cec2-86bb-47ee-9d1e-a558fb97c6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85280
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.852804978
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3366944805
Short name T3039
Test name
Test status
Simulation time 145041165 ps
CPU time 0.81 seconds
Started Aug 08 06:16:55 PM PDT 24
Finished Aug 08 06:16:55 PM PDT 24
Peak memory 207472 kb
Host smart-1203888a-338d-4859-a2f9-0ecd634294b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33669
44805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3366944805
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.102434884
Short name T655
Test name
Test status
Simulation time 351990575 ps
CPU time 1.38 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207504 kb
Host smart-f2ee4482-92eb-45f7-a780-d544d0639729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10243
4884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.102434884
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1983004990
Short name T472
Test name
Test status
Simulation time 141443013 ps
CPU time 0.85 seconds
Started Aug 08 06:16:48 PM PDT 24
Finished Aug 08 06:16:49 PM PDT 24
Peak memory 207556 kb
Host smart-9a027d88-d0ad-48ba-9ca6-942bcb91d85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19830
04990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1983004990
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2317705112
Short name T2309
Test name
Test status
Simulation time 150108340 ps
CPU time 0.84 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207552 kb
Host smart-1282a809-2981-4e59-8213-65cb12d532c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23177
05112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2317705112
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1625026326
Short name T3605
Test name
Test status
Simulation time 207390591 ps
CPU time 1 seconds
Started Aug 08 06:16:57 PM PDT 24
Finished Aug 08 06:16:58 PM PDT 24
Peak memory 207544 kb
Host smart-8b22a436-4425-4203-a617-c70c070c300f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
26326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1625026326
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1871887909
Short name T2314
Test name
Test status
Simulation time 2103492271 ps
CPU time 20.64 seconds
Started Aug 08 06:16:54 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 224044 kb
Host smart-bdc59461-e90d-4b4d-8986-702b9d85101e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1871887909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1871887909
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1017242059
Short name T969
Test name
Test status
Simulation time 191865918 ps
CPU time 0.9 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207556 kb
Host smart-d5d8f58b-6ef4-48b3-ba7b-d48544e10e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
42059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1017242059
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3838081975
Short name T2849
Test name
Test status
Simulation time 802015770 ps
CPU time 1.89 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207588 kb
Host smart-5a63ef02-78bd-4d33-873e-817b5f8433da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38380
81975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3838081975
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3232306253
Short name T551
Test name
Test status
Simulation time 3691490919 ps
CPU time 107.86 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 217488 kb
Host smart-000ec4f6-512b-4c38-b137-ff6671692365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32323
06253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3232306253
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.4084079193
Short name T1634
Test name
Test status
Simulation time 478220855 ps
CPU time 8.19 seconds
Started Aug 08 06:16:58 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207724 kb
Host smart-3641e50b-1814-48a8-9c9b-d6b614becc8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084079193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.4084079193
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2296749153
Short name T1936
Test name
Test status
Simulation time 508026262 ps
CPU time 1.64 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207584 kb
Host smart-cf23338b-8bde-4307-8a21-077b8b799229
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296749153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2296749153
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.3144664445
Short name T3386
Test name
Test status
Simulation time 456440702 ps
CPU time 1.41 seconds
Started Aug 08 06:21:54 PM PDT 24
Finished Aug 08 06:21:56 PM PDT 24
Peak memory 207616 kb
Host smart-eb362f68-4854-4244-9202-962e84f72f77
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144664445 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.3144664445
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.3220232348
Short name T2689
Test name
Test status
Simulation time 589807312 ps
CPU time 1.55 seconds
Started Aug 08 06:21:58 PM PDT 24
Finished Aug 08 06:22:00 PM PDT 24
Peak memory 207584 kb
Host smart-d7f3094e-8794-4d59-9971-19c166e633e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220232348 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.3220232348
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.1611867414
Short name T1720
Test name
Test status
Simulation time 504546339 ps
CPU time 1.7 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207520 kb
Host smart-86d9bbb1-2eb0-4fb0-a57a-a0eb738cb7e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611867414 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.1611867414
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.1758634875
Short name T3417
Test name
Test status
Simulation time 565398974 ps
CPU time 1.61 seconds
Started Aug 08 06:22:03 PM PDT 24
Finished Aug 08 06:22:05 PM PDT 24
Peak memory 207660 kb
Host smart-17cbb4d4-af04-44b7-b21b-ad636b3d6369
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758634875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.1758634875
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.3623678978
Short name T2868
Test name
Test status
Simulation time 451282111 ps
CPU time 1.44 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:57 PM PDT 24
Peak memory 207556 kb
Host smart-c3a89c30-e3c0-409c-aff4-1ab2e04dc20d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623678978 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.3623678978
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.4219547934
Short name T1302
Test name
Test status
Simulation time 465707409 ps
CPU time 1.42 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 207580 kb
Host smart-662d497b-627f-45b7-b42b-874e328b5e53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219547934 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.4219547934
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.1237810359
Short name T1359
Test name
Test status
Simulation time 475497119 ps
CPU time 1.46 seconds
Started Aug 08 06:22:04 PM PDT 24
Finished Aug 08 06:22:06 PM PDT 24
Peak memory 207540 kb
Host smart-84f15f71-2004-4cde-9168-e5561c2b62f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237810359 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.1237810359
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.1052539517
Short name T2369
Test name
Test status
Simulation time 496171919 ps
CPU time 1.48 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207552 kb
Host smart-8db199c4-f523-41ba-890b-c6a3812e5a27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052539517 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.1052539517
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.1124102972
Short name T2296
Test name
Test status
Simulation time 682888487 ps
CPU time 1.73 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207520 kb
Host smart-ce5196bd-e2da-4aac-b86f-2a694586cfc8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124102972 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.1124102972
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.3224197576
Short name T1113
Test name
Test status
Simulation time 506388318 ps
CPU time 1.56 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207588 kb
Host smart-9f850710-69d7-4e87-ac39-6e07c826bc99
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224197576 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.3224197576
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2876181919
Short name T805
Test name
Test status
Simulation time 74564393 ps
CPU time 0.71 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207524 kb
Host smart-4c08987b-1fb4-40be-a1ab-18107cdf898a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2876181919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2876181919
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.401289755
Short name T3236
Test name
Test status
Simulation time 3858471482 ps
CPU time 6.34 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 215992 kb
Host smart-5ac6fbca-8d0d-43c6-addd-02d53823ed85
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401289755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_disconnect.401289755
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3441627854
Short name T2914
Test name
Test status
Simulation time 19452047525 ps
CPU time 23.95 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207824 kb
Host smart-1978db22-994b-4cff-9f26-39e48c84b9c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441627854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3441627854
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1871130162
Short name T2933
Test name
Test status
Simulation time 25197556939 ps
CPU time 34 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:37 PM PDT 24
Peak memory 216036 kb
Host smart-949acd3d-4136-45e8-89c9-4180758f43b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871130162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1871130162
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2092076854
Short name T1208
Test name
Test status
Simulation time 206008345 ps
CPU time 0.94 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 207532 kb
Host smart-048acede-65fa-4235-b5fb-32dacc1c085f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
76854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2092076854
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3506945689
Short name T3380
Test name
Test status
Simulation time 146362866 ps
CPU time 0.85 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207520 kb
Host smart-7db1aac4-28e7-4f0f-ac6d-7a5e52ebc665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
45689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3506945689
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.731147033
Short name T3171
Test name
Test status
Simulation time 354240367 ps
CPU time 1.34 seconds
Started Aug 08 06:17:16 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207512 kb
Host smart-d7092e27-d9b1-47c0-8a5c-5b6e90068ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73114
7033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.731147033
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3547164775
Short name T2602
Test name
Test status
Simulation time 1183856389 ps
CPU time 2.82 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207736 kb
Host smart-2b78b5bb-f2ee-4feb-8a4a-be70aec4fae2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3547164775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3547164775
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3148742467
Short name T1507
Test name
Test status
Simulation time 34935649836 ps
CPU time 51.19 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207816 kb
Host smart-70b2982e-f312-422e-80a5-4302e356b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31487
42467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3148742467
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.4116569527
Short name T2825
Test name
Test status
Simulation time 908126504 ps
CPU time 18.41 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:24 PM PDT 24
Peak memory 207720 kb
Host smart-173522ba-9c7e-485d-be1c-697e115e0716
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116569527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.4116569527
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2544778263
Short name T1454
Test name
Test status
Simulation time 508523266 ps
CPU time 1.44 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207752 kb
Host smart-e1aa339c-6743-4b53-a0e7-b3687b472fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
78263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2544778263
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2546744463
Short name T835
Test name
Test status
Simulation time 149416581 ps
CPU time 0.81 seconds
Started Aug 08 06:17:08 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207520 kb
Host smart-45be0d61-ed7d-4c1e-95b0-b14fd0550c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25467
44463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2546744463
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3353717272
Short name T2191
Test name
Test status
Simulation time 34042272 ps
CPU time 0.74 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207400 kb
Host smart-3b4c7f7d-1671-47f6-beec-3b34b49a9716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33537
17272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3353717272
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.4059220039
Short name T2893
Test name
Test status
Simulation time 760514239 ps
CPU time 2.33 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207716 kb
Host smart-fe079726-ac8e-443b-aebc-4524ee638bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40592
20039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.4059220039
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.2592622951
Short name T2147
Test name
Test status
Simulation time 253767366 ps
CPU time 1.03 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207508 kb
Host smart-0fb6d272-f71a-416f-9571-324a39e5a193
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2592622951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.2592622951
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.56939900
Short name T1520
Test name
Test status
Simulation time 322980564 ps
CPU time 2.54 seconds
Started Aug 08 06:17:04 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207720 kb
Host smart-c1a6d5ec-e936-4def-8814-5577e44428f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56939
900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.56939900
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3191240796
Short name T987
Test name
Test status
Simulation time 190112812 ps
CPU time 0.97 seconds
Started Aug 08 06:17:05 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 215880 kb
Host smart-dc093ed3-c250-4b87-b94a-c7a33f4dad7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3191240796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3191240796
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.3739245599
Short name T785
Test name
Test status
Simulation time 208844389 ps
CPU time 0.87 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207524 kb
Host smart-a2c9ef13-3969-4a17-8636-0b3545ed6bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37392
45599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.3739245599
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1690426881
Short name T1368
Test name
Test status
Simulation time 176802307 ps
CPU time 0.96 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207620 kb
Host smart-393f1ee6-9e80-4ad5-9dbf-5d6aeccbcfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
26881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1690426881
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1079166867
Short name T1230
Test name
Test status
Simulation time 5891022166 ps
CPU time 169.77 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 217416 kb
Host smart-d935e433-4df7-44fb-bda7-cd8ac4d64e3c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1079166867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1079166867
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.834934378
Short name T1680
Test name
Test status
Simulation time 4506168790 ps
CPU time 32.46 seconds
Started Aug 08 06:17:08 PM PDT 24
Finished Aug 08 06:17:41 PM PDT 24
Peak memory 207856 kb
Host smart-2e9c5dd8-0082-4008-9c47-d12b37c1f1b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=834934378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.834934378
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2146285909
Short name T1856
Test name
Test status
Simulation time 216215430 ps
CPU time 0.95 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207560 kb
Host smart-b52b6fe4-7252-4990-9e65-90a45ddf99bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
85909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2146285909
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2153936389
Short name T1169
Test name
Test status
Simulation time 9847939898 ps
CPU time 15.68 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207844 kb
Host smart-5b351c8f-279b-4289-892e-898e3c6c21f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
36389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2153936389
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.579736676
Short name T1814
Test name
Test status
Simulation time 10461190211 ps
CPU time 13.56 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207832 kb
Host smart-9764b441-c25e-43f7-b66c-df55790dc67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57973
6676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.579736676
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1142780346
Short name T2275
Test name
Test status
Simulation time 4888804467 ps
CPU time 48.93 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 224388 kb
Host smart-0eb1c1bf-0edf-40bc-aac9-8efc3313793c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
80346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1142780346
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1836156309
Short name T2528
Test name
Test status
Simulation time 2596456130 ps
CPU time 71.32 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 216108 kb
Host smart-c07a00ba-8a15-46ba-a3e0-6660f1e5fdd8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1836156309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1836156309
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.729014598
Short name T1985
Test name
Test status
Simulation time 244480010 ps
CPU time 1.05 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 207556 kb
Host smart-d2b70da7-2761-44bb-912e-9e86c39458e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=729014598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.729014598
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.455634310
Short name T2182
Test name
Test status
Simulation time 208433159 ps
CPU time 0.95 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207572 kb
Host smart-3b389372-230e-4737-bf88-0c17843b596a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45563
4310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.455634310
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.1494382216
Short name T821
Test name
Test status
Simulation time 2396194819 ps
CPU time 69.21 seconds
Started Aug 08 06:17:10 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 224184 kb
Host smart-55977a6a-202b-492c-acbf-127a800eaff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14943
82216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.1494382216
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2511940289
Short name T3322
Test name
Test status
Simulation time 2008900448 ps
CPU time 55.08 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:18:04 PM PDT 24
Peak memory 224028 kb
Host smart-597d9600-0bc0-4d43-80c0-7a0f9acbf38b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2511940289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2511940289
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1928451439
Short name T3560
Test name
Test status
Simulation time 160491909 ps
CPU time 0.91 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 207648 kb
Host smart-57c086dd-ad0d-41ad-ab9d-cedd5fba0e33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1928451439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1928451439
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.494347618
Short name T3069
Test name
Test status
Simulation time 185758852 ps
CPU time 0.89 seconds
Started Aug 08 06:16:59 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207604 kb
Host smart-d2623568-93f8-42cc-aec4-d0545eda1f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49434
7618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.494347618
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3173403002
Short name T627
Test name
Test status
Simulation time 167083299 ps
CPU time 0.87 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207508 kb
Host smart-6cb2a43d-27a5-4fee-bd3b-f9006c8d356e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734
03002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3173403002
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2735644323
Short name T2306
Test name
Test status
Simulation time 192367643 ps
CPU time 0.89 seconds
Started Aug 08 06:17:04 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 207560 kb
Host smart-f16e906d-31bf-46bf-81fe-f0a47f3e5358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27356
44323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2735644323
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.117516245
Short name T2866
Test name
Test status
Simulation time 191374873 ps
CPU time 0.98 seconds
Started Aug 08 06:17:10 PM PDT 24
Finished Aug 08 06:17:11 PM PDT 24
Peak memory 207608 kb
Host smart-81b74153-9a52-405d-bb1b-fa538ff32004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
6245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.117516245
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1739677644
Short name T1453
Test name
Test status
Simulation time 169452199 ps
CPU time 0.89 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:08 PM PDT 24
Peak memory 207656 kb
Host smart-50803ecf-0082-4ded-bbee-d582da435859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17396
77644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1739677644
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1483241466
Short name T619
Test name
Test status
Simulation time 196196443 ps
CPU time 0.97 seconds
Started Aug 08 06:16:59 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207664 kb
Host smart-3946e397-db35-4e8e-8926-aa421241f892
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1483241466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1483241466
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.458624208
Short name T2466
Test name
Test status
Simulation time 144680144 ps
CPU time 0.79 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207588 kb
Host smart-3bfd91bc-33a3-4846-a182-ea46a853ec22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45862
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.458624208
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1650030393
Short name T2865
Test name
Test status
Simulation time 37794189 ps
CPU time 0.7 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207532 kb
Host smart-84c2f0f6-5b39-4e31-817f-f6220a4f617f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16500
30393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1650030393
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1266020608
Short name T2617
Test name
Test status
Simulation time 23162137458 ps
CPU time 59.55 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:18:05 PM PDT 24
Peak memory 216108 kb
Host smart-3700e935-b6ef-4455-8652-929859f672cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
20608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1266020608
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2656364024
Short name T1670
Test name
Test status
Simulation time 217839739 ps
CPU time 0.92 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207568 kb
Host smart-45848889-57a8-4ea3-8c50-08e4eda90556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26563
64024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2656364024
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.742294070
Short name T586
Test name
Test status
Simulation time 220109342 ps
CPU time 0.98 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207512 kb
Host smart-bc7efc92-2d74-474f-be77-0ef44189fea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74229
4070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.742294070
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.886670236
Short name T1024
Test name
Test status
Simulation time 227119083 ps
CPU time 0.99 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:08 PM PDT 24
Peak memory 207564 kb
Host smart-0bff58b2-f989-4e34-85d6-a8194a947e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88667
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.886670236
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1901682178
Short name T1007
Test name
Test status
Simulation time 166833840 ps
CPU time 0.9 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:02 PM PDT 24
Peak memory 207552 kb
Host smart-583e7135-8780-4fce-8f58-95295754db67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19016
82178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1901682178
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.4186041762
Short name T1330
Test name
Test status
Simulation time 255731605 ps
CPU time 1.1 seconds
Started Aug 08 06:17:04 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 207560 kb
Host smart-5af3542a-b396-4d10-ae07-d55e0e96790e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41860
41762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.4186041762
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2237093862
Short name T2564
Test name
Test status
Simulation time 157100089 ps
CPU time 0.85 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:07 PM PDT 24
Peak memory 207556 kb
Host smart-2c10ee19-e4fc-4af4-ba09-719cf63cb404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22370
93862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2237093862
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2229797758
Short name T2673
Test name
Test status
Simulation time 154797302 ps
CPU time 0.84 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:05 PM PDT 24
Peak memory 207592 kb
Host smart-77aa309f-20ff-4fdf-b956-73af1146a996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22297
97758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2229797758
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2614515600
Short name T3351
Test name
Test status
Simulation time 241931083 ps
CPU time 1.03 seconds
Started Aug 08 06:17:08 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207564 kb
Host smart-a0e37c74-b5c2-44d3-b529-fc6c669e66fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26145
15600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2614515600
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1715466724
Short name T2154
Test name
Test status
Simulation time 2733869665 ps
CPU time 79.99 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 216120 kb
Host smart-633f571a-2e33-4bb5-8052-4d0cecc84610
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1715466724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1715466724
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2974309243
Short name T1749
Test name
Test status
Simulation time 206555228 ps
CPU time 0.99 seconds
Started Aug 08 06:17:18 PM PDT 24
Finished Aug 08 06:17:19 PM PDT 24
Peak memory 207572 kb
Host smart-453370e0-7867-458b-922b-a7cf75dbce68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29743
09243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2974309243
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1201460477
Short name T626
Test name
Test status
Simulation time 152700634 ps
CPU time 0.85 seconds
Started Aug 08 06:17:16 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 207556 kb
Host smart-33a73cc7-ffaf-4210-88af-20262044c209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014
60477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1201460477
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.2668797430
Short name T688
Test name
Test status
Simulation time 1030409268 ps
CPU time 2.61 seconds
Started Aug 08 06:17:03 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207676 kb
Host smart-abe84d5a-b675-4f14-8567-46a5a7ec18fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
97430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2668797430
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.120175190
Short name T1991
Test name
Test status
Simulation time 2623402935 ps
CPU time 73.08 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:18:31 PM PDT 24
Peak memory 216124 kb
Host smart-6b688913-bcc7-46d0-9b95-929b6b43f9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.120175190
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1949005973
Short name T1040
Test name
Test status
Simulation time 1116889712 ps
CPU time 26.56 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207824 kb
Host smart-d5fc943f-b51e-47cf-be2a-35899482213c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949005973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1949005973
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.3111871646
Short name T1304
Test name
Test status
Simulation time 503719262 ps
CPU time 1.56 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207512 kb
Host smart-8b2aa959-7b42-498f-a39c-38b44700096d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111871646 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.3111871646
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.801825113
Short name T3191
Test name
Test status
Simulation time 494809092 ps
CPU time 1.5 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207600 kb
Host smart-040d0753-e267-4754-8efe-12e283b18769
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801825113 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.801825113
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.1433123250
Short name T2170
Test name
Test status
Simulation time 404356024 ps
CPU time 1.36 seconds
Started Aug 08 06:21:55 PM PDT 24
Finished Aug 08 06:21:57 PM PDT 24
Peak memory 207544 kb
Host smart-f72749be-0cd4-4d2f-a24c-397f89e7f4ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433123250 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.1433123250
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.1289347478
Short name T2884
Test name
Test status
Simulation time 723153819 ps
CPU time 1.87 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207612 kb
Host smart-3322ec2a-d291-4439-82ac-f6042c22272d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289347478 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.1289347478
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.3351230510
Short name T1923
Test name
Test status
Simulation time 496771531 ps
CPU time 1.64 seconds
Started Aug 08 06:21:57 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207584 kb
Host smart-dd1fd717-aa73-4471-b973-f33891d3ec9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351230510 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.3351230510
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.2839568367
Short name T1810
Test name
Test status
Simulation time 481783789 ps
CPU time 1.64 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207548 kb
Host smart-ed3200f6-c471-4948-b521-6168eebba861
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839568367 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.2839568367
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.390837108
Short name T1223
Test name
Test status
Simulation time 592911743 ps
CPU time 1.66 seconds
Started Aug 08 06:22:01 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 207564 kb
Host smart-b29c6c0a-3205-488b-99fe-76a5da0c4bc8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390837108 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.390837108
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.4193003998
Short name T221
Test name
Test status
Simulation time 480855553 ps
CPU time 1.48 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207548 kb
Host smart-5b5b612f-9266-45e6-9b84-d201058736b7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193003998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.4193003998
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.3578667559
Short name T1931
Test name
Test status
Simulation time 508663955 ps
CPU time 1.59 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207600 kb
Host smart-c51c54a0-bd4b-4d5e-9894-67c92b495d7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578667559 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.3578667559
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.605033488
Short name T2126
Test name
Test status
Simulation time 569111826 ps
CPU time 1.6 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207584 kb
Host smart-ac8089d6-9f5c-42c2-b08b-ccb846978b27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605033488 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.605033488
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.2878908787
Short name T927
Test name
Test status
Simulation time 461562679 ps
CPU time 1.46 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207548 kb
Host smart-c1156d7e-12e5-469c-8a9a-7576670c3c36
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878908787 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.2878908787
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.397167542
Short name T2329
Test name
Test status
Simulation time 76611440 ps
CPU time 0.68 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207560 kb
Host smart-5445e9b4-20c2-44a3-841a-705f888ba672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=397167542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.397167542
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1822969577
Short name T2511
Test name
Test status
Simulation time 6853766515 ps
CPU time 9.33 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:28 PM PDT 24
Peak memory 215988 kb
Host smart-b5550777-79f0-4ee0-a6cb-0befd8c6dc2a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822969577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.1822969577
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3192257592
Short name T16
Test name
Test status
Simulation time 21178527976 ps
CPU time 28.64 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:44 PM PDT 24
Peak memory 207776 kb
Host smart-4fab4919-f68b-4f97-bcbb-272279edc63b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192257592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3192257592
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.34740426
Short name T3209
Test name
Test status
Simulation time 28620081934 ps
CPU time 36.5 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207812 kb
Host smart-c3af4f0f-b4da-43db-9e35-d2dfe4ae9417
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34740426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon
_wake_resume.34740426
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4166296342
Short name T3537
Test name
Test status
Simulation time 177982876 ps
CPU time 0.89 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207576 kb
Host smart-7437109e-df5e-4607-b979-05a282cda90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41662
96342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4166296342
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3948079249
Short name T85
Test name
Test status
Simulation time 158506844 ps
CPU time 0.84 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207544 kb
Host smart-ca9ebb09-9557-4fe6-aeda-895663709637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
79249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3948079249
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2192676612
Short name T3076
Test name
Test status
Simulation time 473933466 ps
CPU time 1.59 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:19 PM PDT 24
Peak memory 207508 kb
Host smart-218f3dbc-de39-43e5-b743-69450ea2827a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21926
76612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2192676612
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2485867060
Short name T2823
Test name
Test status
Simulation time 1417196529 ps
CPU time 3.51 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207788 kb
Host smart-d71ea4ef-f8e4-4282-b1ab-cbc07c54d5c9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2485867060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2485867060
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2810363032
Short name T3505
Test name
Test status
Simulation time 54548950491 ps
CPU time 87.6 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:18:35 PM PDT 24
Peak memory 207888 kb
Host smart-c28a330e-8243-4293-afbd-8b8dce630e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28103
63032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2810363032
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.3731139178
Short name T2831
Test name
Test status
Simulation time 580776444 ps
CPU time 11.33 seconds
Started Aug 08 06:17:08 PM PDT 24
Finished Aug 08 06:17:19 PM PDT 24
Peak memory 207632 kb
Host smart-edb61083-151a-4065-bda5-5dc46850bb06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731139178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.3731139178
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1997870420
Short name T2096
Test name
Test status
Simulation time 770583109 ps
CPU time 1.87 seconds
Started Aug 08 06:17:16 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207492 kb
Host smart-89ef4c4a-958a-422a-a67e-1ae7bec7cf30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19978
70420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1997870420
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1988260906
Short name T1672
Test name
Test status
Simulation time 136400339 ps
CPU time 0.86 seconds
Started Aug 08 06:17:00 PM PDT 24
Finished Aug 08 06:17:01 PM PDT 24
Peak memory 207524 kb
Host smart-13b36c1e-08cb-4280-965f-1b3201977d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19882
60906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1988260906
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1360769404
Short name T565
Test name
Test status
Simulation time 37356076 ps
CPU time 0.73 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:03 PM PDT 24
Peak memory 207524 kb
Host smart-89fb057b-e02e-4054-ad36-297521962f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607
69404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1360769404
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.873870745
Short name T3034
Test name
Test status
Simulation time 974473106 ps
CPU time 2.55 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:09 PM PDT 24
Peak memory 207756 kb
Host smart-1d8e1306-64ac-4144-b257-bd42e928f8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87387
0745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.873870745
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.2006355988
Short name T454
Test name
Test status
Simulation time 290850754 ps
CPU time 1.1 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207464 kb
Host smart-6889a4b0-f7e7-4618-bdb7-2e54ad20a0ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2006355988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.2006355988
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1315415092
Short name T1409
Test name
Test status
Simulation time 206015348 ps
CPU time 1.43 seconds
Started Aug 08 06:17:02 PM PDT 24
Finished Aug 08 06:17:04 PM PDT 24
Peak memory 207704 kb
Host smart-6a231507-fc62-45fd-8a17-7d3aac51c53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13154
15092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1315415092
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.4212742031
Short name T1155
Test name
Test status
Simulation time 225511332 ps
CPU time 1.13 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 215944 kb
Host smart-9083e9c4-9396-441a-a006-109a4afb4b64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4212742031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.4212742031
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3856242580
Short name T3580
Test name
Test status
Simulation time 156696313 ps
CPU time 0.85 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:06 PM PDT 24
Peak memory 207556 kb
Host smart-f55d8745-da81-4910-8390-5a11c80413e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
42580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3856242580
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2153999902
Short name T3442
Test name
Test status
Simulation time 236853490 ps
CPU time 1.05 seconds
Started Aug 08 06:17:07 PM PDT 24
Finished Aug 08 06:17:08 PM PDT 24
Peak memory 207544 kb
Host smart-bbbffc96-e758-4936-a072-eaf41532f1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
99902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2153999902
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2001977704
Short name T163
Test name
Test status
Simulation time 5472658182 ps
CPU time 157.75 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 217916 kb
Host smart-838db662-c82b-42af-a897-32197e5d51c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2001977704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2001977704
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.3299199917
Short name T1924
Test name
Test status
Simulation time 3484462989 ps
CPU time 42.99 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 207832 kb
Host smart-d1e7c880-495e-451c-bafd-123c149c2e5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3299199917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.3299199917
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2250708920
Short name T2328
Test name
Test status
Simulation time 268672479 ps
CPU time 1.03 seconds
Started Aug 08 06:17:09 PM PDT 24
Finished Aug 08 06:17:11 PM PDT 24
Peak memory 207572 kb
Host smart-995408fc-9f82-4f21-a47f-577c49a31553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22507
08920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2250708920
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3851623604
Short name T2265
Test name
Test status
Simulation time 27228560407 ps
CPU time 30.27 seconds
Started Aug 08 06:17:01 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 215956 kb
Host smart-caf6def8-f593-4e2f-b109-3c02b03cc6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38516
23604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3851623604
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1280143117
Short name T2215
Test name
Test status
Simulation time 10946834597 ps
CPU time 13.03 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207816 kb
Host smart-3ad626ef-80fa-4126-8226-98678f075793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
43117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1280143117
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.4108967147
Short name T3436
Test name
Test status
Simulation time 3742989706 ps
CPU time 28.16 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 224224 kb
Host smart-5bf83566-db2e-4251-8d80-079a103d3de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
67147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.4108967147
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3795049075
Short name T2433
Test name
Test status
Simulation time 2747219652 ps
CPU time 27.45 seconds
Started Aug 08 06:17:22 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 224184 kb
Host smart-d5d05485-d1b8-4c57-8e1f-fad2d8a813e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3795049075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3795049075
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3462091793
Short name T597
Test name
Test status
Simulation time 263257904 ps
CPU time 0.98 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207544 kb
Host smart-679e8531-0025-4702-8252-fbd7d60de93d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3462091793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3462091793
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3183885519
Short name T1446
Test name
Test status
Simulation time 219089496 ps
CPU time 0.98 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207564 kb
Host smart-97a05d6d-340f-4f1c-a762-69bd6037fa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
85519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3183885519
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.2268560805
Short name T913
Test name
Test status
Simulation time 2409346544 ps
CPU time 65.7 seconds
Started Aug 08 06:17:10 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 218036 kb
Host smart-ec991dee-9ad1-45e7-926b-dd886074289c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
60805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.2268560805
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3865320778
Short name T591
Test name
Test status
Simulation time 2625929816 ps
CPU time 74.76 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 224240 kb
Host smart-7adab6e3-6c1d-4f75-a0e5-2f6334eb2c9c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3865320778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3865320778
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.4262617145
Short name T2660
Test name
Test status
Simulation time 206105773 ps
CPU time 0.95 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207516 kb
Host smart-677e9ec6-0894-4fa2-91ce-ea5f8b8f41cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4262617145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.4262617145
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1642534458
Short name T1798
Test name
Test status
Simulation time 143765888 ps
CPU time 0.84 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 207572 kb
Host smart-1f64d841-b50f-49ad-87c8-f8ae1a4e2aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
34458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1642534458
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1443339521
Short name T3337
Test name
Test status
Simulation time 194438994 ps
CPU time 0.9 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207512 kb
Host smart-e3724d2d-0675-4068-80e1-fd4e508dffc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14433
39521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1443339521
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.4015443533
Short name T608
Test name
Test status
Simulation time 142774834 ps
CPU time 0.84 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207508 kb
Host smart-71a057d5-16b1-41a1-b514-c9a11bf52486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
43533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.4015443533
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.132194721
Short name T1729
Test name
Test status
Simulation time 200973626 ps
CPU time 0.94 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207596 kb
Host smart-66c1b12d-433c-403e-bbdc-d83fe35acac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13219
4721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.132194721
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4283703808
Short name T2980
Test name
Test status
Simulation time 161750178 ps
CPU time 0.85 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 207560 kb
Host smart-5fe9eaae-b5c5-4466-9e54-cfaa929fad71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42837
03808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4283703808
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.324265573
Short name T806
Test name
Test status
Simulation time 198011981 ps
CPU time 0.92 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207568 kb
Host smart-f5afe98b-c846-40a5-ac49-25371f85ea2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32426
5573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.324265573
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1214591156
Short name T1828
Test name
Test status
Simulation time 227642598 ps
CPU time 1.09 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:22 PM PDT 24
Peak memory 207504 kb
Host smart-c50ab615-9981-4c5b-8ccf-9e3255b1eb59
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1214591156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1214591156
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4245377277
Short name T3395
Test name
Test status
Simulation time 148805283 ps
CPU time 0.82 seconds
Started Aug 08 06:17:24 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207512 kb
Host smart-70e1090b-6c65-43dd-a85f-0615d2a9b6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
77277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4245377277
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3041627822
Short name T925
Test name
Test status
Simulation time 39156049 ps
CPU time 0.69 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207592 kb
Host smart-af487160-44f8-418e-9d51-57362bdd9c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30416
27822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3041627822
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.733715191
Short name T296
Test name
Test status
Simulation time 22230522908 ps
CPU time 59.88 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 216032 kb
Host smart-9f6c3193-c5f1-445e-a1ec-b6a163581f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73371
5191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.733715191
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.397417549
Short name T1032
Test name
Test status
Simulation time 189000298 ps
CPU time 0.9 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207592 kb
Host smart-9a27c944-4dba-424c-8d67-893a6e1b9aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741
7549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.397417549
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3245333917
Short name T2495
Test name
Test status
Simulation time 218199230 ps
CPU time 0.94 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207584 kb
Host smart-c4de42c9-aa70-43d9-ba65-dec27d55f88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453
33917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3245333917
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2261610297
Short name T1271
Test name
Test status
Simulation time 191889730 ps
CPU time 0.98 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207552 kb
Host smart-6a05ca0a-ee8e-40d1-8977-c04bf3d2bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
10297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2261610297
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.4270270958
Short name T3579
Test name
Test status
Simulation time 219050988 ps
CPU time 1.04 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:17:22 PM PDT 24
Peak memory 207588 kb
Host smart-a9c92424-a8c4-4b4b-aa91-ac3b378268a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
70958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.4270270958
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3739453452
Short name T3302
Test name
Test status
Simulation time 175439247 ps
CPU time 0.96 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207564 kb
Host smart-5cc3c5ab-0e8a-4e48-be62-c533c9bd3969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
53452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3739453452
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.4236940199
Short name T3139
Test name
Test status
Simulation time 346441296 ps
CPU time 1.37 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:20 PM PDT 24
Peak memory 207392 kb
Host smart-29681451-4f85-4162-9e71-e664c757220a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42369
40199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.4236940199
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3932724352
Short name T690
Test name
Test status
Simulation time 162383046 ps
CPU time 0.85 seconds
Started Aug 08 06:17:16 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207528 kb
Host smart-e4132761-9377-4e76-a632-64f201f3d30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
24352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3932724352
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.261160237
Short name T1716
Test name
Test status
Simulation time 176684696 ps
CPU time 0.96 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:20 PM PDT 24
Peak memory 207440 kb
Host smart-c3245f72-3379-40cb-9fb6-2ae797b1e565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
0237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.261160237
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.73851792
Short name T3590
Test name
Test status
Simulation time 186411203 ps
CPU time 0.95 seconds
Started Aug 08 06:17:12 PM PDT 24
Finished Aug 08 06:17:13 PM PDT 24
Peak memory 207556 kb
Host smart-51068cd8-ed5a-480e-a27c-65582f6f4968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73851
792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.73851792
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.4273100260
Short name T1941
Test name
Test status
Simulation time 3135816853 ps
CPU time 29.04 seconds
Started Aug 08 06:17:24 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 224280 kb
Host smart-c9d7511a-4e78-4bd0-9da7-957e46ebac33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4273100260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.4273100260
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3950179212
Short name T2814
Test name
Test status
Simulation time 206737988 ps
CPU time 0.98 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207612 kb
Host smart-228e0a36-ec96-46d9-af2b-a9458dae439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39501
79212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3950179212
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1450656229
Short name T29
Test name
Test status
Simulation time 171365816 ps
CPU time 0.89 seconds
Started Aug 08 06:17:23 PM PDT 24
Finished Aug 08 06:17:24 PM PDT 24
Peak memory 207544 kb
Host smart-16f7b674-287c-42c3-96aa-fb47a86c69b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506
56229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1450656229
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.2819042398
Short name T1809
Test name
Test status
Simulation time 576928601 ps
CPU time 1.71 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 207536 kb
Host smart-d00d8052-3a04-44a1-9e7c-5a0434e41f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28190
42398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2819042398
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.527437406
Short name T2525
Test name
Test status
Simulation time 2527358352 ps
CPU time 20.44 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:35 PM PDT 24
Peak memory 216132 kb
Host smart-f146c807-4feb-445f-bf14-4451a7f40267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52743
7406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.527437406
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.3311708093
Short name T1216
Test name
Test status
Simulation time 1054643972 ps
CPU time 20.53 seconds
Started Aug 08 06:17:06 PM PDT 24
Finished Aug 08 06:17:27 PM PDT 24
Peak memory 207480 kb
Host smart-8379b108-e3e4-4848-827f-44b70e06ce91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311708093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.3311708093
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.166480173
Short name T541
Test name
Test status
Simulation time 605495057 ps
CPU time 1.62 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:22 PM PDT 24
Peak memory 207572 kb
Host smart-be100c3f-95d4-489e-9f91-374999bd79ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166480173 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.166480173
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.2314983207
Short name T871
Test name
Test status
Simulation time 631177542 ps
CPU time 1.77 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:55 PM PDT 24
Peak memory 207548 kb
Host smart-35bdfd7a-bef3-4321-916a-9fb23e1b7ebe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314983207 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.2314983207
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.904651341
Short name T81
Test name
Test status
Simulation time 452771913 ps
CPU time 1.33 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207624 kb
Host smart-9439ffa8-96ce-47ee-b307-5a208333c197
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904651341 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.904651341
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.3648740397
Short name T2071
Test name
Test status
Simulation time 545227988 ps
CPU time 1.44 seconds
Started Aug 08 06:21:52 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207540 kb
Host smart-8dc38de1-4f8c-4d66-b68d-8beb43ec703c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648740397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.3648740397
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.3228679115
Short name T2565
Test name
Test status
Simulation time 599432005 ps
CPU time 1.58 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207624 kb
Host smart-d1992108-302d-49f1-8914-33ab46d82c5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228679115 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.3228679115
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.1763694886
Short name T3387
Test name
Test status
Simulation time 627899282 ps
CPU time 1.52 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207544 kb
Host smart-8d1e92da-1809-4f6c-9527-c9ef92746c0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763694886 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.1763694886
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.3532613184
Short name T3097
Test name
Test status
Simulation time 467729462 ps
CPU time 1.58 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207644 kb
Host smart-95ae39b5-0d05-4ff9-b2d0-21ee1b3f6550
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532613184 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.3532613184
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.3459042834
Short name T1880
Test name
Test status
Simulation time 622722134 ps
CPU time 1.59 seconds
Started Aug 08 06:21:38 PM PDT 24
Finished Aug 08 06:21:40 PM PDT 24
Peak memory 207588 kb
Host smart-18aaa7b0-075f-4937-8842-2429b08b8de8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459042834 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.3459042834
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.1113308562
Short name T1623
Test name
Test status
Simulation time 442984492 ps
CPU time 1.43 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207604 kb
Host smart-f49facec-8dd5-4eb8-8e10-64ee55edc0d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113308562 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.1113308562
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.2842855837
Short name T2935
Test name
Test status
Simulation time 544768977 ps
CPU time 1.61 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:48 PM PDT 24
Peak memory 207616 kb
Host smart-bee31a41-9dec-4b0e-8827-9e328f837a41
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842855837 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.2842855837
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2994205512
Short name T3601
Test name
Test status
Simulation time 35481265 ps
CPU time 0.64 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 207660 kb
Host smart-98cbfbe5-85c3-4894-a566-0e3186eb63db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2994205512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2994205512
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3665931082
Short name T9
Test name
Test status
Simulation time 11213001707 ps
CPU time 13.91 seconds
Started Aug 08 06:17:23 PM PDT 24
Finished Aug 08 06:17:37 PM PDT 24
Peak memory 207836 kb
Host smart-f6832269-7eac-42b6-b9df-c9c1ca91525f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665931082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.3665931082
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2251993894
Short name T3093
Test name
Test status
Simulation time 21399563271 ps
CPU time 24.32 seconds
Started Aug 08 06:17:23 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207828 kb
Host smart-0c3c4d0e-33be-4cc4-b527-1815654ed2ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251993894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2251993894
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.219292725
Short name T3226
Test name
Test status
Simulation time 163351025 ps
CPU time 0.85 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:20 PM PDT 24
Peak memory 207588 kb
Host smart-58253f2a-6665-4cb3-a5e1-2ed0c1e04476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
2725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.219292725
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2667450213
Short name T1658
Test name
Test status
Simulation time 155103764 ps
CPU time 0.84 seconds
Started Aug 08 06:17:22 PM PDT 24
Finished Aug 08 06:17:23 PM PDT 24
Peak memory 207600 kb
Host smart-638efcf1-3532-4cc1-8df4-8568a9fb871a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26674
50213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2667450213
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1636525665
Short name T3107
Test name
Test status
Simulation time 325948044 ps
CPU time 1.34 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 207604 kb
Host smart-d2784b77-e030-4fe1-93a8-a9d4b684f3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
25665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1636525665
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1625999417
Short name T999
Test name
Test status
Simulation time 1055858169 ps
CPU time 2.64 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207780 kb
Host smart-1383920a-d18c-44f1-8ba5-c4791e642396
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1625999417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1625999417
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.435652050
Short name T1577
Test name
Test status
Simulation time 56846737305 ps
CPU time 93.37 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207912 kb
Host smart-609a0e0c-dcbf-4b3c-926f-abff06abe997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43565
2050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.435652050
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.1704940553
Short name T1367
Test name
Test status
Simulation time 3016228302 ps
CPU time 26.53 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:40 PM PDT 24
Peak memory 207808 kb
Host smart-642635ad-8f54-4ff9-96d4-58bfaf21b6c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704940553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1704940553
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3341362477
Short name T2167
Test name
Test status
Simulation time 931917418 ps
CPU time 2.43 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:17 PM PDT 24
Peak memory 207756 kb
Host smart-b74f668f-872e-438b-9de3-b0b0c09c82c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
62477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3341362477
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2946864212
Short name T736
Test name
Test status
Simulation time 183357632 ps
CPU time 0.85 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:22 PM PDT 24
Peak memory 207508 kb
Host smart-761a9bd2-3599-4f45-a304-676ed30c4d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29468
64212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2946864212
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3600584447
Short name T3458
Test name
Test status
Simulation time 37460377 ps
CPU time 0.7 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207508 kb
Host smart-bd1e6db9-e33c-43ac-a4b1-88d1c777fc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
84447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3600584447
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.996035430
Short name T2532
Test name
Test status
Simulation time 1032317799 ps
CPU time 2.55 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 207844 kb
Host smart-4f3f3dca-4627-43eb-aec6-f03457f38ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99603
5430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.996035430
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.666327963
Short name T451
Test name
Test status
Simulation time 159836217 ps
CPU time 0.97 seconds
Started Aug 08 06:17:15 PM PDT 24
Finished Aug 08 06:17:16 PM PDT 24
Peak memory 207452 kb
Host smart-646392d8-9c81-46b9-aa2e-d608a24753aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=666327963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.666327963
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2731126089
Short name T1209
Test name
Test status
Simulation time 215753754 ps
CPU time 1.43 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207732 kb
Host smart-63dce628-a75f-4d8e-b1c6-523244fa4616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27311
26089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2731126089
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1712326120
Short name T2142
Test name
Test status
Simulation time 252031615 ps
CPU time 1.26 seconds
Started Aug 08 06:17:25 PM PDT 24
Finished Aug 08 06:17:26 PM PDT 24
Peak memory 216964 kb
Host smart-5eeb770a-f616-4efe-9e16-f4e523c96c4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1712326120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1712326120
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1481462373
Short name T1196
Test name
Test status
Simulation time 155244399 ps
CPU time 0.85 seconds
Started Aug 08 06:17:14 PM PDT 24
Finished Aug 08 06:17:15 PM PDT 24
Peak memory 207564 kb
Host smart-4413de57-9a4d-48f7-a077-71f86854c807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
62373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1481462373
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3443656338
Short name T3530
Test name
Test status
Simulation time 242972596 ps
CPU time 1.04 seconds
Started Aug 08 06:17:24 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207540 kb
Host smart-1fd49cc6-74ca-4765-bf85-81ef83e455cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34436
56338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3443656338
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.709911926
Short name T2145
Test name
Test status
Simulation time 2711383051 ps
CPU time 74.45 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:18:25 PM PDT 24
Peak memory 218720 kb
Host smart-c007e74e-ec94-4e51-8735-8bedd3c23264
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=709911926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.709911926
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2848839078
Short name T3019
Test name
Test status
Simulation time 9425413799 ps
CPU time 69.49 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 207792 kb
Host smart-b80d2ae9-bf8f-4690-b26c-fba64798fdbc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2848839078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2848839078
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1841802827
Short name T615
Test name
Test status
Simulation time 204591748 ps
CPU time 0.97 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:18 PM PDT 24
Peak memory 207632 kb
Host smart-12da1ab1-5474-4276-9407-4c20fa061099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
02827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1841802827
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3478019147
Short name T1875
Test name
Test status
Simulation time 9678753426 ps
CPU time 16.07 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 216112 kb
Host smart-70c42bd2-5c0c-42fe-9101-daa0cf736b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
19147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3478019147
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1157322589
Short name T38
Test name
Test status
Simulation time 4268350151 ps
CPU time 6.64 seconds
Started Aug 08 06:17:22 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 207828 kb
Host smart-b6da5d82-0214-4799-9d3c-34f4400adba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573
22589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1157322589
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1105807993
Short name T1413
Test name
Test status
Simulation time 5084092974 ps
CPU time 37.92 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 218596 kb
Host smart-19033982-df19-47f0-9a6e-13acdd815c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
07993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1105807993
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3600544958
Short name T3173
Test name
Test status
Simulation time 1733622964 ps
CPU time 48.36 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 215928 kb
Host smart-be58f584-a92c-480b-866a-43acafba6ee3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3600544958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3600544958
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3487499916
Short name T571
Test name
Test status
Simulation time 257993408 ps
CPU time 1.06 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:12 PM PDT 24
Peak memory 207580 kb
Host smart-31e245e1-00fb-4905-8b50-c2c0865d632e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3487499916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3487499916
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.618554750
Short name T2952
Test name
Test status
Simulation time 234523408 ps
CPU time 0.98 seconds
Started Aug 08 06:17:21 PM PDT 24
Finished Aug 08 06:17:22 PM PDT 24
Peak memory 207548 kb
Host smart-c6e6ca4f-5802-48f6-9d93-30717af0abfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61855
4750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.618554750
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.1792344239
Short name T2855
Test name
Test status
Simulation time 3272287060 ps
CPU time 32.19 seconds
Started Aug 08 06:17:17 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 217928 kb
Host smart-1c858602-811f-4407-afa7-ddf856d04ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17923
44239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.1792344239
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3489079575
Short name T3564
Test name
Test status
Simulation time 3021988909 ps
CPU time 21.35 seconds
Started Aug 08 06:17:11 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 224236 kb
Host smart-fc75cb9a-2dfd-43bd-aa20-b4087b6fff69
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3489079575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3489079575
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1603926131
Short name T809
Test name
Test status
Simulation time 166168302 ps
CPU time 0.87 seconds
Started Aug 08 06:17:13 PM PDT 24
Finished Aug 08 06:17:14 PM PDT 24
Peak memory 207592 kb
Host smart-1a666e34-bb42-47d9-8081-cad71890b174
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1603926131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1603926131
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1510718866
Short name T2204
Test name
Test status
Simulation time 157407111 ps
CPU time 0.88 seconds
Started Aug 08 06:17:20 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 207532 kb
Host smart-8969a27c-cc36-404e-a5b9-db52ea4357ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15107
18866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1510718866
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.799343075
Short name T1657
Test name
Test status
Simulation time 139171517 ps
CPU time 0.8 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:30 PM PDT 24
Peak memory 207544 kb
Host smart-bf479797-c7ee-446f-8b6c-5c60464f7a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79934
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.799343075
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3708328174
Short name T1083
Test name
Test status
Simulation time 214239254 ps
CPU time 0.9 seconds
Started Aug 08 06:17:31 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207544 kb
Host smart-953b0d0b-a233-455e-9de7-a4b2884d11fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37083
28174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3708328174
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3529433226
Short name T2017
Test name
Test status
Simulation time 252527855 ps
CPU time 0.94 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207528 kb
Host smart-8fd8bc86-583b-45cd-a90a-2bb3cd86364f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294
33226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3529433226
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.168797448
Short name T190
Test name
Test status
Simulation time 154332060 ps
CPU time 0.98 seconds
Started Aug 08 06:17:24 PM PDT 24
Finished Aug 08 06:17:25 PM PDT 24
Peak memory 207540 kb
Host smart-083fea6d-ad88-4930-8ac5-e10366eaa849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
7448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.168797448
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3101586011
Short name T1806
Test name
Test status
Simulation time 261140147 ps
CPU time 1.02 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:30 PM PDT 24
Peak memory 207588 kb
Host smart-c8eebb70-e15c-4820-97c4-86e547a9093d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3101586011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3101586011
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1743867434
Short name T3425
Test name
Test status
Simulation time 157553871 ps
CPU time 0.85 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207500 kb
Host smart-76b1376f-6963-4d7b-affb-e61f781104a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17438
67434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1743867434
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1911117667
Short name T3348
Test name
Test status
Simulation time 34549087 ps
CPU time 0.67 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:30 PM PDT 24
Peak memory 207484 kb
Host smart-2ef08902-a85b-4a3e-b463-4461bbd28d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
17667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1911117667
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1185366699
Short name T2440
Test name
Test status
Simulation time 7076536577 ps
CPU time 20.3 seconds
Started Aug 08 06:17:24 PM PDT 24
Finished Aug 08 06:17:44 PM PDT 24
Peak memory 220288 kb
Host smart-1d1dbd12-7d36-456f-9851-47daacfd2100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11853
66699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1185366699
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3919816250
Short name T1713
Test name
Test status
Simulation time 201043087 ps
CPU time 0.93 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207644 kb
Host smart-299e7967-22f6-49fa-98c9-e14051fd5b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
16250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3919816250
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2977855305
Short name T1031
Test name
Test status
Simulation time 229934321 ps
CPU time 1.02 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:30 PM PDT 24
Peak memory 207532 kb
Host smart-c0e43823-fa2c-4870-9cb9-be70980825b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29778
55305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2977855305
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4192679223
Short name T3492
Test name
Test status
Simulation time 228073295 ps
CPU time 0.92 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207564 kb
Host smart-d3d3bd7a-2ecd-48ff-856f-9ee09d2c28be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
79223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4192679223
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.703844394
Short name T1288
Test name
Test status
Simulation time 209607934 ps
CPU time 0.93 seconds
Started Aug 08 06:17:37 PM PDT 24
Finished Aug 08 06:17:38 PM PDT 24
Peak memory 207600 kb
Host smart-f087fecc-d620-46bd-8d58-1654e04c342b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70384
4394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.703844394
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.4247325133
Short name T636
Test name
Test status
Simulation time 136865844 ps
CPU time 0.86 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207572 kb
Host smart-065a8a5d-d0c7-4036-ade1-f7362841d681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42473
25133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.4247325133
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.1718093837
Short name T1229
Test name
Test status
Simulation time 363078487 ps
CPU time 1.32 seconds
Started Aug 08 06:17:37 PM PDT 24
Finished Aug 08 06:17:39 PM PDT 24
Peak memory 207604 kb
Host smart-7c5ded8e-5431-4172-a624-9e54f1adc7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
93837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.1718093837
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2022793195
Short name T850
Test name
Test status
Simulation time 155435504 ps
CPU time 0.81 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:17:41 PM PDT 24
Peak memory 207516 kb
Host smart-b698d61a-cd2b-4f0a-8eca-a2ca1f7764db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20227
93195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2022793195
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3315190331
Short name T1550
Test name
Test status
Simulation time 153975988 ps
CPU time 0.86 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207564 kb
Host smart-ff408c37-7a28-4042-bcb8-78e90c75a2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
90331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3315190331
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2338890684
Short name T602
Test name
Test status
Simulation time 243823684 ps
CPU time 0.99 seconds
Started Aug 08 06:17:38 PM PDT 24
Finished Aug 08 06:17:39 PM PDT 24
Peak memory 207548 kb
Host smart-9bf95234-8b30-4851-aeb8-85907e98f8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23388
90684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2338890684
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2948509576
Short name T1095
Test name
Test status
Simulation time 2341989137 ps
CPU time 63.11 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:18:33 PM PDT 24
Peak memory 224208 kb
Host smart-72198d0d-dacc-4112-b959-ee03d991f13f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2948509576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2948509576
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1698043127
Short name T3583
Test name
Test status
Simulation time 177010251 ps
CPU time 0.91 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207512 kb
Host smart-08d3196f-715a-41cf-aad4-7bee27ba5197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
43127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1698043127
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.727651156
Short name T692
Test name
Test status
Simulation time 155736700 ps
CPU time 0.8 seconds
Started Aug 08 06:17:33 PM PDT 24
Finished Aug 08 06:17:34 PM PDT 24
Peak memory 207512 kb
Host smart-820c74f7-e7c1-495e-a5d0-1f5329ffacc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72765
1156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.727651156
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.3068599952
Short name T923
Test name
Test status
Simulation time 845969560 ps
CPU time 2.25 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207716 kb
Host smart-f134a75d-b39d-4d7f-8663-5bc5496d4100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685
99952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.3068599952
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.217277509
Short name T2119
Test name
Test status
Simulation time 2844734738 ps
CPU time 83.72 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 217680 kb
Host smart-64ee2ed8-95cc-4340-bcce-29b1504fee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21727
7509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.217277509
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.2917605438
Short name T2009
Test name
Test status
Simulation time 2070197212 ps
CPU time 17.68 seconds
Started Aug 08 06:17:19 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207664 kb
Host smart-5e979dd0-49ef-4b0d-b113-bd297ceea8b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917605438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.2917605438
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.2838578166
Short name T732
Test name
Test status
Simulation time 475642622 ps
CPU time 1.42 seconds
Started Aug 08 06:17:27 PM PDT 24
Finished Aug 08 06:17:28 PM PDT 24
Peak memory 207564 kb
Host smart-603f8909-0a5b-4a5c-b059-f5d9311d22c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838578166 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.2838578166
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.2233632782
Short name T1486
Test name
Test status
Simulation time 484974388 ps
CPU time 1.65 seconds
Started Aug 08 06:21:57 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207512 kb
Host smart-4ca05096-507f-4a57-858a-2a990cc03438
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233632782 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.2233632782
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.4012772650
Short name T2519
Test name
Test status
Simulation time 577442398 ps
CPU time 1.55 seconds
Started Aug 08 06:21:53 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207608 kb
Host smart-bd2ae681-6dec-4bc5-9fdd-3b298d43c56f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012772650 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.4012772650
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.2685787813
Short name T1322
Test name
Test status
Simulation time 449010591 ps
CPU time 1.61 seconds
Started Aug 08 06:21:57 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207620 kb
Host smart-bdc4d267-6a1a-4627-a522-5bf9b6463265
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685787813 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.2685787813
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.2272501590
Short name T1990
Test name
Test status
Simulation time 499680593 ps
CPU time 1.49 seconds
Started Aug 08 06:22:07 PM PDT 24
Finished Aug 08 06:22:08 PM PDT 24
Peak memory 207548 kb
Host smart-fe13ec89-7587-49a2-8426-5a02961d325b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272501590 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.2272501590
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.1212383239
Short name T3423
Test name
Test status
Simulation time 449073291 ps
CPU time 1.49 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207564 kb
Host smart-4872cea6-e274-43a3-9337-26b42967b8e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212383239 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.1212383239
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.3402349992
Short name T1508
Test name
Test status
Simulation time 507028746 ps
CPU time 1.59 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207540 kb
Host smart-845a4429-1002-4bad-991b-ad3f4faa10d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402349992 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.3402349992
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.1387147718
Short name T3303
Test name
Test status
Simulation time 670923743 ps
CPU time 1.73 seconds
Started Aug 08 06:21:43 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 207564 kb
Host smart-eaaeda4d-5285-4716-8230-7f122e06ae19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387147718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1387147718
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.2878603294
Short name T2101
Test name
Test status
Simulation time 521978999 ps
CPU time 1.61 seconds
Started Aug 08 06:22:00 PM PDT 24
Finished Aug 08 06:22:04 PM PDT 24
Peak memory 207584 kb
Host smart-6c0088e4-2584-4383-9687-933232ba5688
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878603294 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.2878603294
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.1141764640
Short name T2672
Test name
Test status
Simulation time 472481788 ps
CPU time 1.6 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207564 kb
Host smart-e570f281-d012-40fa-8e73-43ca4c1a3df4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141764640 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.1141764640
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.3936899800
Short name T772
Test name
Test status
Simulation time 452954559 ps
CPU time 1.37 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207620 kb
Host smart-c8b1a3d8-42a7-4aaa-90a0-b4b532e27356
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936899800 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.3936899800
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3931844251
Short name T2848
Test name
Test status
Simulation time 44592461 ps
CPU time 0.7 seconds
Started Aug 08 06:17:33 PM PDT 24
Finished Aug 08 06:17:34 PM PDT 24
Peak memory 207516 kb
Host smart-044f1804-8ab2-434d-a319-9b29c7c73b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3931844251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3931844251
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.4085441403
Short name T2892
Test name
Test status
Simulation time 9985962447 ps
CPU time 12.76 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:42 PM PDT 24
Peak memory 207840 kb
Host smart-876a58d0-5cf7-4c9f-96ae-808dc56abf4c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085441403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.4085441403
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3416577559
Short name T1374
Test name
Test status
Simulation time 15716843649 ps
CPU time 20.6 seconds
Started Aug 08 06:17:27 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 216020 kb
Host smart-fec72a0c-8999-4d14-8f0a-61e2836a6452
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416577559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3416577559
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1621923215
Short name T2797
Test name
Test status
Simulation time 30637483972 ps
CPU time 40.62 seconds
Started Aug 08 06:17:25 PM PDT 24
Finished Aug 08 06:18:05 PM PDT 24
Peak memory 207828 kb
Host smart-88339170-c78b-422c-95d9-9dc013233ad0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621923215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1621923215
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3905858174
Short name T3522
Test name
Test status
Simulation time 238922278 ps
CPU time 0.98 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:30 PM PDT 24
Peak memory 207516 kb
Host smart-de78ffe3-9939-4b11-923f-b084a358e327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
58174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3905858174
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1754759147
Short name T794
Test name
Test status
Simulation time 141781931 ps
CPU time 0.81 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207484 kb
Host smart-ac959896-f39e-42a4-9d47-4eef48f612a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17547
59147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1754759147
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3027991429
Short name T590
Test name
Test status
Simulation time 315491665 ps
CPU time 1.26 seconds
Started Aug 08 06:17:37 PM PDT 24
Finished Aug 08 06:17:38 PM PDT 24
Peak memory 207496 kb
Host smart-3df7557d-1f8d-42c4-a9c9-95d40441321f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
91429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3027991429
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3804121585
Short name T3190
Test name
Test status
Simulation time 405661555 ps
CPU time 1.39 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207468 kb
Host smart-3cf85f66-62bc-4384-9ab0-702b849f7523
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3804121585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3804121585
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.37343850
Short name T467
Test name
Test status
Simulation time 21069881387 ps
CPU time 31.02 seconds
Started Aug 08 06:17:34 PM PDT 24
Finished Aug 08 06:18:05 PM PDT 24
Peak memory 207824 kb
Host smart-f2f9be45-6ac6-452d-8931-fb60debaa0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37343
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.37343850
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.2716208488
Short name T3468
Test name
Test status
Simulation time 1005103805 ps
CPU time 22.4 seconds
Started Aug 08 06:17:34 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207648 kb
Host smart-b2c749a5-124a-481c-9ba3-979893b935f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716208488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.2716208488
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.805956727
Short name T444
Test name
Test status
Simulation time 1118405234 ps
CPU time 2.31 seconds
Started Aug 08 06:17:34 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207432 kb
Host smart-f9bed445-f62a-4839-8c71-49df5ee195ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80595
6727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.805956727
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3869956086
Short name T1868
Test name
Test status
Simulation time 162349103 ps
CPU time 0.84 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207488 kb
Host smart-8505ea71-a12b-4f8e-8829-d3f9c801adaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699
56086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3869956086
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1538962476
Short name T1945
Test name
Test status
Simulation time 77037827 ps
CPU time 0.78 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207520 kb
Host smart-c441cc3b-7939-49c0-9342-e01a6c9fe7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15389
62476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1538962476
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2372936028
Short name T1436
Test name
Test status
Simulation time 1015828150 ps
CPU time 2.69 seconds
Started Aug 08 06:17:41 PM PDT 24
Finished Aug 08 06:17:44 PM PDT 24
Peak memory 207744 kb
Host smart-04341c3c-217c-4da3-850b-992d7ec8f693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
36028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2372936028
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1552495941
Short name T2255
Test name
Test status
Simulation time 278246579 ps
CPU time 1.6 seconds
Started Aug 08 06:17:41 PM PDT 24
Finished Aug 08 06:17:43 PM PDT 24
Peak memory 207664 kb
Host smart-144d7bd7-4e65-4e59-8dd3-c24101dc7e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
95941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1552495941
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2369597735
Short name T3420
Test name
Test status
Simulation time 171242941 ps
CPU time 0.92 seconds
Started Aug 08 06:17:42 PM PDT 24
Finished Aug 08 06:17:43 PM PDT 24
Peak memory 207520 kb
Host smart-4f375688-363f-4b2a-8727-62e205bb03ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2369597735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2369597735
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2216552352
Short name T3381
Test name
Test status
Simulation time 145394710 ps
CPU time 0.86 seconds
Started Aug 08 06:17:36 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207588 kb
Host smart-553b2873-6fc7-4a3a-90d5-788518cb74ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22165
52352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2216552352
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2842184709
Short name T1635
Test name
Test status
Simulation time 236121099 ps
CPU time 0.96 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207616 kb
Host smart-0915cfc8-0b04-4d9f-bdd4-b88a3c75492b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28421
84709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2842184709
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.656242331
Short name T2502
Test name
Test status
Simulation time 2256316704 ps
CPU time 22.43 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 217716 kb
Host smart-42122188-051c-4804-a26c-33edc65e6995
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=656242331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.656242331
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.209192131
Short name T3001
Test name
Test status
Simulation time 8012642905 ps
CPU time 98.41 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:19:29 PM PDT 24
Peak memory 207800 kb
Host smart-e143bb62-709f-4b8a-be52-04aa1d749e6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=209192131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.209192131
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1099311060
Short name T1732
Test name
Test status
Simulation time 236607214 ps
CPU time 1.02 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207524 kb
Host smart-214ec5b6-1880-409a-816e-3c38fc1475e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
11060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1099311060
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3708148826
Short name T595
Test name
Test status
Simulation time 28186638573 ps
CPU time 40.84 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 216204 kb
Host smart-7068ca67-003a-427a-a86b-d17126f32cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37081
48826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3708148826
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.695371771
Short name T1294
Test name
Test status
Simulation time 3663920481 ps
CPU time 6.25 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:17:46 PM PDT 24
Peak memory 207844 kb
Host smart-67fa7917-61e5-49f2-bcbb-6cf2e6383629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69537
1771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.695371771
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.339001341
Short name T3437
Test name
Test status
Simulation time 4502793331 ps
CPU time 123.95 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 218548 kb
Host smart-bc1e1650-2bd2-40f4-8259-3d81ab7c06e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33900
1341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.339001341
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3199899212
Short name T514
Test name
Test status
Simulation time 4143888327 ps
CPU time 31.89 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 216160 kb
Host smart-d3dd36b8-d68f-47cc-9dcc-7531c4dc4f4e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3199899212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3199899212
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2997577447
Short name T2340
Test name
Test status
Simulation time 254673530 ps
CPU time 1.09 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:17:41 PM PDT 24
Peak memory 207528 kb
Host smart-442e18fb-2586-49ba-b51c-cc4c62ced08c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2997577447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2997577447
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.4154940450
Short name T739
Test name
Test status
Simulation time 217732222 ps
CPU time 0.96 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207480 kb
Host smart-db1ebae4-3e70-497e-9686-75b2ffe747c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41549
40450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.4154940450
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.2315793882
Short name T1513
Test name
Test status
Simulation time 2015891468 ps
CPU time 54.02 seconds
Started Aug 08 06:17:25 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 217560 kb
Host smart-fd3b1e81-25eb-4d64-b69b-ddcd42ca9080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
93882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.2315793882
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2046457843
Short name T3469
Test name
Test status
Simulation time 2461714587 ps
CPU time 25.28 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 217344 kb
Host smart-bf87e6b8-2ee4-4cb4-9cb9-5c6cd0dbd89d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2046457843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2046457843
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.671861059
Short name T2083
Test name
Test status
Simulation time 197072083 ps
CPU time 0.91 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207528 kb
Host smart-dd6551e8-5fd6-4a0e-a26f-6786619eaffe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=671861059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.671861059
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.772595243
Short name T2343
Test name
Test status
Simulation time 174674553 ps
CPU time 0.87 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207496 kb
Host smart-2b035053-2d22-44de-a4fb-1d066f44ea0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77259
5243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.772595243
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1288331098
Short name T1447
Test name
Test status
Simulation time 197069905 ps
CPU time 0.92 seconds
Started Aug 08 06:17:27 PM PDT 24
Finished Aug 08 06:17:28 PM PDT 24
Peak memory 207572 kb
Host smart-fbf243d1-1e8b-46f4-a894-83d73cdc0640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
31098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1288331098
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3226630456
Short name T1900
Test name
Test status
Simulation time 190053066 ps
CPU time 1.04 seconds
Started Aug 08 06:17:43 PM PDT 24
Finished Aug 08 06:17:44 PM PDT 24
Peak memory 207780 kb
Host smart-b570dc9d-6541-4ac7-b7fa-134487afe63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32266
30456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3226630456
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2919738027
Short name T3393
Test name
Test status
Simulation time 201927608 ps
CPU time 0.89 seconds
Started Aug 08 06:17:25 PM PDT 24
Finished Aug 08 06:17:26 PM PDT 24
Peak memory 207596 kb
Host smart-7e07d14a-bb1a-41a0-be4d-ed2c12b0e384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29197
38027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2919738027
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.546589718
Short name T2186
Test name
Test status
Simulation time 182878740 ps
CPU time 0.93 seconds
Started Aug 08 06:17:41 PM PDT 24
Finished Aug 08 06:17:42 PM PDT 24
Peak memory 207564 kb
Host smart-be1e0b6f-180e-46d1-a4a9-67a2cc8f2afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54658
9718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.546589718
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1814583072
Short name T2662
Test name
Test status
Simulation time 153286059 ps
CPU time 0.85 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207548 kb
Host smart-6bd39d05-3dd9-4418-a6bc-fee0ab89d6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18145
83072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1814583072
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3894859171
Short name T594
Test name
Test status
Simulation time 230084836 ps
CPU time 1.08 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:17:41 PM PDT 24
Peak memory 207592 kb
Host smart-1b36d1dd-34d9-4fe1-ba8a-24f7c1ca39e5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3894859171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3894859171
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2298556017
Short name T3388
Test name
Test status
Simulation time 163957390 ps
CPU time 0.87 seconds
Started Aug 08 06:17:37 PM PDT 24
Finished Aug 08 06:17:38 PM PDT 24
Peak memory 207524 kb
Host smart-6160d08b-c12b-414c-a1b8-bfb0d7f16d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
56017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2298556017
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3065610436
Short name T40
Test name
Test status
Simulation time 31520739 ps
CPU time 0.67 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207532 kb
Host smart-c1da3787-9947-4848-8a6b-f14118c31091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
10436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3065610436
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2863673801
Short name T3321
Test name
Test status
Simulation time 22107305572 ps
CPU time 55.27 seconds
Started Aug 08 06:17:27 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 216112 kb
Host smart-bdbc0d29-0541-4a34-83c7-1f6dc2d66808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28636
73801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2863673801
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3574754701
Short name T765
Test name
Test status
Simulation time 168049009 ps
CPU time 0.9 seconds
Started Aug 08 06:17:34 PM PDT 24
Finished Aug 08 06:17:35 PM PDT 24
Peak memory 207508 kb
Host smart-b1c3d0bd-e722-4013-ab7b-653b1682025d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35747
54701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3574754701
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1177880339
Short name T1891
Test name
Test status
Simulation time 237183682 ps
CPU time 1.03 seconds
Started Aug 08 06:17:31 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207540 kb
Host smart-b042d1f2-66d8-4c0f-85fa-14df6d988df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11778
80339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1177880339
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.974553906
Short name T1637
Test name
Test status
Simulation time 201977305 ps
CPU time 0.96 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:31 PM PDT 24
Peak memory 207512 kb
Host smart-f0951edf-bc22-4eed-aa83-28779afa499b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97455
3906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.974553906
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.1336541023
Short name T1344
Test name
Test status
Simulation time 163821775 ps
CPU time 0.82 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 207612 kb
Host smart-8a7eef57-82cf-4339-9b5d-f580c1019578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13365
41023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1336541023
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3002332756
Short name T1480
Test name
Test status
Simulation time 142757164 ps
CPU time 0.79 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:27 PM PDT 24
Peak memory 207560 kb
Host smart-47110e69-096e-49d8-a655-1ec85c7a8b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
32756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3002332756
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.1806521320
Short name T321
Test name
Test status
Simulation time 255666764 ps
CPU time 1.05 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:34 PM PDT 24
Peak memory 207604 kb
Host smart-537b4244-7948-4cdf-8e45-5d929679d3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18065
21320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.1806521320
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2812033296
Short name T625
Test name
Test status
Simulation time 174749768 ps
CPU time 0.9 seconds
Started Aug 08 06:17:25 PM PDT 24
Finished Aug 08 06:17:26 PM PDT 24
Peak memory 207572 kb
Host smart-75a20fdb-d1ad-41cd-8602-034ff6d1c45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2812033296
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3918929137
Short name T2709
Test name
Test status
Simulation time 147246917 ps
CPU time 0.83 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 207592 kb
Host smart-ccb4e4db-0873-4dbe-840f-cf0ef6ace77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39189
29137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3918929137
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4152614513
Short name T1737
Test name
Test status
Simulation time 190314653 ps
CPU time 1 seconds
Started Aug 08 06:17:41 PM PDT 24
Finished Aug 08 06:17:42 PM PDT 24
Peak memory 207592 kb
Host smart-98f2ce8b-4fb5-4917-ad4f-426fb0fdf02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41526
14513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4152614513
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4264255944
Short name T1022
Test name
Test status
Simulation time 3736246755 ps
CPU time 28.96 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 218020 kb
Host smart-05c82bf7-7092-4350-9468-a89085a09137
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4264255944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4264255944
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3878643441
Short name T1543
Test name
Test status
Simulation time 168400929 ps
CPU time 0.86 seconds
Started Aug 08 06:17:31 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207652 kb
Host smart-145f3648-0dc9-42a0-9d6c-62251fe2a302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
43441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3878643441
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.372565486
Short name T2479
Test name
Test status
Simulation time 158712284 ps
CPU time 0.89 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207464 kb
Host smart-ea8fd50c-5a65-48b5-95c8-36e95c985521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37256
5486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.372565486
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3153690592
Short name T17
Test name
Test status
Simulation time 453150052 ps
CPU time 1.46 seconds
Started Aug 08 06:17:40 PM PDT 24
Finished Aug 08 06:17:41 PM PDT 24
Peak memory 207628 kb
Host smart-5e1ee5b3-9aa6-449d-96ee-6b27bbb6aa99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
90592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3153690592
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1756882935
Short name T2227
Test name
Test status
Simulation time 2207982589 ps
CPU time 59.74 seconds
Started Aug 08 06:17:31 PM PDT 24
Finished Aug 08 06:18:31 PM PDT 24
Peak memory 217196 kb
Host smart-8d70e4bf-9942-480a-8b3f-2c141a431315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
82935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1756882935
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.3603221059
Short name T2313
Test name
Test status
Simulation time 2954317829 ps
CPU time 24.01 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207732 kb
Host smart-8c970fc8-c775-472b-968c-1007e1161f4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603221059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.3603221059
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.2505992844
Short name T1197
Test name
Test status
Simulation time 577992291 ps
CPU time 1.52 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207496 kb
Host smart-253a4f6c-9613-415c-af1c-61e1ff4cd50a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505992844 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.2505992844
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.3662538418
Short name T1394
Test name
Test status
Simulation time 618535886 ps
CPU time 1.6 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207564 kb
Host smart-400f455f-6bd1-4c60-9a2d-2561400d0642
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662538418 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.3662538418
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.2504099445
Short name T899
Test name
Test status
Simulation time 475197154 ps
CPU time 1.6 seconds
Started Aug 08 06:21:52 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207596 kb
Host smart-4f1ce41e-74e9-458f-bd99-e6288ab321cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504099445 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.2504099445
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.4023475218
Short name T957
Test name
Test status
Simulation time 557318126 ps
CPU time 1.54 seconds
Started Aug 08 06:21:47 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207548 kb
Host smart-42944e53-fada-4060-9ce5-69b7057a7bfe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023475218 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.4023475218
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.503080606
Short name T2699
Test name
Test status
Simulation time 589282006 ps
CPU time 1.73 seconds
Started Aug 08 06:21:44 PM PDT 24
Finished Aug 08 06:21:46 PM PDT 24
Peak memory 207500 kb
Host smart-d2f9071d-eba1-494e-892d-13d8474bda8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503080606 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.503080606
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.2522734938
Short name T1371
Test name
Test status
Simulation time 617522913 ps
CPU time 1.65 seconds
Started Aug 08 06:21:50 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207560 kb
Host smart-f0d4a45e-274b-45b2-a6a7-ae2d3187fe5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522734938 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.2522734938
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.1018473611
Short name T1489
Test name
Test status
Simulation time 701389651 ps
CPU time 1.76 seconds
Started Aug 08 06:22:03 PM PDT 24
Finished Aug 08 06:22:04 PM PDT 24
Peak memory 207660 kb
Host smart-589d3d4a-59a1-4c12-9635-c61d76d23d37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018473611 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.1018473611
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.406452887
Short name T2054
Test name
Test status
Simulation time 544735511 ps
CPU time 1.66 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:01 PM PDT 24
Peak memory 207492 kb
Host smart-cf7011d5-9e5b-4b0a-9026-90cf19cc5b19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406452887 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.406452887
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.1673639217
Short name T932
Test name
Test status
Simulation time 664278180 ps
CPU time 1.66 seconds
Started Aug 08 06:22:07 PM PDT 24
Finished Aug 08 06:22:08 PM PDT 24
Peak memory 207472 kb
Host smart-574447e9-d063-4529-9c9e-ef60f534330a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673639217 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.1673639217
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.3479172432
Short name T1738
Test name
Test status
Simulation time 466489143 ps
CPU time 1.5 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:04 PM PDT 24
Peak memory 207472 kb
Host smart-5f3c17c7-6da5-42d7-a55f-90f91cf61050
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479172432 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.3479172432
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.2462778437
Short name T515
Test name
Test status
Simulation time 578491980 ps
CPU time 1.59 seconds
Started Aug 08 06:21:57 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 207660 kb
Host smart-382777d1-57d9-4e49-909e-90c2978704be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462778437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.2462778437
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1062529013
Short name T2228
Test name
Test status
Simulation time 49001559 ps
CPU time 0.68 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 207616 kb
Host smart-6af9c7a0-e7e3-4d6e-9078-da6a2d1e2f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1062529013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1062529013
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2829295767
Short name T2135
Test name
Test status
Simulation time 4475055423 ps
CPU time 6.75 seconds
Started Aug 08 06:17:33 PM PDT 24
Finished Aug 08 06:17:40 PM PDT 24
Peak memory 215988 kb
Host smart-a5ed8584-d706-491d-8f05-2e035c3c3f59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829295767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.2829295767
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3644325644
Short name T717
Test name
Test status
Simulation time 21076549120 ps
CPU time 29.88 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207856 kb
Host smart-d07a85eb-34bf-4b2e-b02a-734a976151e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644325644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3644325644
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2081289779
Short name T263
Test name
Test status
Simulation time 29378791132 ps
CPU time 38.29 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207788 kb
Host smart-b1706023-3a0e-4971-88f7-0e1ad49b3fc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081289779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.2081289779
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2088750336
Short name T2330
Test name
Test status
Simulation time 209620220 ps
CPU time 0.97 seconds
Started Aug 08 06:17:32 PM PDT 24
Finished Aug 08 06:17:33 PM PDT 24
Peak memory 207524 kb
Host smart-7c05ab53-a7ae-47c4-ace0-c827164c5d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
50336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2088750336
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2992644925
Short name T3031
Test name
Test status
Simulation time 156824250 ps
CPU time 0.9 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207536 kb
Host smart-0bf54e81-80cc-4945-9be0-26036d6e139a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29926
44925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2992644925
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3019105405
Short name T34
Test name
Test status
Simulation time 252378714 ps
CPU time 1.05 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207572 kb
Host smart-22602a86-fc31-4139-bf3d-e167f40f9794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30191
05405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3019105405
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1459015622
Short name T3474
Test name
Test status
Simulation time 576743003 ps
CPU time 1.74 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:28 PM PDT 24
Peak memory 207532 kb
Host smart-b522a698-db3f-4247-b5a2-7c69d1fa38f0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1459015622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1459015622
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3428175118
Short name T2018
Test name
Test status
Simulation time 52798330417 ps
CPU time 84.59 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:18:59 PM PDT 24
Peak memory 207916 kb
Host smart-1849f92b-d317-40e7-a0f6-72b69d49d7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
75118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3428175118
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.592967500
Short name T176
Test name
Test status
Simulation time 896563118 ps
CPU time 19.77 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 207672 kb
Host smart-23e9811a-0b8b-459b-8682-abd54cd5c713
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592967500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.592967500
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.4167213621
Short name T1110
Test name
Test status
Simulation time 702035555 ps
CPU time 1.81 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:17:37 PM PDT 24
Peak memory 207552 kb
Host smart-f133861b-d9ce-44c6-8472-caa319b4c738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41672
13621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.4167213621
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4167461568
Short name T68
Test name
Test status
Simulation time 153330204 ps
CPU time 0.82 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207492 kb
Host smart-1aff5538-7df6-4277-8b52-4efdba3222f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
61568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4167461568
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3168915518
Short name T963
Test name
Test status
Simulation time 73153724 ps
CPU time 0.73 seconds
Started Aug 08 06:17:35 PM PDT 24
Finished Aug 08 06:17:36 PM PDT 24
Peak memory 207584 kb
Host smart-48b8cdfe-5490-4478-944e-6242f34d0267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
15518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3168915518
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3188176817
Short name T1599
Test name
Test status
Simulation time 984205503 ps
CPU time 2.64 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 207784 kb
Host smart-6ff2b7f2-a3c8-48a1-a909-851a5186246a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
76817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3188176817
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2128555246
Short name T1823
Test name
Test status
Simulation time 224049773 ps
CPU time 1.42 seconds
Started Aug 08 06:17:30 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207752 kb
Host smart-88f1d2ad-8910-440f-a6f9-986954a77982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
55246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2128555246
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1671950235
Short name T622
Test name
Test status
Simulation time 173431274 ps
CPU time 0.88 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207532 kb
Host smart-8c7ecd64-d187-4523-b7c2-9ce2df6de29c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1671950235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1671950235
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1500013091
Short name T2452
Test name
Test status
Simulation time 193030237 ps
CPU time 0.95 seconds
Started Aug 08 06:17:28 PM PDT 24
Finished Aug 08 06:17:29 PM PDT 24
Peak memory 207456 kb
Host smart-2eba299d-4711-4522-afae-e4d6d37ece2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15000
13091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1500013091
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.695241588
Short name T1693
Test name
Test status
Simulation time 240163044 ps
CPU time 1.02 seconds
Started Aug 08 06:17:48 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 207520 kb
Host smart-0258b819-e3f3-42a4-b7d8-bc79dd8305e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69524
1588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.695241588
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2790792929
Short name T3172
Test name
Test status
Simulation time 2639347251 ps
CPU time 72.71 seconds
Started Aug 08 06:17:36 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 216156 kb
Host smart-a7fe6fac-186f-45a5-a76e-3615ea1dd975
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2790792929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2790792929
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.3418167667
Short name T2225
Test name
Test status
Simulation time 12553801112 ps
CPU time 87.71 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:18:54 PM PDT 24
Peak memory 207800 kb
Host smart-aa0780e5-be3e-4a49-b80d-48981c5fb7bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3418167667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3418167667
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.392514044
Short name T2880
Test name
Test status
Simulation time 171424790 ps
CPU time 0.89 seconds
Started Aug 08 06:17:26 PM PDT 24
Finished Aug 08 06:17:27 PM PDT 24
Peak memory 207648 kb
Host smart-feddb7d9-c654-43ac-a01b-c6fc062ccddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
4044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.392514044
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1797489282
Short name T561
Test name
Test status
Simulation time 22905136465 ps
CPU time 39.41 seconds
Started Aug 08 06:17:29 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 216140 kb
Host smart-e8cef56d-422d-4803-99c1-1a069974587b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17974
89282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1797489282
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2664426619
Short name T3406
Test name
Test status
Simulation time 3907319884 ps
CPU time 6.81 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 216176 kb
Host smart-ea291cc4-0ea2-40d8-9ea8-9e9f4f37349f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26644
26619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2664426619
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.405594636
Short name T2004
Test name
Test status
Simulation time 4845367154 ps
CPU time 37.45 seconds
Started Aug 08 06:17:39 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 216072 kb
Host smart-a6036e7b-0c33-436a-98d1-60a200ac21db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40559
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.405594636
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3887555816
Short name T1717
Test name
Test status
Simulation time 1844384179 ps
CPU time 18.4 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:18:05 PM PDT 24
Peak memory 216200 kb
Host smart-c3c9a88c-5af7-42e7-8974-d1f3ba262ad7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3887555816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3887555816
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1950808358
Short name T1691
Test name
Test status
Simulation time 302318859 ps
CPU time 1.14 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 207580 kb
Host smart-93b77823-378d-4da9-9c67-99a684323cab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1950808358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1950808358
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3160835702
Short name T2759
Test name
Test status
Simulation time 203227892 ps
CPU time 0.97 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:17:45 PM PDT 24
Peak memory 207568 kb
Host smart-dc0b896d-6254-4ce5-9d65-72ad6cb9a0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
35702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3160835702
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1663930363
Short name T938
Test name
Test status
Simulation time 2924037464 ps
CPU time 22.27 seconds
Started Aug 08 06:17:44 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207908 kb
Host smart-45f0aaaf-857f-492e-b006-249ab1a12d44
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1663930363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1663930363
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1254797950
Short name T1705
Test name
Test status
Simulation time 196254678 ps
CPU time 0.91 seconds
Started Aug 08 06:17:34 PM PDT 24
Finished Aug 08 06:17:35 PM PDT 24
Peak memory 207504 kb
Host smart-7bfb46d7-23d0-409a-94f5-d26e0db5f231
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254797950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1254797950
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2380305334
Short name T3169
Test name
Test status
Simulation time 207995643 ps
CPU time 0.87 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207568 kb
Host smart-576f21b0-1f00-4c96-85ff-de3898af3b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
05334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2380305334
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1366810694
Short name T2764
Test name
Test status
Simulation time 254977069 ps
CPU time 1 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207580 kb
Host smart-8c730b2d-35b5-42d0-9a64-47c3176d29e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
10694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1366810694
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2402974720
Short name T1363
Test name
Test status
Simulation time 185949856 ps
CPU time 0.92 seconds
Started Aug 08 06:17:42 PM PDT 24
Finished Aug 08 06:17:43 PM PDT 24
Peak memory 207540 kb
Host smart-464f5eb0-dbc0-4903-b0b5-60fcb4236693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
74720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2402974720
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1348306313
Short name T1082
Test name
Test status
Simulation time 188012651 ps
CPU time 0.96 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207584 kb
Host smart-207841af-6272-4838-8b37-3705007e7819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
06313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1348306313
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3189301801
Short name T2211
Test name
Test status
Simulation time 260449742 ps
CPU time 0.91 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207612 kb
Host smart-6cf596b2-0559-4a3f-adf3-e52b0016cdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
01801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3189301801
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1261816085
Short name T2129
Test name
Test status
Simulation time 149568222 ps
CPU time 0.89 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207548 kb
Host smart-01fe15af-f4f0-4e74-bc42-4751eaa92c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
16085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1261816085
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2938730088
Short name T1460
Test name
Test status
Simulation time 214925497 ps
CPU time 0.99 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207584 kb
Host smart-7805ba15-477e-4929-bd24-087f15b1083c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2938730088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2938730088
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2775976400
Short name T3563
Test name
Test status
Simulation time 150725729 ps
CPU time 0.82 seconds
Started Aug 08 06:17:38 PM PDT 24
Finished Aug 08 06:17:39 PM PDT 24
Peak memory 207588 kb
Host smart-a0e558f2-f96c-438d-88c9-4d958da4d568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27759
76400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2775976400
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3722970127
Short name T1842
Test name
Test status
Simulation time 30225169 ps
CPU time 0.68 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207492 kb
Host smart-7df727b0-dd2f-4353-aafc-dd741f0e8e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37229
70127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3722970127
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2914655257
Short name T2793
Test name
Test status
Simulation time 8020487448 ps
CPU time 20.56 seconds
Started Aug 08 06:17:48 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 216140 kb
Host smart-ed436a06-5b9c-4981-a6dd-8da5a3cd297a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29146
55257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2914655257
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1144507525
Short name T1946
Test name
Test status
Simulation time 160349401 ps
CPU time 0.85 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 207524 kb
Host smart-70cacd4e-8828-4c8e-a75d-e933895e9056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11445
07525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1144507525
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.502295281
Short name T3356
Test name
Test status
Simulation time 218126949 ps
CPU time 0.97 seconds
Started Aug 08 06:17:43 PM PDT 24
Finished Aug 08 06:17:44 PM PDT 24
Peak memory 207544 kb
Host smart-1965678a-dfae-403f-8d87-27d44bc18e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50229
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.502295281
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3301547093
Short name T759
Test name
Test status
Simulation time 241536612 ps
CPU time 1.02 seconds
Started Aug 08 06:17:45 PM PDT 24
Finished Aug 08 06:17:46 PM PDT 24
Peak memory 207604 kb
Host smart-a8810db5-85f3-40ad-855b-4af2788069f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
47093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3301547093
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.380982571
Short name T1896
Test name
Test status
Simulation time 215325414 ps
CPU time 0.99 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207600 kb
Host smart-a418dcf3-d68a-4478-bb98-addc605de601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38098
2571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.380982571
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1929372387
Short name T2698
Test name
Test status
Simulation time 228703197 ps
CPU time 0.97 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 207576 kb
Host smart-da377e6d-a6c7-4bf1-b47a-29d761316d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
72387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1929372387
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.2982220233
Short name T3082
Test name
Test status
Simulation time 387945562 ps
CPU time 1.36 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207592 kb
Host smart-7d86d976-89cf-4f6e-a791-fd492248014f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29822
20233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.2982220233
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3804913621
Short name T3000
Test name
Test status
Simulation time 237243665 ps
CPU time 0.94 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 207560 kb
Host smart-2bb2c419-1e5f-48f2-bb10-46cf03c71f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
13621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3804913621
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2563381515
Short name T1844
Test name
Test status
Simulation time 176919429 ps
CPU time 0.89 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207612 kb
Host smart-700e67c2-be97-4023-a073-a942b76584bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25633
81515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2563381515
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1670996717
Short name T1742
Test name
Test status
Simulation time 282241383 ps
CPU time 1.07 seconds
Started Aug 08 06:17:45 PM PDT 24
Finished Aug 08 06:17:46 PM PDT 24
Peak memory 207600 kb
Host smart-244f850d-2fe5-4baa-8f4f-7df7edb39131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709
96717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1670996717
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3295952306
Short name T2279
Test name
Test status
Simulation time 3535785101 ps
CPU time 28.15 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 218076 kb
Host smart-cc5e6d79-02b5-4d89-ad81-f13f3410f2f7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3295952306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3295952306
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.615164787
Short name T1597
Test name
Test status
Simulation time 181252131 ps
CPU time 0.87 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207528 kb
Host smart-2e0d5c01-daf1-400b-a94f-ecc9fcb2a9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61516
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.615164787
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3479058100
Short name T3341
Test name
Test status
Simulation time 203357140 ps
CPU time 0.94 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207556 kb
Host smart-f7f3de57-5a88-4eec-ac59-67e165e8f273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
58100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3479058100
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.4127163669
Short name T3501
Test name
Test status
Simulation time 1387010029 ps
CPU time 3.17 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207696 kb
Host smart-fc085980-f348-414c-ad63-463f5a29d964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41271
63669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.4127163669
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2513263266
Short name T1093
Test name
Test status
Simulation time 3292056778 ps
CPU time 24.97 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 217808 kb
Host smart-5ff31ece-f057-4299-bdf2-7b611a69395c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132
63266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2513263266
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.4182025243
Short name T2132
Test name
Test status
Simulation time 1277825623 ps
CPU time 28.14 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207736 kb
Host smart-a6271bc5-2ab6-4163-ba6d-044ca5226a9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182025243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.4182025243
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.1199114378
Short name T1892
Test name
Test status
Simulation time 443262948 ps
CPU time 1.37 seconds
Started Aug 08 06:17:48 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 207600 kb
Host smart-57b9a163-d26a-4114-8fc9-1dff172efb8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199114378 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.1199114378
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.4271958106
Short name T617
Test name
Test status
Simulation time 439465999 ps
CPU time 1.4 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207472 kb
Host smart-97f197f3-6a65-4db9-a017-2fba9896b36d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271958106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.4271958106
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.1679034318
Short name T611
Test name
Test status
Simulation time 636296644 ps
CPU time 1.61 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207616 kb
Host smart-c6b00b7d-5ea5-4cdf-8e64-eb41c84bb26f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679034318 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.1679034318
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.763076664
Short name T2890
Test name
Test status
Simulation time 489149867 ps
CPU time 1.56 seconds
Started Aug 08 06:21:55 PM PDT 24
Finished Aug 08 06:21:56 PM PDT 24
Peak memory 207488 kb
Host smart-ee597202-efe9-48cf-92eb-f77d209b7602
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763076664 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.763076664
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.2358632215
Short name T2131
Test name
Test status
Simulation time 626962950 ps
CPU time 1.68 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:01 PM PDT 24
Peak memory 207468 kb
Host smart-b2929994-923e-4f55-bbcc-e475f97d8c4a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358632215 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.2358632215
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.3555826483
Short name T2246
Test name
Test status
Simulation time 528505822 ps
CPU time 1.53 seconds
Started Aug 08 06:22:03 PM PDT 24
Finished Aug 08 06:22:05 PM PDT 24
Peak memory 207488 kb
Host smart-bf99d393-7cb4-4a45-a421-6063c9a25766
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555826483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.3555826483
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.2602238993
Short name T1554
Test name
Test status
Simulation time 583962838 ps
CPU time 1.78 seconds
Started Aug 08 06:21:51 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207500 kb
Host smart-3d705c92-4127-48b2-8670-6b13885278ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602238993 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.2602238993
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.1576286446
Short name T2197
Test name
Test status
Simulation time 550097010 ps
CPU time 1.63 seconds
Started Aug 08 06:21:39 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 207592 kb
Host smart-7c261942-9b90-4f28-9c1f-1cc6c044e997
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576286446 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1576286446
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.1287828545
Short name T1107
Test name
Test status
Simulation time 662433193 ps
CPU time 1.78 seconds
Started Aug 08 06:21:46 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207584 kb
Host smart-12ecb66d-b603-4e43-a673-5a73ca4e20d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287828545 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.1287828545
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.913588513
Short name T2143
Test name
Test status
Simulation time 495599034 ps
CPU time 1.51 seconds
Started Aug 08 06:21:48 PM PDT 24
Finished Aug 08 06:21:50 PM PDT 24
Peak memory 207584 kb
Host smart-9e1b725d-22bc-423f-83eb-e2db6043faf8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913588513 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.913588513
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.4180645681
Short name T1932
Test name
Test status
Simulation time 536583900 ps
CPU time 1.74 seconds
Started Aug 08 06:21:40 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 207588 kb
Host smart-9fac1560-a219-4d76-83e3-3f26d3dcbbd0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180645681 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.4180645681
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.3002413729
Short name T2189
Test name
Test status
Simulation time 58269604 ps
CPU time 0.76 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207556 kb
Host smart-29afc24c-1550-4759-83a2-3a4291745eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3002413729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.3002413729
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.354721507
Short name T2816
Test name
Test status
Simulation time 10192507133 ps
CPU time 12.67 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 207836 kb
Host smart-8b774c05-2061-49c3-b6cf-95e1a1fa77c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354721507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_disconnect.354721507
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2825251331
Short name T1259
Test name
Test status
Simulation time 20462021773 ps
CPU time 23.91 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207836 kb
Host smart-5d4ef3fa-7d4b-4fdb-84e8-2a5b239c0c24
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825251331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2825251331
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1130909204
Short name T3249
Test name
Test status
Simulation time 30383135584 ps
CPU time 38.54 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207820 kb
Host smart-e4b183af-2c3c-49fa-bf5a-3aa44007a1d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130909204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.1130909204
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2955215517
Short name T2093
Test name
Test status
Simulation time 156394958 ps
CPU time 0.86 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207492 kb
Host smart-4f4cf5ad-7f38-4d65-a755-dc97060a8667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552
15517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2955215517
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.36428560
Short name T2082
Test name
Test status
Simulation time 153486492 ps
CPU time 0.86 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207536 kb
Host smart-bcf46b28-afa4-49cc-9a8e-2699aab4cdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.36428560
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.60303838
Short name T3482
Test name
Test status
Simulation time 428501665 ps
CPU time 1.5 seconds
Started Aug 08 06:17:45 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207532 kb
Host smart-19181aca-5bd9-4553-a526-a2aa3b1c3c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60303
838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.60303838
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3582345216
Short name T112
Test name
Test status
Simulation time 908667398 ps
CPU time 2.46 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207796 kb
Host smart-96ced0de-f088-4e15-bec1-844de4058c29
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3582345216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3582345216
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.594900407
Short name T2501
Test name
Test status
Simulation time 56642410986 ps
CPU time 93.02 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:19:19 PM PDT 24
Peak memory 207816 kb
Host smart-913ed64f-3432-4c02-b725-f9e226d8509d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59490
0407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.594900407
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3934449622
Short name T3481
Test name
Test status
Simulation time 600483530 ps
CPU time 5.07 seconds
Started Aug 08 06:17:48 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207724 kb
Host smart-b42aa4a6-bc03-4f27-8049-2a393fbc86fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934449622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3934449622
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1351131251
Short name T3358
Test name
Test status
Simulation time 1019715759 ps
CPU time 2.07 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 207624 kb
Host smart-be33255f-37a0-4bff-83f7-afdab73f347c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
31251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1351131251
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2441546297
Short name T848
Test name
Test status
Simulation time 141472313 ps
CPU time 0.86 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207528 kb
Host smart-22211bae-a069-49ad-b2c0-cb8c85b8dee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24415
46297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2441546297
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.678617616
Short name T1517
Test name
Test status
Simulation time 34625948 ps
CPU time 0.69 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 207488 kb
Host smart-a0c780a7-f5e7-4c09-8afa-3118fb285580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67861
7616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.678617616
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3698997030
Short name T2300
Test name
Test status
Simulation time 943902459 ps
CPU time 2.52 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207804 kb
Host smart-5224ee36-1bd4-4b58-b161-d4bf8959c9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
97030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3698997030
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.1450539779
Short name T382
Test name
Test status
Simulation time 726668488 ps
CPU time 1.54 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207568 kb
Host smart-c4c500fa-27ae-422f-a633-dbdcf58cf9bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1450539779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.1450539779
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.758459327
Short name T240
Test name
Test status
Simulation time 237942225 ps
CPU time 1.55 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:47 PM PDT 24
Peak memory 207724 kb
Host smart-95bb89e4-4c59-4b73-9453-6f6920af6edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75845
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.758459327
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.4099946546
Short name T3431
Test name
Test status
Simulation time 276244296 ps
CPU time 1.27 seconds
Started Aug 08 06:17:46 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 215880 kb
Host smart-e174ad96-f713-4f21-bc2c-1477356b7bd1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4099946546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.4099946546
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1679315031
Short name T3450
Test name
Test status
Simulation time 152336178 ps
CPU time 0.86 seconds
Started Aug 08 06:17:48 PM PDT 24
Finished Aug 08 06:17:49 PM PDT 24
Peak memory 207564 kb
Host smart-fc6ca11f-984f-4c0e-a2c2-b388c51c1aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
15031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1679315031
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2880620308
Short name T2959
Test name
Test status
Simulation time 212255838 ps
CPU time 0.95 seconds
Started Aug 08 06:17:42 PM PDT 24
Finished Aug 08 06:17:43 PM PDT 24
Peak memory 207608 kb
Host smart-76ac09c8-1585-4264-af65-aabc56dd22c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
20308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2880620308
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.2836940363
Short name T510
Test name
Test status
Simulation time 4911089137 ps
CPU time 141.43 seconds
Started Aug 08 06:17:43 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 216036 kb
Host smart-10d2f462-8c8e-49c3-bf6f-bba53ec5e31d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2836940363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.2836940363
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3113668601
Short name T2533
Test name
Test status
Simulation time 11849400240 ps
CPU time 151.91 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207800 kb
Host smart-692f8dc0-732e-47b5-98a3-89388213b21d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3113668601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3113668601
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.519184798
Short name T62
Test name
Test status
Simulation time 236428391 ps
CPU time 1.05 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207560 kb
Host smart-6952c7e3-6223-40ee-9fac-1af4f6831e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51918
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.519184798
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2298310994
Short name T3355
Test name
Test status
Simulation time 26372834787 ps
CPU time 41.63 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:18:29 PM PDT 24
Peak memory 216104 kb
Host smart-5c44a8a6-591b-412f-96b7-4fbe79043647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
10994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2298310994
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1259989594
Short name T288
Test name
Test status
Simulation time 5016084975 ps
CPU time 6.94 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 216196 kb
Host smart-51737efc-a2f5-47d0-9629-6bded4fc05f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12599
89594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1259989594
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2701642393
Short name T2817
Test name
Test status
Simulation time 4051460659 ps
CPU time 40.79 seconds
Started Aug 08 06:17:45 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 218276 kb
Host smart-944bccc8-817f-411e-bb90-02fd15cf5767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
42393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2701642393
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1329424330
Short name T1488
Test name
Test status
Simulation time 3101085328 ps
CPU time 88.78 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 217436 kb
Host smart-146c1ec8-9570-43e8-9e75-8cf6e30472db
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1329424330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1329424330
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.550680115
Short name T744
Test name
Test status
Simulation time 242918309 ps
CPU time 0.99 seconds
Started Aug 08 06:17:47 PM PDT 24
Finished Aug 08 06:17:48 PM PDT 24
Peak memory 207616 kb
Host smart-7322eae7-881c-44cf-904f-04eef1bbb0da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=550680115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.550680115
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.23452793
Short name T787
Test name
Test status
Simulation time 221826635 ps
CPU time 0.96 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 207576 kb
Host smart-0c5e1013-0d6c-44ab-a730-551882ac1822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23452
793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.23452793
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.267182871
Short name T788
Test name
Test status
Simulation time 1767377224 ps
CPU time 49.41 seconds
Started Aug 08 06:18:05 PM PDT 24
Finished Aug 08 06:18:54 PM PDT 24
Peak memory 224104 kb
Host smart-d32aa945-fe2a-499c-b9e3-1996c5aed3fa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=267182871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.267182871
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3212177188
Short name T2373
Test name
Test status
Simulation time 164469951 ps
CPU time 0.92 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:01 PM PDT 24
Peak memory 207516 kb
Host smart-127371c1-6132-4294-ab71-9d5d1d9de419
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3212177188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3212177188
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1850098367
Short name T781
Test name
Test status
Simulation time 170274417 ps
CPU time 0.9 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207560 kb
Host smart-8b572ed8-3bdb-4afe-8792-8b7ef4957357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
98367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1850098367
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2216322939
Short name T823
Test name
Test status
Simulation time 186223463 ps
CPU time 0.96 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207780 kb
Host smart-94920d31-ec89-408e-afe7-816fce6938d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
22939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2216322939
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.11358688
Short name T327
Test name
Test status
Simulation time 212381812 ps
CPU time 0.97 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207588 kb
Host smart-8163f6cf-aeaa-4943-9348-aa484c2c03a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11358
688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.11358688
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2102538620
Short name T939
Test name
Test status
Simulation time 185281776 ps
CPU time 0.9 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207556 kb
Host smart-8224ec61-15e8-457a-81a4-0aed9b8aa7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
38620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2102538620
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2468043633
Short name T769
Test name
Test status
Simulation time 180495932 ps
CPU time 0.88 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:01 PM PDT 24
Peak memory 207528 kb
Host smart-92114bb8-66ac-4478-aa5d-c83202a27b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
43633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2468043633
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1352726359
Short name T2092
Test name
Test status
Simulation time 228374422 ps
CPU time 1 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207664 kb
Host smart-ff6d24ac-27da-4c1e-8753-05adb0326965
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1352726359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1352726359
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2730750436
Short name T3310
Test name
Test status
Simulation time 152589845 ps
CPU time 0.83 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207500 kb
Host smart-85d00483-1a84-4abd-bfce-b9e8d2948c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
50436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2730750436
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1063921997
Short name T3432
Test name
Test status
Simulation time 76276810 ps
CPU time 0.75 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207472 kb
Host smart-8f5cea3c-ac0e-45a4-acff-960e4cf8ef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
21997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1063921997
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.178011211
Short name T1548
Test name
Test status
Simulation time 8092560079 ps
CPU time 21 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 215996 kb
Host smart-97e1f15f-77bf-41ba-b8e3-46a0dc859789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
1211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.178011211
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1483355663
Short name T1441
Test name
Test status
Simulation time 232768873 ps
CPU time 0.99 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207540 kb
Host smart-62b91519-5c69-4acb-9ca2-255b84c95460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14833
55663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1483355663
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.20163965
Short name T3113
Test name
Test status
Simulation time 235064815 ps
CPU time 1.06 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207512 kb
Host smart-a98f1ce7-8d97-4cd3-af60-8b1be0b9ae30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20163
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.20163965
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.180110504
Short name T2175
Test name
Test status
Simulation time 218795641 ps
CPU time 0.91 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207564 kb
Host smart-61fb3a45-c968-4d3a-90be-fc45da4991b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011
0504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.180110504
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3135416361
Short name T779
Test name
Test status
Simulation time 186821334 ps
CPU time 0.93 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207552 kb
Host smart-4b44d411-ce78-4cbb-9c3e-d57a53929fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
16361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3135416361
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.615424526
Short name T1675
Test name
Test status
Simulation time 137461079 ps
CPU time 0.85 seconds
Started Aug 08 06:18:06 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207552 kb
Host smart-38961ad3-53a4-45bb-81a7-2fb248773a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61542
4526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.615424526
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.3853795624
Short name T322
Test name
Test status
Simulation time 303585803 ps
CPU time 1.2 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207480 kb
Host smart-741ffd03-a84b-4501-8375-5bef33adf4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537
95624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.3853795624
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.389003992
Short name T827
Test name
Test status
Simulation time 152999165 ps
CPU time 0.9 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:01 PM PDT 24
Peak memory 207532 kb
Host smart-871efad0-3b71-4a1f-bb37-8501950c9316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.389003992
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.203306158
Short name T2612
Test name
Test status
Simulation time 180106386 ps
CPU time 0.87 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207592 kb
Host smart-0306a6a8-7fbe-47ef-82fa-efee37ed1667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330
6158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.203306158
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4115737467
Short name T3189
Test name
Test status
Simulation time 202402649 ps
CPU time 0.93 seconds
Started Aug 08 06:18:02 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 207548 kb
Host smart-f640ac07-7589-45ef-b91b-72ecb8e54696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
37467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4115737467
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2805498644
Short name T3270
Test name
Test status
Simulation time 2049733149 ps
CPU time 20.12 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 217104 kb
Host smart-51da839f-2ff4-46cf-abbf-36109c1fc67d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2805498644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2805498644
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.637126896
Short name T3325
Test name
Test status
Simulation time 241648612 ps
CPU time 0.97 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207636 kb
Host smart-6e2b8c4d-a353-457d-b91d-144540091399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63712
6896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.637126896
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3212277816
Short name T3043
Test name
Test status
Simulation time 159304481 ps
CPU time 0.83 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207496 kb
Host smart-3b01b135-c375-4fb8-9de5-f199ff52ff7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32122
77816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3212277816
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3149123995
Short name T774
Test name
Test status
Simulation time 993539293 ps
CPU time 2.42 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207652 kb
Host smart-8115f00b-1357-4517-876a-45816bd171c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
23995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3149123995
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2160291480
Short name T2474
Test name
Test status
Simulation time 3009782591 ps
CPU time 29.86 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 217632 kb
Host smart-fa57bd14-f13c-45cb-890d-f831d187b4ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
91480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2160291480
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3899746195
Short name T1655
Test name
Test status
Simulation time 3208357732 ps
CPU time 22.13 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207824 kb
Host smart-13253c7b-a0fc-4d84-af93-ecca68c5c20d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899746195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3899746195
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.999473848
Short name T3146
Test name
Test status
Simulation time 564745266 ps
CPU time 1.67 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207648 kb
Host smart-e23eadb4-f564-4872-bd07-a9db0cca77a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999473848 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.999473848
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.455907295
Short name T1515
Test name
Test status
Simulation time 465182331 ps
CPU time 1.36 seconds
Started Aug 08 06:21:45 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207584 kb
Host smart-17b6cc3a-0537-4165-a521-4e8a87aa2421
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455907295 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.455907295
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.2021574346
Short name T167
Test name
Test status
Simulation time 462902101 ps
CPU time 1.4 seconds
Started Aug 08 06:21:53 PM PDT 24
Finished Aug 08 06:21:54 PM PDT 24
Peak memory 207524 kb
Host smart-97f887a7-cd4e-4e02-89ed-9fdc7be5ddd8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021574346 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.2021574346
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.3241757706
Short name T2057
Test name
Test status
Simulation time 615392785 ps
CPU time 1.56 seconds
Started Aug 08 06:21:42 PM PDT 24
Finished Aug 08 06:21:44 PM PDT 24
Peak memory 207536 kb
Host smart-d213a081-1290-4539-a6ca-e2bab0ed45a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241757706 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.3241757706
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.287580661
Short name T2022
Test name
Test status
Simulation time 553872697 ps
CPU time 1.57 seconds
Started Aug 08 06:21:49 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207548 kb
Host smart-6f98fd98-46c9-4773-b8b5-baeda726c5b7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287580661 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.287580661
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.3944570579
Short name T1185
Test name
Test status
Simulation time 510719671 ps
CPU time 1.55 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:01 PM PDT 24
Peak memory 207588 kb
Host smart-aca4127a-d2d7-4873-a129-de48d6a2a605
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944570579 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.3944570579
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.2463381908
Short name T2194
Test name
Test status
Simulation time 461822420 ps
CPU time 1.42 seconds
Started Aug 08 06:22:11 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 207496 kb
Host smart-de962094-1688-435d-8c2d-d3f161d5273d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463381908 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.2463381908
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.39118066
Short name T2100
Test name
Test status
Simulation time 559238834 ps
CPU time 1.51 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207548 kb
Host smart-bd338d7a-7660-4952-9498-eb373c955321
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39118066 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.39118066
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.3230574291
Short name T1267
Test name
Test status
Simulation time 490940556 ps
CPU time 1.55 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207520 kb
Host smart-3603cf45-7317-4963-bc5e-202a7fe88bab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230574291 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.3230574291
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.1466585686
Short name T256
Test name
Test status
Simulation time 537423469 ps
CPU time 1.64 seconds
Started Aug 08 06:22:07 PM PDT 24
Finished Aug 08 06:22:09 PM PDT 24
Peak memory 207592 kb
Host smart-827ec779-699e-49c0-bf5f-ff7dd44b383b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466585686 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.1466585686
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.3157772053
Short name T873
Test name
Test status
Simulation time 511019080 ps
CPU time 1.53 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207572 kb
Host smart-35b84540-6864-4acc-affc-25e29bf624d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157772053 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.3157772053
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.47912787
Short name T3478
Test name
Test status
Simulation time 33968797 ps
CPU time 0.64 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207608 kb
Host smart-eaaacb95-14ac-4735-a6fd-fd5dd4559402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=47912787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.47912787
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1720880104
Short name T2801
Test name
Test status
Simulation time 9366496816 ps
CPU time 12.13 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207836 kb
Host smart-a9d231a8-471d-44a7-85f5-f9351662a14d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720880104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1720880104
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3509754678
Short name T2335
Test name
Test status
Simulation time 14460985191 ps
CPU time 19.65 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 215964 kb
Host smart-4a26b8fc-df3f-4de3-8558-cb692a340713
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509754678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3509754678
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3145974351
Short name T847
Test name
Test status
Simulation time 26063189184 ps
CPU time 34.79 seconds
Started Aug 08 06:18:03 PM PDT 24
Finished Aug 08 06:18:38 PM PDT 24
Peak memory 215980 kb
Host smart-a82d3137-983b-4e2b-82f0-3e8546fcc2c8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145974351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3145974351
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2275956509
Short name T1198
Test name
Test status
Simulation time 148904102 ps
CPU time 0.84 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207540 kb
Host smart-cc573d5e-8af6-49ec-a547-c43b94caf765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759
56509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2275956509
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1651395308
Short name T2575
Test name
Test status
Simulation time 176266495 ps
CPU time 0.87 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207532 kb
Host smart-bc25b180-fa7c-4074-90ff-f3171b730de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16513
95308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1651395308
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.902446316
Short name T2504
Test name
Test status
Simulation time 434016875 ps
CPU time 1.46 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207588 kb
Host smart-1e6b88ed-367b-41a1-8126-b121665253ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90244
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.902446316
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1302438819
Short name T113
Test name
Test status
Simulation time 1070326853 ps
CPU time 3 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207740 kb
Host smart-74e75237-4f3d-4a17-baa4-bb6ed155d544
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1302438819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1302438819
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1222195760
Short name T1673
Test name
Test status
Simulation time 44577129318 ps
CPU time 64.81 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207896 kb
Host smart-d5a5c243-4bf4-4fbf-afb0-b5133adec1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1222195760
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.586160957
Short name T936
Test name
Test status
Simulation time 1163293943 ps
CPU time 26.29 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207756 kb
Host smart-26f5f7b5-60e0-474a-a874-af14663034b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586160957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.586160957
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1567861399
Short name T2864
Test name
Test status
Simulation time 1682918553 ps
CPU time 2.92 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207532 kb
Host smart-e3eedd8f-bb92-476b-a182-bac27c2238d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
61399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1567861399
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2868843996
Short name T1419
Test name
Test status
Simulation time 139870335 ps
CPU time 0.82 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207520 kb
Host smart-80a71d30-687c-40c4-b758-9004f9a61f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28688
43996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2868843996
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.560322921
Short name T3024
Test name
Test status
Simulation time 43632120 ps
CPU time 0.7 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207524 kb
Host smart-a195aba9-362a-4324-b7ca-fab321e1f101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56032
2921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.560322921
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1827729870
Short name T1017
Test name
Test status
Simulation time 904238402 ps
CPU time 2.34 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207772 kb
Host smart-117a1e59-f31c-4d87-8119-b8427d00ee02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18277
29870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1827729870
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.3648073256
Short name T1140
Test name
Test status
Simulation time 342987286 ps
CPU time 1.09 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207536 kb
Host smart-6c4f96d8-8d13-4282-885e-6afeb89bbb72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3648073256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.3648073256
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2875935734
Short name T204
Test name
Test status
Simulation time 431234338 ps
CPU time 2.92 seconds
Started Aug 08 06:18:05 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207712 kb
Host smart-c95b111f-de4e-4858-8012-3243db0b146c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
35734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2875935734
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2386241249
Short name T3300
Test name
Test status
Simulation time 154743757 ps
CPU time 0.93 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207528 kb
Host smart-80d48522-3175-4fd3-9ee1-8b3c47694bd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2386241249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2386241249
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1545525050
Short name T2087
Test name
Test status
Simulation time 141327143 ps
CPU time 0.8 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207504 kb
Host smart-58ed0ca3-8d70-4391-b3b1-d7f5af4999d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
25050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1545525050
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.873696215
Short name T2234
Test name
Test status
Simulation time 188642822 ps
CPU time 0.96 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207556 kb
Host smart-bffe456f-93bb-415d-9ba8-0774ea2de19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87369
6215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.873696215
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.4236539831
Short name T2919
Test name
Test status
Simulation time 3370073798 ps
CPU time 34.68 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:33 PM PDT 24
Peak memory 218484 kb
Host smart-8859fb88-7ec6-407c-a620-6729b9def4fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4236539831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.4236539831
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.260403663
Short name T3237
Test name
Test status
Simulation time 7036614256 ps
CPU time 89.07 seconds
Started Aug 08 06:18:04 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207840 kb
Host smart-8336ab5d-82a7-4be8-a34b-8ea7c74e1ed0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=260403663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.260403663
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3726982015
Short name T893
Test name
Test status
Simulation time 233561836 ps
CPU time 0.97 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207600 kb
Host smart-40b117f5-5966-43b4-ac12-e39a66aa8b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37269
82015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3726982015
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3683609572
Short name T1410
Test name
Test status
Simulation time 6873495991 ps
CPU time 11.89 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207852 kb
Host smart-162e2d4a-9dd5-4b9a-bf48-a35f90649a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
09572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3683609572
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2136338580
Short name T3538
Test name
Test status
Simulation time 3711165079 ps
CPU time 5.82 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:04 PM PDT 24
Peak memory 216192 kb
Host smart-97dec745-0275-45ab-900e-c992e8b5e7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21363
38580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2136338580
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2829324235
Short name T3529
Test name
Test status
Simulation time 4612571513 ps
CPU time 45.28 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 218756 kb
Host smart-f4ec5ff3-fd60-46de-9d1b-c0387424c7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
24235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2829324235
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1840558459
Short name T2964
Test name
Test status
Simulation time 2260457201 ps
CPU time 22.16 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:18:15 PM PDT 24
Peak memory 216052 kb
Host smart-4cba1ad8-2e27-468b-95c6-ffc9cf1421ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1840558459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1840558459
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2840690919
Short name T3255
Test name
Test status
Simulation time 258170862 ps
CPU time 1.02 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207584 kb
Host smart-cf52b5b0-3f6d-40f0-ba0d-dccae74f5247
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2840690919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2840690919
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.616447161
Short name T2777
Test name
Test status
Simulation time 190017305 ps
CPU time 0.93 seconds
Started Aug 08 06:18:13 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 207512 kb
Host smart-2927802e-31ab-490a-8a3a-3c031f4913be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61644
7161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.616447161
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.61203055
Short name T2063
Test name
Test status
Simulation time 2369602164 ps
CPU time 19.16 seconds
Started Aug 08 06:18:03 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 216144 kb
Host smart-280d6546-81f7-4a70-8c50-66b9a6e353cb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=61203055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.61203055
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1443834843
Short name T1170
Test name
Test status
Simulation time 185908894 ps
CPU time 0.86 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207592 kb
Host smart-4147e203-de1b-4783-867b-2c6052088fe4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1443834843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1443834843
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.605664999
Short name T2000
Test name
Test status
Simulation time 153384320 ps
CPU time 0.87 seconds
Started Aug 08 06:17:49 PM PDT 24
Finished Aug 08 06:17:50 PM PDT 24
Peak memory 207544 kb
Host smart-c128dcd2-fd6e-470c-9d15-8b16a15cf838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60566
4999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.605664999
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1910569545
Short name T130
Test name
Test status
Simulation time 239186516 ps
CPU time 0.97 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207588 kb
Host smart-15de627d-cde7-4f1c-be43-03e609d118cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
69545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1910569545
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2726261339
Short name T1666
Test name
Test status
Simulation time 155365467 ps
CPU time 0.93 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207564 kb
Host smart-547089a5-3cb7-497c-8db6-db7e062be095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27262
61339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2726261339
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1773460284
Short name T3625
Test name
Test status
Simulation time 163589778 ps
CPU time 0.86 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207572 kb
Host smart-1836c76b-3299-454b-a68d-d2d7dc1dd5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
60284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1773460284
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.433718715
Short name T2202
Test name
Test status
Simulation time 189225444 ps
CPU time 0.99 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207544 kb
Host smart-e4f48a23-ad0f-471c-b710-b19bf6c6efa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43371
8715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.433718715
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.870056511
Short name T172
Test name
Test status
Simulation time 142464741 ps
CPU time 0.99 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207572 kb
Host smart-77034f19-7e4e-4977-ba5d-2df2b532f518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87005
6511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.870056511
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.4113290918
Short name T2382
Test name
Test status
Simulation time 247054768 ps
CPU time 1.04 seconds
Started Aug 08 06:18:02 PM PDT 24
Finished Aug 08 06:18:04 PM PDT 24
Peak memory 207572 kb
Host smart-20746f0e-e9a3-43b6-acbe-67928dfe1a91
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4113290918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.4113290918
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.247749734
Short name T2424
Test name
Test status
Simulation time 159815466 ps
CPU time 0.81 seconds
Started Aug 08 06:18:02 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 207516 kb
Host smart-08422db5-3359-4c33-bff6-5e3d16027f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24774
9734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.247749734
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1280365283
Short name T819
Test name
Test status
Simulation time 46798367 ps
CPU time 0.7 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207512 kb
Host smart-20e9dbd0-84d8-40b4-b912-fa69913916f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
65283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1280365283
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1192804367
Short name T512
Test name
Test status
Simulation time 9461184490 ps
CPU time 24.63 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 216080 kb
Host smart-237d157f-6e0c-4d7b-b2a1-dd54062aef35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
04367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1192804367
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3784464305
Short name T2566
Test name
Test status
Simulation time 158542296 ps
CPU time 0.87 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207560 kb
Host smart-0ea43283-5665-446d-b946-236985fcbda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37844
64305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3784464305
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3895796465
Short name T3058
Test name
Test status
Simulation time 171144563 ps
CPU time 0.89 seconds
Started Aug 08 06:17:50 PM PDT 24
Finished Aug 08 06:17:51 PM PDT 24
Peak memory 207480 kb
Host smart-bda067ea-3c69-4bc3-92a6-6f7c9ccb5a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
96465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3895796465
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2953057190
Short name T2949
Test name
Test status
Simulation time 206608765 ps
CPU time 0.94 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207500 kb
Host smart-0168f36a-0d2e-46f6-adcc-eeffb58e1fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
57190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2953057190
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1691055307
Short name T3552
Test name
Test status
Simulation time 159753089 ps
CPU time 0.95 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207564 kb
Host smart-5cdee103-734e-4717-9fc9-3da755d85997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
55307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1691055307
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3871726104
Short name T1706
Test name
Test status
Simulation time 140732649 ps
CPU time 0.78 seconds
Started Aug 08 06:18:04 PM PDT 24
Finished Aug 08 06:18:04 PM PDT 24
Peak memory 207480 kb
Host smart-c7638283-cebd-4611-ba5b-ab44058bcb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
26104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3871726104
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.1253863473
Short name T3224
Test name
Test status
Simulation time 383268635 ps
CPU time 1.31 seconds
Started Aug 08 06:17:54 PM PDT 24
Finished Aug 08 06:17:55 PM PDT 24
Peak memory 207576 kb
Host smart-3825f0a8-1419-4415-93d2-7c33f49c0075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
63473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.1253863473
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.308873755
Short name T3340
Test name
Test status
Simulation time 151283578 ps
CPU time 0.82 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207616 kb
Host smart-408b643b-5e5a-4411-8ba7-aac53625cc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30887
3755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.308873755
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3959660346
Short name T858
Test name
Test status
Simulation time 180316023 ps
CPU time 0.93 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207792 kb
Host smart-344acd85-1599-4419-a6f6-6c6dfbd5329f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39596
60346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3959660346
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2196377085
Short name T2098
Test name
Test status
Simulation time 233094085 ps
CPU time 1.05 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207496 kb
Host smart-163a8d28-c4b1-41fc-83a3-153dc0820454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21963
77085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2196377085
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3515429236
Short name T1350
Test name
Test status
Simulation time 2822870600 ps
CPU time 81.01 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 217892 kb
Host smart-d13e813d-b0fe-4f3a-a4c8-2f1e569afdaa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3515429236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3515429236
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2743002624
Short name T1894
Test name
Test status
Simulation time 155363768 ps
CPU time 0.88 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207512 kb
Host smart-8e1284f5-c135-4ca2-b40a-dd4b624c2fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
02624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2743002624
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1881165684
Short name T738
Test name
Test status
Simulation time 159301831 ps
CPU time 0.82 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:56 PM PDT 24
Peak memory 207504 kb
Host smart-3eb9eec4-8073-4314-8b6a-b8cc0e96f409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
65684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1881165684
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.4091922696
Short name T709
Test name
Test status
Simulation time 524812380 ps
CPU time 1.49 seconds
Started Aug 08 06:17:56 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207564 kb
Host smart-d15381fd-3ac4-42f0-a5d0-8f2c987448ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
22696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.4091922696
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.234560410
Short name T2597
Test name
Test status
Simulation time 2001964332 ps
CPU time 15.87 seconds
Started Aug 08 06:18:03 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 215952 kb
Host smart-a5e9e4cc-9266-4b8b-b195-795d936a5694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23456
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.234560410
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.1086421675
Short name T1335
Test name
Test status
Simulation time 190956088 ps
CPU time 0.9 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207576 kb
Host smart-50f7863a-7177-4a9a-a4db-cad3b1bc128b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086421675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.1086421675
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.4007389977
Short name T662
Test name
Test status
Simulation time 535450850 ps
CPU time 1.57 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207596 kb
Host smart-76821e88-0815-4de2-a8e9-51c5d6b648dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007389977 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.4007389977
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.2916671587
Short name T1949
Test name
Test status
Simulation time 550388946 ps
CPU time 1.61 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207536 kb
Host smart-ac7c3ba6-4f26-4e3f-9f77-a2309b6ea795
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916671587 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.2916671587
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.1288734942
Short name T3524
Test name
Test status
Simulation time 430226092 ps
CPU time 1.49 seconds
Started Aug 08 06:22:12 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 207584 kb
Host smart-33029690-04af-44b7-8964-651a20979d7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288734942 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.1288734942
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.1800715680
Short name T35
Test name
Test status
Simulation time 621451030 ps
CPU time 1.62 seconds
Started Aug 08 06:22:09 PM PDT 24
Finished Aug 08 06:22:11 PM PDT 24
Peak memory 207592 kb
Host smart-40c8c41d-107a-4305-842a-3faa102b122e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800715680 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.1800715680
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.3055478606
Short name T2697
Test name
Test status
Simulation time 532489458 ps
CPU time 1.47 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207520 kb
Host smart-a2c1681a-6fd0-420c-a64c-45078b33ed63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055478606 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.3055478606
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.2704445135
Short name T2168
Test name
Test status
Simulation time 522193190 ps
CPU time 1.57 seconds
Started Aug 08 06:22:17 PM PDT 24
Finished Aug 08 06:22:19 PM PDT 24
Peak memory 207620 kb
Host smart-a955dc2a-d439-405f-9ef8-aa744cdb0e25
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704445135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.2704445135
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.2596304005
Short name T888
Test name
Test status
Simulation time 607750291 ps
CPU time 1.6 seconds
Started Aug 08 06:22:12 PM PDT 24
Finished Aug 08 06:22:14 PM PDT 24
Peak memory 207540 kb
Host smart-7b3c3658-0a55-420c-b4c0-9e95f02123ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596304005 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.2596304005
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.3184150070
Short name T3095
Test name
Test status
Simulation time 446575447 ps
CPU time 1.4 seconds
Started Aug 08 06:22:17 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207572 kb
Host smart-81ef8bc9-f31f-4cea-bc17-dde726900de5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184150070 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.3184150070
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.1004827305
Short name T2559
Test name
Test status
Simulation time 573430785 ps
CPU time 1.49 seconds
Started Aug 08 06:21:59 PM PDT 24
Finished Aug 08 06:22:01 PM PDT 24
Peak memory 207580 kb
Host smart-7a060808-4ed0-4c97-bbb6-a5de2b2e9ce0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004827305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.1004827305
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.1850674869
Short name T3125
Test name
Test status
Simulation time 508203316 ps
CPU time 1.6 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207516 kb
Host smart-35e314b7-c17b-4832-9cda-2c1bb357a43c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850674869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.1850674869
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.3275103574
Short name T1029
Test name
Test status
Simulation time 515567410 ps
CPU time 1.64 seconds
Started Aug 08 06:22:07 PM PDT 24
Finished Aug 08 06:22:08 PM PDT 24
Peak memory 207584 kb
Host smart-a2e6474a-bfe5-4581-a443-970ab4105bd7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275103574 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.3275103574
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3176817639
Short name T1078
Test name
Test status
Simulation time 51979722 ps
CPU time 0.71 seconds
Started Aug 08 06:18:11 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207556 kb
Host smart-cfb15958-f1cb-4c37-9044-744ecd5823a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3176817639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3176817639
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3225905701
Short name T988
Test name
Test status
Simulation time 5347660881 ps
CPU time 8.16 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 216004 kb
Host smart-e972c25d-8e12-4630-aa5c-8fe14e04236c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225905701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.3225905701
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3589187219
Short name T3240
Test name
Test status
Simulation time 15704632594 ps
CPU time 18.92 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 216040 kb
Host smart-f0410464-5072-4bc9-8fd3-aff93a61d779
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589187219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3589187219
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.4006577130
Short name T2899
Test name
Test status
Simulation time 24077759526 ps
CPU time 31.95 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 216004 kb
Host smart-eef78753-9dd7-4bb8-8b22-b86786adaf0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006577130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.4006577130
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.810672190
Short name T1079
Test name
Test status
Simulation time 162571014 ps
CPU time 0.93 seconds
Started Aug 08 06:18:01 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 207592 kb
Host smart-a19de0e3-f7ac-4a3f-9916-3ed34fd70d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81067
2190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.810672190
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3191996215
Short name T2881
Test name
Test status
Simulation time 146079762 ps
CPU time 0.86 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207496 kb
Host smart-810ded42-3c86-452d-8a7d-1791bd927c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919
96215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3191996215
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.4102280686
Short name T3617
Test name
Test status
Simulation time 522356871 ps
CPU time 1.61 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:17:57 PM PDT 24
Peak memory 207532 kb
Host smart-32d19e09-9d3e-4a54-a987-598b3a60faec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022
80686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.4102280686
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2593165273
Short name T2702
Test name
Test status
Simulation time 626991204 ps
CPU time 2.09 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 207664 kb
Host smart-3a2deed5-6392-455e-8b5e-f8bcda6a9ded
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2593165273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2593165273
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.712713827
Short name T2588
Test name
Test status
Simulation time 30166840380 ps
CPU time 51.75 seconds
Started Aug 08 06:18:06 PM PDT 24
Finished Aug 08 06:18:58 PM PDT 24
Peak memory 207824 kb
Host smart-630dfa7e-69c0-4335-9d79-6d3c744b2a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271
3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.712713827
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.1754517871
Short name T2897
Test name
Test status
Simulation time 422068686 ps
CPU time 8.04 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207744 kb
Host smart-d169c428-3e1b-4f7b-b120-b9da1eb03d4a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754517871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.1754517871
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3490810281
Short name T1390
Test name
Test status
Simulation time 831806197 ps
CPU time 2.08 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 207516 kb
Host smart-cb777a26-4902-4597-bc4e-6dafdad65ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
10281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3490810281
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2626133847
Short name T1626
Test name
Test status
Simulation time 141729699 ps
CPU time 0.85 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207528 kb
Host smart-1ecaef6b-9a6a-42de-ab94-421412a59d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
33847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2626133847
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.237758282
Short name T2028
Test name
Test status
Simulation time 31489312 ps
CPU time 0.68 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:17:53 PM PDT 24
Peak memory 207520 kb
Host smart-f34caa03-b00f-4048-ac82-24602715b789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
8282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.237758282
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1800366400
Short name T1589
Test name
Test status
Simulation time 962887391 ps
CPU time 2.81 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:01 PM PDT 24
Peak memory 207676 kb
Host smart-aa63c9c9-43e1-473e-b3f5-b90437e3f48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
66400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1800366400
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.2428523006
Short name T3471
Test name
Test status
Simulation time 176369198 ps
CPU time 0.92 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207548 kb
Host smart-5c83fa38-742f-4e31-84e0-bee68fc4cb85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2428523006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.2428523006
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.585057723
Short name T1103
Test name
Test status
Simulation time 191547916 ps
CPU time 2.34 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207692 kb
Host smart-c2168546-bb40-41b4-9dff-e66df11c169f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58505
7723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.585057723
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1075139814
Short name T2927
Test name
Test status
Simulation time 166452340 ps
CPU time 0.95 seconds
Started Aug 08 06:17:57 PM PDT 24
Finished Aug 08 06:17:58 PM PDT 24
Peak memory 207564 kb
Host smart-3460fad1-5dff-40c9-b11c-2dde9973e86f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1075139814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1075139814
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2876869150
Short name T1474
Test name
Test status
Simulation time 226050107 ps
CPU time 0.92 seconds
Started Aug 08 06:17:51 PM PDT 24
Finished Aug 08 06:17:52 PM PDT 24
Peak memory 207512 kb
Host smart-ba1b2c0f-2503-44a7-8299-c88c888bdb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
69150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2876869150
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.301102444
Short name T2589
Test name
Test status
Simulation time 186945400 ps
CPU time 0.93 seconds
Started Aug 08 06:17:53 PM PDT 24
Finished Aug 08 06:17:54 PM PDT 24
Peak memory 207564 kb
Host smart-13cc9109-d18a-48fb-988e-b62e728fbee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
2444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.301102444
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3134969805
Short name T552
Test name
Test status
Simulation time 3436032816 ps
CPU time 31.97 seconds
Started Aug 08 06:17:55 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 224260 kb
Host smart-c62b54b7-635d-488a-a9a5-d71ab2974a99
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3134969805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3134969805
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.3611514657
Short name T3623
Test name
Test status
Simulation time 3626925687 ps
CPU time 44.86 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207788 kb
Host smart-8225ac24-ece6-46f5-ac8f-f45662497175
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3611514657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.3611514657
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2528076820
Short name T1366
Test name
Test status
Simulation time 197631832 ps
CPU time 0.97 seconds
Started Aug 08 06:18:01 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 207564 kb
Host smart-860cca2c-782f-4129-aa25-6e08c2c9b097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25280
76820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2528076820
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1921980299
Short name T21
Test name
Test status
Simulation time 31054240383 ps
CPU time 52.73 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:19:00 PM PDT 24
Peak memory 207868 kb
Host smart-42235d8a-11e4-43f9-953e-63358b65ad64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19219
80299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1921980299
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3301741511
Short name T2081
Test name
Test status
Simulation time 10675389223 ps
CPU time 14.73 seconds
Started Aug 08 06:18:01 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207880 kb
Host smart-b5091bd9-5d82-4bc1-a224-d3926b7d0e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33017
41511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3301741511
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1235879839
Short name T2364
Test name
Test status
Simulation time 3408673897 ps
CPU time 94.2 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 224264 kb
Host smart-f3fb1356-b971-43cb-bb0d-4128477038ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12358
79839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1235879839
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1105752913
Short name T2810
Test name
Test status
Simulation time 4307889301 ps
CPU time 44.38 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:52 PM PDT 24
Peak memory 217672 kb
Host smart-6a89a695-581e-4d1b-9336-88d3570ca936
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1105752913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1105752913
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3584730552
Short name T2832
Test name
Test status
Simulation time 259799575 ps
CPU time 1.02 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:17:59 PM PDT 24
Peak memory 207536 kb
Host smart-6492faf9-b91f-46b6-9b5a-53dd12a8f583
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3584730552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3584730552
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3969864157
Short name T3013
Test name
Test status
Simulation time 247875788 ps
CPU time 0.99 seconds
Started Aug 08 06:18:01 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 207524 kb
Host smart-5b644f28-f012-4ff7-a600-099bb9524ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39698
64157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3969864157
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2520413957
Short name T3288
Test name
Test status
Simulation time 4124593691 ps
CPU time 41.42 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 217740 kb
Host smart-bf49d7ee-9365-4b97-852e-f5ac04c17bd3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2520413957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2520413957
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1039124826
Short name T3129
Test name
Test status
Simulation time 181125061 ps
CPU time 0.87 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207600 kb
Host smart-79bddc97-a08f-4991-bc80-8bdf114aa317
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1039124826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1039124826
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3561834455
Short name T1573
Test name
Test status
Simulation time 167166045 ps
CPU time 0.85 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207520 kb
Host smart-bd894cae-a63c-4e2d-b5c8-3a67b7526298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35618
34455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3561834455
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.474217474
Short name T2889
Test name
Test status
Simulation time 182652594 ps
CPU time 0.94 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207556 kb
Host smart-05d170c3-c172-45e9-a8a2-4267e09d5240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47421
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.474217474
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3821118173
Short name T287
Test name
Test status
Simulation time 155929327 ps
CPU time 0.81 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207560 kb
Host smart-a4fff097-9a9b-4fa0-839d-02cd613cc93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38211
18173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3821118173
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2011117294
Short name T2377
Test name
Test status
Simulation time 159776889 ps
CPU time 0.84 seconds
Started Aug 08 06:18:05 PM PDT 24
Finished Aug 08 06:18:06 PM PDT 24
Peak memory 207564 kb
Host smart-663afa11-bfc8-41fb-9c7f-143dcc97f776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111
17294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2011117294
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3928586696
Short name T1417
Test name
Test status
Simulation time 165639461 ps
CPU time 0.94 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 207540 kb
Host smart-75e22a26-713f-4dca-8268-331728f0b370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285
86696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3928586696
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3165507808
Short name T585
Test name
Test status
Simulation time 241456568 ps
CPU time 1.07 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207592 kb
Host smart-9dedff07-b658-4381-a360-d82e57e9b841
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3165507808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3165507808
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3762970565
Short name T1347
Test name
Test status
Simulation time 147465900 ps
CPU time 0.84 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:18:25 PM PDT 24
Peak memory 207512 kb
Host smart-112b94b2-8d73-4701-b535-d95825dc6b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37629
70565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3762970565
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1756115955
Short name T2477
Test name
Test status
Simulation time 39320244 ps
CPU time 0.68 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207504 kb
Host smart-dc553f5a-f1d9-4324-94df-faf521a2c57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
15955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1756115955
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3784097810
Short name T2722
Test name
Test status
Simulation time 19036534039 ps
CPU time 48.91 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 216036 kb
Host smart-da536605-8595-4954-ad63-3d8e6e01894f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
97810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3784097810
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2677492786
Short name T1163
Test name
Test status
Simulation time 180000648 ps
CPU time 0.9 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207544 kb
Host smart-1584f610-3a35-4d3f-8715-8e890519b1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
92786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2677492786
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1474372091
Short name T3204
Test name
Test status
Simulation time 165336992 ps
CPU time 0.92 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:18 PM PDT 24
Peak memory 207520 kb
Host smart-b5dab4d2-7969-4160-8347-b75aaedf92a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743
72091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1474372091
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2995751797
Short name T2552
Test name
Test status
Simulation time 287365812 ps
CPU time 1.06 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207608 kb
Host smart-50e690fc-a17c-4962-9956-d65e9336862a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29957
51797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2995751797
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1870331329
Short name T547
Test name
Test status
Simulation time 175730890 ps
CPU time 0.88 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 207500 kb
Host smart-a969277b-ce9b-4f6b-b025-f2c675de891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18703
31329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1870331329
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.37119680
Short name T1424
Test name
Test status
Simulation time 178002599 ps
CPU time 0.84 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:09 PM PDT 24
Peak memory 207492 kb
Host smart-9c46048c-b574-4e41-8e48-cc297f5c3e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37119
680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.37119680
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.2351976998
Short name T1071
Test name
Test status
Simulation time 367965129 ps
CPU time 1.3 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207608 kb
Host smart-e0f1c612-eab5-4fd6-bcc2-65944619cfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23519
76998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2351976998
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1973884723
Short name T2629
Test name
Test status
Simulation time 145079439 ps
CPU time 0.8 seconds
Started Aug 08 06:18:06 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207436 kb
Host smart-9d066594-e532-4d33-984a-5b217d817f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738
84723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1973884723
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1841965319
Short name T3246
Test name
Test status
Simulation time 147157345 ps
CPU time 0.84 seconds
Started Aug 08 06:18:13 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 207572 kb
Host smart-6eeaf270-7213-463b-9418-d32ee06c3e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18419
65319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1841965319
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2547421542
Short name T582
Test name
Test status
Simulation time 265695565 ps
CPU time 1.01 seconds
Started Aug 08 06:18:20 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207528 kb
Host smart-78be722b-03d7-43f6-9095-660a1fff6917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
21542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2547421542
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1697892380
Short name T1130
Test name
Test status
Simulation time 2462081800 ps
CPU time 18.26 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 218120 kb
Host smart-a38d3e2b-12fb-48b1-8c51-7306f603bca0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1697892380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1697892380
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.386542865
Short name T3123
Test name
Test status
Simulation time 190044152 ps
CPU time 0.94 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207508 kb
Host smart-1a3dcd0d-b393-4ef6-ab3c-dc5f4d89a93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
2865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.386542865
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.930065675
Short name T2161
Test name
Test status
Simulation time 184763776 ps
CPU time 0.91 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207588 kb
Host smart-5ffd4179-a485-4a52-a739-2aebd7e4980b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93006
5675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.930065675
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1555605764
Short name T2322
Test name
Test status
Simulation time 785021390 ps
CPU time 2.03 seconds
Started Aug 08 06:18:13 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207732 kb
Host smart-9c2237e6-2488-4e56-9da5-2c64bcc5da83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556
05764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1555605764
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3657991256
Short name T3198
Test name
Test status
Simulation time 2570324854 ps
CPU time 73.93 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 216040 kb
Host smart-6b352a51-e742-451e-81c3-529721717738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36579
91256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3657991256
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.4244897276
Short name T3516
Test name
Test status
Simulation time 3711270783 ps
CPU time 27.12 seconds
Started Aug 08 06:17:52 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207876 kb
Host smart-f3c30c66-a8c3-409b-a621-46d4ed5352c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244897276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.4244897276
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.3523551393
Short name T2726
Test name
Test status
Simulation time 529856938 ps
CPU time 1.61 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 207620 kb
Host smart-31b15e36-73a0-4c7a-9b2c-df9bc6de5979
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523551393 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.3523551393
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.4259072690
Short name T2807
Test name
Test status
Simulation time 597019295 ps
CPU time 1.7 seconds
Started Aug 08 06:22:05 PM PDT 24
Finished Aug 08 06:22:07 PM PDT 24
Peak memory 207536 kb
Host smart-36ac5304-9e7b-420c-9064-cd412ca36185
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259072690 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.4259072690
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.1784867029
Short name T1034
Test name
Test status
Simulation time 495363078 ps
CPU time 1.54 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207548 kb
Host smart-cc386311-3503-4559-a272-87ae2719d3ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784867029 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.1784867029
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.3316105273
Short name T1978
Test name
Test status
Simulation time 510490843 ps
CPU time 1.59 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207540 kb
Host smart-759038af-6d71-4477-b97b-dbf83a365ef7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316105273 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.3316105273
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.1456303833
Short name T1109
Test name
Test status
Simulation time 508408064 ps
CPU time 1.53 seconds
Started Aug 08 06:22:07 PM PDT 24
Finished Aug 08 06:22:09 PM PDT 24
Peak memory 207524 kb
Host smart-610a93c8-b780-4d77-836a-9a2d0dccd8b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456303833 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.1456303833
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.1274814536
Short name T852
Test name
Test status
Simulation time 588535735 ps
CPU time 1.68 seconds
Started Aug 08 06:22:06 PM PDT 24
Finished Aug 08 06:22:07 PM PDT 24
Peak memory 207612 kb
Host smart-ac80210f-b1bb-4da4-ab9a-74924b61620a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274814536 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.1274814536
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.602784956
Short name T124
Test name
Test status
Simulation time 590349567 ps
CPU time 1.69 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:16 PM PDT 24
Peak memory 207600 kb
Host smart-30549f32-1990-4f66-a883-4bf3cf3b46bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602784956 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.602784956
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.3416854967
Short name T3464
Test name
Test status
Simulation time 490958351 ps
CPU time 1.45 seconds
Started Aug 08 06:22:01 PM PDT 24
Finished Aug 08 06:22:07 PM PDT 24
Peak memory 207540 kb
Host smart-d77de036-2584-43e1-be52-937e2f5a7901
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416854967 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.3416854967
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.2475139689
Short name T1275
Test name
Test status
Simulation time 558253633 ps
CPU time 1.71 seconds
Started Aug 08 06:22:10 PM PDT 24
Finished Aug 08 06:22:12 PM PDT 24
Peak memory 207580 kb
Host smart-a04b5f19-3799-4b3f-a32a-9c0f9aca95a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475139689 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.2475139689
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.126653315
Short name T182
Test name
Test status
Simulation time 560415943 ps
CPU time 1.61 seconds
Started Aug 08 06:22:09 PM PDT 24
Finished Aug 08 06:22:11 PM PDT 24
Peak memory 207616 kb
Host smart-9454b743-f866-4d75-bb4b-291e0961009f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126653315 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.126653315
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3789032804
Short name T1013
Test name
Test status
Simulation time 36900692 ps
CPU time 0.72 seconds
Started Aug 08 06:18:27 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207512 kb
Host smart-8ebdfebc-f6f3-40fc-90ec-adaf699fd240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3789032804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3789032804
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1253164322
Short name T825
Test name
Test status
Simulation time 9999622208 ps
CPU time 12.53 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207892 kb
Host smart-8c686185-0099-44d1-8213-edb46b01890a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253164322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1253164322
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2790407898
Short name T2444
Test name
Test status
Simulation time 20761670224 ps
CPU time 26.4 seconds
Started Aug 08 06:18:13 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 207856 kb
Host smart-ecbaeacd-f064-4cc7-82c3-0e325846311c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790407898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2790407898
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.501414068
Short name T849
Test name
Test status
Simulation time 23527674171 ps
CPU time 29.46 seconds
Started Aug 08 06:18:37 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 216076 kb
Host smart-88e755af-a90e-498d-9ca0-20355e454596
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501414068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_resume.501414068
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1191338338
Short name T1226
Test name
Test status
Simulation time 149418964 ps
CPU time 0.85 seconds
Started Aug 08 06:18:23 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207592 kb
Host smart-8516749a-4338-43bb-a04e-9b0ceed29437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
38338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1191338338
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3850638
Short name T2192
Test name
Test status
Simulation time 153592460 ps
CPU time 0.86 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207528 kb
Host smart-db0c7250-8f91-4b38-897b-8db84d38695e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3850638
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2289495631
Short name T3118
Test name
Test status
Simulation time 248425820 ps
CPU time 1.1 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207576 kb
Host smart-a8f41459-0896-4bd7-a908-7e3701ee11b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22894
95631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2289495631
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1464368721
Short name T127
Test name
Test status
Simulation time 653313136 ps
CPU time 2.04 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207792 kb
Host smart-397122d4-12dd-4749-b02e-d58065a20460
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1464368721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1464368721
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.438043669
Short name T1385
Test name
Test status
Simulation time 1392037435 ps
CPU time 35.69 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207748 kb
Host smart-8b283ede-6fe9-4c8b-a5dd-0d59b9e1f22a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438043669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.438043669
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1580996662
Short name T371
Test name
Test status
Simulation time 1271563358 ps
CPU time 2.52 seconds
Started Aug 08 06:18:29 PM PDT 24
Finished Aug 08 06:18:31 PM PDT 24
Peak memory 207580 kb
Host smart-81bd01b7-da62-4e54-8bfc-ce3cb7303763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
96662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1580996662
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1236988234
Short name T3294
Test name
Test status
Simulation time 143355908 ps
CPU time 0.83 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207520 kb
Host smart-8f98e91a-7506-4b11-984c-232b894b26b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12369
88234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1236988234
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3013250076
Short name T2821
Test name
Test status
Simulation time 56803928 ps
CPU time 0.71 seconds
Started Aug 08 06:18:01 PM PDT 24
Finished Aug 08 06:18:02 PM PDT 24
Peak memory 207476 kb
Host smart-acf66a3c-ed4b-4cb9-8e73-54634ff57512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30132
50076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3013250076
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2528501132
Short name T1986
Test name
Test status
Simulation time 926922910 ps
CPU time 2.45 seconds
Started Aug 08 06:18:20 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 207768 kb
Host smart-199a422f-026a-4471-a0f2-a772c274b92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
01132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2528501132
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.852241663
Short name T2947
Test name
Test status
Simulation time 356865603 ps
CPU time 1.22 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207564 kb
Host smart-507b2e27-645c-4cdb-b280-8740fcb49591
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=852241663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.852241663
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1223098163
Short name T638
Test name
Test status
Simulation time 164071777 ps
CPU time 1.63 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 207708 kb
Host smart-a799ddd1-2d30-49b7-b5de-fb5c6ef9f8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
98163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1223098163
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2457883818
Short name T2651
Test name
Test status
Simulation time 245301536 ps
CPU time 1.14 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 215976 kb
Host smart-a5c55bfe-9387-46bb-8b72-14ac03c5d5f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2457883818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2457883818
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3966559510
Short name T2873
Test name
Test status
Simulation time 135493878 ps
CPU time 0.82 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207452 kb
Host smart-faf7e01e-57dd-421c-a512-a6ca24654e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39665
59510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3966559510
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1155665295
Short name T2239
Test name
Test status
Simulation time 160695923 ps
CPU time 0.86 seconds
Started Aug 08 06:17:59 PM PDT 24
Finished Aug 08 06:18:00 PM PDT 24
Peak memory 207564 kb
Host smart-22056d3e-873c-4997-801a-29c3d5371154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556
65295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1155665295
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.4081091209
Short name T2113
Test name
Test status
Simulation time 2702043077 ps
CPU time 21.21 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 218732 kb
Host smart-b8699b0e-a7cb-454a-a923-b094534ce0be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4081091209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.4081091209
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2785033486
Short name T3487
Test name
Test status
Simulation time 4723170252 ps
CPU time 60.57 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:19:24 PM PDT 24
Peak memory 207780 kb
Host smart-16d977ad-2d30-4aeb-b7bd-cacff03ebbd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2785033486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2785033486
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.749119736
Short name T879
Test name
Test status
Simulation time 202352665 ps
CPU time 0.94 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207524 kb
Host smart-67983bb4-5163-47f0-b578-31ac758ebc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74911
9736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.749119736
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1317239400
Short name T2103
Test name
Test status
Simulation time 30964473446 ps
CPU time 48.61 seconds
Started Aug 08 06:18:05 PM PDT 24
Finished Aug 08 06:18:53 PM PDT 24
Peak memory 207904 kb
Host smart-07e59727-3858-4561-91f3-d5ffdce8d7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172
39400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1317239400
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3525419818
Short name T867
Test name
Test status
Simulation time 3329143856 ps
CPU time 5.07 seconds
Started Aug 08 06:17:58 PM PDT 24
Finished Aug 08 06:18:03 PM PDT 24
Peak memory 216024 kb
Host smart-dee6284a-78dc-48e7-a1ac-6086a17d5508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
19818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3525419818
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2104858184
Short name T3335
Test name
Test status
Simulation time 3325603195 ps
CPU time 23.95 seconds
Started Aug 08 06:18:06 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 224272 kb
Host smart-91ff03f2-4233-41b1-8cd7-76c713d04d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21048
58184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2104858184
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.999326454
Short name T800
Test name
Test status
Simulation time 1750136822 ps
CPU time 16.98 seconds
Started Aug 08 06:18:11 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 216920 kb
Host smart-2392434f-768a-4e46-b184-ca2a65e61301
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=999326454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.999326454
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2021159957
Short name T1504
Test name
Test status
Simulation time 276314897 ps
CPU time 1.11 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:18:11 PM PDT 24
Peak memory 207556 kb
Host smart-97bb3a3b-c703-406f-bfcc-5400ff017f0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2021159957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2021159957
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.552853910
Short name T2988
Test name
Test status
Simulation time 196276916 ps
CPU time 0.96 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:01 PM PDT 24
Peak memory 207548 kb
Host smart-372c7c8c-240d-4d66-be83-642bbab80c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55285
3910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.552853910
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3120762854
Short name T1118
Test name
Test status
Simulation time 2821563800 ps
CPU time 83.6 seconds
Started Aug 08 06:18:10 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 217616 kb
Host smart-9ef35f41-e437-4a26-8c8f-f7f890b6d9d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3120762854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3120762854
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2308143525
Short name T3444
Test name
Test status
Simulation time 176362690 ps
CPU time 0.88 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207544 kb
Host smart-b05c2841-10ca-4547-8c8b-6dd67bd5033f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2308143525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2308143525
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1734736103
Short name T1695
Test name
Test status
Simulation time 147450552 ps
CPU time 0.8 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207544 kb
Host smart-ad0b7e31-ea9f-4ed7-80ee-33beedc7733a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347
36103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1734736103
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.16203598
Short name T3140
Test name
Test status
Simulation time 262904778 ps
CPU time 1.06 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207540 kb
Host smart-26fc9471-eae6-4498-9e52-1e5463a478ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16203
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.16203598
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3994411170
Short name T984
Test name
Test status
Simulation time 176592351 ps
CPU time 0.9 seconds
Started Aug 08 06:18:08 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 207564 kb
Host smart-c9b560c1-d05b-44a5-a40f-d93bc3a2276f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39944
11170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3994411170
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2780163947
Short name T3328
Test name
Test status
Simulation time 191496474 ps
CPU time 0.9 seconds
Started Aug 08 06:18:07 PM PDT 24
Finished Aug 08 06:18:08 PM PDT 24
Peak memory 207528 kb
Host smart-be8f9277-40d2-4e59-872e-a043ca9fd95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
63947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2780163947
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3714553035
Short name T2378
Test name
Test status
Simulation time 206332686 ps
CPU time 0.97 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207628 kb
Host smart-c95cc40e-e683-4f4d-83ae-64f3509ff4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145
53035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3714553035
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1244068533
Short name T3594
Test name
Test status
Simulation time 165541208 ps
CPU time 0.88 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207476 kb
Host smart-671bff65-e3a8-4d77-af2b-54a75cc54056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
68533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1244068533
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.4066144293
Short name T1751
Test name
Test status
Simulation time 243996648 ps
CPU time 1 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 207548 kb
Host smart-f61b28c8-3bd9-4e32-9505-e1b47e490f61
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4066144293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.4066144293
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.510474403
Short name T3080
Test name
Test status
Simulation time 157314765 ps
CPU time 0.81 seconds
Started Aug 08 06:18:06 PM PDT 24
Finished Aug 08 06:18:07 PM PDT 24
Peak memory 207604 kb
Host smart-d1b80176-d5c5-4368-810f-77753158c49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51047
4403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.510474403
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1412850381
Short name T1315
Test name
Test status
Simulation time 106822372 ps
CPU time 0.79 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207488 kb
Host smart-fe92f200-1ec9-4ae2-b06c-4e01d819056d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
50381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1412850381
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2065592277
Short name T2201
Test name
Test status
Simulation time 16483313344 ps
CPU time 37.49 seconds
Started Aug 08 06:18:00 PM PDT 24
Finished Aug 08 06:18:38 PM PDT 24
Peak memory 216048 kb
Host smart-10947ae4-3d1a-4309-ac48-88b266642fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20655
92277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2065592277
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2235779643
Short name T801
Test name
Test status
Simulation time 188236497 ps
CPU time 0.94 seconds
Started Aug 08 06:18:20 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207528 kb
Host smart-dadc3d70-459c-4f29-9f16-41607feb7981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22357
79643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2235779643
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.388154623
Short name T754
Test name
Test status
Simulation time 208960843 ps
CPU time 0.95 seconds
Started Aug 08 06:18:13 PM PDT 24
Finished Aug 08 06:18:14 PM PDT 24
Peak memory 207572 kb
Host smart-63efbc55-74e1-45bc-9d19-7aa46e4a6f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.388154623
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1810771440
Short name T3101
Test name
Test status
Simulation time 188710022 ps
CPU time 0.91 seconds
Started Aug 08 06:18:29 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 207612 kb
Host smart-0e630812-fdf6-499e-abd2-8ecfcd2d9ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
71440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1810771440
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3006429279
Short name T1174
Test name
Test status
Simulation time 147867386 ps
CPU time 0.85 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207524 kb
Host smart-584791da-6d21-4b4a-91fc-f8a90ce2d5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30064
29279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3006429279
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.332123922
Short name T1018
Test name
Test status
Simulation time 173420936 ps
CPU time 0.87 seconds
Started Aug 08 06:18:26 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207584 kb
Host smart-ec95a396-88a2-4a3a-9c48-f829f2ea4902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33212
3922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.332123922
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.392262954
Short name T55
Test name
Test status
Simulation time 350240528 ps
CPU time 1.31 seconds
Started Aug 08 06:18:09 PM PDT 24
Finished Aug 08 06:18:10 PM PDT 24
Peak memory 207584 kb
Host smart-bba85788-2b96-4daa-94e2-882e4d34455f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.392262954
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.281725347
Short name T1150
Test name
Test status
Simulation time 188655213 ps
CPU time 0.87 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207456 kb
Host smart-492ea4df-14cb-4e53-a404-99a70e9bb1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
5347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.281725347
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.177817834
Short name T1383
Test name
Test status
Simulation time 158653185 ps
CPU time 0.89 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207572 kb
Host smart-37854b6a-a8f4-49af-bbd9-6a01ec94509c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
7834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.177817834
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3857142448
Short name T3397
Test name
Test status
Simulation time 216992055 ps
CPU time 0.99 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207584 kb
Host smart-64eccc44-df3b-4b13-b062-729b70051d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
42448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3857142448
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.541722794
Short name T2987
Test name
Test status
Simulation time 3223019335 ps
CPU time 89.39 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 218060 kb
Host smart-5c854ba8-76fd-46ef-b81c-607461cb3d3e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=541722794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.541722794
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3283913590
Short name T3561
Test name
Test status
Simulation time 174132065 ps
CPU time 0.91 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207572 kb
Host smart-40e42417-9db2-48ac-b3ee-540ff8993647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839
13590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3283913590
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.4193977135
Short name T3188
Test name
Test status
Simulation time 210654701 ps
CPU time 0.95 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:18 PM PDT 24
Peak memory 207584 kb
Host smart-17339fea-6ab1-49a4-b273-9f4d2fa5e302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939
77135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4193977135
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1969151437
Short name T2549
Test name
Test status
Simulation time 485172608 ps
CPU time 1.39 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207560 kb
Host smart-d271c19a-ffe8-426d-a383-d1e7f15f1f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
51437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1969151437
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.955865038
Short name T3315
Test name
Test status
Simulation time 2569428731 ps
CPU time 27.89 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 217740 kb
Host smart-6bf9278c-9dde-4804-a6f5-9b64ae358654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95586
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.955865038
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.2254352526
Short name T2226
Test name
Test status
Simulation time 4984506289 ps
CPU time 33.48 seconds
Started Aug 08 06:18:29 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207884 kb
Host smart-92d303ef-2de4-4b16-a642-ec5df0817481
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254352526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.2254352526
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.3451041188
Short name T3369
Test name
Test status
Simulation time 495061798 ps
CPU time 1.53 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 207580 kb
Host smart-7f3c53ce-5e52-4a29-9e6e-fb36f974f705
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451041188 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.3451041188
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.2983957887
Short name T2536
Test name
Test status
Simulation time 565385064 ps
CPU time 1.6 seconds
Started Aug 08 06:22:08 PM PDT 24
Finished Aug 08 06:22:10 PM PDT 24
Peak memory 207588 kb
Host smart-28267577-9c72-44d1-95a0-aa0f1f35c781
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983957887 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.2983957887
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.1567143408
Short name T3371
Test name
Test status
Simulation time 536470079 ps
CPU time 1.53 seconds
Started Aug 08 06:22:01 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 207540 kb
Host smart-231632f1-cad0-4659-be21-a7c8cbcb1c48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567143408 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.1567143408
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.2740404516
Short name T1639
Test name
Test status
Simulation time 628522851 ps
CPU time 1.64 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207564 kb
Host smart-ee56e0b2-4460-4126-808d-be5c48ea4394
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740404516 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.2740404516
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.2641901416
Short name T2634
Test name
Test status
Simulation time 494728903 ps
CPU time 1.59 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207576 kb
Host smart-5d26d35a-a8b9-4b97-9a7c-16f6f8108789
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641901416 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.2641901416
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.131911267
Short name T2916
Test name
Test status
Simulation time 631824694 ps
CPU time 1.7 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207556 kb
Host smart-bb6a8ae9-f9ee-4d69-8e5d-cb64bda450e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131911267 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.131911267
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.3896909383
Short name T1592
Test name
Test status
Simulation time 500129833 ps
CPU time 1.53 seconds
Started Aug 08 06:22:04 PM PDT 24
Finished Aug 08 06:22:05 PM PDT 24
Peak memory 207636 kb
Host smart-bebf6071-4a56-40ee-85c9-6feb6adc1719
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896909383 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.3896909383
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.3844990939
Short name T3181
Test name
Test status
Simulation time 588653834 ps
CPU time 1.65 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207548 kb
Host smart-db4cb3ac-821b-46c8-b2de-fb8c40e42241
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844990939 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.3844990939
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.1073966285
Short name T989
Test name
Test status
Simulation time 592040859 ps
CPU time 1.6 seconds
Started Aug 08 06:22:04 PM PDT 24
Finished Aug 08 06:22:06 PM PDT 24
Peak memory 207644 kb
Host smart-e4ae8488-bc5f-468b-88f2-1fd414838b5e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073966285 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.1073966285
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.1931070038
Short name T3542
Test name
Test status
Simulation time 592816911 ps
CPU time 1.55 seconds
Started Aug 08 06:22:02 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 207560 kb
Host smart-c65119f2-5261-48cd-b656-4d7ac97f23d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931070038 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.1931070038
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.1979408746
Short name T570
Test name
Test status
Simulation time 506773609 ps
CPU time 1.56 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207552 kb
Host smart-b9b1a149-7102-43cd-a268-cb27530625ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979408746 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.1979408746
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1896009703
Short name T3462
Test name
Test status
Simulation time 31302637 ps
CPU time 0.7 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:06 PM PDT 24
Peak memory 207604 kb
Host smart-5fa2a36a-a1a8-49cd-9231-6580211cea4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1896009703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1896009703
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1628240764
Short name T2637
Test name
Test status
Simulation time 11778738085 ps
CPU time 14.37 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 207876 kb
Host smart-d6863e5a-eb67-4ac5-9537-943ad91f3c0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628240764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.1628240764
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.246094284
Short name T970
Test name
Test status
Simulation time 20950261414 ps
CPU time 23.82 seconds
Started Aug 08 06:13:40 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207844 kb
Host smart-beb20d00-e320-4e2e-aad5-7f368e72fd65
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=246094284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.246094284
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1976448104
Short name T1252
Test name
Test status
Simulation time 23598646494 ps
CPU time 35.28 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:14:19 PM PDT 24
Peak memory 216004 kb
Host smart-71d0ccf3-340d-481e-a121-ab4c07b4582c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976448104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1976448104
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1466891079
Short name T3223
Test name
Test status
Simulation time 163897754 ps
CPU time 0.89 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207584 kb
Host smart-9f90e58f-93a3-44d5-bf8d-924f8f75b838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14668
91079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1466891079
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.199115455
Short name T48
Test name
Test status
Simulation time 194767194 ps
CPU time 0.86 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:42 PM PDT 24
Peak memory 207560 kb
Host smart-9c8858b3-81c0-45a8-b558-bb535a90b1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19911
5455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.199115455
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.977197088
Short name T96
Test name
Test status
Simulation time 138455891 ps
CPU time 0.81 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207544 kb
Host smart-8b270447-4b86-4675-b3fe-cb391e30a99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97719
7088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.977197088
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3852972383
Short name T3500
Test name
Test status
Simulation time 143371246 ps
CPU time 0.84 seconds
Started Aug 08 06:13:48 PM PDT 24
Finished Aug 08 06:13:49 PM PDT 24
Peak memory 207504 kb
Host smart-96a66b7c-dc8f-4af6-a1fc-17dd4ba3c609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38529
72383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3852972383
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3100096157
Short name T2627
Test name
Test status
Simulation time 416915610 ps
CPU time 1.54 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:44 PM PDT 24
Peak memory 207256 kb
Host smart-da4f9881-b7ca-4d4f-a8de-f230ea5d31f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
96157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3100096157
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3540123730
Short name T2362
Test name
Test status
Simulation time 751461767 ps
CPU time 1.91 seconds
Started Aug 08 06:13:41 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207592 kb
Host smart-73ed2f88-54bf-4fa7-aacb-2b0ede4f5598
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3540123730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3540123730
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.5094034
Short name T2388
Test name
Test status
Simulation time 49800390796 ps
CPU time 75.34 seconds
Started Aug 08 06:13:47 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207812 kb
Host smart-79c717f4-fcb5-4ab2-99ef-5b7a481eae46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50940
34 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.5094034
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2129443295
Short name T2344
Test name
Test status
Simulation time 205535461 ps
CPU time 0.99 seconds
Started Aug 08 06:13:47 PM PDT 24
Finished Aug 08 06:13:48 PM PDT 24
Peak memory 207476 kb
Host smart-0279e509-beff-40bd-a6ac-39c73c79a36b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129443295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2129443295
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.180041278
Short name T2074
Test name
Test status
Simulation time 791178444 ps
CPU time 1.83 seconds
Started Aug 08 06:13:44 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207516 kb
Host smart-28148a15-bfe9-461a-83e3-f0e49fd67a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18004
1278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.180041278
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1294648518
Short name T722
Test name
Test status
Simulation time 138528080 ps
CPU time 0.85 seconds
Started Aug 08 06:13:40 PM PDT 24
Finished Aug 08 06:13:41 PM PDT 24
Peak memory 207568 kb
Host smart-a954662d-aa4c-4e65-80f9-5b36406ed4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12946
48518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1294648518
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2154026983
Short name T2652
Test name
Test status
Simulation time 86190773 ps
CPU time 0.73 seconds
Started Aug 08 06:13:47 PM PDT 24
Finished Aug 08 06:13:48 PM PDT 24
Peak memory 207472 kb
Host smart-a03468c3-8038-4cfc-9504-32500016d28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
26983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2154026983
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3625663128
Short name T2310
Test name
Test status
Simulation time 944516922 ps
CPU time 2.61 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207444 kb
Host smart-f9f854ab-066d-4985-bdec-2e3e6137d1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36256
63128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3625663128
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.956500810
Short name T2875
Test name
Test status
Simulation time 238444244 ps
CPU time 1.06 seconds
Started Aug 08 06:13:50 PM PDT 24
Finished Aug 08 06:13:51 PM PDT 24
Peak memory 207572 kb
Host smart-4fc7097b-41cb-4879-acab-e02dd49aca31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=956500810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.956500810
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2675918100
Short name T2508
Test name
Test status
Simulation time 233145502 ps
CPU time 1.5 seconds
Started Aug 08 06:13:49 PM PDT 24
Finished Aug 08 06:13:51 PM PDT 24
Peak memory 207780 kb
Host smart-7500db56-f408-43d3-8e12-e0749d2bc28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
18100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2675918100
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1987668100
Short name T859
Test name
Test status
Simulation time 108187778923 ps
CPU time 185.33 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:16:47 PM PDT 24
Peak memory 207820 kb
Host smart-c6a9890a-5d14-4a50-9fa3-486f614fc950
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1987668100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1987668100
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.1725332791
Short name T519
Test name
Test status
Simulation time 90319713916 ps
CPU time 138.04 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 207836 kb
Host smart-5f2e1f25-b772-4e2c-88bb-1154d427aa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725332791 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.1725332791
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3709834613
Short name T3271
Test name
Test status
Simulation time 121103808708 ps
CPU time 189.92 seconds
Started Aug 08 06:13:50 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207848 kb
Host smart-043b035e-d25d-49ea-ad3d-7d0e9fce3ff1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3709834613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3709834613
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.531414601
Short name T521
Test name
Test status
Simulation time 82967833587 ps
CPU time 145.7 seconds
Started Aug 08 06:13:46 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 207860 kb
Host smart-2643a6ac-1edd-4462-ac72-db0dd36d6753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531414601 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.531414601
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2764825293
Short name T2567
Test name
Test status
Simulation time 99137302411 ps
CPU time 153.69 seconds
Started Aug 08 06:13:50 PM PDT 24
Finished Aug 08 06:16:24 PM PDT 24
Peak memory 207872 kb
Host smart-74bc6de1-04d3-452f-84e4-248100dd19f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
25293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2764825293
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.891681137
Short name T2537
Test name
Test status
Simulation time 194320801 ps
CPU time 1 seconds
Started Aug 08 06:13:49 PM PDT 24
Finished Aug 08 06:13:50 PM PDT 24
Peak memory 215964 kb
Host smart-8380b3db-dfaf-43cf-8f54-e3b3f26f04e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=891681137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.891681137
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3427592764
Short name T1104
Test name
Test status
Simulation time 175278808 ps
CPU time 0.85 seconds
Started Aug 08 06:13:43 PM PDT 24
Finished Aug 08 06:13:44 PM PDT 24
Peak memory 207528 kb
Host smart-50f38cdb-6a64-42de-ba83-21c074928c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
92764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3427592764
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1204102975
Short name T2298
Test name
Test status
Simulation time 181186223 ps
CPU time 0.89 seconds
Started Aug 08 06:13:44 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 207524 kb
Host smart-b17e8c7d-444a-4a3f-9998-a1f346b51a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
02975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1204102975
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2838921543
Short name T1030
Test name
Test status
Simulation time 4323181101 ps
CPU time 125.27 seconds
Started Aug 08 06:13:50 PM PDT 24
Finished Aug 08 06:15:56 PM PDT 24
Peak memory 216128 kb
Host smart-0c357ef7-b3a0-4b25-8dae-d7d2eb6f0d6f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2838921543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2838921543
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.3343796578
Short name T2198
Test name
Test status
Simulation time 8389627282 ps
CPU time 58.73 seconds
Started Aug 08 06:13:46 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 207828 kb
Host smart-332c58df-144a-47db-bd19-de108e8897d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3343796578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3343796578
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.961919165
Short name T2366
Test name
Test status
Simulation time 192660677 ps
CPU time 0.91 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:13:43 PM PDT 24
Peak memory 207532 kb
Host smart-68a1101d-4b0e-43b6-a350-b1921943c5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96191
9165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.961919165
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3615034438
Short name T1757
Test name
Test status
Simulation time 29100015792 ps
CPU time 46.16 seconds
Started Aug 08 06:13:45 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 207800 kb
Host smart-cbddc86c-eb16-4b46-8653-7e13b32c970c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36150
34438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3615034438
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1230385432
Short name T1357
Test name
Test status
Simulation time 11433906056 ps
CPU time 14.73 seconds
Started Aug 08 06:13:46 PM PDT 24
Finished Aug 08 06:14:01 PM PDT 24
Peak memory 207824 kb
Host smart-38fb974f-b3af-43c5-a24e-f4630e7e5318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
85432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1230385432
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1599177235
Short name T2934
Test name
Test status
Simulation time 5689331350 ps
CPU time 41.76 seconds
Started Aug 08 06:13:45 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 218712 kb
Host smart-a358cf4d-2bc6-4ed7-971f-76f4af73eb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15991
77235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1599177235
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.587502882
Short name T2999
Test name
Test status
Simulation time 2060023427 ps
CPU time 59.44 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 215964 kb
Host smart-871e169a-a710-4702-afc1-afaeb58b4809
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587502882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.587502882
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3994808658
Short name T631
Test name
Test status
Simulation time 236607555 ps
CPU time 1.01 seconds
Started Aug 08 06:13:45 PM PDT 24
Finished Aug 08 06:13:46 PM PDT 24
Peak memory 207544 kb
Host smart-f6f8e765-faf6-4d87-b9e4-fd05903e0810
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3994808658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3994808658
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.296307082
Short name T3126
Test name
Test status
Simulation time 194742446 ps
CPU time 0.94 seconds
Started Aug 08 06:13:55 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 207588 kb
Host smart-a51072d5-a801-494d-a898-9e69b23bd7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
7082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.296307082
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.3169383889
Short name T2661
Test name
Test status
Simulation time 2808352773 ps
CPU time 21.66 seconds
Started Aug 08 06:13:56 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 218108 kb
Host smart-41dd4010-ce10-43d7-86de-bc32a057b7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
83889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.3169383889
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1071652409
Short name T1603
Test name
Test status
Simulation time 2781194668 ps
CPU time 25.37 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:14:20 PM PDT 24
Peak memory 224072 kb
Host smart-87099be6-de82-43d7-b62f-6479da9acd90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1071652409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1071652409
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.316113765
Short name T2992
Test name
Test status
Simulation time 4310813673 ps
CPU time 42.99 seconds
Started Aug 08 06:13:56 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 217580 kb
Host smart-48944b07-3cbc-4806-9004-a72af800e16e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=316113765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.316113765
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1265365451
Short name T1181
Test name
Test status
Simulation time 186617181 ps
CPU time 0.92 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207536 kb
Host smart-4dea7144-f577-48fd-8ded-31379e22c89b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1265365451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1265365451
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3585846101
Short name T3284
Test name
Test status
Simulation time 151663954 ps
CPU time 0.82 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207596 kb
Host smart-bae33b24-367b-4e1e-9da1-55aefc09b9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
46101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3585846101
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2055577746
Short name T1105
Test name
Test status
Simulation time 164411195 ps
CPU time 0.88 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207596 kb
Host smart-a0177ee8-4880-4408-a4e3-f39e1c86d14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20555
77746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2055577746
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3698657671
Short name T1585
Test name
Test status
Simulation time 170595931 ps
CPU time 0.88 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207564 kb
Host smart-e04455c2-ee7c-46de-abd9-ed6656455e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986
57671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3698657671
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3043215458
Short name T572
Test name
Test status
Simulation time 188106790 ps
CPU time 0.87 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207544 kb
Host smart-85bae5ff-e571-486a-a4c7-a2d5214c023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30432
15458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3043215458
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3452664614
Short name T1607
Test name
Test status
Simulation time 168076931 ps
CPU time 0.83 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207648 kb
Host smart-119ef2b4-000d-498e-8a75-e68b00cdc174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
64614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3452664614
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.915096019
Short name T3498
Test name
Test status
Simulation time 212797066 ps
CPU time 1 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 207536 kb
Host smart-285306ad-165f-459f-a2a4-771d1ff01f03
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=915096019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.915096019
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1847141432
Short name T668
Test name
Test status
Simulation time 268413982 ps
CPU time 1.15 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207544 kb
Host smart-c43c4986-58e9-4f93-bfca-76bef2f69d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18471
41432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1847141432
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3605495950
Short name T3102
Test name
Test status
Simulation time 154228010 ps
CPU time 0.83 seconds
Started Aug 08 06:13:51 PM PDT 24
Finished Aug 08 06:13:52 PM PDT 24
Peak memory 207756 kb
Host smart-171be2f9-ec74-4992-839a-234755aa794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36054
95950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3605495950
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.136157551
Short name T45
Test name
Test status
Simulation time 35102953 ps
CPU time 0.7 seconds
Started Aug 08 06:13:56 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 207528 kb
Host smart-d691da8f-7c2a-4cf6-bb1e-1a535fcc9a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
7551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.136157551
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.103300509
Short name T2599
Test name
Test status
Simulation time 18646663386 ps
CPU time 46.44 seconds
Started Aug 08 06:13:55 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 216000 kb
Host smart-5af2bed1-4967-47e6-b5c7-9f7fbb7d8796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
0509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.103300509
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2149823955
Short name T2679
Test name
Test status
Simulation time 165482019 ps
CPU time 0.86 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207528 kb
Host smart-d0b69bab-5e93-443e-aba0-90293dde6672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
23955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2149823955
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.4215012282
Short name T872
Test name
Test status
Simulation time 186018622 ps
CPU time 0.86 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 207580 kb
Host smart-a61ca138-7aa9-49ec-b593-1ea9f1288ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
12282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.4215012282
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3345013021
Short name T1614
Test name
Test status
Simulation time 9876429112 ps
CPU time 48.42 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 224368 kb
Host smart-1bf088c0-f1d3-406d-87e2-fd97775ad350
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345013021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3345013021
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2977953856
Short name T2691
Test name
Test status
Simulation time 6925591220 ps
CPU time 36.79 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 224292 kb
Host smart-63404578-9674-452c-b10f-54015a44f484
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977953856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2977953856
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.255856394
Short name T2923
Test name
Test status
Simulation time 226389749 ps
CPU time 0.98 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 207584 kb
Host smart-20ce9e8d-60e6-4c91-b261-355dd314ba50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25585
6394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.255856394
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1796010892
Short name T3409
Test name
Test status
Simulation time 146139518 ps
CPU time 0.88 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 207536 kb
Host smart-2d8269c7-6f92-4502-924c-ceb6fbfd3bf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
10892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1796010892
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.1386662513
Short name T1624
Test name
Test status
Simulation time 20166484416 ps
CPU time 27.41 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:14:21 PM PDT 24
Peak memory 207656 kb
Host smart-590c00ff-1ed9-42ed-a4cf-ec6701a70619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13866
62513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.1386662513
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1870228354
Short name T1784
Test name
Test status
Simulation time 184463144 ps
CPU time 0.87 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207500 kb
Host smart-ad3f5b97-6251-4365-8c6a-a18fe1e49f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
28354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1870228354
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.549016275
Short name T960
Test name
Test status
Simulation time 265310434 ps
CPU time 1.11 seconds
Started Aug 08 06:13:51 PM PDT 24
Finished Aug 08 06:13:52 PM PDT 24
Peak memory 207560 kb
Host smart-d8689366-b178-4073-b164-d3cc98c9e0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54901
6275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.549016275
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3550585213
Short name T2106
Test name
Test status
Simulation time 207497574 ps
CPU time 0.91 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:54 PM PDT 24
Peak memory 207528 kb
Host smart-8d37d5f2-c6fa-4936-9ed3-fc78b0424e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
85213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3550585213
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1442091622
Short name T228
Test name
Test status
Simulation time 286131720 ps
CPU time 1.15 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 223440 kb
Host smart-1cacb387-9fed-4bd1-bf94-834a9682f93d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1442091622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1442091622
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3925836861
Short name T57
Test name
Test status
Simulation time 401042331 ps
CPU time 1.5 seconds
Started Aug 08 06:13:57 PM PDT 24
Finished Aug 08 06:13:58 PM PDT 24
Peak memory 207508 kb
Host smart-a80faf5a-1aed-4685-892b-67b99c56dd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
36861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3925836861
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2827747267
Short name T3155
Test name
Test status
Simulation time 302992419 ps
CPU time 1.16 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 207536 kb
Host smart-b028fbb7-b10c-4c76-b233-3c7355beb8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
47267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2827747267
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.575032689
Short name T1404
Test name
Test status
Simulation time 154243457 ps
CPU time 0.85 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207512 kb
Host smart-61f5b06a-898b-45f4-a71f-aee36f664340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57503
2689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.575032689
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2216785586
Short name T902
Test name
Test status
Simulation time 156445045 ps
CPU time 0.88 seconds
Started Aug 08 06:13:55 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 207528 kb
Host smart-af46a64b-5cdd-4a9e-8e53-4bf7465932b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
85586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2216785586
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2046770088
Short name T915
Test name
Test status
Simulation time 251816927 ps
CPU time 1.07 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207636 kb
Host smart-a83545dd-c16c-414a-9823-a0fcab5708bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
70088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2046770088
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3121899266
Short name T2171
Test name
Test status
Simulation time 2692495572 ps
CPU time 74.39 seconds
Started Aug 08 06:13:54 PM PDT 24
Finished Aug 08 06:15:08 PM PDT 24
Peak memory 224284 kb
Host smart-f1ebdf08-a796-4a78-96ac-d42877374643
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3121899266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3121899266
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1523821648
Short name T607
Test name
Test status
Simulation time 182955266 ps
CPU time 0.9 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207592 kb
Host smart-c09dbad7-564c-4d2e-9bc2-9f8176138f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15238
21648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1523821648
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1454646443
Short name T2078
Test name
Test status
Simulation time 186207600 ps
CPU time 0.87 seconds
Started Aug 08 06:13:55 PM PDT 24
Finished Aug 08 06:13:56 PM PDT 24
Peak memory 207584 kb
Host smart-d120cf7d-a2c3-4a2f-9bb4-59e4054c276b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
46443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1454646443
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1764793497
Short name T1878
Test name
Test status
Simulation time 464957320 ps
CPU time 1.5 seconds
Started Aug 08 06:13:53 PM PDT 24
Finished Aug 08 06:13:55 PM PDT 24
Peak memory 207560 kb
Host smart-93314969-0a1f-431a-a22d-6961dc102350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17647
93497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1764793497
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.759443826
Short name T1153
Test name
Test status
Simulation time 3850176809 ps
CPU time 110.28 seconds
Started Aug 08 06:13:51 PM PDT 24
Finished Aug 08 06:15:42 PM PDT 24
Peak memory 216108 kb
Host smart-c4cf2989-b432-48e7-a24a-ff0006708b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75944
3826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.759443826
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.207937965
Short name T620
Test name
Test status
Simulation time 2946028259 ps
CPU time 26.23 seconds
Started Aug 08 06:13:42 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 207864 kb
Host smart-e01391f4-810c-4d20-9f7d-6435eb409398
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207937965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host_
handshake.207937965
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.2700240141
Short name T2978
Test name
Test status
Simulation time 521087338 ps
CPU time 1.59 seconds
Started Aug 08 06:13:52 PM PDT 24
Finished Aug 08 06:13:53 PM PDT 24
Peak memory 207532 kb
Host smart-20165ed7-c618-445d-b452-2669d1b716ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700240141 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.2700240141
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3103556948
Short name T3426
Test name
Test status
Simulation time 41856627 ps
CPU time 0.7 seconds
Started Aug 08 06:18:38 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 207584 kb
Host smart-7a5ba962-6702-4397-938b-dca465e54e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3103556948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3103556948
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3165646564
Short name T2015
Test name
Test status
Simulation time 6766093898 ps
CPU time 8.72 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:31 PM PDT 24
Peak memory 216040 kb
Host smart-173481f4-16d6-45af-bec5-ed98301e5023
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165646564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3165646564
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3315250336
Short name T830
Test name
Test status
Simulation time 16143342147 ps
CPU time 19.56 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 216032 kb
Host smart-1f1da9b6-4d7c-44db-9192-bc21a690c144
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315250336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3315250336
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.238971756
Short name T262
Test name
Test status
Simulation time 31224723221 ps
CPU time 37.21 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 207860 kb
Host smart-6a872516-5a92-474c-8ace-f036d8bc5de7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238971756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.238971756
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1629894974
Short name T674
Test name
Test status
Simulation time 169341579 ps
CPU time 0.91 seconds
Started Aug 08 06:18:35 PM PDT 24
Finished Aug 08 06:18:37 PM PDT 24
Peak memory 207512 kb
Host smart-5f845518-6366-45f6-9367-2d7a464f5fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
94974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1629894974
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1161990739
Short name T1808
Test name
Test status
Simulation time 163230379 ps
CPU time 0.85 seconds
Started Aug 08 06:18:11 PM PDT 24
Finished Aug 08 06:18:12 PM PDT 24
Peak memory 207496 kb
Host smart-b7f1228f-5fe7-44cb-98d0-e8ff102e9e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
90739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1161990739
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2873280639
Short name T1231
Test name
Test status
Simulation time 383645429 ps
CPU time 1.4 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207532 kb
Host smart-2efe454a-006e-44a1-894a-5b055b3132e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28732
80639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2873280639
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1839157129
Short name T1228
Test name
Test status
Simulation time 723827922 ps
CPU time 2.07 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207756 kb
Host smart-72dccb91-6a71-48d2-9a30-8113735879e5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1839157129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1839157129
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3794203887
Short name T593
Test name
Test status
Simulation time 6366949599 ps
CPU time 39.7 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:58 PM PDT 24
Peak memory 207848 kb
Host smart-c08ced5f-8c93-4e6f-aca7-7c421373c4f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794203887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3794203887
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1909233867
Short name T356
Test name
Test status
Simulation time 725594226 ps
CPU time 2.03 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:18:34 PM PDT 24
Peak memory 207568 kb
Host smart-e7478ce9-d221-4677-9418-8326a068de60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
33867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1909233867
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1334628023
Short name T1341
Test name
Test status
Simulation time 192432156 ps
CPU time 0.92 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207612 kb
Host smart-5b59728e-8e5f-4fb0-9e62-247469505063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13346
28023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1334628023
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1545693979
Short name T3424
Test name
Test status
Simulation time 38045470 ps
CPU time 0.72 seconds
Started Aug 08 06:18:19 PM PDT 24
Finished Aug 08 06:18:20 PM PDT 24
Peak memory 207608 kb
Host smart-b278a3ac-7c87-4713-afdb-d2ba415bc357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456
93979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1545693979
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1238299418
Short name T1973
Test name
Test status
Simulation time 711303255 ps
CPU time 2.2 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:18:35 PM PDT 24
Peak memory 207768 kb
Host smart-15a36d80-cec8-449e-92eb-8df876cdb1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
99418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1238299418
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.2808516222
Short name T1463
Test name
Test status
Simulation time 227418189 ps
CPU time 0.97 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207468 kb
Host smart-8868450b-c55d-4b88-a6e1-42d24cfc832a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2808516222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.2808516222
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2711870543
Short name T977
Test name
Test status
Simulation time 165844223 ps
CPU time 1.73 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207700 kb
Host smart-abaff46a-0884-4e31-8c64-9a852de0618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27118
70543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2711870543
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.552555151
Short name T1677
Test name
Test status
Simulation time 235944961 ps
CPU time 1.22 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 215896 kb
Host smart-02d1d422-7a63-4c86-a7d5-c0ec9eb3258b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=552555151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.552555151
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.710164630
Short name T2060
Test name
Test status
Simulation time 170958869 ps
CPU time 0.88 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:18:15 PM PDT 24
Peak memory 207580 kb
Host smart-016938d1-c819-4cd7-a9f1-40cca4aa981c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71016
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.710164630
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1310667670
Short name T3112
Test name
Test status
Simulation time 215620231 ps
CPU time 0.97 seconds
Started Aug 08 06:18:12 PM PDT 24
Finished Aug 08 06:18:13 PM PDT 24
Peak memory 207532 kb
Host smart-3e57e4dc-5073-4997-8dff-2db59ad45055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13106
67670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1310667670
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.3451279769
Short name T2837
Test name
Test status
Simulation time 3905246226 ps
CPU time 112.74 seconds
Started Aug 08 06:18:30 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 216164 kb
Host smart-a9cc51ad-de70-4f63-be0d-c7e4a45cb942
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3451279769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3451279769
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.3119430739
Short name T2288
Test name
Test status
Simulation time 12851445069 ps
CPU time 157.39 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207796 kb
Host smart-29decc31-6a1d-4772-a8ad-d34de4683208
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3119430739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3119430739
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4036011230
Short name T1660
Test name
Test status
Simulation time 193846779 ps
CPU time 0.99 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207588 kb
Host smart-b7cd1003-822b-4ac1-a844-9ca9fadc5402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40360
11230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4036011230
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3640365186
Short name T2896
Test name
Test status
Simulation time 28758431178 ps
CPU time 41.95 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 207828 kb
Host smart-1673b0cf-f0f6-4237-93af-9dcd6a901641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
65186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3640365186
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3019967538
Short name T2742
Test name
Test status
Simulation time 8420198444 ps
CPU time 11.3 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207768 kb
Host smart-6f6ae5c1-ec70-4b3f-8fd6-93a7f4738591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30199
67538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3019967538
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.2880724208
Short name T2799
Test name
Test status
Simulation time 5669128108 ps
CPU time 58.19 seconds
Started Aug 08 06:18:20 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 224204 kb
Host smart-ae40c897-36cd-4bf8-ac69-ba0fe07e4d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28807
24208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.2880724208
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1170035140
Short name T3350
Test name
Test status
Simulation time 1856720720 ps
CPU time 47.79 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:19:29 PM PDT 24
Peak memory 224124 kb
Host smart-f101a0c3-3466-4302-b51a-56e2a6750c10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1170035140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1170035140
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.4085819741
Short name T1324
Test name
Test status
Simulation time 241660637 ps
CPU time 1.01 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:18:34 PM PDT 24
Peak memory 207576 kb
Host smart-f8ebcb86-8c42-460f-a8b4-d48373a44272
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4085819741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.4085819741
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1474647475
Short name T1477
Test name
Test status
Simulation time 187690555 ps
CPU time 0.93 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:18:34 PM PDT 24
Peak memory 207524 kb
Host smart-3940288c-77d2-4e66-a214-d3876f45788e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14746
47475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1474647475
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3314223492
Short name T583
Test name
Test status
Simulation time 2885779013 ps
CPU time 29.53 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 217252 kb
Host smart-89245beb-c920-4907-ba99-235d61ddbcae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3314223492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3314223492
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.117816829
Short name T1358
Test name
Test status
Simulation time 157857011 ps
CPU time 0.91 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 207532 kb
Host smart-d50a1c1d-08e4-4515-bcd8-f2d79c5a5acc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=117816829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.117816829
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.348465190
Short name T1502
Test name
Test status
Simulation time 157104894 ps
CPU time 0.85 seconds
Started Aug 08 06:18:38 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 207656 kb
Host smart-739bb8c1-1ce0-4107-b721-03ae8c6bb6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34846
5190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.348465190
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2073170033
Short name T2065
Test name
Test status
Simulation time 207155227 ps
CPU time 0.87 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207580 kb
Host smart-56b75d80-192b-472c-8a4e-5ece5974d994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20731
70033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2073170033
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.341728736
Short name T3279
Test name
Test status
Simulation time 165419984 ps
CPU time 0.87 seconds
Started Aug 08 06:18:34 PM PDT 24
Finished Aug 08 06:18:35 PM PDT 24
Peak memory 207652 kb
Host smart-45acccb0-a302-4ae9-bade-1f5c0e80a532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
8736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.341728736
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.131752753
Short name T600
Test name
Test status
Simulation time 185607244 ps
CPU time 0.9 seconds
Started Aug 08 06:18:14 PM PDT 24
Finished Aug 08 06:18:15 PM PDT 24
Peak memory 207596 kb
Host smart-f57202a6-94d7-4e40-939f-e353d3e5fb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.131752753
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1041268979
Short name T2561
Test name
Test status
Simulation time 172605854 ps
CPU time 0.86 seconds
Started Aug 08 06:18:27 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207504 kb
Host smart-eaeb9ffc-a9ab-49f6-8231-53865d3fbcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
68979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1041268979
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3771935515
Short name T175
Test name
Test status
Simulation time 191091314 ps
CPU time 0.9 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207584 kb
Host smart-21439044-372e-4232-b1f3-6064c4d6bf7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37719
35515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3771935515
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.69465083
Short name T198
Test name
Test status
Simulation time 212296748 ps
CPU time 0.96 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 207572 kb
Host smart-7dd893e9-a4ad-43b8-9127-68dff9643700
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=69465083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.69465083
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3851776725
Short name T3353
Test name
Test status
Simulation time 151385526 ps
CPU time 0.82 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 207480 kb
Host smart-4206af99-e44a-46e2-af8d-e56e6d999d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
76725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3851776725
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2778622383
Short name T3243
Test name
Test status
Simulation time 41238156 ps
CPU time 0.7 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:18:23 PM PDT 24
Peak memory 207616 kb
Host smart-0539e292-4cf3-4a86-866f-ad86f361aec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
22383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2778622383
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.425126502
Short name T317
Test name
Test status
Simulation time 20344600609 ps
CPU time 52.57 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 215996 kb
Host smart-2ad8d9a0-1455-49af-b9b4-893d3c185e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42512
6502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.425126502
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1746715838
Short name T1684
Test name
Test status
Simulation time 158368922 ps
CPU time 0.87 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207528 kb
Host smart-b97932ff-ef45-45e8-8adc-703ee7fa92b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467
15838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1746715838
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1201907336
Short name T2663
Test name
Test status
Simulation time 203931650 ps
CPU time 1 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 207528 kb
Host smart-668ca586-b925-44b4-9c32-373590c6ef4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
07336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1201907336
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.474224186
Short name T3383
Test name
Test status
Simulation time 190960508 ps
CPU time 0.98 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:18:34 PM PDT 24
Peak memory 207488 kb
Host smart-8e1b1ce2-5e5a-4fa5-9916-9d6a3b93236f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47422
4186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.474224186
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1258833597
Short name T3472
Test name
Test status
Simulation time 171210844 ps
CPU time 1 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:18:33 PM PDT 24
Peak memory 207496 kb
Host smart-98128eb5-c0a9-49b0-b393-e6d7b8fdbcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12588
33597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1258833597
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1231670860
Short name T78
Test name
Test status
Simulation time 192046451 ps
CPU time 0.89 seconds
Started Aug 08 06:18:15 PM PDT 24
Finished Aug 08 06:18:16 PM PDT 24
Peak memory 207536 kb
Host smart-2e1b12ac-6a3b-4ee0-9335-3620013448a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
70860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1231670860
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.113223869
Short name T3193
Test name
Test status
Simulation time 244526486 ps
CPU time 1.04 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207544 kb
Host smart-f4f7d184-fbbb-409b-8780-7fa040bb8f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.113223869
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3178061620
Short name T2429
Test name
Test status
Simulation time 161553775 ps
CPU time 0.88 seconds
Started Aug 08 06:18:20 PM PDT 24
Finished Aug 08 06:18:21 PM PDT 24
Peak memory 207516 kb
Host smart-f0f392a7-240b-41e2-aea3-e39a0737b2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
61620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3178061620
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2366162622
Short name T2325
Test name
Test status
Simulation time 153652073 ps
CPU time 0.86 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207596 kb
Host smart-23a32b78-ce00-4459-9e98-3821b9cfdc67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23661
62622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2366162622
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.4183236669
Short name T1551
Test name
Test status
Simulation time 217430205 ps
CPU time 1.03 seconds
Started Aug 08 06:18:18 PM PDT 24
Finished Aug 08 06:18:19 PM PDT 24
Peak memory 207536 kb
Host smart-4fa24e54-1d88-4306-b097-d5a73af1a46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41832
36669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4183236669
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.915007341
Short name T1496
Test name
Test status
Simulation time 2307252623 ps
CPU time 67.04 seconds
Started Aug 08 06:18:22 PM PDT 24
Finished Aug 08 06:19:29 PM PDT 24
Peak memory 217756 kb
Host smart-724ad155-f989-4608-8215-e51a8eb57458
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=915007341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.915007341
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2244051845
Short name T903
Test name
Test status
Simulation time 222814326 ps
CPU time 1.02 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:18:25 PM PDT 24
Peak memory 207512 kb
Host smart-8e18f710-fb7d-426f-96da-f326ec55fd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
51845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2244051845
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4001487611
Short name T3073
Test name
Test status
Simulation time 166722489 ps
CPU time 0.85 seconds
Started Aug 08 06:18:16 PM PDT 24
Finished Aug 08 06:18:17 PM PDT 24
Peak memory 207604 kb
Host smart-ba4c63d3-f826-499f-adcc-2f65ed7d819b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014
87611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4001487611
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.609991992
Short name T2819
Test name
Test status
Simulation time 218004844 ps
CPU time 1 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207628 kb
Host smart-6924a9de-33bf-4420-9a89-50acf6e1deac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60999
1992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.609991992
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2327103935
Short name T2715
Test name
Test status
Simulation time 1463902149 ps
CPU time 11.27 seconds
Started Aug 08 06:18:26 PM PDT 24
Finished Aug 08 06:18:38 PM PDT 24
Peak memory 207796 kb
Host smart-701606ff-ac68-4ba8-a5ad-e4c0a3f0e1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
03935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2327103935
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1727003673
Short name T2068
Test name
Test status
Simulation time 4701344234 ps
CPU time 41.74 seconds
Started Aug 08 06:18:17 PM PDT 24
Finished Aug 08 06:18:59 PM PDT 24
Peak memory 207808 kb
Host smart-5ab2f11d-e718-4c61-ac68-f726ba507e7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727003673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.1727003673
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.2339385135
Short name T1006
Test name
Test status
Simulation time 551030272 ps
CPU time 1.72 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207580 kb
Host smart-6ebed9b8-887c-4c30-b27a-02a15bc6ba57
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339385135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.2339385135
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.2810583043
Short name T3230
Test name
Test status
Simulation time 498404272 ps
CPU time 1.56 seconds
Started Aug 08 06:22:13 PM PDT 24
Finished Aug 08 06:22:15 PM PDT 24
Peak memory 207620 kb
Host smart-0e438303-78a0-49d1-9263-ac97c22e2093
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810583043 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.2810583043
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.463006177
Short name T2346
Test name
Test status
Simulation time 480075769 ps
CPU time 1.49 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207572 kb
Host smart-87cf7e46-a8df-45c9-b71b-14217014aafe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463006177 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.463006177
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.4170866753
Short name T3493
Test name
Test status
Simulation time 640168444 ps
CPU time 1.77 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207588 kb
Host smart-b21e3ebc-26ba-4a9a-a56e-f76d347cc1ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170866753 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.4170866753
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.919350347
Short name T566
Test name
Test status
Simulation time 490231643 ps
CPU time 1.47 seconds
Started Aug 08 06:22:12 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 207568 kb
Host smart-4774b6e6-951e-4021-88e6-da22768d1f81
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919350347 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.919350347
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.2454570797
Short name T1901
Test name
Test status
Simulation time 559402890 ps
CPU time 1.47 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207544 kb
Host smart-3dab4353-ebe7-4ef7-9582-9dcc6e7cc720
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454570797 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.2454570797
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.1329665138
Short name T1293
Test name
Test status
Simulation time 591626916 ps
CPU time 1.51 seconds
Started Aug 08 06:22:09 PM PDT 24
Finished Aug 08 06:22:10 PM PDT 24
Peak memory 207588 kb
Host smart-d4e2b2c3-78f2-4dc0-9abf-c2e9a733fb58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329665138 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.1329665138
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.275338874
Short name T1664
Test name
Test status
Simulation time 598041998 ps
CPU time 1.48 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207540 kb
Host smart-e2beab79-7501-4b6b-84f3-bbbe85cf968a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275338874 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.275338874
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.2490573889
Short name T179
Test name
Test status
Simulation time 443132972 ps
CPU time 1.46 seconds
Started Aug 08 06:22:22 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207616 kb
Host smart-b90334fe-dc06-40e2-a94a-6682852e2217
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490573889 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.2490573889
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.3309881320
Short name T33
Test name
Test status
Simulation time 485524705 ps
CPU time 1.47 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:22 PM PDT 24
Peak memory 207528 kb
Host smart-7d603cbd-df49-4fda-8420-f650b5bc2164
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309881320 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.3309881320
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.1950516270
Short name T1380
Test name
Test status
Simulation time 656383873 ps
CPU time 1.7 seconds
Started Aug 08 06:22:34 PM PDT 24
Finished Aug 08 06:22:36 PM PDT 24
Peak memory 207616 kb
Host smart-85a7834e-7192-4335-9990-d0449ab0ebaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950516270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.1950516270
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2789992349
Short name T3007
Test name
Test status
Simulation time 35568497 ps
CPU time 0.66 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 207556 kb
Host smart-1c79b892-9468-4914-a65c-0da1e0902192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2789992349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2789992349
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2471582375
Short name T222
Test name
Test status
Simulation time 10986039266 ps
CPU time 13.75 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207848 kb
Host smart-e3165b63-9892-46e0-9555-4193cfb287ee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471582375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.2471582375
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3128074762
Short name T2033
Test name
Test status
Simulation time 13449576948 ps
CPU time 16.33 seconds
Started Aug 08 06:18:31 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 215996 kb
Host smart-92b1dec1-743a-4b33-99b9-4d08ede688e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128074762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3128074762
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3179925919
Short name T2836
Test name
Test status
Simulation time 30076751057 ps
CPU time 33.15 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207600 kb
Host smart-83aac204-052f-4b58-8846-78be6004ccfc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179925919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3179925919
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2870803952
Short name T3187
Test name
Test status
Simulation time 171725702 ps
CPU time 0.89 seconds
Started Aug 08 06:18:37 PM PDT 24
Finished Aug 08 06:18:38 PM PDT 24
Peak memory 207504 kb
Host smart-0c1ca933-6d5f-4b7e-97cb-b9cec2d694c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28708
03952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2870803952
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2757240436
Short name T1428
Test name
Test status
Simulation time 144878670 ps
CPU time 0.93 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207564 kb
Host smart-3dc755fa-92e3-42cc-aa71-b68de79cbebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
40436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2757240436
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.744020180
Short name T1199
Test name
Test status
Simulation time 411728173 ps
CPU time 1.38 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207624 kb
Host smart-edf18afc-b6c0-4ed0-9da8-3a8aa949faaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74402
0180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.744020180
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2588416191
Short name T2781
Test name
Test status
Simulation time 61618695456 ps
CPU time 92.3 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207840 kb
Host smart-6647c3a8-5ded-4e66-a9be-34e21023692b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
16191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2588416191
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.2913401277
Short name T2124
Test name
Test status
Simulation time 481757188 ps
CPU time 8.08 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207764 kb
Host smart-28369103-968f-4c45-a96c-799777300ec9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913401277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2913401277
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3228928544
Short name T3257
Test name
Test status
Simulation time 890173812 ps
CPU time 1.92 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207496 kb
Host smart-adacae47-7c16-422f-b88f-0a56cc296837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
28544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3228928544
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1317197062
Short name T2717
Test name
Test status
Simulation time 152380515 ps
CPU time 0.84 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207532 kb
Host smart-b815c8d3-3ab8-4939-b5fa-c3e369c99b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
97062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1317197062
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.951710185
Short name T1143
Test name
Test status
Simulation time 65109627 ps
CPU time 0.73 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:22 PM PDT 24
Peak memory 207516 kb
Host smart-e176109d-3b98-4c86-acfe-9e0d9f92a480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95171
0185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.951710185
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2966285164
Short name T1183
Test name
Test status
Simulation time 1001789773 ps
CPU time 2.6 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207808 kb
Host smart-bd603be4-d439-410d-a5bc-8884111dda21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
85164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2966285164
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.1455913844
Short name T486
Test name
Test status
Simulation time 392429907 ps
CPU time 1.32 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:18:29 PM PDT 24
Peak memory 207500 kb
Host smart-5107be16-6323-403f-9b42-a4c6e617807b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1455913844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.1455913844
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3081000842
Short name T1249
Test name
Test status
Simulation time 162126589 ps
CPU time 1.78 seconds
Started Aug 08 06:18:29 PM PDT 24
Finished Aug 08 06:18:31 PM PDT 24
Peak memory 207764 kb
Host smart-e9d5b587-ef42-4a26-ace4-8704f44006d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
00842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3081000842
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3062513980
Short name T1905
Test name
Test status
Simulation time 192783725 ps
CPU time 1.05 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 215908 kb
Host smart-b0b388d0-18b0-4f0f-8f5b-8936af402086
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3062513980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3062513980
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1282963287
Short name T1638
Test name
Test status
Simulation time 163381531 ps
CPU time 0.89 seconds
Started Aug 08 06:18:23 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207532 kb
Host smart-ddaba15c-5d9a-43fc-9a41-9895398bde54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12829
63287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1282963287
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4181086329
Short name T2688
Test name
Test status
Simulation time 238463698 ps
CPU time 1.02 seconds
Started Aug 08 06:18:38 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 207568 kb
Host smart-f91f105c-ac29-4426-a06a-07a5aa34d715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41810
86329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4181086329
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.916486074
Short name T1609
Test name
Test status
Simulation time 2610852340 ps
CPU time 73.04 seconds
Started Aug 08 06:18:36 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 218724 kb
Host smart-82d70f09-d963-4661-9ae5-8069088e770b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=916486074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.916486074
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.4292097088
Short name T1726
Test name
Test status
Simulation time 8767250833 ps
CPU time 61.45 seconds
Started Aug 08 06:18:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207796 kb
Host smart-33551745-6603-4c3a-ac00-4b97f3d1778a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4292097088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.4292097088
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1894966605
Short name T1692
Test name
Test status
Simulation time 319832695 ps
CPU time 1.11 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207548 kb
Host smart-b8424c6a-53c4-4fe6-8d72-8ced2d2d3a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18949
66605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1894966605
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.24309031
Short name T997
Test name
Test status
Simulation time 35073344709 ps
CPU time 53.12 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207828 kb
Host smart-fe5d1511-a397-4c8a-a554-00a9db83a33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309
031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.24309031
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2432968995
Short name T3502
Test name
Test status
Simulation time 4215015449 ps
CPU time 5.72 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207840 kb
Host smart-5129cdef-8339-47f6-8cad-9cf58a26205e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24329
68995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2432968995
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1899180687
Short name T1319
Test name
Test status
Simulation time 3485308003 ps
CPU time 27.83 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 216176 kb
Host smart-9d2a5a2b-1ccb-486f-9856-1a81c2161a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
80687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1899180687
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3007665739
Short name T978
Test name
Test status
Simulation time 3369110718 ps
CPU time 26.62 seconds
Started Aug 08 06:18:36 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 216108 kb
Host smart-9cefe067-7f23-4d58-a2f5-85a9c94a43c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3007665739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3007665739
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1433799759
Short name T1408
Test name
Test status
Simulation time 245536294 ps
CPU time 1 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 207528 kb
Host smart-b4ce80ea-59d5-43b8-8adb-91775a9c9048
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1433799759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1433799759
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.6296921
Short name T1020
Test name
Test status
Simulation time 206302291 ps
CPU time 0.93 seconds
Started Aug 08 06:18:38 PM PDT 24
Finished Aug 08 06:18:39 PM PDT 24
Peak memory 207592 kb
Host smart-9ab99c1e-bc7c-4e52-b46e-cdf727e66b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62969
21 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.6296921
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1243511887
Short name T1518
Test name
Test status
Simulation time 2289605674 ps
CPU time 23.67 seconds
Started Aug 08 06:18:25 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 216044 kb
Host smart-b32399f6-8b1f-4d5a-bc2d-59d6b5d54b2c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1243511887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1243511887
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1452849480
Short name T2456
Test name
Test status
Simulation time 161850826 ps
CPU time 0.86 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207592 kb
Host smart-8fb442b3-7f66-454b-9473-291630f14add
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1452849480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1452849480
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.910383780
Short name T1061
Test name
Test status
Simulation time 162077705 ps
CPU time 0.85 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:18:25 PM PDT 24
Peak memory 207584 kb
Host smart-4ddaca74-2a62-4448-a068-e72a00a8fe4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91038
3780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.910383780
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3445980048
Short name T131
Test name
Test status
Simulation time 211952366 ps
CPU time 0.96 seconds
Started Aug 08 06:18:23 PM PDT 24
Finished Aug 08 06:18:24 PM PDT 24
Peak memory 207544 kb
Host smart-3c740440-c7f5-4103-a6f3-1a46d8cef130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34459
80048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3445980048
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1802372849
Short name T1147
Test name
Test status
Simulation time 175722337 ps
CPU time 0.88 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207588 kb
Host smart-b4c27e2d-2d34-4e33-aacf-bb677cfb5c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18023
72849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1802372849
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1211132824
Short name T1491
Test name
Test status
Simulation time 189447808 ps
CPU time 0.9 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207580 kb
Host smart-a61f221f-45c7-4900-a235-b525f8f6c7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12111
32824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1211132824
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1141110749
Short name T2677
Test name
Test status
Simulation time 154929921 ps
CPU time 0.87 seconds
Started Aug 08 06:18:26 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207560 kb
Host smart-11f894be-a50b-405c-aca3-75121b3e41a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
10749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1141110749
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2111417820
Short name T2472
Test name
Test status
Simulation time 190003580 ps
CPU time 0.86 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207560 kb
Host smart-b5efe350-9c5f-45ed-b761-a3a96a64bed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
17820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2111417820
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3658728522
Short name T3615
Test name
Test status
Simulation time 222544713 ps
CPU time 1.02 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:18:25 PM PDT 24
Peak memory 207568 kb
Host smart-3b3260b6-da4f-48c6-9202-e336f552006c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3658728522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3658728522
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1354201365
Short name T1225
Test name
Test status
Simulation time 164410997 ps
CPU time 0.87 seconds
Started Aug 08 06:18:37 PM PDT 24
Finished Aug 08 06:18:38 PM PDT 24
Peak memory 207540 kb
Host smart-2a5e30d5-0c5f-4934-8c08-2420bed78c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13542
01365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1354201365
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.4025384055
Short name T2579
Test name
Test status
Simulation time 33642624 ps
CPU time 0.7 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207588 kb
Host smart-b89d66da-ac2a-4fec-9b34-c89dddae0e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
84055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.4025384055
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.135005097
Short name T295
Test name
Test status
Simulation time 14315306464 ps
CPU time 40.99 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 216116 kb
Host smart-75609deb-3830-43b8-be81-91da17be20e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13500
5097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.135005097
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1823185041
Short name T1456
Test name
Test status
Simulation time 160256182 ps
CPU time 0.86 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:18:33 PM PDT 24
Peak memory 207480 kb
Host smart-f890f35e-9269-4882-bca1-0cb0ea6dd9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18231
85041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1823185041
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3082497035
Short name T1395
Test name
Test status
Simulation time 193925400 ps
CPU time 0.95 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207512 kb
Host smart-40b6359b-87e8-4959-b8af-9fcf296d10de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
97035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3082497035
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1555360850
Short name T3401
Test name
Test status
Simulation time 234996421 ps
CPU time 1.03 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207500 kb
Host smart-f0d4cb8b-700e-43b4-9d7e-adae899c0d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
60850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1555360850
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.219448461
Short name T783
Test name
Test status
Simulation time 154425250 ps
CPU time 0.88 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207496 kb
Host smart-f6032515-58a6-4298-b28c-f6a20c4ecdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21944
8461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.219448461
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.731511354
Short name T1994
Test name
Test status
Simulation time 164350653 ps
CPU time 0.86 seconds
Started Aug 08 06:18:27 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207452 kb
Host smart-46406e72-b34c-49c8-9652-fbba9e07e26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73151
1354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.731511354
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.212174838
Short name T2066
Test name
Test status
Simulation time 343140694 ps
CPU time 1.24 seconds
Started Aug 08 06:18:27 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207524 kb
Host smart-fa5cce67-0868-477e-8b7a-9b279f369917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
4838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.212174838
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4259856831
Short name T1340
Test name
Test status
Simulation time 162328561 ps
CPU time 0.88 seconds
Started Aug 08 06:18:26 PM PDT 24
Finished Aug 08 06:18:27 PM PDT 24
Peak memory 207488 kb
Host smart-a7f4ae46-98eb-42e8-960f-1e700b9519ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42598
56831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4259856831
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3909350822
Short name T1802
Test name
Test status
Simulation time 158069974 ps
CPU time 0.84 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:18:29 PM PDT 24
Peak memory 207536 kb
Host smart-b75ff94e-455c-4c3b-a334-1a1c7e6ae7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
50822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3909350822
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1231095380
Short name T2748
Test name
Test status
Simulation time 244742827 ps
CPU time 1.04 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207564 kb
Host smart-6f6f8225-9e38-449b-80e8-ab7d83f442a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12310
95380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1231095380
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2512558350
Short name T2827
Test name
Test status
Simulation time 3205591061 ps
CPU time 88.33 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 224208 kb
Host smart-e92db7cc-c8a4-4d05-9ffd-fb496157222e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2512558350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2512558350
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4276128553
Short name T2458
Test name
Test status
Simulation time 164536528 ps
CPU time 0.84 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207480 kb
Host smart-98e0021d-88d5-487f-929e-ef1d20839fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42761
28553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4276128553
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2378192871
Short name T2339
Test name
Test status
Simulation time 187021092 ps
CPU time 0.94 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207560 kb
Host smart-da0e4ef5-cdd7-4c8f-ab3a-1717558c592c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
92871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2378192871
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2864618904
Short name T3008
Test name
Test status
Simulation time 679326669 ps
CPU time 1.9 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207536 kb
Host smart-8add3c51-e536-4822-8b68-bb656cea8b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
18904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2864618904
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1490528880
Short name T1039
Test name
Test status
Simulation time 1723931427 ps
CPU time 17.01 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 224096 kb
Host smart-053181bf-a441-423d-b32e-57ac2d4c13b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
28880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1490528880
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.3495724789
Short name T3099
Test name
Test status
Simulation time 642281888 ps
CPU time 10.72 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:50 PM PDT 24
Peak memory 207672 kb
Host smart-4490dbbc-af44-4601-afe5-3b1a24eef034
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495724789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.3495724789
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.4035991090
Short name T3251
Test name
Test status
Simulation time 470782241 ps
CPU time 1.46 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207616 kb
Host smart-4ba9d0fd-474c-4c3c-aedd-8369e2825849
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035991090 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.4035991090
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.1740021616
Short name T162
Test name
Test status
Simulation time 495361401 ps
CPU time 1.62 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207584 kb
Host smart-b7e90666-116d-464c-b629-f899937b086b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740021616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.1740021616
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.2052963808
Short name T2224
Test name
Test status
Simulation time 472122995 ps
CPU time 1.59 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207584 kb
Host smart-496c0c64-ae57-49b4-b69d-7e91bf34d379
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052963808 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.2052963808
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.4244895408
Short name T1398
Test name
Test status
Simulation time 578505298 ps
CPU time 1.61 seconds
Started Aug 08 06:22:11 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 207552 kb
Host smart-ee2ab0f1-ad7f-47ff-a8fa-28153d9b9876
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244895408 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.4244895408
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.196945109
Short name T1048
Test name
Test status
Simulation time 614996838 ps
CPU time 1.61 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207572 kb
Host smart-6a5351b5-1ec5-4350-9b10-15b14f0e9e00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196945109 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.196945109
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.2332807484
Short name T2431
Test name
Test status
Simulation time 570047631 ps
CPU time 1.6 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207564 kb
Host smart-6e528270-4524-4abd-b16a-5f2d6b406db7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332807484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.2332807484
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.1075877108
Short name T1451
Test name
Test status
Simulation time 547441127 ps
CPU time 1.65 seconds
Started Aug 08 06:22:14 PM PDT 24
Finished Aug 08 06:22:16 PM PDT 24
Peak memory 207552 kb
Host smart-0c32dd16-8a44-4d51-993b-3deed3bfde2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075877108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.1075877108
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.546090554
Short name T2572
Test name
Test status
Simulation time 527637272 ps
CPU time 1.78 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 207516 kb
Host smart-4e0ce5b6-7009-4c80-b30f-310de3be0d0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546090554 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.546090554
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.4123757984
Short name T1200
Test name
Test status
Simulation time 566988380 ps
CPU time 1.67 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207588 kb
Host smart-27a5373d-cb15-418f-9a9c-dad0c27705f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123757984 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.4123757984
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.3843900257
Short name T2787
Test name
Test status
Simulation time 524336661 ps
CPU time 1.5 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207592 kb
Host smart-e9610e34-2619-492c-9106-9bc27f39ed56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843900257 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.3843900257
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.60408455
Short name T1239
Test name
Test status
Simulation time 574602349 ps
CPU time 1.67 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207616 kb
Host smart-0301c3d1-4cf1-4b51-931f-96f0545732fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60408455 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.60408455
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.222360566
Short name T2094
Test name
Test status
Simulation time 62847286 ps
CPU time 0.71 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207632 kb
Host smart-39e725ac-eebb-4c90-85e1-660ef23adf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=222360566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.222360566
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3919793069
Short name T2773
Test name
Test status
Simulation time 5970984670 ps
CPU time 7.43 seconds
Started Aug 08 06:18:23 PM PDT 24
Finished Aug 08 06:18:30 PM PDT 24
Peak memory 216068 kb
Host smart-95568efe-2f61-445c-a88e-ff2b25a86f9b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919793069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3919793069
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1233527249
Short name T3402
Test name
Test status
Simulation time 21282941269 ps
CPU time 25.96 seconds
Started Aug 08 06:18:21 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207844 kb
Host smart-73affbe9-a630-4e09-bd13-df487536c234
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233527249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1233527249
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1678782666
Short name T3027
Test name
Test status
Simulation time 26028522263 ps
CPU time 32.37 seconds
Started Aug 08 06:18:28 PM PDT 24
Finished Aug 08 06:19:01 PM PDT 24
Peak memory 215988 kb
Host smart-23f6a92a-69ed-4625-bf6f-dbd05c97fae0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678782666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.1678782666
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.795424350
Short name T1431
Test name
Test status
Simulation time 200166756 ps
CPU time 0.94 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 207592 kb
Host smart-60f6cb89-df29-4e23-9f5e-8556f35beb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79542
4350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.795424350
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1636449410
Short name T1791
Test name
Test status
Simulation time 197095870 ps
CPU time 0.89 seconds
Started Aug 08 06:18:27 PM PDT 24
Finished Aug 08 06:18:28 PM PDT 24
Peak memory 207516 kb
Host smart-c6190ad4-328e-444a-9408-2b5af6078bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16364
49410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1636449410
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.889551788
Short name T817
Test name
Test status
Simulation time 403603936 ps
CPU time 1.4 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207472 kb
Host smart-f64833aa-d96b-4541-9e74-f299d50ad941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88955
1788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.889551788
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1522754451
Short name T2166
Test name
Test status
Simulation time 546151148 ps
CPU time 1.58 seconds
Started Aug 08 06:18:24 PM PDT 24
Finished Aug 08 06:18:26 PM PDT 24
Peak memory 207524 kb
Host smart-e174f8ee-3073-4d92-9e41-fec9af243664
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1522754451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1522754451
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2253518566
Short name T506
Test name
Test status
Simulation time 56301732341 ps
CPU time 107.14 seconds
Started Aug 08 06:18:32 PM PDT 24
Finished Aug 08 06:20:19 PM PDT 24
Peak memory 207832 kb
Host smart-203ea4f7-037f-43d3-a9f3-d158f6d3856c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
18566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2253518566
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.2909693501
Short name T3473
Test name
Test status
Simulation time 606130518 ps
CPU time 11.52 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207744 kb
Host smart-696dc28a-a966-4062-82f5-d0b2d629a34a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909693501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.2909693501
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3336906897
Short name T731
Test name
Test status
Simulation time 787848767 ps
CPU time 1.89 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207540 kb
Host smart-ebfe3a4c-c930-4b20-8936-976fadfba938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
06897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3336906897
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3608948698
Short name T2149
Test name
Test status
Simulation time 191350761 ps
CPU time 0.87 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207572 kb
Host smart-0bf735dd-957d-4226-aebf-5d3f81791950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36089
48698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3608948698
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3582966545
Short name T2333
Test name
Test status
Simulation time 64583816 ps
CPU time 0.73 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207572 kb
Host smart-4bc9ac9c-3e1d-4e8d-b48d-390f40ebf980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35829
66545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3582966545
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2197609067
Short name T703
Test name
Test status
Simulation time 848063827 ps
CPU time 2.37 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207792 kb
Host smart-e306d06e-1268-4699-9dfe-ffbd2c04c96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
09067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2197609067
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.3893357230
Short name T3428
Test name
Test status
Simulation time 226390388 ps
CPU time 0.96 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207588 kb
Host smart-a7618c70-08ce-475f-9de1-3fd208d2db42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3893357230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.3893357230
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2439365462
Short name T1066
Test name
Test status
Simulation time 299847462 ps
CPU time 2.39 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207688 kb
Host smart-e6241caf-7028-4974-8f2a-22bdeaefd5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
65462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2439365462
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3464627557
Short name T1133
Test name
Test status
Simulation time 256800883 ps
CPU time 1.33 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 215940 kb
Host smart-07c4bbb4-b9c3-482c-8b58-e25972abc501
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3464627557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3464627557
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1047130604
Short name T2970
Test name
Test status
Simulation time 153355337 ps
CPU time 0.84 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207508 kb
Host smart-a67f0614-513f-41f2-bffd-b09411c11d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10471
30604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1047130604
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1889037434
Short name T549
Test name
Test status
Simulation time 185150236 ps
CPU time 0.93 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 207576 kb
Host smart-0e1806b7-fc29-48ef-b155-04db3fcf4ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18890
37434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1889037434
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1498463736
Short name T2040
Test name
Test status
Simulation time 3509478215 ps
CPU time 33.44 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 224336 kb
Host smart-9375d186-e23c-4f4b-9b4e-b7758ade4572
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1498463736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1498463736
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.3540205557
Short name T1947
Test name
Test status
Simulation time 5033274462 ps
CPU time 62.66 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:51 PM PDT 24
Peak memory 207788 kb
Host smart-64246208-2a38-4b55-bad1-6a8c8e497470
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540205557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3540205557
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1519732737
Short name T2064
Test name
Test status
Simulation time 157937091 ps
CPU time 0.9 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207524 kb
Host smart-3a41ff86-38df-4824-88a4-450e32bd7052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15197
32737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1519732737
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.902988556
Short name T1247
Test name
Test status
Simulation time 25114910665 ps
CPU time 30.84 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:19:19 PM PDT 24
Peak memory 215988 kb
Host smart-96332238-3b4a-4d9c-beb3-952647d00e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90298
8556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.902988556
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3033082788
Short name T3449
Test name
Test status
Simulation time 10335156999 ps
CPU time 13.19 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:55 PM PDT 24
Peak memory 207860 kb
Host smart-7817b548-e9cb-469f-ac26-611c31f7ef0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30330
82788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3033082788
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.617514798
Short name T332
Test name
Test status
Simulation time 4522890056 ps
CPU time 129.41 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 216072 kb
Host smart-154ccf6e-76e0-4a01-b4c5-1ebe98b4ef27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61751
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.617514798
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2461693401
Short name T181
Test name
Test status
Simulation time 2313980049 ps
CPU time 23.91 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 217712 kb
Host smart-fb23591f-d89a-4a7c-9771-7b6e03d55f22
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2461693401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2461693401
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2465055197
Short name T3020
Test name
Test status
Simulation time 290267790 ps
CPU time 1.17 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207552 kb
Host smart-b9cb35d7-d861-4fc5-afd3-33657691def0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2465055197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2465055197
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1067222188
Short name T3330
Test name
Test status
Simulation time 186264837 ps
CPU time 0.95 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207564 kb
Host smart-8a2db3f1-f55c-45fe-b409-03b3bee58552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
22188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1067222188
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.4134797840
Short name T952
Test name
Test status
Simulation time 2357343086 ps
CPU time 17.42 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 217744 kb
Host smart-f18ce5b0-188b-4b50-a88e-e5a467c172bb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4134797840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.4134797840
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1407066279
Short name T1464
Test name
Test status
Simulation time 149466625 ps
CPU time 0.85 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207564 kb
Host smart-2688ca19-5fa6-4579-b2e9-7c390a5f0cdc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1407066279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1407066279
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3484758803
Short name T3130
Test name
Test status
Simulation time 145677184 ps
CPU time 0.85 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207544 kb
Host smart-3914160f-7cbb-4109-a8e8-11a067a7ef67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
58803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3484758803
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3085255430
Short name T137
Test name
Test status
Simulation time 215015019 ps
CPU time 1.05 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207648 kb
Host smart-3e1893ff-5464-412e-bcdc-11ad45d1d1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
55430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3085255430
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3331730865
Short name T2727
Test name
Test status
Simulation time 187120722 ps
CPU time 0.95 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207624 kb
Host smart-c9b9951d-ecf9-491d-839c-371547121e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33317
30865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3331730865
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3221942821
Short name T3611
Test name
Test status
Simulation time 165297347 ps
CPU time 0.83 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207592 kb
Host smart-ea4ea769-d639-4212-b8e3-50cbf728a3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
42821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3221942821
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.423549863
Short name T3536
Test name
Test status
Simulation time 177098267 ps
CPU time 0.97 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207188 kb
Host smart-27e080ac-3e24-404a-bd98-fb8dad3bd717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42354
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.423549863
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.4190559664
Short name T2379
Test name
Test status
Simulation time 160422278 ps
CPU time 0.89 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207564 kb
Host smart-5a6fd28d-43b8-449b-aa38-2cbf1f847b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41905
59664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.4190559664
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1567554166
Short name T1375
Test name
Test status
Simulation time 243141722 ps
CPU time 1.03 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207596 kb
Host smart-327f522c-1e5f-48bf-a049-834e156f311d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1567554166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1567554166
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2818064118
Short name T2213
Test name
Test status
Simulation time 157856779 ps
CPU time 0.88 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207488 kb
Host smart-34537848-da73-472e-a201-6d2328af553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
64118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2818064118
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2549196219
Short name T2207
Test name
Test status
Simulation time 61539725 ps
CPU time 0.74 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207576 kb
Host smart-4e08c12c-f8e5-42e2-8559-df78fc3f8cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
96219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2549196219
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2515808430
Short name T3396
Test name
Test status
Simulation time 10292892658 ps
CPU time 23.86 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:19:12 PM PDT 24
Peak memory 216080 kb
Host smart-15521904-3aea-43c9-8518-0493dc7fa6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25158
08430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2515808430
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3840914588
Short name T2061
Test name
Test status
Simulation time 163833760 ps
CPU time 0.86 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207540 kb
Host smart-0d5ed230-fe29-411f-8559-f657e21d5e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38409
14588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3840914588
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4181424312
Short name T926
Test name
Test status
Simulation time 243972339 ps
CPU time 1.01 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207564 kb
Host smart-748be486-dd11-421f-b558-7faa3c62b784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
24312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4181424312
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.751877806
Short name T1578
Test name
Test status
Simulation time 185395384 ps
CPU time 0.92 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207588 kb
Host smart-f4547fec-9333-48d3-a2b0-ad593d906c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75187
7806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.751877806
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.254967048
Short name T2013
Test name
Test status
Simulation time 147252440 ps
CPU time 0.9 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:53 PM PDT 24
Peak memory 207536 kb
Host smart-786490e9-18df-4e6d-b084-60c1d1163b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
7048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.254967048
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3969495142
Short name T2426
Test name
Test status
Simulation time 150467753 ps
CPU time 0.86 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207604 kb
Host smart-6cf1d6ba-bceb-43dc-8207-297d7ba8aa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
95142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3969495142
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.775039456
Short name T1037
Test name
Test status
Simulation time 246342950 ps
CPU time 1.04 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:41 PM PDT 24
Peak memory 207540 kb
Host smart-c0accd75-bf8e-4112-8790-281c69c11cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77503
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.775039456
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.175935101
Short name T2492
Test name
Test status
Simulation time 166337269 ps
CPU time 0.85 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207528 kb
Host smart-052416ef-7a56-4d1a-a259-69bfa991559d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17593
5101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.175935101
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2327356878
Short name T2267
Test name
Test status
Simulation time 172567320 ps
CPU time 0.84 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207616 kb
Host smart-eff5528f-dea0-449b-904b-fede30bb5433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
56878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2327356878
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1548045089
Short name T2419
Test name
Test status
Simulation time 226318123 ps
CPU time 1 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 207516 kb
Host smart-09cf3ed8-c533-4f76-87bc-d71909743c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
45089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1548045089
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2738892581
Short name T1248
Test name
Test status
Simulation time 1683363681 ps
CPU time 44.52 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:19:25 PM PDT 24
Peak memory 217636 kb
Host smart-c2df98b5-2220-46a3-bcd0-dc8edc28a7c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2738892581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2738892581
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1229448093
Short name T2176
Test name
Test status
Simulation time 195317724 ps
CPU time 0.86 seconds
Started Aug 08 06:18:35 PM PDT 24
Finished Aug 08 06:18:36 PM PDT 24
Peak memory 207576 kb
Host smart-6a342a31-1716-4aca-80a5-ec175fd2ede3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12294
48093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1229448093
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.497795400
Short name T2990
Test name
Test status
Simulation time 174026463 ps
CPU time 0.87 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207552 kb
Host smart-756e4083-0d71-4b8b-bf60-7d0416b0c0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49779
5400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.497795400
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1625350173
Short name T1755
Test name
Test status
Simulation time 510794511 ps
CPU time 1.5 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:18:52 PM PDT 24
Peak memory 207464 kb
Host smart-f9280c88-d5a8-43c3-a2f1-eda219a125fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
50173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1625350173
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.532046005
Short name T1817
Test name
Test status
Simulation time 3376383778 ps
CPU time 34.74 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 216084 kb
Host smart-fe2831ba-a947-4a19-a0ff-9c99a7e99536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53204
6005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.532046005
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.4017861501
Short name T2461
Test name
Test status
Simulation time 2051719664 ps
CPU time 16.3 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:19:01 PM PDT 24
Peak memory 207748 kb
Host smart-add31c05-bde4-49d6-8e1d-2048049f6a92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017861501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.4017861501
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.3714368315
Short name T1158
Test name
Test status
Simulation time 479746967 ps
CPU time 1.46 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207620 kb
Host smart-59b1b7fc-6827-4f1a-b17b-7c8a6ab2dbfb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714368315 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.3714368315
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.2226900422
Short name T1144
Test name
Test status
Simulation time 518157799 ps
CPU time 1.62 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207596 kb
Host smart-d9f17d0d-a79d-4c41-93f2-2c22c75aea7b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226900422 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.2226900422
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.2272626248
Short name T2576
Test name
Test status
Simulation time 507298306 ps
CPU time 1.72 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207640 kb
Host smart-3753e4bc-3941-476b-9f22-aaad1dcbe952
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272626248 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.2272626248
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.472630099
Short name T1220
Test name
Test status
Simulation time 552026252 ps
CPU time 1.65 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207564 kb
Host smart-e38bb29c-3ff7-4772-bc2a-866086af2ded
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472630099 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.472630099
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.4055079981
Short name T2212
Test name
Test status
Simulation time 505292235 ps
CPU time 1.47 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207588 kb
Host smart-2da8bdba-71c4-4871-8bff-173e899d6639
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055079981 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.4055079981
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.349562744
Short name T3496
Test name
Test status
Simulation time 516710099 ps
CPU time 1.52 seconds
Started Aug 08 06:22:30 PM PDT 24
Finished Aug 08 06:22:32 PM PDT 24
Peak memory 207520 kb
Host smart-ac713f1f-e009-4712-95f0-b35be7f639a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349562744 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.349562744
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.4184391638
Short name T3366
Test name
Test status
Simulation time 477536819 ps
CPU time 1.47 seconds
Started Aug 08 06:22:32 PM PDT 24
Finished Aug 08 06:22:34 PM PDT 24
Peak memory 207596 kb
Host smart-84f9a8dd-ea66-4960-be4e-139d596f13d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184391638 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.4184391638
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.2259106685
Short name T3180
Test name
Test status
Simulation time 496785258 ps
CPU time 1.46 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207808 kb
Host smart-8473b754-7744-4f6a-9539-6af737be9805
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259106685 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.2259106685
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.1134842913
Short name T1254
Test name
Test status
Simulation time 601915266 ps
CPU time 1.68 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:48 PM PDT 24
Peak memory 207612 kb
Host smart-5c6959e3-6201-466e-a228-3ded454120a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134842913 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.1134842913
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.3035202099
Short name T1379
Test name
Test status
Simulation time 495884380 ps
CPU time 1.51 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:39 PM PDT 24
Peak memory 207592 kb
Host smart-c4d46082-5c43-40d9-a2fe-d4a488c903e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035202099 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.3035202099
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.223272466
Short name T2324
Test name
Test status
Simulation time 36889142 ps
CPU time 0.66 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207512 kb
Host smart-5e873154-d53f-4d8f-9d87-5ad686e5dc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=223272466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.223272466
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.430823143
Short name T2261
Test name
Test status
Simulation time 5719285332 ps
CPU time 8.05 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:56 PM PDT 24
Peak memory 216004 kb
Host smart-ccbbde44-1b4a-41a2-8c4c-3ce6148e752c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430823143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_disconnect.430823143
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1895424894
Short name T2053
Test name
Test status
Simulation time 20177874718 ps
CPU time 26.31 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 207840 kb
Host smart-eef99e8b-5409-4b41-90ec-d3a243b97b22
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895424894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1895424894
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.576857860
Short name T905
Test name
Test status
Simulation time 25547011900 ps
CPU time 32.92 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:22 PM PDT 24
Peak memory 215704 kb
Host smart-b08536cd-ab00-4486-803d-a66ff566d404
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576857860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_resume.576857860
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4065328459
Short name T2051
Test name
Test status
Simulation time 201290250 ps
CPU time 0.97 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207536 kb
Host smart-9f8f4c5c-1db4-4415-9b05-c2d9986ff1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
28459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4065328459
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1030350168
Short name T1775
Test name
Test status
Simulation time 175728429 ps
CPU time 0.91 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207572 kb
Host smart-9ddd19c4-8926-4d62-86f4-9aa8ec943d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303
50168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1030350168
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3425017933
Short name T663
Test name
Test status
Simulation time 395300696 ps
CPU time 1.43 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207492 kb
Host smart-2ff32aa1-a00a-4c9c-8af2-b24b930a74ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
17933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3425017933
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1841613286
Short name T2753
Test name
Test status
Simulation time 567949064 ps
CPU time 1.64 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207596 kb
Host smart-bff8c5e9-46a8-4f6b-b53d-a324f7a37b9f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1841613286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1841613286
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3768170168
Short name T1956
Test name
Test status
Simulation time 60006894443 ps
CPU time 91.71 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 207848 kb
Host smart-5062fc8a-cc4e-4df1-9bea-e5830f57da52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
70168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3768170168
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.3197434213
Short name T876
Test name
Test status
Simulation time 5609200824 ps
CPU time 37.97 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207900 kb
Host smart-798170a4-1f33-4f15-b2c7-3f983e349637
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197434213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3197434213
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.4210674773
Short name T107
Test name
Test status
Simulation time 819868632 ps
CPU time 1.97 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:50 PM PDT 24
Peak memory 207504 kb
Host smart-8b97c9bd-879d-4170-b48c-ebf29011bc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
74773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.4210674773
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2002183669
Short name T2355
Test name
Test status
Simulation time 135365057 ps
CPU time 0.83 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207488 kb
Host smart-ac9e0e1c-f103-4d9b-af09-c088563f36e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20021
83669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2002183669
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.793934520
Short name T3595
Test name
Test status
Simulation time 71761101 ps
CPU time 0.76 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207572 kb
Host smart-0901fb81-7b65-425f-bc0d-88889b55b201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79393
4520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.793934520
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2222016773
Short name T3148
Test name
Test status
Simulation time 1020332143 ps
CPU time 2.87 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207728 kb
Host smart-2698059e-8093-48d7-be3d-2973df238212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
16773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2222016773
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.3493689851
Short name T473
Test name
Test status
Simulation time 661182590 ps
CPU time 1.69 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207480 kb
Host smart-b0c07b55-333b-4911-b4c2-d7372e597325
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3493689851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.3493689851
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3087302632
Short name T2664
Test name
Test status
Simulation time 278986244 ps
CPU time 1.87 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207804 kb
Host smart-02106734-0c9a-4030-bfc4-00278bb035f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
02632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3087302632
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1703285508
Short name T812
Test name
Test status
Simulation time 185475596 ps
CPU time 0.94 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 215880 kb
Host smart-0523e396-c8fc-4e03-99f9-d9c1e2625a68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1703285508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1703285508
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1084684713
Short name T3
Test name
Test status
Simulation time 143035303 ps
CPU time 0.8 seconds
Started Aug 08 06:18:39 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 207560 kb
Host smart-f69d5a13-4aff-424a-90f6-86fbcbc35fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846
84713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1084684713
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.815935255
Short name T1590
Test name
Test status
Simulation time 186215869 ps
CPU time 0.91 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207516 kb
Host smart-45458bc1-f68b-43b8-a993-636d7909d47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81593
5255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.815935255
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1035282053
Short name T3289
Test name
Test status
Simulation time 5331761770 ps
CPU time 157.52 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 218032 kb
Host smart-c71e1ce9-8cf5-42be-8046-6b6f3bf3b6f4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1035282053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1035282053
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2615066559
Short name T2535
Test name
Test status
Simulation time 11614363464 ps
CPU time 77.63 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207832 kb
Host smart-1a774e3a-5063-428a-93ef-28b17d89edb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2615066559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2615066559
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.971797553
Short name T1134
Test name
Test status
Simulation time 213337326 ps
CPU time 0.92 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:45 PM PDT 24
Peak memory 207628 kb
Host smart-df9a3317-628b-4bda-83ec-acd6a40fe04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97179
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.971797553
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.4160873682
Short name T1243
Test name
Test status
Simulation time 27787099579 ps
CPU time 50.93 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 207788 kb
Host smart-89ff10a7-edf1-489a-9637-200342a9a317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41608
73682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.4160873682
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3873381008
Short name T1495
Test name
Test status
Simulation time 4710528018 ps
CPU time 7.86 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:56 PM PDT 24
Peak memory 207880 kb
Host smart-6a23f5e3-d425-44a3-a79a-98e4020b274e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38733
81008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3873381008
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.423340834
Short name T803
Test name
Test status
Simulation time 2959336029 ps
CPU time 26.74 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 217668 kb
Host smart-b2393fd9-d54f-46a6-b0cb-ed79f1a122f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334
0834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.423340834
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.540190149
Short name T2624
Test name
Test status
Simulation time 2797018874 ps
CPU time 21.64 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 217984 kb
Host smart-23217ad0-2689-4328-918d-bd78cfb0c056
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=540190149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.540190149
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.547568889
Short name T3577
Test name
Test status
Simulation time 253943978 ps
CPU time 1.07 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:18:52 PM PDT 24
Peak memory 207620 kb
Host smart-04e7373e-7228-41d6-a107-83e7abba7aa4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=547568889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.547568889
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2780781306
Short name T1877
Test name
Test status
Simulation time 207604952 ps
CPU time 0.94 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207536 kb
Host smart-7d2e5c25-ab8e-4e9d-aa08-b00f3e27463a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807
81306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2780781306
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3700600172
Short name T784
Test name
Test status
Simulation time 3583936213 ps
CPU time 25.52 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:19:13 PM PDT 24
Peak memory 217608 kb
Host smart-50f4ece9-2a65-4e14-b46f-499de5384bd2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3700600172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3700600172
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1571358714
Short name T2350
Test name
Test status
Simulation time 157472719 ps
CPU time 0.91 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207516 kb
Host smart-0d365039-039b-48d8-941d-7defde0cf039
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1571358714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1571358714
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.669494951
Short name T1845
Test name
Test status
Simulation time 146339504 ps
CPU time 0.84 seconds
Started Aug 08 06:18:40 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207636 kb
Host smart-c30a095e-f355-44e7-be76-03d7c44b6065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66949
4951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.669494951
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.510308234
Short name T573
Test name
Test status
Simulation time 158935928 ps
CPU time 0.94 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207536 kb
Host smart-f4b3be69-0080-4c7d-94a8-ae131ab5dfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51030
8234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.510308234
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2592401259
Short name T3445
Test name
Test status
Simulation time 164403858 ps
CPU time 0.85 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207588 kb
Host smart-6778a1bf-6bb5-421b-bfb0-9d74fe813c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25924
01259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2592401259
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2463089523
Short name T3142
Test name
Test status
Simulation time 161155609 ps
CPU time 0.86 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207556 kb
Host smart-1596d5c7-a8f4-4304-a29c-0d0ac8c50156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
89523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2463089523
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2349357965
Short name T2090
Test name
Test status
Simulation time 160979886 ps
CPU time 0.85 seconds
Started Aug 08 06:18:42 PM PDT 24
Finished Aug 08 06:18:43 PM PDT 24
Peak memory 207552 kb
Host smart-53f9f78b-e15f-45d8-9c00-2b0a1b7624ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
57965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2349357965
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2054184567
Short name T3439
Test name
Test status
Simulation time 247200775 ps
CPU time 1.09 seconds
Started Aug 08 06:18:41 PM PDT 24
Finished Aug 08 06:18:42 PM PDT 24
Peak memory 207620 kb
Host smart-75448dee-ccea-40ab-907a-2c82d382506d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2054184567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2054184567
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3586515363
Short name T3216
Test name
Test status
Simulation time 153629414 ps
CPU time 0.82 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207564 kb
Host smart-0a53c5cc-2a50-48da-b860-9cdcdc610143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
15363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3586515363
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.140246743
Short name T2841
Test name
Test status
Simulation time 46793386 ps
CPU time 0.7 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207540 kb
Host smart-735fc88a-6f16-442c-bd96-a9354a2c937a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
6743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.140246743
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.749611254
Short name T2604
Test name
Test status
Simulation time 21251268057 ps
CPU time 52.52 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 216076 kb
Host smart-b2b44aa7-4996-4685-b61e-070d1407e194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74961
1254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.749611254
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2755660231
Short name T2203
Test name
Test status
Simulation time 153989548 ps
CPU time 0.9 seconds
Started Aug 08 06:18:45 PM PDT 24
Finished Aug 08 06:18:46 PM PDT 24
Peak memory 207784 kb
Host smart-dc373e0f-fb1d-4409-88e1-26cd80f42570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
60231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2755660231
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1399258444
Short name T2254
Test name
Test status
Simulation time 238089524 ps
CPU time 1.04 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:02 PM PDT 24
Peak memory 207632 kb
Host smart-abc0ca8e-9db6-49e4-be19-9506de262cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13992
58444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1399258444
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3090697205
Short name T3357
Test name
Test status
Simulation time 179068291 ps
CPU time 0.87 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207508 kb
Host smart-94313f30-7fcc-40fd-ad1b-69dc1c8702dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30906
97205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3090697205
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2796090995
Short name T676
Test name
Test status
Simulation time 156793035 ps
CPU time 0.84 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207544 kb
Host smart-a57a3765-479a-4c75-89ae-db1d103e33f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27960
90995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2796090995
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1008330226
Short name T3283
Test name
Test status
Simulation time 138928666 ps
CPU time 0.82 seconds
Started Aug 08 06:18:56 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207572 kb
Host smart-94354cf7-5095-47a4-aa91-5296a64d97fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10083
30226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1008330226
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.1915327552
Short name T54
Test name
Test status
Simulation time 321601108 ps
CPU time 1.26 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:18:50 PM PDT 24
Peak memory 207564 kb
Host smart-a8e26e65-e276-4c6c-b3d8-3bb62859a322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19153
27552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.1915327552
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1397188143
Short name T3290
Test name
Test status
Simulation time 155499925 ps
CPU time 0.88 seconds
Started Aug 08 06:18:56 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207584 kb
Host smart-5a0621c0-3dd3-452e-95b1-840f272dd2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13971
88143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1397188143
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1551667545
Short name T2178
Test name
Test status
Simulation time 156313869 ps
CPU time 0.87 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207544 kb
Host smart-0763a21d-4e50-4f87-85d7-791b046ff51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
67545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1551667545
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3821730833
Short name T1850
Test name
Test status
Simulation time 259436258 ps
CPU time 1.15 seconds
Started Aug 08 06:19:00 PM PDT 24
Finished Aug 08 06:19:02 PM PDT 24
Peak memory 207548 kb
Host smart-87aad565-dc76-4aba-8ab4-4c787639ded7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
30833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3821730833
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3960580265
Short name T3363
Test name
Test status
Simulation time 2004035398 ps
CPU time 16.22 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 224188 kb
Host smart-01ed6593-0a74-4599-b247-7f874634e0e8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3960580265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3960580265
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.554778536
Short name T3202
Test name
Test status
Simulation time 182640796 ps
CPU time 0.89 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207604 kb
Host smart-0fbe839f-1da2-4ed1-927d-97cfeeaa8423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55477
8536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.554778536
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1068652588
Short name T1628
Test name
Test status
Simulation time 210341218 ps
CPU time 1 seconds
Started Aug 08 06:18:52 PM PDT 24
Finished Aug 08 06:18:53 PM PDT 24
Peak memory 207604 kb
Host smart-5946771a-ecdb-47f8-9c2e-f49aaf0d8bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686
52588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1068652588
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.969045430
Short name T1862
Test name
Test status
Simulation time 489518283 ps
CPU time 1.56 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:01 PM PDT 24
Peak memory 207488 kb
Host smart-3946ad59-e7d3-4220-8ece-037facbf949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96904
5430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.969045430
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2827361337
Short name T1699
Test name
Test status
Simulation time 2167503282 ps
CPU time 16.02 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 217548 kb
Host smart-cb983606-8878-452a-89ae-d3c3db6f9fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
61337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2827361337
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.515727678
Short name T2719
Test name
Test status
Simulation time 3606809702 ps
CPU time 22.44 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207864 kb
Host smart-5b8311cb-b692-4bfe-8d5a-4ce5af121f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515727678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_host
_handshake.515727678
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.266488573
Short name T1440
Test name
Test status
Simulation time 463806646 ps
CPU time 1.4 seconds
Started Aug 08 06:18:55 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207520 kb
Host smart-7fb51887-19e2-4341-b372-3845fd8faaf2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266488573 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.266488573
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.2421920135
Short name T2886
Test name
Test status
Simulation time 562954624 ps
CPU time 1.68 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207544 kb
Host smart-9903e428-c866-4221-99f8-25f3383996d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421920135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.2421920135
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.1979687751
Short name T1963
Test name
Test status
Simulation time 510653683 ps
CPU time 1.53 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207512 kb
Host smart-f030ad5b-67aa-4adb-beb7-04e5f145bcf7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979687751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.1979687751
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.1400922119
Short name T2674
Test name
Test status
Simulation time 438967944 ps
CPU time 1.55 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207544 kb
Host smart-7fec4873-757c-45bd-a8e5-c9c917a7d404
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400922119 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.1400922119
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.2106675838
Short name T2815
Test name
Test status
Simulation time 575027448 ps
CPU time 1.65 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207520 kb
Host smart-a24d19b5-7288-42f9-9d15-928011adafc2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106675838 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.2106675838
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.266801226
Short name T2623
Test name
Test status
Simulation time 488640778 ps
CPU time 1.42 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207512 kb
Host smart-bdbb68e0-7632-4c32-85ce-6b05edfeb08b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266801226 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.266801226
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.80508162
Short name T1568
Test name
Test status
Simulation time 561693055 ps
CPU time 1.66 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207556 kb
Host smart-aa5780e7-a1b0-486a-9a69-e5356051df8e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80508162 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.80508162
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.3921355190
Short name T196
Test name
Test status
Simulation time 684100274 ps
CPU time 1.83 seconds
Started Aug 08 06:22:30 PM PDT 24
Finished Aug 08 06:22:32 PM PDT 24
Peak memory 207568 kb
Host smart-1e149160-bb02-4e31-9bff-673b6c3d701e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921355190 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.3921355190
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.1958782083
Short name T1255
Test name
Test status
Simulation time 574452002 ps
CPU time 1.74 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207612 kb
Host smart-841a4926-1da1-48c2-bd3b-26f4232c234f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958782083 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.1958782083
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.2035592479
Short name T950
Test name
Test status
Simulation time 668825005 ps
CPU time 1.98 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207584 kb
Host smart-148b5bcb-0de0-4835-9508-fa01401a5ac3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035592479 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.2035592479
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.2250473450
Short name T3377
Test name
Test status
Simulation time 619989409 ps
CPU time 1.65 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207588 kb
Host smart-4eecb2a4-59de-4900-aab7-e8935f6bb78f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250473450 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.2250473450
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3357482234
Short name T2606
Test name
Test status
Simulation time 60129049 ps
CPU time 0.7 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207552 kb
Host smart-36241247-544b-4e81-839d-b85bb07d3815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3357482234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3357482234
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1941742040
Short name T2854
Test name
Test status
Simulation time 5603748686 ps
CPU time 8.56 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 216088 kb
Host smart-61b13faa-855a-4c76-9a4d-bfddec51fe0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941742040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.1941742040
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3724196483
Short name T3265
Test name
Test status
Simulation time 20200645813 ps
CPU time 27.98 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207828 kb
Host smart-58a593c9-9cb2-4980-aa78-d4494bb37f4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724196483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3724196483
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1911106323
Short name T1752
Test name
Test status
Simulation time 24730373300 ps
CPU time 32.44 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 216024 kb
Host smart-0e782853-277d-4c9b-9670-be5e6c7d81e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911106323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1911106323
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1909675271
Short name T2851
Test name
Test status
Simulation time 145808574 ps
CPU time 0.94 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207584 kb
Host smart-7d170858-8638-4c9c-abe5-14732fe68225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
75271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1909675271
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3103336540
Short name T2878
Test name
Test status
Simulation time 146142983 ps
CPU time 0.84 seconds
Started Aug 08 06:18:54 PM PDT 24
Finished Aug 08 06:18:55 PM PDT 24
Peak memory 207484 kb
Host smart-e8fd60ac-e8de-4feb-8fe8-17fd2cf7f7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
36540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3103336540
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.626917124
Short name T1053
Test name
Test status
Simulation time 619078858 ps
CPU time 1.85 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207568 kb
Host smart-8264a5c0-438e-41c0-839d-718eb7e70bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62691
7124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.626917124
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.446110861
Short name T1047
Test name
Test status
Simulation time 911168809 ps
CPU time 2.4 seconds
Started Aug 08 06:18:44 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207688 kb
Host smart-69e7e6e4-bd4e-47b3-9fb3-f383cacbd352
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=446110861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.446110861
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1312241038
Short name T3544
Test name
Test status
Simulation time 36875114613 ps
CPU time 57.85 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207916 kb
Host smart-2b73fbdd-9890-4efb-8f8d-57772e14b15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13122
41038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1312241038
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.4011515874
Short name T3147
Test name
Test status
Simulation time 2995191745 ps
CPU time 26.87 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:28 PM PDT 24
Peak memory 207820 kb
Host smart-6c551860-e72c-426b-a411-3b21d8fc18bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011515874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.4011515874
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.198975311
Short name T1516
Test name
Test status
Simulation time 688426840 ps
CPU time 1.88 seconds
Started Aug 08 06:18:55 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207536 kb
Host smart-40e3a0d2-ec37-48ee-b555-fbd0e1e2986c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
5311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.198975311
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1736465248
Short name T658
Test name
Test status
Simulation time 174763050 ps
CPU time 0.88 seconds
Started Aug 08 06:18:46 PM PDT 24
Finished Aug 08 06:18:47 PM PDT 24
Peak memory 207576 kb
Host smart-9116cef2-5053-4730-9389-e250a9bc405f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17364
65248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1736465248
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.789063722
Short name T1962
Test name
Test status
Simulation time 55311785 ps
CPU time 0.73 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207432 kb
Host smart-5b792a36-5e93-4e22-9c59-a284cd935ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78906
3722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.789063722
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2623706533
Short name T1405
Test name
Test status
Simulation time 843077914 ps
CPU time 2.46 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207752 kb
Host smart-86059734-4e7a-459b-9769-95efcacf0034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26237
06533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2623706533
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.582602685
Short name T367
Test name
Test status
Simulation time 467720016 ps
CPU time 1.38 seconds
Started Aug 08 06:18:52 PM PDT 24
Finished Aug 08 06:18:54 PM PDT 24
Peak memory 207536 kb
Host smart-cd6c7477-9426-4dbf-92c0-9e09b1a6b863
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=582602685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.582602685
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2757041924
Short name T2418
Test name
Test status
Simulation time 183098896 ps
CPU time 1.42 seconds
Started Aug 08 06:19:00 PM PDT 24
Finished Aug 08 06:19:02 PM PDT 24
Peak memory 207776 kb
Host smart-c78079e1-c0ba-4ad9-a49b-baf055fe891a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27570
41924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2757041924
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2924874361
Short name T660
Test name
Test status
Simulation time 177671384 ps
CPU time 0.92 seconds
Started Aug 08 06:18:56 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207608 kb
Host smart-f80252e5-57e5-42da-b655-8ae9a1a024b0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2924874361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2924874361
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3217889523
Short name T3459
Test name
Test status
Simulation time 147386764 ps
CPU time 0.88 seconds
Started Aug 08 06:18:53 PM PDT 24
Finished Aug 08 06:18:54 PM PDT 24
Peak memory 207516 kb
Host smart-e7140903-d4de-4912-b2de-e27779e658bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32178
89523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3217889523
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4085221101
Short name T3152
Test name
Test status
Simulation time 212229875 ps
CPU time 0.98 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207532 kb
Host smart-e46192cc-a322-49be-b9fd-cee6218ae939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
21101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4085221101
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2032330470
Short name T1965
Test name
Test status
Simulation time 3467710894 ps
CPU time 34.4 seconds
Started Aug 08 06:18:54 PM PDT 24
Finished Aug 08 06:19:28 PM PDT 24
Peak memory 224296 kb
Host smart-2ba5515a-e398-4b7e-a2bc-8fd2aa98345f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2032330470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2032330470
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.11695098
Short name T1190
Test name
Test status
Simulation time 12654385014 ps
CPU time 163.73 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 207804 kb
Host smart-8ad9660f-703d-46db-aed5-bd3dd2526db4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=11695098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.11695098
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.979292820
Short name T3311
Test name
Test status
Simulation time 206001156 ps
CPU time 0.98 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207632 kb
Host smart-e31db9cb-9503-448b-ba11-9ea9e389c8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97929
2820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.979292820
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2848698150
Short name T598
Test name
Test status
Simulation time 22208065656 ps
CPU time 34.25 seconds
Started Aug 08 06:18:57 PM PDT 24
Finished Aug 08 06:19:32 PM PDT 24
Peak memory 216100 kb
Host smart-288af912-e425-4709-a0c1-4ab613ba923f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28486
98150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2848698150
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.504647024
Short name T3182
Test name
Test status
Simulation time 5440860231 ps
CPU time 8.16 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 216168 kb
Host smart-67f49d62-292f-48d7-9151-621506ab8f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50464
7024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.504647024
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3994257366
Short name T2786
Test name
Test status
Simulation time 4996276229 ps
CPU time 144.33 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 224288 kb
Host smart-1b0bef5d-035f-4d3e-9ea5-5a84f1bee941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
57366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3994257366
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2598417320
Short name T568
Test name
Test status
Simulation time 3948318713 ps
CPU time 29.72 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 216072 kb
Host smart-d96917c4-c2fa-4bfc-b829-93a829e22c3f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2598417320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2598417320
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2888668907
Short name T770
Test name
Test status
Simulation time 250037425 ps
CPU time 1.05 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207488 kb
Host smart-527d53ac-f653-4a0d-8207-67b3e0602359
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2888668907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2888668907
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2223457874
Short name T3331
Test name
Test status
Simulation time 182509613 ps
CPU time 0.97 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207632 kb
Host smart-15bdf0cf-1900-496d-ad9b-19663586eeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22234
57874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2223457874
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.855883536
Short name T2760
Test name
Test status
Simulation time 2600918423 ps
CPU time 26.42 seconds
Started Aug 08 06:18:54 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 216052 kb
Host smart-304fc865-4432-4336-ac5a-f5a3cd2b1316
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=855883536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.855883536
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.273102825
Short name T2490
Test name
Test status
Simulation time 157433975 ps
CPU time 0.81 seconds
Started Aug 08 06:19:00 PM PDT 24
Finished Aug 08 06:19:01 PM PDT 24
Peak memory 207564 kb
Host smart-e7f144ff-a2a3-4889-ba58-827318986068
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=273102825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.273102825
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2042398002
Short name T2042
Test name
Test status
Simulation time 182982639 ps
CPU time 0.87 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207656 kb
Host smart-b542cfd8-e18e-4091-ba8e-cfeddd83b7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
98002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2042398002
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.881644116
Short name T145
Test name
Test status
Simulation time 227360717 ps
CPU time 0.98 seconds
Started Aug 08 06:18:55 PM PDT 24
Finished Aug 08 06:18:56 PM PDT 24
Peak memory 207568 kb
Host smart-e31cdbfe-fecd-4dd0-9847-3709ff3f5008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88164
4116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.881644116
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2200456108
Short name T3535
Test name
Test status
Simulation time 181706345 ps
CPU time 0.95 seconds
Started Aug 08 06:18:57 PM PDT 24
Finished Aug 08 06:18:58 PM PDT 24
Peak memory 207508 kb
Host smart-5641d21b-4906-4df2-bbba-db48dffba986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
56108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2200456108
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3266022667
Short name T1461
Test name
Test status
Simulation time 158038883 ps
CPU time 0.81 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207520 kb
Host smart-fd0fc121-4673-4157-ad00-1ca8c6c8d35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32660
22667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3266022667
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1158751848
Short name T837
Test name
Test status
Simulation time 181122692 ps
CPU time 0.83 seconds
Started Aug 08 06:19:11 PM PDT 24
Finished Aug 08 06:19:12 PM PDT 24
Peak memory 207592 kb
Host smart-0c6189fb-1db0-454d-a55b-d68e41f2ed4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
51848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1158751848
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4165308760
Short name T854
Test name
Test status
Simulation time 141859731 ps
CPU time 0.81 seconds
Started Aug 08 06:18:43 PM PDT 24
Finished Aug 08 06:18:44 PM PDT 24
Peak memory 207612 kb
Host smart-da3783c2-af62-44f1-a09a-76bf37ccc053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41653
08760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4165308760
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2999756368
Short name T2571
Test name
Test status
Simulation time 213933919 ps
CPU time 0.95 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207492 kb
Host smart-e7f76c87-57b8-47c5-83f7-71d16768c19e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2999756368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2999756368
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.798718818
Short name T2755
Test name
Test status
Simulation time 163708410 ps
CPU time 0.9 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207568 kb
Host smart-b3344db6-e1e2-48ab-9b4a-9b94d9629d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79871
8818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.798718818
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4275898569
Short name T2072
Test name
Test status
Simulation time 46470496 ps
CPU time 0.69 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207500 kb
Host smart-93ad7b83-e983-494a-935f-cb66d0b999ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
98569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4275898569
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2580475560
Short name T1727
Test name
Test status
Simulation time 12547139669 ps
CPU time 33.17 seconds
Started Aug 08 06:18:52 PM PDT 24
Finished Aug 08 06:19:25 PM PDT 24
Peak memory 220692 kb
Host smart-e4c535d4-609d-438d-bfdb-ca89775e3470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804
75560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2580475560
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.15305953
Short name T3160
Test name
Test status
Simulation time 152026036 ps
CPU time 0.87 seconds
Started Aug 08 06:18:54 PM PDT 24
Finished Aug 08 06:18:55 PM PDT 24
Peak memory 207564 kb
Host smart-4dbab8df-02ad-4ff9-8a92-eb42213b047d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15305
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.15305953
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.918227136
Short name T3372
Test name
Test status
Simulation time 214749234 ps
CPU time 0.96 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:00 PM PDT 24
Peak memory 207540 kb
Host smart-a68b7949-effa-4dc4-a9dc-1e968ae7076d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91822
7136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.918227136
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3501314346
Short name T1161
Test name
Test status
Simulation time 180974947 ps
CPU time 0.98 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:48 PM PDT 24
Peak memory 207600 kb
Host smart-adc27d06-dbd1-4ce3-97ec-4581429f4186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
14346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3501314346
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2481641426
Short name T1165
Test name
Test status
Simulation time 167447550 ps
CPU time 0.85 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207532 kb
Host smart-63f8ca25-b821-46e8-9b82-c7f8b5375b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
41426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2481641426
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1440076870
Short name T2394
Test name
Test status
Simulation time 180713074 ps
CPU time 0.87 seconds
Started Aug 08 06:18:52 PM PDT 24
Finished Aug 08 06:18:53 PM PDT 24
Peak memory 207544 kb
Host smart-10462260-5315-443f-bada-6bf6e55ab5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14400
76870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1440076870
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.508826436
Short name T3403
Test name
Test status
Simulation time 249969795 ps
CPU time 1.16 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207504 kb
Host smart-4265e86f-3668-4b00-8f4f-8fc0f3719f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50882
6436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.508826436
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4047481894
Short name T2236
Test name
Test status
Simulation time 168651693 ps
CPU time 0.9 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207436 kb
Host smart-52cb4309-acc4-44f0-b014-4f699facf88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
81894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4047481894
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.913772349
Short name T1184
Test name
Test status
Simulation time 149083915 ps
CPU time 0.86 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207568 kb
Host smart-3cb24b9e-1622-42d8-a568-2bba617965c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91377
2349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.913772349
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1663901183
Short name T2913
Test name
Test status
Simulation time 229202813 ps
CPU time 1.01 seconds
Started Aug 08 06:18:54 PM PDT 24
Finished Aug 08 06:18:56 PM PDT 24
Peak memory 207508 kb
Host smart-380ef5d3-e8ef-4316-b94f-7e3108ba5010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
01183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1663901183
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1955827729
Short name T1258
Test name
Test status
Simulation time 1690694528 ps
CPU time 49.03 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 217388 kb
Host smart-9b52e545-0772-40bb-94c0-fb8280680771
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1955827729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1955827729
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3622611953
Short name T1719
Test name
Test status
Simulation time 153089676 ps
CPU time 0.85 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207504 kb
Host smart-5d831e7b-4c9c-4dcd-bcb0-1e5cffffcdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
11953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3622611953
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1501058193
Short name T870
Test name
Test status
Simulation time 239836794 ps
CPU time 0.98 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207568 kb
Host smart-91f2f211-c8ad-4f01-a27c-5c727044598f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15010
58193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1501058193
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.915999797
Short name T3620
Test name
Test status
Simulation time 1300060560 ps
CPU time 3.36 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207688 kb
Host smart-10458832-49cd-481c-851f-ccb266dc36cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91599
9797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.915999797
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1793819897
Short name T1855
Test name
Test status
Simulation time 2837925159 ps
CPU time 22.93 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:31 PM PDT 24
Peak memory 217080 kb
Host smart-bf2a9af0-3360-40d3-946c-38a6ad22bdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
19897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1793819897
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.453097028
Short name T2420
Test name
Test status
Simulation time 3827835761 ps
CPU time 34.59 seconds
Started Aug 08 06:18:58 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207852 kb
Host smart-106098c6-6c3c-43ac-8d2f-cb1e90987501
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453097028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host
_handshake.453097028
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.901992518
Short name T2169
Test name
Test status
Simulation time 486737763 ps
CPU time 1.45 seconds
Started Aug 08 06:18:47 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207560 kb
Host smart-201b7914-13c7-43d8-a491-3969cbe69edc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901992518 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.901992518
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.3161553396
Short name T3196
Test name
Test status
Simulation time 459248092 ps
CPU time 1.42 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207616 kb
Host smart-8730cd36-f9af-4269-9b46-857971df3bc9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161553396 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.3161553396
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.1314100818
Short name T2883
Test name
Test status
Simulation time 652123076 ps
CPU time 1.71 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207544 kb
Host smart-3a7bdc86-28b5-4d23-9f4f-6b5137bee41e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314100818 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.1314100818
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.3537132847
Short name T2183
Test name
Test status
Simulation time 612947114 ps
CPU time 1.85 seconds
Started Aug 08 06:22:32 PM PDT 24
Finished Aug 08 06:22:34 PM PDT 24
Peak memory 207544 kb
Host smart-dd6ca2e9-4322-42ac-b6fd-2fa5058a0a54
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537132847 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.3537132847
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.2553639968
Short name T2838
Test name
Test status
Simulation time 668273581 ps
CPU time 1.87 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207620 kb
Host smart-f72fdbf8-e932-4044-87db-d555025e0771
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553639968 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.2553639968
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.2898685590
Short name T956
Test name
Test status
Simulation time 592585450 ps
CPU time 1.62 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207528 kb
Host smart-7d92bc82-eea5-46c2-9afd-1e182205297f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898685590 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.2898685590
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.3844333825
Short name T1292
Test name
Test status
Simulation time 613499788 ps
CPU time 1.71 seconds
Started Aug 08 06:22:45 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207548 kb
Host smart-a513247b-1435-4bb8-bd5a-0e39e9c287eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844333825 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.3844333825
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.2188715211
Short name T174
Test name
Test status
Simulation time 538377965 ps
CPU time 1.47 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207588 kb
Host smart-1d52a26d-37cc-47e2-8c43-0815bc16148e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188715211 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.2188715211
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.4028046075
Short name T3592
Test name
Test status
Simulation time 491624314 ps
CPU time 1.54 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207564 kb
Host smart-70c444e1-f4ce-4c37-aab9-255ec61bb835
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028046075 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.4028046075
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.1496845059
Short name T187
Test name
Test status
Simulation time 446842155 ps
CPU time 1.52 seconds
Started Aug 08 06:22:16 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207544 kb
Host smart-d4901e47-e62d-450d-87dc-4fbad1c8a906
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496845059 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.1496845059
Directory /workspace/348.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.2620774365
Short name T1861
Test name
Test status
Simulation time 489098767 ps
CPU time 1.58 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:22 PM PDT 24
Peak memory 207632 kb
Host smart-7b261e95-aeb9-4207-b657-b6479409ecc6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620774365 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.2620774365
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3344934838
Short name T1100
Test name
Test status
Simulation time 43991779 ps
CPU time 0.69 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207604 kb
Host smart-23580070-c23e-4a3d-b1b3-f672a061c620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3344934838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3344934838
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.439780737
Short name T1703
Test name
Test status
Simulation time 9508034270 ps
CPU time 12.56 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 207840 kb
Host smart-fe05c930-8a3b-4720-8c6e-c6c5085023a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439780737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_disconnect.439780737
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1793120669
Short name T2450
Test name
Test status
Simulation time 18444806631 ps
CPU time 22.64 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 207816 kb
Host smart-4aaf98f6-6ea5-4f87-86ae-2d71dce008fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793120669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1793120669
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1950208155
Short name T1596
Test name
Test status
Simulation time 26230489010 ps
CPU time 32.13 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 216004 kb
Host smart-05c1b983-8ce5-492f-9de2-e08d96236279
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950208155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.1950208155
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1576037930
Short name T3055
Test name
Test status
Simulation time 155577202 ps
CPU time 0.89 seconds
Started Aug 08 06:18:48 PM PDT 24
Finished Aug 08 06:18:49 PM PDT 24
Peak memory 207532 kb
Host smart-62e7525a-800b-414a-b3b4-7b042b29a5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15760
37930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1576037930
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3160575078
Short name T1772
Test name
Test status
Simulation time 173222563 ps
CPU time 0.89 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207508 kb
Host smart-26daa0e5-7ed8-4826-9b54-d2c79cb8fd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
75078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3160575078
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.380956152
Short name T3227
Test name
Test status
Simulation time 439652538 ps
CPU time 1.64 seconds
Started Aug 08 06:18:49 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207580 kb
Host smart-ac917f56-eca7-4f80-95d4-e3666d72e987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
6152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.380956152
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.4166312379
Short name T3272
Test name
Test status
Simulation time 608852463 ps
CPU time 1.73 seconds
Started Aug 08 06:18:53 PM PDT 24
Finished Aug 08 06:18:55 PM PDT 24
Peak memory 207540 kb
Host smart-03eb7f3d-885a-4a00-89f8-182972631ed5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4166312379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.4166312379
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.756225785
Short name T1221
Test name
Test status
Simulation time 36173491039 ps
CPU time 54.25 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207824 kb
Host smart-272d96b6-e210-4cc7-af58-cd8d2014df2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75622
5785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.756225785
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.1823062244
Short name T898
Test name
Test status
Simulation time 353713062 ps
CPU time 4.51 seconds
Started Aug 08 06:18:53 PM PDT 24
Finished Aug 08 06:18:57 PM PDT 24
Peak memory 207736 kb
Host smart-c0e7a511-eb88-4665-9931-07ccf00a12cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823062244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1823062244
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2151784798
Short name T3461
Test name
Test status
Simulation time 462940824 ps
CPU time 1.47 seconds
Started Aug 08 06:18:50 PM PDT 24
Finished Aug 08 06:18:51 PM PDT 24
Peak memory 207504 kb
Host smart-a04c7f84-cf15-427a-a5e6-99b1eb79c896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21517
84798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2151784798
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2666482226
Short name T3154
Test name
Test status
Simulation time 154559494 ps
CPU time 0.84 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207508 kb
Host smart-dee2de01-439b-4c47-8802-b24279ad9e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664
82226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2666482226
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1444529181
Short name T2800
Test name
Test status
Simulation time 111512327 ps
CPU time 0.76 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207504 kb
Host smart-7c287992-3b7b-4230-95d6-110880c0c44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
29181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1444529181
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2638355585
Short name T860
Test name
Test status
Simulation time 871557470 ps
CPU time 2.47 seconds
Started Aug 08 06:18:56 PM PDT 24
Finished Aug 08 06:18:59 PM PDT 24
Peak memory 207968 kb
Host smart-d21c1403-545c-4efd-bd49-2e33e12b06a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
55585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2638355585
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.2835716447
Short name T455
Test name
Test status
Simulation time 178939874 ps
CPU time 0.96 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207516 kb
Host smart-7c119dd8-cdfb-46e5-894f-9f4d1e0c2e48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2835716447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.2835716447
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1856540989
Short name T1683
Test name
Test status
Simulation time 211223708 ps
CPU time 1.43 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:03 PM PDT 24
Peak memory 207700 kb
Host smart-67141248-9e01-4194-8b02-9ae3ba658986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
40989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1856540989
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3325910603
Short name T2476
Test name
Test status
Simulation time 161687385 ps
CPU time 0.88 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:02 PM PDT 24
Peak memory 207552 kb
Host smart-4c07e8d4-b7f8-4f8e-ba16-57a793f6985d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3325910603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3325910603
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1490825592
Short name T1989
Test name
Test status
Simulation time 144085431 ps
CPU time 0.79 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:00 PM PDT 24
Peak memory 207528 kb
Host smart-d23e0bc3-fdca-4bfa-8c38-374042a0fa4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14908
25592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1490825592
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1469726871
Short name T3042
Test name
Test status
Simulation time 242884464 ps
CPU time 1.08 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:02 PM PDT 24
Peak memory 207552 kb
Host smart-4c8ca984-d28f-4285-91db-6e463a7bb5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697
26871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1469726871
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3530659249
Short name T1019
Test name
Test status
Simulation time 5538772384 ps
CPU time 44.23 seconds
Started Aug 08 06:19:00 PM PDT 24
Finished Aug 08 06:19:44 PM PDT 24
Peak memory 224248 kb
Host smart-6b7430fd-ffa0-421e-a72a-1ec9ff520880
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3530659249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3530659249
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.104143746
Short name T297
Test name
Test status
Simulation time 10570485217 ps
CPU time 74.49 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:20:17 PM PDT 24
Peak memory 207780 kb
Host smart-6ea53866-5d46-4493-95bc-04966040d458
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=104143746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.104143746
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1297396696
Short name T2994
Test name
Test status
Simulation time 292676594 ps
CPU time 1.06 seconds
Started Aug 08 06:19:05 PM PDT 24
Finished Aug 08 06:19:06 PM PDT 24
Peak memory 207464 kb
Host smart-262ea068-ba5d-4c17-9989-f6b7b06d3253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12973
96696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1297396696
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1996323320
Short name T1353
Test name
Test status
Simulation time 4791393187 ps
CPU time 7.89 seconds
Started Aug 08 06:19:05 PM PDT 24
Finished Aug 08 06:19:13 PM PDT 24
Peak memory 216592 kb
Host smart-008b4529-33cf-4f84-8264-adce8455bf35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1996323320
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2235425753
Short name T1116
Test name
Test status
Simulation time 10058637838 ps
CPU time 13.52 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207880 kb
Host smart-209c6e47-3a86-46f5-a0bc-94281e935554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22354
25753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2235425753
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.674224344
Short name T723
Test name
Test status
Simulation time 3386394991 ps
CPU time 24.46 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:27 PM PDT 24
Peak memory 224336 kb
Host smart-8589d0d1-d8ff-4120-921a-e08e1dde0287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67422
4344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.674224344
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1339458177
Short name T2614
Test name
Test status
Simulation time 3192036566 ps
CPU time 90.15 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 215988 kb
Host smart-3ca90ac2-9ae4-4d6c-b7ff-bee2be18a7ad
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1339458177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1339458177
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.530983860
Short name T3510
Test name
Test status
Simulation time 247711906 ps
CPU time 1.01 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207544 kb
Host smart-24a72b9a-6184-42ab-bcda-02d28f3e826e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=530983860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.530983860
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2482810936
Short name T2686
Test name
Test status
Simulation time 194364914 ps
CPU time 0.89 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:00 PM PDT 24
Peak memory 207472 kb
Host smart-9afb3fc6-692c-4904-9711-b731fcb7c1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
10936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2482810936
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3676431499
Short name T2741
Test name
Test status
Simulation time 3104558341 ps
CPU time 84.95 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 217552 kb
Host smart-ac73f88e-ef3f-44fd-8097-5bedd387dd46
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3676431499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3676431499
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.644223273
Short name T3602
Test name
Test status
Simulation time 151946114 ps
CPU time 0.83 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207556 kb
Host smart-17c9d6fd-4aa7-4288-8ce7-43e58f920a79
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=644223273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.644223273
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.679119257
Short name T1305
Test name
Test status
Simulation time 146148471 ps
CPU time 0.88 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207584 kb
Host smart-6965c3cb-9eea-43ad-a352-65b7dbfbed67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67911
9257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.679119257
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.976828267
Short name T90
Test name
Test status
Simulation time 237267551 ps
CPU time 0.99 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207620 kb
Host smart-dad22a5d-850c-428a-b3a4-91e035101240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97682
8267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.976828267
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2412784483
Short name T1403
Test name
Test status
Simulation time 243616464 ps
CPU time 0.96 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207788 kb
Host smart-3fc84856-055d-4c94-986d-af0dbfd52913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
84483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2412784483
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3284007711
Short name T907
Test name
Test status
Simulation time 193119463 ps
CPU time 0.89 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207616 kb
Host smart-0b69d96e-b9c1-42d4-99a6-84b0816a60c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
07711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3284007711
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.319837462
Short name T1376
Test name
Test status
Simulation time 172155029 ps
CPU time 0.88 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207560 kb
Host smart-1d43c19f-8f15-459d-b609-4a06c0e64297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
7462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.319837462
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2649530933
Short name T616
Test name
Test status
Simulation time 211101650 ps
CPU time 0.98 seconds
Started Aug 08 06:19:13 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 207568 kb
Host smart-cdd67665-bddf-477c-b558-a3b5996153a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2649530933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2649530933
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1526043763
Short name T2305
Test name
Test status
Simulation time 202799938 ps
CPU time 0.86 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207540 kb
Host smart-52ddc120-7444-4e86-abef-1a3ddccce72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15260
43763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1526043763
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3173901622
Short name T1957
Test name
Test status
Simulation time 38941582 ps
CPU time 0.7 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207132 kb
Host smart-4baacd67-b5c3-40eb-96ae-6916089fb817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31739
01622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3173901622
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3404031144
Short name T948
Test name
Test status
Simulation time 17279668511 ps
CPU time 47.69 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 216000 kb
Host smart-26561c69-0b23-419d-ba4b-1c484cdf1540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34040
31144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3404031144
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1137998827
Short name T742
Test name
Test status
Simulation time 168613229 ps
CPU time 0.89 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207576 kb
Host smart-cb9e0aca-7ef9-4902-ba2b-3f2a6bd15f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
98827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1137998827
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.143248474
Short name T1988
Test name
Test status
Simulation time 249482082 ps
CPU time 1.02 seconds
Started Aug 08 06:19:14 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207544 kb
Host smart-6524be87-a2bc-4f68-a3f5-a94abf45c6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
8474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.143248474
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3786551726
Short name T2778
Test name
Test status
Simulation time 186492453 ps
CPU time 0.88 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207480 kb
Host smart-7c5f0b21-8654-463a-9a3e-5a9892f18011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37865
51726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3786551726
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3325998493
Short name T2252
Test name
Test status
Simulation time 191296848 ps
CPU time 0.98 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207568 kb
Host smart-a3856e3e-1dc8-495c-b646-7f5a79105cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
98493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3325998493
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3414297528
Short name T2138
Test name
Test status
Simulation time 177083315 ps
CPU time 0.87 seconds
Started Aug 08 06:19:20 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 207544 kb
Host smart-c7de2396-a4aa-4651-8158-83e3d52c954b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
97528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3414297528
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.2419283970
Short name T1361
Test name
Test status
Simulation time 432710972 ps
CPU time 1.48 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207484 kb
Host smart-f94bf37c-e855-412d-a1a3-f710e489056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192
83970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2419283970
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2282149842
Short name T991
Test name
Test status
Simulation time 185587691 ps
CPU time 0.85 seconds
Started Aug 08 06:19:11 PM PDT 24
Finished Aug 08 06:19:12 PM PDT 24
Peak memory 207528 kb
Host smart-a2a58300-aaae-4aad-a1ad-10840e77df3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22821
49842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2282149842
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.134940497
Short name T1479
Test name
Test status
Simulation time 167596045 ps
CPU time 0.88 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207544 kb
Host smart-c448c6dc-67f1-4a17-bc85-d86469126217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13494
0497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.134940497
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1283305366
Short name T2259
Test name
Test status
Simulation time 213301637 ps
CPU time 1.06 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207588 kb
Host smart-e84f4848-87b1-4a45-a582-a76044cf542c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
05366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1283305366
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1944242283
Short name T2515
Test name
Test status
Simulation time 2755054014 ps
CPU time 21.03 seconds
Started Aug 08 06:19:05 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 216080 kb
Host smart-f2f52fa8-6927-4857-8f91-5a83e86f80e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1944242283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1944242283
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3228936225
Short name T1621
Test name
Test status
Simulation time 167310553 ps
CPU time 0.84 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207568 kb
Host smart-cd00041d-2fa4-437c-857a-7689d953cc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
36225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3228936225
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1548337265
Short name T3385
Test name
Test status
Simulation time 222243454 ps
CPU time 0.96 seconds
Started Aug 08 06:19:19 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 207544 kb
Host smart-6b2581aa-e20a-4e7f-919c-8f9cab161241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
37265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1548337265
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1728971425
Short name T1759
Test name
Test status
Simulation time 505748543 ps
CPU time 1.47 seconds
Started Aug 08 06:19:12 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 207480 kb
Host smart-b74312ca-940c-4bf0-8cab-100759a8de19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
71425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1728971425
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.4293713119
Short name T2269
Test name
Test status
Simulation time 2656981205 ps
CPU time 25.73 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 217896 kb
Host smart-f66119bc-dede-43b9-81f3-c32bf41ab163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42937
13119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.4293713119
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.1172288962
Short name T682
Test name
Test status
Simulation time 594692783 ps
CPU time 5.04 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207720 kb
Host smart-5d46405e-f12e-47a5-89c5-2c14973909ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172288962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.1172288962
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.2362371147
Short name T834
Test name
Test status
Simulation time 670106308 ps
CPU time 1.72 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207584 kb
Host smart-848a5492-e0d9-46a6-ba9b-6d2c309986b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362371147 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.2362371147
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.152419136
Short name T798
Test name
Test status
Simulation time 492409923 ps
CPU time 1.4 seconds
Started Aug 08 06:22:22 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 207528 kb
Host smart-afb36087-4249-4ffc-884b-af986258447b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152419136 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.152419136
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.4237871266
Short name T842
Test name
Test status
Simulation time 673983593 ps
CPU time 1.88 seconds
Started Aug 08 06:22:31 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207596 kb
Host smart-a44f9e7f-30f9-4132-9fd4-9de5153c905d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237871266 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.4237871266
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.627704911
Short name T856
Test name
Test status
Simulation time 482641353 ps
CPU time 1.53 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207516 kb
Host smart-4189934f-7871-4578-a14c-779c2bd22272
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627704911 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.627704911
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.3291394725
Short name T1563
Test name
Test status
Simulation time 524256396 ps
CPU time 1.52 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207616 kb
Host smart-5e165cf1-5eaa-4928-8ec4-79d98981c865
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291394725 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.3291394725
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.2898763052
Short name T2860
Test name
Test status
Simulation time 652667008 ps
CPU time 1.68 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:22 PM PDT 24
Peak memory 207628 kb
Host smart-c9643d53-c332-47d7-b978-088361948f74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898763052 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.2898763052
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.2998183070
Short name T895
Test name
Test status
Simulation time 478633466 ps
CPU time 1.65 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207500 kb
Host smart-dcd92799-a986-4b34-9b02-db4fe14f4aec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998183070 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.2998183070
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.3321613946
Short name T93
Test name
Test status
Simulation time 479025549 ps
CPU time 1.48 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207496 kb
Host smart-3c2c141a-5283-421d-8f7e-c4029a6a7187
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321613946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.3321613946
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.4053156714
Short name T1097
Test name
Test status
Simulation time 590121731 ps
CPU time 1.64 seconds
Started Aug 08 06:22:31 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207540 kb
Host smart-d677aea4-201e-47e3-afde-9086ff6d3011
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053156714 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.4053156714
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.264649469
Short name T1576
Test name
Test status
Simulation time 510753057 ps
CPU time 1.56 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:22 PM PDT 24
Peak memory 207636 kb
Host smart-93717bbf-9f39-4700-9475-9511f3b1fbe3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264649469 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.264649469
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.996774679
Short name T2646
Test name
Test status
Simulation time 455429347 ps
CPU time 1.51 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207636 kb
Host smart-0d4a4820-6462-46d2-95ec-abca3433641d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996774679 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.996774679
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.715913381
Short name T1468
Test name
Test status
Simulation time 33940642 ps
CPU time 0.65 seconds
Started Aug 08 06:19:13 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 207552 kb
Host smart-122e2245-8c86-4b28-81ba-5336f72de6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=715913381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.715913381
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2124355529
Short name T887
Test name
Test status
Simulation time 19371130141 ps
CPU time 25.46 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207760 kb
Host smart-a33661c0-77e6-4227-9ed2-80dd4d3ddfdd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124355529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2124355529
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.992215317
Short name T505
Test name
Test status
Simulation time 30359668818 ps
CPU time 34.91 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207796 kb
Host smart-20600d5d-f8f1-4e9e-b31b-8599e5c98ae3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992215317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_resume.992215317
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1786794563
Short name T1816
Test name
Test status
Simulation time 195851837 ps
CPU time 0.99 seconds
Started Aug 08 06:19:14 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207540 kb
Host smart-64aa7b37-6ee5-449a-9cd1-738704068396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
94563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1786794563
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4091620673
Short name T2962
Test name
Test status
Simulation time 141448826 ps
CPU time 0.81 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207472 kb
Host smart-ca96401c-70d3-4011-b5e0-2305d7e69b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40916
20673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4091620673
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2134862482
Short name T3418
Test name
Test status
Simulation time 338183367 ps
CPU time 1.32 seconds
Started Aug 08 06:19:20 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 207788 kb
Host smart-c56a4384-0ce2-4007-88ca-a2fce92af25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
62482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2134862482
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.139936378
Short name T2918
Test name
Test status
Simulation time 1276308267 ps
CPU time 3.28 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207784 kb
Host smart-40560f3a-1968-420a-b3db-9e5c3862cb74
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=139936378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.139936378
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.892414982
Short name T117
Test name
Test status
Simulation time 42777803239 ps
CPU time 66.94 seconds
Started Aug 08 06:19:12 PM PDT 24
Finished Aug 08 06:20:19 PM PDT 24
Peak memory 207852 kb
Host smart-4aeff679-7a31-4631-bbd9-e6c27f150934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89241
4982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.892414982
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.3331012375
Short name T1735
Test name
Test status
Simulation time 706237271 ps
CPU time 15.17 seconds
Started Aug 08 06:19:25 PM PDT 24
Finished Aug 08 06:19:40 PM PDT 24
Peak memory 207732 kb
Host smart-10a40b03-3a90-4c1a-a9ab-acf1c774445a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331012375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.3331012375
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1719669487
Short name T1099
Test name
Test status
Simulation time 1197658958 ps
CPU time 2.88 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207516 kb
Host smart-c56bbc9e-cc21-44fb-b9c4-a55b87964df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
69487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1719669487
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.527121281
Short name T1955
Test name
Test status
Simulation time 152450578 ps
CPU time 0.81 seconds
Started Aug 08 06:19:21 PM PDT 24
Finished Aug 08 06:19:22 PM PDT 24
Peak memory 207548 kb
Host smart-942e70e4-ac98-4c89-9f88-96e5739fe2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52712
1281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.527121281
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.565229695
Short name T1920
Test name
Test status
Simulation time 32117249 ps
CPU time 0.69 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207180 kb
Host smart-746cfdf7-7421-4f40-9030-d227bd209c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56522
9695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.565229695
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3101663746
Short name T2861
Test name
Test status
Simulation time 912437887 ps
CPU time 2.28 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207832 kb
Host smart-0a57cb45-c605-4a36-a09b-887c8e60599f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31016
63746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3101663746
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.634939849
Short name T390
Test name
Test status
Simulation time 557273997 ps
CPU time 1.55 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:12 PM PDT 24
Peak memory 207540 kb
Host smart-5487cb63-cc4c-490b-b396-03585f05a865
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=634939849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.634939849
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3108790964
Short name T3465
Test name
Test status
Simulation time 166143341 ps
CPU time 1.69 seconds
Started Aug 08 06:19:23 PM PDT 24
Finished Aug 08 06:19:25 PM PDT 24
Peak memory 207756 kb
Host smart-c89486c5-7d43-42c0-a592-5c12361aea30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31087
90964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3108790964
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2540422740
Short name T588
Test name
Test status
Simulation time 213405952 ps
CPU time 1.09 seconds
Started Aug 08 06:19:09 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 216984 kb
Host smart-41001385-558a-4ecc-a46d-4eaa3f00db32
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2540422740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2540422740
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.870835956
Short name T1470
Test name
Test status
Simulation time 156192408 ps
CPU time 0.86 seconds
Started Aug 08 06:19:19 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 207584 kb
Host smart-798592d6-4973-425d-a564-203869deca02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87083
5956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.870835956
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2818884186
Short name T718
Test name
Test status
Simulation time 192658083 ps
CPU time 0.89 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207556 kb
Host smart-38c4016f-37b2-4f33-b79b-5672538e5474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
84186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2818884186
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.4076181953
Short name T633
Test name
Test status
Simulation time 2817962177 ps
CPU time 81.04 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 224240 kb
Host smart-3a91f84f-015e-433c-8f8b-4bd510f18545
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4076181953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4076181953
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.3362067332
Short name T2700
Test name
Test status
Simulation time 4263231043 ps
CPU time 47.38 seconds
Started Aug 08 06:19:01 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 207788 kb
Host smart-ed5e63e8-44c3-494b-9281-8f54fdb43915
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3362067332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.3362067332
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.846641266
Short name T2374
Test name
Test status
Simulation time 225852152 ps
CPU time 0.98 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:05 PM PDT 24
Peak memory 207628 kb
Host smart-7ae77cff-75e4-4391-b368-3cbf3ac3336a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84664
1266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.846641266
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3047218695
Short name T672
Test name
Test status
Simulation time 8133234051 ps
CPU time 11.33 seconds
Started Aug 08 06:18:59 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 216140 kb
Host smart-ad8d570b-957e-4370-998e-5a07d580686c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30472
18695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3047218695
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1152123553
Short name T2457
Test name
Test status
Simulation time 8389276904 ps
CPU time 11.24 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:13 PM PDT 24
Peak memory 207836 kb
Host smart-7e6edcb9-4fa7-4c9b-86c0-6c4c2f673d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11521
23553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1152123553
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.499950747
Short name T2278
Test name
Test status
Simulation time 4932779442 ps
CPU time 37.39 seconds
Started Aug 08 06:19:11 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 224196 kb
Host smart-4d0b7f44-7552-407b-8867-b0bd028c3cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49995
0747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.499950747
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.977589605
Short name T750
Test name
Test status
Simulation time 1767677538 ps
CPU time 50.46 seconds
Started Aug 08 06:19:05 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 217308 kb
Host smart-ba262ee1-5a56-42e7-93f8-4baffcd0970e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=977589605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.977589605
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3122874822
Short name T762
Test name
Test status
Simulation time 245463221 ps
CPU time 1.01 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:19 PM PDT 24
Peak memory 207540 kb
Host smart-44553b70-2d58-442a-addc-55331d33b85c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3122874822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3122874822
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2874584211
Short name T2454
Test name
Test status
Simulation time 197262947 ps
CPU time 0.96 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207572 kb
Host smart-48868428-16d6-4798-afbd-f02906055f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
84211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2874584211
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.2150810677
Short name T640
Test name
Test status
Simulation time 2791781449 ps
CPU time 81.02 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 217792 kb
Host smart-4ddca804-8808-426e-9dd4-e9037d8387cb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2150810677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.2150810677
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3696821419
Short name T2414
Test name
Test status
Simulation time 176224258 ps
CPU time 0.92 seconds
Started Aug 08 06:19:03 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207544 kb
Host smart-8017f7d8-b403-41e0-b9a8-966ec89c4d75
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3696821419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3696821419
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4227330588
Short name T3071
Test name
Test status
Simulation time 211553318 ps
CPU time 0.89 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207516 kb
Host smart-56309ed7-fe20-4279-9e01-785e263bd09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
30588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4227330588
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.12321332
Short name T159
Test name
Test status
Simulation time 279273269 ps
CPU time 1.06 seconds
Started Aug 08 06:19:09 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 207536 kb
Host smart-6a4f178f-85c1-4c84-9307-dd0af33d3d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.12321332
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3368965390
Short name T3344
Test name
Test status
Simulation time 180398017 ps
CPU time 0.92 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:09 PM PDT 24
Peak memory 207464 kb
Host smart-a73aeddb-3def-4178-adc7-e898c6442bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
65390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3368965390
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3793214587
Short name T3362
Test name
Test status
Simulation time 162292906 ps
CPU time 0.86 seconds
Started Aug 08 06:19:05 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207644 kb
Host smart-ac4b8750-30b3-4df7-b81e-43e6124de019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932
14587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3793214587
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2345139528
Short name T1421
Test name
Test status
Simulation time 158755063 ps
CPU time 0.87 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207508 kb
Host smart-9f711a06-b926-4b86-ad7e-f4f7b5790916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
39528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2345139528
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2197834929
Short name T3349
Test name
Test status
Simulation time 184681583 ps
CPU time 0.88 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207504 kb
Host smart-b42ee674-47ad-4296-95aa-9af3b2dd1f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
34929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2197834929
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.446574511
Short name T2937
Test name
Test status
Simulation time 203733142 ps
CPU time 1.04 seconds
Started Aug 08 06:19:09 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 207584 kb
Host smart-3a53082f-f93d-4818-8842-b1e7c77e7b34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=446574511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.446574511
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2665894352
Short name T2716
Test name
Test status
Simulation time 150643186 ps
CPU time 0.85 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207444 kb
Host smart-516f3e57-9d44-41ef-8483-c55558cfa05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
94352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2665894352
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.590223822
Short name T3012
Test name
Test status
Simulation time 49964200 ps
CPU time 0.72 seconds
Started Aug 08 06:19:20 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 207524 kb
Host smart-2fb422e1-c130-4f42-9f16-01b8b423882a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59022
3822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.590223822
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1499147405
Short name T2632
Test name
Test status
Simulation time 20454074247 ps
CPU time 48.78 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 216180 kb
Host smart-9fdffed4-f3d8-4268-8e95-70b962fd5878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991
47405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1499147405
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1992408846
Short name T670
Test name
Test status
Simulation time 184433843 ps
CPU time 0.91 seconds
Started Aug 08 06:19:30 PM PDT 24
Finished Aug 08 06:19:31 PM PDT 24
Peak memory 207560 kb
Host smart-ae45d554-1b4a-4e85-9708-0874ee6d6d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
08846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1992408846
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.989104509
Short name T866
Test name
Test status
Simulation time 166296809 ps
CPU time 0.9 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207544 kb
Host smart-96416fa6-9a31-4ca7-9d1f-e3bf4eed831a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98910
4509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.989104509
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.459488390
Short name T599
Test name
Test status
Simulation time 163781613 ps
CPU time 0.89 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207564 kb
Host smart-78b73810-8282-4c4f-bc82-62de1bf2a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45948
8390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.459488390
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4294579914
Short name T1369
Test name
Test status
Simulation time 216777161 ps
CPU time 0.92 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207532 kb
Host smart-a20b356a-f4d2-4e6a-b39a-00fb1f311adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42945
79914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4294579914
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.897661952
Short name T3314
Test name
Test status
Simulation time 152927899 ps
CPU time 0.89 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207528 kb
Host smart-2846a4a2-9aab-44a7-b331-d9fbcb6b06e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89766
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.897661952
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.803839524
Short name T1915
Test name
Test status
Simulation time 471081440 ps
CPU time 1.5 seconds
Started Aug 08 06:19:12 PM PDT 24
Finished Aug 08 06:19:14 PM PDT 24
Peak memory 207540 kb
Host smart-134c1c24-0d39-48ac-9b89-1fba82ba232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80383
9524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.803839524
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3800792890
Short name T1709
Test name
Test status
Simulation time 169774951 ps
CPU time 0.89 seconds
Started Aug 08 06:19:14 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207512 kb
Host smart-ee8f391c-538e-409d-8252-cb157f78bb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007
92890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3800792890
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1802587328
Short name T1257
Test name
Test status
Simulation time 147603730 ps
CPU time 0.82 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:07 PM PDT 24
Peak memory 207536 kb
Host smart-f02705e4-0623-4810-8781-db24b5015ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
87328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1802587328
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1952540935
Short name T929
Test name
Test status
Simulation time 197103415 ps
CPU time 0.94 seconds
Started Aug 08 06:19:02 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 207532 kb
Host smart-b42ec34d-a179-4848-b7ce-1599b1ed443b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525
40935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1952540935
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.376542553
Short name T513
Test name
Test status
Simulation time 2209987723 ps
CPU time 17.62 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 216136 kb
Host smart-b090cdfd-d6c5-4ff5-aa7e-8189d329ef9c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=376542553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.376542553
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2325001374
Short name T489
Test name
Test status
Simulation time 153208320 ps
CPU time 0.83 seconds
Started Aug 08 06:19:04 PM PDT 24
Finished Aug 08 06:19:04 PM PDT 24
Peak memory 207568 kb
Host smart-ce6754c5-6ef6-4e2b-b2a2-4038c705a5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23250
01374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2325001374
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.919417401
Short name T2276
Test name
Test status
Simulation time 181969127 ps
CPU time 0.91 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207588 kb
Host smart-6a31fa36-7653-4938-b676-9ba795ca4004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91941
7401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.919417401
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2655462185
Short name T1203
Test name
Test status
Simulation time 1016745588 ps
CPU time 2.65 seconds
Started Aug 08 06:19:07 PM PDT 24
Finished Aug 08 06:19:10 PM PDT 24
Peak memory 207744 kb
Host smart-eec2eeff-838a-46de-b077-1ec93df2cc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554
62185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2655462185
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1031298956
Short name T2229
Test name
Test status
Simulation time 2715819749 ps
CPU time 20.18 seconds
Started Aug 08 06:19:06 PM PDT 24
Finished Aug 08 06:19:27 PM PDT 24
Peak memory 217836 kb
Host smart-8c728e67-e0f2-48bc-b340-6c44a53aa7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10312
98956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1031298956
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.772620295
Short name T2798
Test name
Test status
Simulation time 2511972155 ps
CPU time 17.19 seconds
Started Aug 08 06:19:08 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 207828 kb
Host smart-e44ee1e5-c178-4dee-8736-5e181ac18266
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772620295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_host
_handshake.772620295
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.1474771267
Short name T123
Test name
Test status
Simulation time 620424717 ps
CPU time 1.77 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207608 kb
Host smart-ffb757ca-1573-4ac0-8c54-b6c0fe9f059a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474771267 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.1474771267
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.1743817326
Short name T3231
Test name
Test status
Simulation time 488794403 ps
CPU time 1.6 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207632 kb
Host smart-9a782a29-a3ce-4222-9641-2673ebfe5f8b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743817326 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.1743817326
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.543454163
Short name T1669
Test name
Test status
Simulation time 466205156 ps
CPU time 1.46 seconds
Started Aug 08 06:22:29 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207564 kb
Host smart-38c482d4-5b95-4351-9e24-f25926219af5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543454163 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.543454163
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.342508613
Short name T941
Test name
Test status
Simulation time 634540963 ps
CPU time 1.69 seconds
Started Aug 08 06:22:22 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 207632 kb
Host smart-7ffcdf07-d5af-4eea-bb46-b521b391e4c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342508613 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.342508613
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.3865579813
Short name T3631
Test name
Test status
Simulation time 512733076 ps
CPU time 1.52 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:21 PM PDT 24
Peak memory 207564 kb
Host smart-3ab8e8da-430d-442a-bdf5-d68610f4f146
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865579813 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.3865579813
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.2430470996
Short name T202
Test name
Test status
Simulation time 490881925 ps
CPU time 1.54 seconds
Started Aug 08 06:22:29 PM PDT 24
Finished Aug 08 06:22:31 PM PDT 24
Peak memory 207592 kb
Host smart-c184f4b9-476d-487c-87b1-8c10260118a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430470996 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.2430470996
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.2473344110
Short name T2415
Test name
Test status
Simulation time 562338965 ps
CPU time 1.67 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207500 kb
Host smart-4d54bde4-63e7-4ad9-b0cf-f1a9e43c60f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473344110 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.2473344110
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.2072580840
Short name T1407
Test name
Test status
Simulation time 608617361 ps
CPU time 1.7 seconds
Started Aug 08 06:22:19 PM PDT 24
Finished Aug 08 06:22:21 PM PDT 24
Peak memory 207544 kb
Host smart-d7d85c76-2936-4017-8e1a-e00b6c4b2e60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072580840 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.2072580840
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.1191670423
Short name T2099
Test name
Test status
Simulation time 491163163 ps
CPU time 1.43 seconds
Started Aug 08 06:22:17 PM PDT 24
Finished Aug 08 06:22:19 PM PDT 24
Peak memory 207540 kb
Host smart-ac7a6e94-7372-42e4-91b2-dcb51ca1c86d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191670423 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.1191670423
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.595986468
Short name T3479
Test name
Test status
Simulation time 494308925 ps
CPU time 1.55 seconds
Started Aug 08 06:22:17 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207544 kb
Host smart-df47539e-589e-4a30-9e02-b8c3a6ed7f2b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595986468 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.595986468
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.363879153
Short name T1580
Test name
Test status
Simulation time 456185729 ps
CPU time 1.41 seconds
Started Aug 08 06:22:17 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207564 kb
Host smart-6b340aeb-458f-4400-845f-1014b0ce60f4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363879153 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.363879153
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.1318988095
Short name T1046
Test name
Test status
Simulation time 60623875 ps
CPU time 0.67 seconds
Started Aug 08 06:19:12 PM PDT 24
Finished Aug 08 06:19:13 PM PDT 24
Peak memory 207560 kb
Host smart-072a28a1-8fe2-4195-934d-9eee490072ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1318988095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.1318988095
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3328270158
Short name T1538
Test name
Test status
Simulation time 3517806629 ps
CPU time 5.93 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 216040 kb
Host smart-89f9fa3c-de65-4184-b6b5-ab13a3a0445c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328270158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.3328270158
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2459572010
Short name T2048
Test name
Test status
Simulation time 18568038279 ps
CPU time 21.55 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:19:51 PM PDT 24
Peak memory 207896 kb
Host smart-ffa1c294-1b29-42c7-91a7-fd6e4300040f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459572010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2459572010
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2818814767
Short name T2095
Test name
Test status
Simulation time 25160918030 ps
CPU time 34.31 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 216040 kb
Host smart-c4181df9-088b-4588-b2fb-9673613a89b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818814767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2818814767
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.525626684
Short name T1656
Test name
Test status
Simulation time 231515141 ps
CPU time 0.99 seconds
Started Aug 08 06:19:14 PM PDT 24
Finished Aug 08 06:19:15 PM PDT 24
Peak memory 207576 kb
Host smart-a4317c73-c3fc-468b-ab82-a892e78e972a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52562
6684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.525626684
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3122446519
Short name T3454
Test name
Test status
Simulation time 150382309 ps
CPU time 0.87 seconds
Started Aug 08 06:19:24 PM PDT 24
Finished Aug 08 06:19:25 PM PDT 24
Peak memory 207504 kb
Host smart-3da3d62c-5107-49ec-915a-4cbd9467d8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
46519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3122446519
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.170167026
Short name T1960
Test name
Test status
Simulation time 322052724 ps
CPU time 1.29 seconds
Started Aug 08 06:19:30 PM PDT 24
Finished Aug 08 06:19:32 PM PDT 24
Peak memory 207596 kb
Host smart-a952b097-2ffa-484d-8516-8c1eaa0cb2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17016
7026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.170167026
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3396390890
Short name T2367
Test name
Test status
Simulation time 948328383 ps
CPU time 2.55 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207768 kb
Host smart-568a6fef-e43c-4730-bfe2-53989ac77bfb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3396390890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3396390890
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.4224601359
Short name T3585
Test name
Test status
Simulation time 23673653073 ps
CPU time 41.94 seconds
Started Aug 08 06:19:24 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207860 kb
Host smart-2f938814-5169-436d-a14c-71f9366c15c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
01359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.4224601359
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.408148944
Short name T1840
Test name
Test status
Simulation time 7016405067 ps
CPU time 44.5 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207916 kb
Host smart-7efa2b5b-615b-4787-af9c-df7d1fc93f76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408148944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.408148944
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.4235600673
Short name T1112
Test name
Test status
Simulation time 662229866 ps
CPU time 1.85 seconds
Started Aug 08 06:19:31 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207440 kb
Host smart-1844e01d-1932-4f8e-9b62-7e30307791e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42356
00673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.4235600673
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2293298938
Short name T1373
Test name
Test status
Simulation time 160524705 ps
CPU time 0.82 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207528 kb
Host smart-2355c0f4-ad39-4e65-9f4d-387bf199cd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932
98938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2293298938
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3637420387
Short name T2058
Test name
Test status
Simulation time 44001766 ps
CPU time 0.78 seconds
Started Aug 08 06:19:21 PM PDT 24
Finished Aug 08 06:19:22 PM PDT 24
Peak memory 207748 kb
Host smart-60b4f7e3-51d7-4fe1-8962-371db63abd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
20387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3637420387
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3097927320
Short name T1999
Test name
Test status
Simulation time 857674721 ps
CPU time 2.51 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207692 kb
Host smart-baecbf65-4cdf-4209-b80c-da8ffa90b900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
27320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3097927320
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.784856557
Short name T439
Test name
Test status
Simulation time 585620387 ps
CPU time 1.6 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:19:31 PM PDT 24
Peak memory 207584 kb
Host smart-29872608-5f62-48ab-b033-35e211894ca3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=784856557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.784856557
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3849489110
Short name T2725
Test name
Test status
Simulation time 422979940 ps
CPU time 2.74 seconds
Started Aug 08 06:19:17 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 207716 kb
Host smart-1ef58f60-efa3-40c3-bcc3-7e1bb01a756f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
89110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3849489110
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3320024727
Short name T2547
Test name
Test status
Simulation time 272801036 ps
CPU time 1.41 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:19:27 PM PDT 24
Peak memory 215944 kb
Host smart-1d9c0cda-934b-4f1d-8bdf-579d5b26e98c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3320024727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3320024727
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2104500113
Short name T1839
Test name
Test status
Simulation time 168406905 ps
CPU time 0.83 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 207508 kb
Host smart-836f25e3-8821-47b2-a170-f2d3bfc466d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
00113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2104500113
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2907471029
Short name T1980
Test name
Test status
Simulation time 213996696 ps
CPU time 0.96 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207604 kb
Host smart-af75698b-dcfe-4f0a-8075-84e3089a7286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
71029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2907471029
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1420363275
Short name T1872
Test name
Test status
Simulation time 4714560330 ps
CPU time 36.98 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 224180 kb
Host smart-e46e9064-8303-460b-996f-bad598f9f18b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1420363275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1420363275
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.3992437114
Short name T100
Test name
Test status
Simulation time 13058869834 ps
CPU time 82.61 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207844 kb
Host smart-bf1ff364-f2e6-4641-8c3b-23fdc5eab6c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3992437114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3992437114
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3036722753
Short name T3016
Test name
Test status
Simulation time 239189747 ps
CPU time 1.06 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:19:28 PM PDT 24
Peak memory 207560 kb
Host smart-9ee2e6e3-8bea-42ef-8deb-202ff5514140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
22753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3036722753
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3940199468
Short name T3168
Test name
Test status
Simulation time 30903251049 ps
CPU time 47.8 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 207896 kb
Host smart-a2d264c7-de5b-42d7-b882-f8412fb0b1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401
99468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3940199468
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3534493536
Short name T1280
Test name
Test status
Simulation time 11280507456 ps
CPU time 14.65 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207836 kb
Host smart-144edc2b-3324-49fe-bcaf-fc869030153d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
93536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3534493536
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1254360106
Short name T1574
Test name
Test status
Simulation time 3708630921 ps
CPU time 28.95 seconds
Started Aug 08 06:19:28 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 218448 kb
Host smart-c9ac547f-0ca7-4a80-aff3-326be60277cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12543
60106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1254360106
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3226147090
Short name T1284
Test name
Test status
Simulation time 2476868479 ps
CPU time 18.42 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 216092 kb
Host smart-496fef07-cb3b-4ab5-8aea-e979e0593baa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3226147090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3226147090
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3963663824
Short name T2043
Test name
Test status
Simulation time 239203319 ps
CPU time 0.95 seconds
Started Aug 08 06:19:10 PM PDT 24
Finished Aug 08 06:19:11 PM PDT 24
Peak memory 207556 kb
Host smart-e574bbc6-8f07-429f-88c3-b7eacccb9b02
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3963663824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3963663824
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3947504242
Short name T2736
Test name
Test status
Simulation time 215292323 ps
CPU time 0.94 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207612 kb
Host smart-8a495bae-aec9-44f8-9e9e-cfe09428d164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475
04242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3947504242
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1711913297
Short name T3370
Test name
Test status
Simulation time 4156766185 ps
CPU time 43.29 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 216024 kb
Host smart-5dd9f4e7-f867-400e-bf88-1f3a84424971
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1711913297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1711913297
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.142013991
Short name T3077
Test name
Test status
Simulation time 168742750 ps
CPU time 0.9 seconds
Started Aug 08 06:19:20 PM PDT 24
Finished Aug 08 06:19:21 PM PDT 24
Peak memory 207568 kb
Host smart-33b4b2a2-fef5-48f3-b7b2-1ab3cb6dc95f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=142013991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.142013991
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3334420793
Short name T1291
Test name
Test status
Simulation time 170709012 ps
CPU time 0.9 seconds
Started Aug 08 06:19:31 PM PDT 24
Finished Aug 08 06:19:32 PM PDT 24
Peak memory 207608 kb
Host smart-0468e11a-a91a-416b-a46d-c5f523379f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
20793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3334420793
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2506208656
Short name T1741
Test name
Test status
Simulation time 219746618 ps
CPU time 0.95 seconds
Started Aug 08 06:19:30 PM PDT 24
Finished Aug 08 06:19:31 PM PDT 24
Peak memory 207532 kb
Host smart-614b403b-29cf-464f-98e3-30300a38b6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
08656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2506208656
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.792688404
Short name T3382
Test name
Test status
Simulation time 202391546 ps
CPU time 0.87 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207524 kb
Host smart-008f305d-bb50-4f58-9a8b-7a9522e22646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79268
8404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.792688404
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2419110382
Short name T612
Test name
Test status
Simulation time 181336303 ps
CPU time 0.94 seconds
Started Aug 08 06:19:21 PM PDT 24
Finished Aug 08 06:19:22 PM PDT 24
Peak memory 207500 kb
Host smart-5a16448f-282a-4adb-b599-8c4a4054f64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
10382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2419110382
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.369044400
Short name T2393
Test name
Test status
Simulation time 203731182 ps
CPU time 0.98 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:19:24 PM PDT 24
Peak memory 207536 kb
Host smart-5689bf97-0bd6-45bc-9f16-4487621a6737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
4400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.369044400
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.132201379
Short name T891
Test name
Test status
Simulation time 143986182 ps
CPU time 0.81 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207600 kb
Host smart-550b64c7-19c0-424a-8ecb-8b2261cb5f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13220
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.132201379
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1987778497
Short name T741
Test name
Test status
Simulation time 293320732 ps
CPU time 1.04 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207592 kb
Host smart-1d532160-e6db-4138-9d2f-ec5f1cea2813
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987778497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1987778497
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1043992373
Short name T2319
Test name
Test status
Simulation time 185656829 ps
CPU time 0.87 seconds
Started Aug 08 06:19:25 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 207568 kb
Host smart-3918ebb9-511b-4582-bb94-77cb30ec291d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10439
92373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1043992373
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.496538992
Short name T2248
Test name
Test status
Simulation time 70241240 ps
CPU time 0.72 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:19:22 PM PDT 24
Peak memory 207496 kb
Host smart-d036a715-d21f-42ba-ae65-235ad2a354ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49653
8992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.496538992
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2811891625
Short name T292
Test name
Test status
Simulation time 9777453691 ps
CPU time 27.12 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 216084 kb
Host smart-d67026b9-3d79-4f21-8f82-e74355e05979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
91625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2811891625
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3179184023
Short name T2926
Test name
Test status
Simulation time 187944153 ps
CPU time 0.88 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207580 kb
Host smart-3952bbaa-80a5-4c9f-92f8-818554b657e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
84023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3179184023
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.534772716
Short name T1154
Test name
Test status
Simulation time 177343710 ps
CPU time 0.92 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207504 kb
Host smart-370036a2-60d6-45cf-bc46-d67e6514b8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53477
2716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.534772716
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.4279147258
Short name T2080
Test name
Test status
Simulation time 199162542 ps
CPU time 0.91 seconds
Started Aug 08 06:19:25 PM PDT 24
Finished Aug 08 06:19:26 PM PDT 24
Peak memory 207508 kb
Host smart-7a6c1d51-3c06-4693-91ee-61ccb236c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
47258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.4279147258
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.726754112
Short name T2432
Test name
Test status
Simulation time 228561890 ps
CPU time 1.02 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207588 kb
Host smart-b8951d1c-bf1d-464f-b20d-77fa10a27115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72675
4112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.726754112
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1486670921
Short name T1694
Test name
Test status
Simulation time 140859760 ps
CPU time 0.82 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207560 kb
Host smart-7e91382d-e782-45ea-bbf1-d3740ee21385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14866
70921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1486670921
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.967353705
Short name T1123
Test name
Test status
Simulation time 373345214 ps
CPU time 1.39 seconds
Started Aug 08 06:19:21 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 207564 kb
Host smart-fb6b1b97-cbb9-4472-be3e-ac0d5f2530a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96735
3705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.967353705
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2983819363
Short name T2475
Test name
Test status
Simulation time 163646601 ps
CPU time 0.84 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207492 kb
Host smart-92d99eac-6fc4-4773-98ad-3a1ebe507fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
19363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2983819363
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1535553281
Short name T634
Test name
Test status
Simulation time 180025925 ps
CPU time 0.9 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207620 kb
Host smart-617d5f57-d780-411e-a135-1a7021391aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15355
53281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1535553281
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1875268586
Short name T2957
Test name
Test status
Simulation time 250632514 ps
CPU time 1.06 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 207572 kb
Host smart-7ca516c2-a546-44b4-89a2-581121a6d6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752
68586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1875268586
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1695178930
Short name T790
Test name
Test status
Simulation time 2916466808 ps
CPU time 27.78 seconds
Started Aug 08 06:19:30 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 224312 kb
Host smart-7465d5ad-8e74-49cc-b7a5-50a011291c55
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1695178930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1695178930
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3947300158
Short name T2976
Test name
Test status
Simulation time 176793863 ps
CPU time 0.9 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207500 kb
Host smart-ab8f1408-0746-4c16-b7f3-7cf67b73ab1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39473
00158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3947300158
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3709008230
Short name T1338
Test name
Test status
Simulation time 182895702 ps
CPU time 0.92 seconds
Started Aug 08 06:19:19 PM PDT 24
Finished Aug 08 06:19:20 PM PDT 24
Peak memory 207540 kb
Host smart-bae15283-fe6f-40d6-ab79-82697472e38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
08230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3709008230
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3859090003
Short name T749
Test name
Test status
Simulation time 592042952 ps
CPU time 1.7 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207476 kb
Host smart-79306939-7cb2-4dd3-b20c-7fa601dac99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
90003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3859090003
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1081887261
Short name T603
Test name
Test status
Simulation time 2894129876 ps
CPU time 22.57 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 216092 kb
Host smart-0961b7e6-c79d-4480-ac66-1c04d1ad8405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
87261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1081887261
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.968523109
Short name T2550
Test name
Test status
Simulation time 1993371210 ps
CPU time 17.51 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:19:44 PM PDT 24
Peak memory 207696 kb
Host smart-014a57db-a74d-4233-bba7-b0e37f63210f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968523109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host
_handshake.968523109
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.342547885
Short name T2253
Test name
Test status
Simulation time 653803379 ps
CPU time 1.78 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 207552 kb
Host smart-55a91d25-4dee-4119-8b7f-6381b0dd827d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342547885 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.342547885
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.4086831017
Short name T2790
Test name
Test status
Simulation time 500357194 ps
CPU time 1.68 seconds
Started Aug 08 06:22:15 PM PDT 24
Finished Aug 08 06:22:16 PM PDT 24
Peak memory 207500 kb
Host smart-4f740741-5e4e-43a2-8392-326c6ecc93b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086831017 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.4086831017
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.2615156794
Short name T3081
Test name
Test status
Simulation time 593387312 ps
CPU time 1.6 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207592 kb
Host smart-6751b869-29f1-4ce0-aefe-bc30e61c6dd0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615156794 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.2615156794
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.3311576656
Short name T2737
Test name
Test status
Simulation time 532626928 ps
CPU time 1.58 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207496 kb
Host smart-03f18c74-8f10-4890-a81d-11198d700e37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311576656 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.3311576656
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.307735950
Short name T908
Test name
Test status
Simulation time 531817939 ps
CPU time 1.69 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207600 kb
Host smart-818be941-d5ca-40de-9abe-8f3e5c24efc5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307735950 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.307735950
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.2697380640
Short name T2653
Test name
Test status
Simulation time 521584796 ps
CPU time 1.57 seconds
Started Aug 08 06:22:32 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207592 kb
Host smart-e7d55b8d-7ab5-48bb-bdd1-03c2eab05ba8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697380640 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.2697380640
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.1212734523
Short name T3026
Test name
Test status
Simulation time 526019813 ps
CPU time 1.52 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207588 kb
Host smart-03c411e2-8603-4f15-a660-ac1def46a67b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212734523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.1212734523
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.1108547197
Short name T2522
Test name
Test status
Simulation time 619464405 ps
CPU time 1.75 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207576 kb
Host smart-cb507bec-0786-41e3-a0d6-7c908ce0c416
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108547197 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.1108547197
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.2530767935
Short name T651
Test name
Test status
Simulation time 607215594 ps
CPU time 1.57 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207604 kb
Host smart-bf167764-2a49-4f40-b69b-435fc25821d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530767935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.2530767935
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.2116241598
Short name T653
Test name
Test status
Simulation time 32650616 ps
CPU time 0.62 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207544 kb
Host smart-e430e0d9-39e7-43ac-a54c-e9ccfaf1190f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2116241598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.2116241598
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3331026481
Short name T1984
Test name
Test status
Simulation time 6700710528 ps
CPU time 8.54 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 216064 kb
Host smart-e56922bf-b1ca-4b88-9099-d905989b249f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331026481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.3331026481
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.457462647
Short name T1487
Test name
Test status
Simulation time 18820092001 ps
CPU time 24.81 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207748 kb
Host smart-88d550d9-0126-4826-90ec-c04de8895c18
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=457462647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.457462647
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.78754120
Short name T3320
Test name
Test status
Simulation time 31490681837 ps
CPU time 37.84 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207888 kb
Host smart-43d79ec0-872a-4d46-a1f7-dbfa83ce6e66
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78754120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon
_wake_resume.78754120
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3676582102
Short name T2795
Test name
Test status
Simulation time 193322919 ps
CPU time 0.88 seconds
Started Aug 08 06:19:12 PM PDT 24
Finished Aug 08 06:19:18 PM PDT 24
Peak memory 207540 kb
Host smart-93e14d4c-1bca-4ab4-b7f4-eb1b4efacdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36765
82102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3676582102
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3721503555
Short name T2888
Test name
Test status
Simulation time 147235419 ps
CPU time 0.89 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207544 kb
Host smart-bfadc685-4d66-4560-96d6-d30fc4564652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
03555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3721503555
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.890415067
Short name T2117
Test name
Test status
Simulation time 298693895 ps
CPU time 1.22 seconds
Started Aug 08 06:19:15 PM PDT 24
Finished Aug 08 06:19:16 PM PDT 24
Peak memory 207576 kb
Host smart-41fb1bdd-f8bf-42e1-ac47-1169a34a6824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89041
5067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.890415067
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1257205070
Short name T2041
Test name
Test status
Simulation time 332637507 ps
CPU time 1.15 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207616 kb
Host smart-605dabcb-dd95-471d-82c7-554a2203c8f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1257205070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1257205070
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3032573590
Short name T3581
Test name
Test status
Simulation time 51832557492 ps
CPU time 81.07 seconds
Started Aug 08 06:19:21 PM PDT 24
Finished Aug 08 06:20:42 PM PDT 24
Peak memory 207876 kb
Host smart-eeab2f50-a309-4de7-a668-f3fbaa77f5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
73590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3032573590
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.1635463833
Short name T793
Test name
Test status
Simulation time 1700916537 ps
CPU time 41.45 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207732 kb
Host smart-68520b2a-0dfa-48fa-85cb-fe6f5bcea16c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635463833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.1635463833
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1664691789
Short name T1790
Test name
Test status
Simulation time 686204529 ps
CPU time 1.74 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207484 kb
Host smart-69f4c8c7-6347-467f-b30b-d00a3a5e6187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
91789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1664691789
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3862167473
Short name T3509
Test name
Test status
Simulation time 168261301 ps
CPU time 0.84 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207532 kb
Host smart-55c5937a-4b82-4918-89a2-b128c5ecf520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38621
67473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3862167473
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.851565499
Short name T1935
Test name
Test status
Simulation time 37556788 ps
CPU time 0.7 seconds
Started Aug 08 06:19:22 PM PDT 24
Finished Aug 08 06:19:23 PM PDT 24
Peak memory 207480 kb
Host smart-89cfdd3b-ecba-444f-ab36-527ab95c05ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85156
5499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.851565499
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3852535667
Short name T2982
Test name
Test status
Simulation time 959733096 ps
CPU time 2.52 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:40 PM PDT 24
Peak memory 207788 kb
Host smart-58be2382-a101-4eef-8873-5d399fefb368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
35667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3852535667
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.15348811
Short name T396
Test name
Test status
Simulation time 578359839 ps
CPU time 1.39 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207452 kb
Host smart-616c3104-9e39-4002-a595-ef53c0e7c1d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=15348811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.15348811
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2600196965
Short name T697
Test name
Test status
Simulation time 347677649 ps
CPU time 2.41 seconds
Started Aug 08 06:19:31 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207696 kb
Host smart-05eb1dbd-e925-4e62-8580-b1a6db20e6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
96965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2600196965
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.4059974667
Short name T1753
Test name
Test status
Simulation time 182842315 ps
CPU time 0.98 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:19:30 PM PDT 24
Peak memory 216012 kb
Host smart-f60efe4b-6937-4cee-9082-7783951a1ad0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4059974667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.4059974667
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2576842841
Short name T1688
Test name
Test status
Simulation time 147176770 ps
CPU time 0.84 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207556 kb
Host smart-f43223c7-0360-4c2e-8f18-e024d6ee2946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
42841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2576842841
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2617455091
Short name T1503
Test name
Test status
Simulation time 247031990 ps
CPU time 1.02 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:17 PM PDT 24
Peak memory 207576 kb
Host smart-4b462b2c-ece8-4698-96ef-9111f9d163a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26174
55091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2617455091
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2212347530
Short name T775
Test name
Test status
Simulation time 2849152685 ps
CPU time 28.31 seconds
Started Aug 08 06:19:26 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 217244 kb
Host smart-0cdb7c18-17d4-4fa9-922e-8eacacbe45ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2212347530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2212347530
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.263638778
Short name T3247
Test name
Test status
Simulation time 5246110470 ps
CPU time 32.11 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207772 kb
Host smart-c6b0077a-54e1-42bb-b0dc-9e02897ab0af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=263638778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.263638778
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3693120605
Short name T109
Test name
Test status
Simulation time 199108472 ps
CPU time 0.98 seconds
Started Aug 08 06:19:31 PM PDT 24
Finished Aug 08 06:19:32 PM PDT 24
Peak memory 207480 kb
Host smart-825fb0dc-74dd-403f-ad2b-5541cd750d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36931
20605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3693120605
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2697150062
Short name T2332
Test name
Test status
Simulation time 14774393428 ps
CPU time 22.69 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207788 kb
Host smart-3a181cec-90a5-4d4f-9a56-50dc726b645a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26971
50062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2697150062
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3679861541
Short name T2462
Test name
Test status
Simulation time 11307563625 ps
CPU time 15.41 seconds
Started Aug 08 06:19:29 PM PDT 24
Finished Aug 08 06:19:45 PM PDT 24
Peak memory 207884 kb
Host smart-80eed00d-b504-4223-a2a8-3782ced1be32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798
61541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3679861541
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1082002317
Short name T857
Test name
Test status
Simulation time 3724352004 ps
CPU time 26.72 seconds
Started Aug 08 06:19:27 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 218916 kb
Host smart-eaf8347a-ba32-4863-a915-af76d3fd598e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
02317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1082002317
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1462149530
Short name T2622
Test name
Test status
Simulation time 2561939042 ps
CPU time 24.72 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 217732 kb
Host smart-a99086ad-89a8-440b-ace8-b8679df4b6a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1462149530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1462149530
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1214541622
Short name T1769
Test name
Test status
Simulation time 250778836 ps
CPU time 0.96 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207512 kb
Host smart-e2f73337-9038-4bfd-826b-461e699e4312
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1214541622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1214541622
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1822671805
Short name T1598
Test name
Test status
Simulation time 194204185 ps
CPU time 0.95 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207520 kb
Host smart-9fdc6044-87e5-4de6-b5bc-b14f5a706fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18226
71805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1822671805
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1565984154
Short name T683
Test name
Test status
Simulation time 2709657486 ps
CPU time 21.72 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 208148 kb
Host smart-8611fc22-f02b-4912-8293-710a2b200a5f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1565984154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1565984154
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.673073290
Short name T1560
Test name
Test status
Simulation time 160042147 ps
CPU time 0.89 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:42 PM PDT 24
Peak memory 207512 kb
Host smart-a09f9900-a9f7-465d-8241-bb6ff0319cdc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=673073290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.673073290
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2587266273
Short name T1015
Test name
Test status
Simulation time 185030953 ps
CPU time 0.83 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207568 kb
Host smart-84618eb0-b5d3-4a72-a966-b3d3985a12c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25872
66273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2587266273
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3747181895
Short name T149
Test name
Test status
Simulation time 209501048 ps
CPU time 0.93 seconds
Started Aug 08 06:19:32 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207600 kb
Host smart-d097b8d7-0752-4d16-828f-bd1f2f7a04ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471
81895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3747181895
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.165088424
Short name T3441
Test name
Test status
Simulation time 184012952 ps
CPU time 0.99 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 207540 kb
Host smart-095eb737-6d29-40f5-96ee-688792deed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
8424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.165088424
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1577995856
Short name T1781
Test name
Test status
Simulation time 153973534 ps
CPU time 0.83 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207540 kb
Host smart-97210ade-5eee-40ec-9ade-3d43ad7774a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15779
95856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1577995856
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1122686897
Short name T1824
Test name
Test status
Simulation time 185733770 ps
CPU time 0.9 seconds
Started Aug 08 06:19:33 PM PDT 24
Finished Aug 08 06:19:34 PM PDT 24
Peak memory 207552 kb
Host smart-6aa87f31-09e5-470f-ab0b-d0706022549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
86897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1122686897
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3312338094
Short name T178
Test name
Test status
Simulation time 159458498 ps
CPU time 0.85 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 207584 kb
Host smart-85cf4492-bd1c-4e7b-b584-60fe3ddd721c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33123
38094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3312338094
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2741173783
Short name T1512
Test name
Test status
Simulation time 210117914 ps
CPU time 0.98 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:19:40 PM PDT 24
Peak memory 207512 kb
Host smart-e0d7d995-c2b4-4dac-a394-abb95a6b72fa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2741173783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2741173783
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1034398207
Short name T2592
Test name
Test status
Simulation time 146436764 ps
CPU time 0.84 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207528 kb
Host smart-33485655-8f9b-4f0f-ab96-69ae2a7ceef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10343
98207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1034398207
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3534656829
Short name T3376
Test name
Test status
Simulation time 36963467 ps
CPU time 0.71 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207492 kb
Host smart-4c2dba80-d47e-424c-b55c-a733dea7418d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
56829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3534656829
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.959427686
Short name T2050
Test name
Test status
Simulation time 17186597059 ps
CPU time 45.67 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 220492 kb
Host smart-e339f9bc-7b9c-4d27-880b-1393efb409ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95942
7686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.959427686
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2514332264
Short name T3260
Test name
Test status
Simulation time 195782878 ps
CPU time 0.97 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207484 kb
Host smart-6b26c577-8798-4c4d-b5c6-5182b71f4fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25143
32264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2514332264
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.937302851
Short name T2986
Test name
Test status
Simulation time 221537423 ps
CPU time 1.03 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207568 kb
Host smart-a496c21b-5225-4a9a-bf8a-dbc3989097e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93730
2851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.937302851
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1977310355
Short name T1135
Test name
Test status
Simulation time 191177373 ps
CPU time 0.89 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207544 kb
Host smart-31f7c1a3-3012-438c-bb79-b2738af628e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
10355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1977310355
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3644105243
Short name T3517
Test name
Test status
Simulation time 160941602 ps
CPU time 0.83 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207484 kb
Host smart-b73ac0fa-ddec-47d0-a119-a74d57a2113d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36441
05243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3644105243
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.4223445289
Short name T3416
Test name
Test status
Simulation time 173073356 ps
CPU time 0.92 seconds
Started Aug 08 06:19:41 PM PDT 24
Finished Aug 08 06:19:42 PM PDT 24
Peak memory 207584 kb
Host smart-d4173816-5147-4960-a7f5-b80daca993b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42234
45289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.4223445289
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.2142305848
Short name T2423
Test name
Test status
Simulation time 493950905 ps
CPU time 1.41 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 207508 kb
Host smart-622dd311-dc0e-4a13-8ce0-f113b9c26db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
05848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.2142305848
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1703483604
Short name T3546
Test name
Test status
Simulation time 157906253 ps
CPU time 0.85 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 207528 kb
Host smart-378580d0-2935-4cad-bc69-15a8a569621d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
83604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1703483604
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4291940378
Short name T3632
Test name
Test status
Simulation time 149399575 ps
CPU time 0.86 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207572 kb
Host smart-86fb97ab-1f5d-47d0-bf20-7edac06c2efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42919
40378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4291940378
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3928839402
Short name T3025
Test name
Test status
Simulation time 270809892 ps
CPU time 1.18 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207528 kb
Host smart-a93367ad-dbd2-46e7-96f5-aaeeffb9fcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
39402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3928839402
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1912126661
Short name T3584
Test name
Test status
Simulation time 3131448745 ps
CPU time 22.97 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 224212 kb
Host smart-617d2281-8096-408e-821d-dc637d371134
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1912126661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1912126661
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2335206940
Short name T488
Test name
Test status
Simulation time 249927468 ps
CPU time 0.98 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207584 kb
Host smart-1e5ae206-9f96-4e8b-987a-adb525a0849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
06940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2335206940
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1638982130
Short name T621
Test name
Test status
Simulation time 250353765 ps
CPU time 0.94 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207588 kb
Host smart-ab0afee4-f6a8-47bf-8573-29537c690977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389
82130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1638982130
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2759338522
Short name T1397
Test name
Test status
Simulation time 903512280 ps
CPU time 2.37 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207780 kb
Host smart-77db818d-8cd7-4d7c-ba9c-a3cc1fe6604f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27593
38522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2759338522
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.913822104
Short name T3342
Test name
Test status
Simulation time 1680914008 ps
CPU time 17.46 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 217392 kb
Host smart-ce04c53b-b1c9-4c9a-96fb-d303a5ee091d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91382
2104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.913822104
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.3810452280
Short name T2037
Test name
Test status
Simulation time 2003831015 ps
CPU time 16.9 seconds
Started Aug 08 06:19:16 PM PDT 24
Finished Aug 08 06:19:33 PM PDT 24
Peak memory 207724 kb
Host smart-6c570521-b089-4f1c-b42b-2c17e7f5b16b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810452280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.3810452280
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.3541418352
Short name T3078
Test name
Test status
Simulation time 534455412 ps
CPU time 1.54 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207532 kb
Host smart-18b44cd9-257c-427a-981f-f1633ccbe958
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541418352 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.3541418352
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.1875380406
Short name T1579
Test name
Test status
Simulation time 488205472 ps
CPU time 1.54 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207580 kb
Host smart-1d3888f4-40ec-4cc3-a600-c99d3d0b1beb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875380406 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.1875380406
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.3136721817
Short name T2950
Test name
Test status
Simulation time 504505292 ps
CPU time 1.56 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207580 kb
Host smart-13f92e88-16a4-40e4-9303-5c1ada6638f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136721817 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.3136721817
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.1499271418
Short name T3367
Test name
Test status
Simulation time 530887445 ps
CPU time 1.64 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:19 PM PDT 24
Peak memory 207600 kb
Host smart-4ace5bd6-66fd-4e7e-a2ea-4543bc68030e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499271418 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.1499271418
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.1261346214
Short name T1189
Test name
Test status
Simulation time 476359260 ps
CPU time 1.49 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207592 kb
Host smart-78d31772-d6cc-4da9-9230-8702a3297dd5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261346214 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.1261346214
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.3725051819
Short name T1269
Test name
Test status
Simulation time 620686364 ps
CPU time 1.89 seconds
Started Aug 08 06:22:25 PM PDT 24
Finished Aug 08 06:22:27 PM PDT 24
Peak memory 207540 kb
Host smart-80c06d49-8f2a-4342-a509-c16ca4e84690
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725051819 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.3725051819
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.3206952189
Short name T3607
Test name
Test status
Simulation time 630058929 ps
CPU time 1.77 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207580 kb
Host smart-c8f04a05-5cd2-4456-8d3d-caf4566e7b90
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206952189 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.3206952189
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.2128825796
Short name T983
Test name
Test status
Simulation time 615739391 ps
CPU time 1.74 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207580 kb
Host smart-abf2f015-3e15-4772-9636-12ceb8de8b5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128825796 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2128825796
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.2721931385
Short name T289
Test name
Test status
Simulation time 616741243 ps
CPU time 1.75 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207580 kb
Host smart-405eac1b-b1dd-4cc3-993b-d804d63f3aa3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721931385 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.2721931385
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.98463743
Short name T2619
Test name
Test status
Simulation time 593440540 ps
CPU time 1.56 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207592 kb
Host smart-5613b3b1-57d6-421e-a9cd-f4633f2d8432
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98463743 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.98463743
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.11597010
Short name T815
Test name
Test status
Simulation time 450194812 ps
CPU time 1.49 seconds
Started Aug 08 06:22:19 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207592 kb
Host smart-4de7794b-8e04-460b-9c16-32bf5e731a06
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597010 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.11597010
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.618922034
Short name T734
Test name
Test status
Simulation time 97482787 ps
CPU time 0.73 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207664 kb
Host smart-27f037a9-73a1-42f4-9372-ee40487715df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=618922034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.618922034
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3900426586
Short name T13
Test name
Test status
Simulation time 4865060326 ps
CPU time 6.88 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 216116 kb
Host smart-9248c150-64a0-4676-aaca-9abf35657a85
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900426586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.3900426586
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3511956410
Short name T1541
Test name
Test status
Simulation time 16265924540 ps
CPU time 17.35 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 216084 kb
Host smart-09f5e545-4950-4bb5-b205-23f5273ac40d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511956410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3511956410
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2198551907
Short name T10
Test name
Test status
Simulation time 30865332159 ps
CPU time 37.63 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:20:16 PM PDT 24
Peak memory 207880 kb
Host smart-883f06a0-7e88-4c6d-a102-24ff289d3215
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198551907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.2198551907
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2738539160
Short name T2460
Test name
Test status
Simulation time 188627802 ps
CPU time 0.93 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207564 kb
Host smart-024dc119-a361-4c34-b65a-4f9077748a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27385
39160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2738539160
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4048122314
Short name T2038
Test name
Test status
Simulation time 151476479 ps
CPU time 0.87 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207540 kb
Host smart-40a2b10e-8ba5-470a-9a0e-7691a2c18eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481
22314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4048122314
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2531972498
Short name T3480
Test name
Test status
Simulation time 505838753 ps
CPU time 1.66 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207512 kb
Host smart-163948c6-68a0-402e-8d03-2d44b174161a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
72498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2531972498
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1772874995
Short name T3128
Test name
Test status
Simulation time 431870664 ps
CPU time 1.26 seconds
Started Aug 08 06:19:41 PM PDT 24
Finished Aug 08 06:19:42 PM PDT 24
Peak memory 207528 kb
Host smart-b63b96b8-1551-486f-bde1-40c841f4b366
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1772874995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1772874995
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3988261517
Short name T2473
Test name
Test status
Simulation time 35560814931 ps
CPU time 66.51 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:20:42 PM PDT 24
Peak memory 207896 kb
Host smart-60d735bf-f279-4bb4-a0e3-604568fd9a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39882
61517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3988261517
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.1748658406
Short name T1581
Test name
Test status
Simulation time 1292800039 ps
CPU time 30.47 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 207748 kb
Host smart-50484938-0ec9-46c0-9577-ef619ee8d6dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748658406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.1748658406
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.586862066
Short name T2938
Test name
Test status
Simulation time 721696111 ps
CPU time 1.73 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:39 PM PDT 24
Peak memory 207536 kb
Host smart-d162d8ed-b42e-41ea-96f0-3dd052e43803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58686
2066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.586862066
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3129299767
Short name T2030
Test name
Test status
Simulation time 136095573 ps
CPU time 0.78 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:19:40 PM PDT 24
Peak memory 207492 kb
Host smart-50964591-95ff-4187-8c3a-c2f832c303e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
99767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3129299767
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1707606547
Short name T2931
Test name
Test status
Simulation time 46221786 ps
CPU time 0.71 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 207504 kb
Host smart-ca1341e1-4de3-4785-b268-4b40ef8a15dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17076
06547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1707606547
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.359078115
Short name T19
Test name
Test status
Simulation time 700298818 ps
CPU time 2.25 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207760 kb
Host smart-5f06794e-c4db-4ce7-9ce7-af02900f5718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
8115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.359078115
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.2991087841
Short name T406
Test name
Test status
Simulation time 534998778 ps
CPU time 1.44 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:37 PM PDT 24
Peak memory 207536 kb
Host smart-9fea2ed1-a869-48d0-a0a9-7239fe41a225
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2991087841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2991087841
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2703730049
Short name T635
Test name
Test status
Simulation time 345484797 ps
CPU time 2.48 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:38 PM PDT 24
Peak memory 207692 kb
Host smart-321fa976-0017-47fa-9706-0baf23e5f337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
30049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2703730049
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2971538739
Short name T3244
Test name
Test status
Simulation time 165872332 ps
CPU time 0.91 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:45 PM PDT 24
Peak memory 207528 kb
Host smart-5e0215f0-a5c6-4c41-8695-573cac15805b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2971538739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2971538739
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1133204645
Short name T1889
Test name
Test status
Simulation time 139282974 ps
CPU time 0.84 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 207492 kb
Host smart-e0448143-d866-44c5-b60d-56cc3217feb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
04645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1133204645
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1143936400
Short name T3106
Test name
Test status
Simulation time 222653603 ps
CPU time 0.98 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207572 kb
Host smart-510eacca-36f5-4492-a3d7-0fad760b4e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
36400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1143936400
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.663457835
Short name T886
Test name
Test status
Simulation time 4033837169 ps
CPU time 30.85 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 224292 kb
Host smart-4f120fa7-7e8f-47b0-80e7-bbe1437679c5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=663457835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.663457835
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.1209022723
Short name T2557
Test name
Test status
Simulation time 11822238363 ps
CPU time 81.56 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:21:00 PM PDT 24
Peak memory 207880 kb
Host smart-a7112da8-12e5-4dc9-9709-496bb3c82636
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1209022723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1209022723
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4187142974
Short name T1792
Test name
Test status
Simulation time 203130890 ps
CPU time 0.94 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:45 PM PDT 24
Peak memory 207600 kb
Host smart-093d77a7-70fb-450a-8dc8-3590db66a5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
42974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4187142974
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2396816978
Short name T1167
Test name
Test status
Simulation time 10518205410 ps
CPU time 14.56 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:51 PM PDT 24
Peak memory 207880 kb
Host smart-4cbce83f-04f2-48e8-9ddb-ccae22ed67c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23968
16978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2396816978
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3101788877
Short name T2945
Test name
Test status
Simulation time 8621789481 ps
CPU time 11.17 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 207808 kb
Host smart-5987a369-3c4f-4a2b-87d0-21089a829eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
88877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3101788877
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.787902098
Short name T1411
Test name
Test status
Simulation time 4164541349 ps
CPU time 118.6 seconds
Started Aug 08 06:19:36 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 218764 kb
Host smart-798a65ab-417e-4e25-8b00-60427c763994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78790
2098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.787902098
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3956108836
Short name T1763
Test name
Test status
Simulation time 2436531503 ps
CPU time 19.74 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 217956 kb
Host smart-7b49df2f-e4c0-4ed9-ac08-20dd9aaf7389
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3956108836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3956108836
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2433540212
Short name T2750
Test name
Test status
Simulation time 264200017 ps
CPU time 0.99 seconds
Started Aug 08 06:19:34 PM PDT 24
Finished Aug 08 06:19:35 PM PDT 24
Peak memory 207508 kb
Host smart-dc3e57e2-7c7b-483d-8853-0431856473ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2433540212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2433540212
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.791031378
Short name T1485
Test name
Test status
Simulation time 186942085 ps
CPU time 0.9 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:36 PM PDT 24
Peak memory 207584 kb
Host smart-0130e18d-2252-4646-8879-60d6fe9eac59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79103
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.791031378
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2293872033
Short name T3235
Test name
Test status
Simulation time 2871591038 ps
CPU time 21.43 seconds
Started Aug 08 06:19:37 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 217884 kb
Host smart-42096b34-2c9d-45f4-98fd-43ac96a89658
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2293872033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2293872033
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2487658588
Short name T546
Test name
Test status
Simulation time 144248570 ps
CPU time 0.88 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207500 kb
Host smart-3b9f7483-54d0-4201-b0f5-10eadf0dcbe8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2487658588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2487658588
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3327824226
Short name T2780
Test name
Test status
Simulation time 137757597 ps
CPU time 0.79 seconds
Started Aug 08 06:19:45 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207520 kb
Host smart-7f5f591d-ce60-43ce-91b9-428a85113670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
24226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3327824226
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.4203999146
Short name T1253
Test name
Test status
Simulation time 207888335 ps
CPU time 0.95 seconds
Started Aug 08 06:19:42 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207588 kb
Host smart-95f7c8e2-c671-464d-b871-2c9b76edd4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42039
99146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.4203999146
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.350855105
Short name T751
Test name
Test status
Simulation time 162642974 ps
CPU time 0.86 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207484 kb
Host smart-7c29afd8-5317-4bdf-b344-7b1910ac99eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.350855105
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4193508979
Short name T1151
Test name
Test status
Simulation time 176444310 ps
CPU time 0.9 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207560 kb
Host smart-e6abcfce-12d8-479b-a152-61105cfd3e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41935
08979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4193508979
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3649341036
Short name T1595
Test name
Test status
Simulation time 218695201 ps
CPU time 0.9 seconds
Started Aug 08 06:19:45 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207536 kb
Host smart-7eb4281f-81f3-43de-b1df-5bff9fe6a2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
41036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3649341036
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2633959642
Short name T3239
Test name
Test status
Simulation time 169661800 ps
CPU time 0.88 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207564 kb
Host smart-b796473e-c4ef-46d6-850d-ac565701641d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
59642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2633959642
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1257649609
Short name T1505
Test name
Test status
Simulation time 208134935 ps
CPU time 1.05 seconds
Started Aug 08 06:19:50 PM PDT 24
Finished Aug 08 06:19:52 PM PDT 24
Peak memory 207564 kb
Host smart-a4d0ab41-5ebe-4dd4-bdd5-18aa79a8825b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1257649609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1257649609
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2670019239
Short name T782
Test name
Test status
Simulation time 152478121 ps
CPU time 0.89 seconds
Started Aug 08 06:19:45 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207480 kb
Host smart-aea74776-2e7b-481d-9365-245c32631f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26700
19239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2670019239
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1322234004
Short name T2437
Test name
Test status
Simulation time 78916378 ps
CPU time 0.75 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207460 kb
Host smart-bfc82bc2-f9a5-466c-b931-acecfecf9e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
34004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1322234004
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3230331392
Short name T290
Test name
Test status
Simulation time 8161812709 ps
CPU time 19.59 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 216020 kb
Host smart-f965af3d-b27f-4fa3-a803-0fa67230bcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32303
31392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3230331392
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.46981801
Short name T1967
Test name
Test status
Simulation time 181109460 ps
CPU time 0.9 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 207564 kb
Host smart-6c42c4b1-6e8a-4e3e-bdd1-f150a1c4ca7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46981
801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.46981801
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2313644041
Short name T2320
Test name
Test status
Simulation time 186626786 ps
CPU time 0.93 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207532 kb
Host smart-13ed3b21-6bf5-42ff-9565-fd9656387149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
44041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2313644041
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2045632523
Short name T539
Test name
Test status
Simulation time 202564485 ps
CPU time 0.93 seconds
Started Aug 08 06:19:42 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207528 kb
Host smart-e4b5fc89-e11b-4fe5-b58d-6487eaf6d803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456
32523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2045632523
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.823874831
Short name T1149
Test name
Test status
Simulation time 186597193 ps
CPU time 0.91 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207568 kb
Host smart-70690a04-67ae-4f8e-952b-24ff10fe6d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82387
4831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.823874831
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2845331873
Short name T1619
Test name
Test status
Simulation time 169278344 ps
CPU time 0.86 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207600 kb
Host smart-0e68bdfa-4db0-4be3-8978-02e9e602426b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
31873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2845331873
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.2670768828
Short name T3539
Test name
Test status
Simulation time 248278242 ps
CPU time 1.14 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207588 kb
Host smart-1fa66849-33a0-45c6-9ca4-a82c177a3495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
68828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2670768828
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3484558530
Short name T2705
Test name
Test status
Simulation time 153774716 ps
CPU time 0.86 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207520 kb
Host smart-d8c88a28-d0e7-4d54-900c-3b02390ba0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34845
58530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3484558530
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.356556196
Short name T628
Test name
Test status
Simulation time 164253781 ps
CPU time 0.85 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:45 PM PDT 24
Peak memory 207524 kb
Host smart-3824a86d-3fe5-4c46-98fc-80574d5c8286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35655
6196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.356556196
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3433573378
Short name T545
Test name
Test status
Simulation time 247282674 ps
CPU time 1.08 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207592 kb
Host smart-2d7672bc-932f-4e8b-bdc9-08eaf5d39f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34335
73378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3433573378
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1252946161
Short name T1859
Test name
Test status
Simulation time 1969266987 ps
CPU time 19.87 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 217780 kb
Host smart-657acc1e-685c-4497-93ee-48df08ba2d84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1252946161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1252946161
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3994649496
Short name T669
Test name
Test status
Simulation time 166590409 ps
CPU time 0.91 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207596 kb
Host smart-f75aea9d-a520-4734-a87f-f0e95c1522c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
49496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3994649496
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3177518068
Short name T574
Test name
Test status
Simulation time 160945609 ps
CPU time 0.82 seconds
Started Aug 08 06:20:00 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207536 kb
Host smart-70be6ea1-333d-4002-9ad9-2123ab834b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31775
18068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3177518068
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1250709564
Short name T2638
Test name
Test status
Simulation time 452383443 ps
CPU time 1.52 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207508 kb
Host smart-454178dc-2dca-4d06-a9cd-681122e414d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507
09564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1250709564
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3392487483
Short name T2560
Test name
Test status
Simulation time 3284149224 ps
CPU time 32.11 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 216096 kb
Host smart-8461eddb-e256-4fc6-b5be-2b2c46a21dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924
87483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3392487483
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.3348565438
Short name T3411
Test name
Test status
Simulation time 3676282071 ps
CPU time 23.07 seconds
Started Aug 08 06:19:35 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207860 kb
Host smart-16689d55-e046-4c53-b5ac-c38457645d0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348565438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.3348565438
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.2795015973
Short name T1442
Test name
Test status
Simulation time 470898439 ps
CPU time 1.39 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207664 kb
Host smart-cf0fc340-9c47-47e6-b307-f4d51a391dad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795015973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2795015973
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.2888085039
Short name T3127
Test name
Test status
Simulation time 475840881 ps
CPU time 1.49 seconds
Started Aug 08 06:22:20 PM PDT 24
Finished Aug 08 06:22:22 PM PDT 24
Peak memory 207572 kb
Host smart-8f590320-f3bd-4d95-a630-b8641510db25
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888085039 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.2888085039
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.4176086540
Short name T1647
Test name
Test status
Simulation time 633378641 ps
CPU time 1.67 seconds
Started Aug 08 06:22:32 PM PDT 24
Finished Aug 08 06:22:34 PM PDT 24
Peak memory 207616 kb
Host smart-674e7ff0-666b-48fc-9a8c-e2cace7719ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176086540 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.4176086540
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.3547489888
Short name T177
Test name
Test status
Simulation time 605563970 ps
CPU time 1.63 seconds
Started Aug 08 06:22:30 PM PDT 24
Finished Aug 08 06:22:32 PM PDT 24
Peak memory 207588 kb
Host smart-d55b772d-5f35-44bc-a614-a2df86d4bb71
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547489888 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.3547489888
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.2220051889
Short name T712
Test name
Test status
Simulation time 497643097 ps
CPU time 1.55 seconds
Started Aug 08 06:22:18 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 207612 kb
Host smart-459a0ce5-a460-4a76-924e-a178085ded12
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220051889 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.2220051889
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.112177833
Short name T2872
Test name
Test status
Simulation time 483733203 ps
CPU time 1.58 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207580 kb
Host smart-13e4563c-0d6b-45f1-b250-56c72b5393e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112177833 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.112177833
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.3540145441
Short name T2408
Test name
Test status
Simulation time 569104109 ps
CPU time 1.64 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207580 kb
Host smart-f2bbbe1d-9e25-4d9c-b59c-0121205eb44c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540145441 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.3540145441
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.3473338921
Short name T2694
Test name
Test status
Simulation time 470549256 ps
CPU time 1.36 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207636 kb
Host smart-1a0fb7d7-646b-4cb1-87c8-f50f92be90a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473338921 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.3473338921
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.2843461658
Short name T2331
Test name
Test status
Simulation time 479159099 ps
CPU time 1.53 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 207604 kb
Host smart-5226738f-0e8a-4cc5-b177-f3c67c6496f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843461658 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.2843461658
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.1334557033
Short name T1501
Test name
Test status
Simulation time 526098853 ps
CPU time 1.67 seconds
Started Aug 08 06:22:54 PM PDT 24
Finished Aug 08 06:22:55 PM PDT 24
Peak memory 207596 kb
Host smart-ca10d17a-1fa6-4f2a-8972-0369d77e92e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334557033 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.1334557033
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.1203713735
Short name T992
Test name
Test status
Simulation time 557848980 ps
CPU time 1.56 seconds
Started Aug 08 06:22:22 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 207588 kb
Host smart-6760b6b3-33b2-4ee3-bdfa-b0b162677d87
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203713735 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.1203713735
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.1261500739
Short name T3038
Test name
Test status
Simulation time 44434353 ps
CPU time 0.68 seconds
Started Aug 08 06:14:16 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207580 kb
Host smart-91de7c8f-9c88-45db-8c4e-657a516bc197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1261500739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.1261500739
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2765698235
Short name T1261
Test name
Test status
Simulation time 10046378687 ps
CPU time 14.71 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207920 kb
Host smart-44169cb4-768d-4869-9eb8-e05f53bb9be5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765698235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.2765698235
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2612092511
Short name T2091
Test name
Test status
Simulation time 13610000672 ps
CPU time 15.75 seconds
Started Aug 08 06:14:07 PM PDT 24
Finished Aug 08 06:14:23 PM PDT 24
Peak memory 216080 kb
Host smart-ba202b72-5d9d-41c5-98eb-339a6cc55919
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612092511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2612092511
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1171686358
Short name T699
Test name
Test status
Simulation time 26228123969 ps
CPU time 36.97 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 216032 kb
Host smart-e6601f1e-29da-4ee7-92c9-c8bee0912b55
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171686358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.1171686358
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3479048709
Short name T1364
Test name
Test status
Simulation time 155790841 ps
CPU time 0.88 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:06 PM PDT 24
Peak memory 207596 kb
Host smart-36b43030-2224-4296-b909-36850c5d36f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
48709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3479048709
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2993769814
Short name T50
Test name
Test status
Simulation time 193375659 ps
CPU time 0.92 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:14:07 PM PDT 24
Peak memory 207464 kb
Host smart-dfae803f-1950-4f92-bff8-aa1c84b359f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29937
69814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2993769814
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.122042783
Short name T65
Test name
Test status
Simulation time 167983062 ps
CPU time 0.87 seconds
Started Aug 08 06:14:01 PM PDT 24
Finished Aug 08 06:14:02 PM PDT 24
Peak memory 207540 kb
Host smart-ab2184fc-5bcf-40b0-8c78-3be5d6af4bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
2783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.122042783
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3578212726
Short name T1114
Test name
Test status
Simulation time 145887576 ps
CPU time 0.85 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207484 kb
Host smart-955b5f05-de94-4d49-bcb1-5f0799de4afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35782
12726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3578212726
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.248778868
Short name T558
Test name
Test status
Simulation time 384377138 ps
CPU time 1.44 seconds
Started Aug 08 06:14:01 PM PDT 24
Finished Aug 08 06:14:02 PM PDT 24
Peak memory 207560 kb
Host smart-eba16c48-1c41-4ac8-84bd-f8a7a59f45cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24877
8868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.248778868
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1636965839
Short name T1558
Test name
Test status
Simulation time 722470163 ps
CPU time 2.04 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207796 kb
Host smart-ddb182d0-1e76-42e7-beed-ffc42878d0e2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1636965839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1636965839
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2748189700
Short name T2784
Test name
Test status
Simulation time 29347211262 ps
CPU time 42.53 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 207848 kb
Host smart-f8221882-6603-4ca1-9af8-ecceee634bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27481
89700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2748189700
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.820983087
Short name T3419
Test name
Test status
Simulation time 851116305 ps
CPU time 18.52 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:21 PM PDT 24
Peak memory 207768 kb
Host smart-fa3aa885-b4df-4e1f-a80e-b3a30bb5d166
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820983087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.820983087
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2723410491
Short name T2554
Test name
Test status
Simulation time 1385458892 ps
CPU time 2.56 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:07 PM PDT 24
Peak memory 207516 kb
Host smart-06a697de-3b03-46a4-84f9-769cdad766aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
10491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2723410491
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2876098734
Short name T3111
Test name
Test status
Simulation time 144465803 ps
CPU time 0.85 seconds
Started Aug 08 06:14:07 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 207584 kb
Host smart-5094eea6-9281-4682-b385-f99a1614d3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28760
98734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2876098734
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1238230477
Short name T2442
Test name
Test status
Simulation time 36135310 ps
CPU time 0.71 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:03 PM PDT 24
Peak memory 207524 kb
Host smart-3b7c0796-ab53-4878-8a8f-d8f37a6065f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
30477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1238230477
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.4124239528
Short name T1632
Test name
Test status
Simulation time 977889536 ps
CPU time 2.4 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 207828 kb
Host smart-30e263b5-70b8-4c25-b3a6-9a6606534b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
39528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.4124239528
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.4165775600
Short name T357
Test name
Test status
Simulation time 758993414 ps
CPU time 1.72 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 207496 kb
Host smart-7f721e64-b010-4a85-8928-9f340fca650d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4165775600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.4165775600
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4103607518
Short name T2954
Test name
Test status
Simulation time 209182118 ps
CPU time 1.48 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 207684 kb
Host smart-ee68e83b-7d24-460d-ad87-60f2ea5bfdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
07518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4103607518
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.3352886055
Short name T3531
Test name
Test status
Simulation time 85178212966 ps
CPU time 139.9 seconds
Started Aug 08 06:14:00 PM PDT 24
Finished Aug 08 06:16:20 PM PDT 24
Peak memory 207892 kb
Host smart-87001662-42b7-4f57-acfd-a941524b4a81
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3352886055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.3352886055
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3251605069
Short name T934
Test name
Test status
Simulation time 120355241487 ps
CPU time 203.87 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:17:38 PM PDT 24
Peak memory 207744 kb
Host smart-6883732f-1095-4b22-87a2-1f07278ef661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251605069 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3251605069
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1404726537
Short name T2850
Test name
Test status
Simulation time 108110455854 ps
CPU time 159.72 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:16:45 PM PDT 24
Peak memory 207784 kb
Host smart-e5d56a7a-2a1d-4e5e-892e-40ccc9a9cfbe
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1404726537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1404726537
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1938799970
Short name T520
Test name
Test status
Simulation time 109026762440 ps
CPU time 159.57 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:16:46 PM PDT 24
Peak memory 207764 kb
Host smart-30b38356-9f5d-4e2c-9930-ae30fca3c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938799970 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1938799970
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2225923382
Short name T3429
Test name
Test status
Simulation time 94165138179 ps
CPU time 167.88 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:16:54 PM PDT 24
Peak memory 207784 kb
Host smart-d5ae96e4-7a4c-4c1d-9140-d7f0ff124536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
23382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2225923382
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.716296816
Short name T2307
Test name
Test status
Simulation time 259954528 ps
CPU time 1.16 seconds
Started Aug 08 06:14:07 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 216000 kb
Host smart-805d0177-ea06-4811-9846-1788a07e6069
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=716296816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.716296816
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.398457976
Short name T2118
Test name
Test status
Simulation time 139908454 ps
CPU time 0.83 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:14:07 PM PDT 24
Peak memory 207548 kb
Host smart-dea41cd2-56b6-43b5-9726-20367a2d3a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39845
7976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.398457976
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1324786852
Short name T1668
Test name
Test status
Simulation time 168974604 ps
CPU time 0.86 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:03 PM PDT 24
Peak memory 207540 kb
Host smart-39c936ff-1d46-4b08-afcf-855149b0eb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
86852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1324786852
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.1999451053
Short name T1498
Test name
Test status
Simulation time 4812787235 ps
CPU time 36.43 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:14:43 PM PDT 24
Peak memory 224312 kb
Host smart-8871bef9-d50e-4b34-9e7a-ce0ba9acacea
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1999451053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.1999451053
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3329806625
Short name T3507
Test name
Test status
Simulation time 12665075960 ps
CPU time 93.25 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 207832 kb
Host smart-744f1ef9-bc1e-49a6-a597-fb0ce8eaf41e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329806625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3329806625
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1207735729
Short name T1476
Test name
Test status
Simulation time 201839507 ps
CPU time 0.92 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207492 kb
Host smart-100dd693-1868-43ff-b23a-aaa2e65006c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
35729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1207735729
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1124034168
Short name T3015
Test name
Test status
Simulation time 24178960353 ps
CPU time 37.33 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 207808 kb
Host smart-31373558-0aab-450a-9346-48f179b21ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
34168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1124034168
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1997676509
Short name T1457
Test name
Test status
Simulation time 10190776847 ps
CPU time 12.78 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207884 kb
Host smart-ab12ca52-8e02-438e-873d-e9060c0717f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976
76509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1997676509
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3922962535
Short name T3361
Test name
Test status
Simulation time 2960979999 ps
CPU time 82.61 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:15:29 PM PDT 24
Peak memory 224300 kb
Host smart-e541fc10-948a-407b-84cf-8cda4400c711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229
62535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3922962535
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.74074534
Short name T516
Test name
Test status
Simulation time 2766902656 ps
CPU time 80.51 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:15:24 PM PDT 24
Peak memory 217640 kb
Host smart-b6bd9eac-4607-4078-b381-64e52cb83333
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=74074534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.74074534
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3114367843
Short name T2555
Test name
Test status
Simulation time 251160815 ps
CPU time 0.99 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 207580 kb
Host smart-3869df41-e846-477a-8ea0-0d6a98ba1f87
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3114367843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3114367843
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.504313579
Short name T1744
Test name
Test status
Simulation time 221480068 ps
CPU time 0.99 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207572 kb
Host smart-f2284a92-cc4f-4dc4-b915-d617c6be55ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50431
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.504313579
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.2175508700
Short name T1278
Test name
Test status
Simulation time 2326439074 ps
CPU time 23.01 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 217400 kb
Host smart-97d58b2e-52ab-4169-8f7f-366a649e8806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21755
08700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.2175508700
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.227174186
Short name T2338
Test name
Test status
Simulation time 2255976295 ps
CPU time 65.19 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:15:09 PM PDT 24
Peak memory 218184 kb
Host smart-c6117437-2b45-40f7-b381-a6091ecedd72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=227174186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.227174186
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2115436023
Short name T1689
Test name
Test status
Simulation time 2487852402 ps
CPU time 66.65 seconds
Started Aug 08 06:14:07 PM PDT 24
Finished Aug 08 06:15:14 PM PDT 24
Peak memory 217636 kb
Host smart-57a21e3a-a07b-49c2-b206-447f2331862a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2115436023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2115436023
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2726190063
Short name T3553
Test name
Test status
Simulation time 150809007 ps
CPU time 0.85 seconds
Started Aug 08 06:14:06 PM PDT 24
Finished Aug 08 06:14:07 PM PDT 24
Peak memory 207484 kb
Host smart-5fd7d76f-f386-4134-b2d3-1398dff29fbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2726190063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2726190063
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3793092716
Short name T557
Test name
Test status
Simulation time 161717760 ps
CPU time 0.9 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:06 PM PDT 24
Peak memory 206360 kb
Host smart-203c145f-267f-48b6-a517-0434a1bb8f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
92716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3793092716
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3709027461
Short name T2718
Test name
Test status
Simulation time 186620541 ps
CPU time 0.93 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207532 kb
Host smart-67a4fc33-f028-4341-83af-5dfbfaad3dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
27461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3709027461
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2445563881
Short name T1795
Test name
Test status
Simulation time 155388131 ps
CPU time 0.89 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207540 kb
Host smart-15bdfe74-4618-432a-bfd8-aa7ae3f15896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
63881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2445563881
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.150550583
Short name T3285
Test name
Test status
Simulation time 184421363 ps
CPU time 0.94 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207536 kb
Host smart-04c5b18f-ecbc-40c8-8e46-d16e3fa7f8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.150550583
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.379918802
Short name T1618
Test name
Test status
Simulation time 178846327 ps
CPU time 0.89 seconds
Started Aug 08 06:14:07 PM PDT 24
Finished Aug 08 06:14:08 PM PDT 24
Peak memory 207616 kb
Host smart-d12584f9-8360-46db-84b8-25c1eb9b095b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
8802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.379918802
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1534641930
Short name T684
Test name
Test status
Simulation time 164462983 ps
CPU time 0.87 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 206368 kb
Host smart-9dd1b6dc-0825-4833-8053-4a903757f75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15346
41930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1534641930
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1576885270
Short name T3352
Test name
Test status
Simulation time 235343077 ps
CPU time 1.03 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207476 kb
Host smart-fc9ba571-3126-48d5-8e9d-51758244d364
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1576885270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1576885270
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3327423576
Short name T3384
Test name
Test status
Simulation time 226545469 ps
CPU time 1.07 seconds
Started Aug 08 06:14:02 PM PDT 24
Finished Aug 08 06:14:03 PM PDT 24
Peak memory 207516 kb
Host smart-a0e17cd8-32c7-4ae7-8853-b52c18b32170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274
23576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3327423576
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.304398846
Short name T909
Test name
Test status
Simulation time 144112359 ps
CPU time 0.83 seconds
Started Aug 08 06:14:04 PM PDT 24
Finished Aug 08 06:14:04 PM PDT 24
Peak memory 207508 kb
Host smart-7c1af3a8-d93a-4a65-8414-0a2e985dc8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
8846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.304398846
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.477483479
Short name T1119
Test name
Test status
Simulation time 29236317 ps
CPU time 0.66 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:05 PM PDT 24
Peak memory 206324 kb
Host smart-1b4f0133-4827-4274-abfa-a1cb0a330ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47748
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.477483479
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.527164431
Short name T1827
Test name
Test status
Simulation time 15834309261 ps
CPU time 38.4 seconds
Started Aug 08 06:14:03 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 216096 kb
Host smart-2d26a18c-4453-476c-babc-125c98ccf577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52716
4431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.527164431
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3905912113
Short name T1264
Test name
Test status
Simulation time 185026978 ps
CPU time 0.91 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207484 kb
Host smart-2afa52a4-ab07-4c87-8277-2498caa7e438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
12113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3905912113
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3142409294
Short name T3092
Test name
Test status
Simulation time 209785475 ps
CPU time 0.91 seconds
Started Aug 08 06:14:01 PM PDT 24
Finished Aug 08 06:14:02 PM PDT 24
Peak memory 207560 kb
Host smart-0c8e40eb-2d87-4516-8349-605083423f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31424
09294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3142409294
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3960074346
Short name T3618
Test name
Test status
Simulation time 7205754277 ps
CPU time 112.12 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:16:07 PM PDT 24
Peak memory 216032 kb
Host smart-1fe9d713-63b2-4407-8257-f4869aff2f0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960074346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3960074346
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1103424220
Short name T1427
Test name
Test status
Simulation time 6693063809 ps
CPU time 95.84 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:15:50 PM PDT 24
Peak memory 224192 kb
Host smart-f3440537-e10b-4a56-895c-d5179bd1656f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1103424220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1103424220
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.707260657
Short name T1028
Test name
Test status
Simulation time 5027862308 ps
CPU time 16.54 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 216052 kb
Host smart-491cc580-7e54-45e6-b86a-293f597fde33
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=707260657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.707260657
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3902960241
Short name T538
Test name
Test status
Simulation time 239794828 ps
CPU time 0.99 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207484 kb
Host smart-57cf40c5-d6f4-4213-8b75-59c77f44ab7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39029
60241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3902960241
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.872467392
Short name T1546
Test name
Test status
Simulation time 153657430 ps
CPU time 0.85 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:06 PM PDT 24
Peak memory 207492 kb
Host smart-bd57767d-da7c-4eb0-8a93-38db21086471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87246
7392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.872467392
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.4072329852
Short name T892
Test name
Test status
Simulation time 20177758030 ps
CPU time 28.16 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:33 PM PDT 24
Peak memory 207576 kb
Host smart-5dadc14e-54e7-4ee5-96d3-e678b243345a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723
29852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.4072329852
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1712480914
Short name T2852
Test name
Test status
Simulation time 187718476 ps
CPU time 0.9 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:06 PM PDT 24
Peak memory 207464 kb
Host smart-90e749c4-0963-4fbe-aa1a-114281014660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
80914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1712480914
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.1322097059
Short name T1869
Test name
Test status
Simulation time 366578987 ps
CPU time 1.32 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207560 kb
Host smart-ea100758-3e6d-4cd1-95f4-09353e421cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13220
97059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.1322097059
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3698986556
Short name T82
Test name
Test status
Simulation time 186301098 ps
CPU time 0.91 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207528 kb
Host smart-6a5aedcd-1128-41b1-8896-d18740969959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
86556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3698986556
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3864068972
Short name T232
Test name
Test status
Simulation time 848814150 ps
CPU time 1.74 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:19 PM PDT 24
Peak memory 224468 kb
Host smart-0e0169b0-0efa-4b51-876f-fefd0fc5b61a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3864068972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3864068972
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.500432963
Short name T3494
Test name
Test status
Simulation time 399826692 ps
CPU time 1.38 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207540 kb
Host smart-0d05eadf-515b-455d-8f3b-7450aaeca246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50043
2963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.500432963
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.964773128
Short name T193
Test name
Test status
Simulation time 163598890 ps
CPU time 0.89 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207564 kb
Host smart-12883a71-4800-492f-ad4c-377fc1514221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96477
3128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.964773128
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.532378369
Short name T2792
Test name
Test status
Simulation time 218360330 ps
CPU time 0.9 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:18 PM PDT 24
Peak memory 207492 kb
Host smart-f312b40c-9c88-470d-8770-2323188879f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53237
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.532378369
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3726110864
Short name T3466
Test name
Test status
Simulation time 150137191 ps
CPU time 0.82 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207620 kb
Host smart-73343e96-a90b-4c2a-91cf-f43e08809fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37261
10864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3726110864
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1728696772
Short name T1121
Test name
Test status
Simulation time 183403778 ps
CPU time 0.94 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207616 kb
Host smart-96ca62a4-2431-44d0-863b-db6fcbae4a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
96772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1728696772
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4178942126
Short name T1750
Test name
Test status
Simulation time 2561726813 ps
CPU time 26.02 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 217968 kb
Host smart-ef2ee15f-f3f7-4e38-9eb6-7762a2b6e496
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4178942126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4178942126
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3855959692
Short name T1182
Test name
Test status
Simulation time 185447799 ps
CPU time 0.97 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207604 kb
Host smart-e72cc530-1ab9-44cf-b633-6ddae8b1b773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38559
59692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3855959692
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.853004797
Short name T1807
Test name
Test status
Simulation time 172626449 ps
CPU time 0.89 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207620 kb
Host smart-2046d131-c25a-4384-83e3-d1b5bd16a139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85300
4797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.853004797
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.2466702753
Short name T23
Test name
Test status
Simulation time 435441725 ps
CPU time 1.36 seconds
Started Aug 08 06:14:12 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207560 kb
Host smart-335ee4f0-dac3-474b-a66c-a9cc352bff1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24667
02753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.2466702753
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2413827434
Short name T3347
Test name
Test status
Simulation time 2350986519 ps
CPU time 18.19 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:32 PM PDT 24
Peak memory 216252 kb
Host smart-42244858-8477-477c-b082-71181125bb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
27434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2413827434
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.641313088
Short name T111
Test name
Test status
Simulation time 11035271991 ps
CPU time 211.27 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:17:46 PM PDT 24
Peak memory 218352 kb
Host smart-91b01494-3972-4629-aa38-425153b1e51c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641313088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.641313088
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.1524917041
Short name T63
Test name
Test status
Simulation time 3426166929 ps
CPU time 30.66 seconds
Started Aug 08 06:14:05 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 207888 kb
Host smart-8aa555a9-056f-4db4-93a2-d89640fd1ee3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524917041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.1524917041
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.168470907
Short name T1770
Test name
Test status
Simulation time 567689590 ps
CPU time 1.71 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207532 kb
Host smart-ac3de479-e433-40db-8e17-29df53697834
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168470907 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.168470907
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3910078739
Short name T758
Test name
Test status
Simulation time 74252029 ps
CPU time 0.67 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207512 kb
Host smart-e6490161-b015-4134-adf1-2ea1f0107938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3910078739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3910078739
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.904645554
Short name T897
Test name
Test status
Simulation time 6311229248 ps
CPU time 10.52 seconds
Started Aug 08 06:20:03 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 215992 kb
Host smart-f83161d7-ed2e-4264-ad6f-e58dd46c7498
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904645554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_disconnect.904645554
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1083351329
Short name T1789
Test name
Test status
Simulation time 15419024701 ps
CPU time 18.86 seconds
Started Aug 08 06:19:55 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 216072 kb
Host smart-e8b153a1-81e1-4e1a-bb3a-799f9e1ffe76
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083351329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1083351329
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.4042710649
Short name T1235
Test name
Test status
Simulation time 31382807224 ps
CPU time 35.91 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:20:44 PM PDT 24
Peak memory 207896 kb
Host smart-087fb4ce-d8b7-4865-9e77-03127238c9d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042710649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.4042710649
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2937662357
Short name T1530
Test name
Test status
Simulation time 186510013 ps
CPU time 0.91 seconds
Started Aug 08 06:20:04 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 207608 kb
Host smart-01c28ed6-7af2-4b16-b5d1-78acb4ab5411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29376
62357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2937662357
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2553844618
Short name T1352
Test name
Test status
Simulation time 201193188 ps
CPU time 0.92 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207616 kb
Host smart-60f5cf7f-a33d-4641-95f5-c134b51a9928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25538
44618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2553844618
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.244598909
Short name T2316
Test name
Test status
Simulation time 180914263 ps
CPU time 0.94 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207620 kb
Host smart-eba8a0d7-3a59-4dc8-898e-be73e2b2a066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
8909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.244598909
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1117455396
Short name T3050
Test name
Test status
Simulation time 858239383 ps
CPU time 2.32 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207712 kb
Host smart-bac9d52a-39d3-42d6-bbee-b001a9280913
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1117455396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1117455396
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1871598964
Short name T1767
Test name
Test status
Simulation time 29224518292 ps
CPU time 41.66 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207812 kb
Host smart-0ded7e4c-5614-44b3-9945-1d2b26d0d704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
98964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1871598964
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.3846292465
Short name T824
Test name
Test status
Simulation time 686766938 ps
CPU time 5.06 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207704 kb
Host smart-21318303-98f6-4e10-8e4c-75c6dbd12e27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846292465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.3846292465
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.260508336
Short name T3359
Test name
Test status
Simulation time 1013512436 ps
CPU time 2.15 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207524 kb
Host smart-15291972-fe3f-41e9-93d2-59cd1f72b98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
8336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.260508336
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3623772640
Short name T1835
Test name
Test status
Simulation time 148737190 ps
CPU time 0.82 seconds
Started Aug 08 06:20:03 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207484 kb
Host smart-b36e13a6-6959-4406-8896-42e36c743d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
72640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3623772640
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.4017812486
Short name T705
Test name
Test status
Simulation time 36901206 ps
CPU time 0.74 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207512 kb
Host smart-50bd3655-4099-4717-abdd-d22d17b5d116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40178
12486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4017812486
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3506996746
Short name T914
Test name
Test status
Simulation time 899376268 ps
CPU time 2.75 seconds
Started Aug 08 06:19:42 PM PDT 24
Finished Aug 08 06:19:49 PM PDT 24
Peak memory 207792 kb
Host smart-732258af-64ac-4a3a-a01d-7791f9f3863d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
96746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3506996746
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.4057764992
Short name T2842
Test name
Test status
Simulation time 332211905 ps
CPU time 1.08 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 206340 kb
Host smart-27769bb1-b251-419a-8ef2-39fa82b075f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4057764992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.4057764992
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3831312501
Short name T3575
Test name
Test status
Simulation time 261366767 ps
CPU time 2.5 seconds
Started Aug 08 06:20:04 PM PDT 24
Finished Aug 08 06:20:07 PM PDT 24
Peak memory 207708 kb
Host smart-244334f7-88d7-477a-91d4-e1ac87700742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
12501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3831312501
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2597504937
Short name T1527
Test name
Test status
Simulation time 238553440 ps
CPU time 1.27 seconds
Started Aug 08 06:20:12 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 215968 kb
Host smart-694b842e-4862-4273-aba7-b259d32ee02d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2597504937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2597504937
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3656572799
Short name T125
Test name
Test status
Simulation time 144041868 ps
CPU time 0.81 seconds
Started Aug 08 06:20:04 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 207532 kb
Host smart-9ec5b281-6846-49a2-82ea-19bbc18b4ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36565
72799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3656572799
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3413443753
Short name T1125
Test name
Test status
Simulation time 246361856 ps
CPU time 1.01 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207588 kb
Host smart-28711a55-7ec1-4f0c-9f95-1e7767662a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34134
43753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3413443753
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2730731367
Short name T945
Test name
Test status
Simulation time 4214935673 ps
CPU time 43.42 seconds
Started Aug 08 06:19:49 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 216856 kb
Host smart-9b4f73a1-b0bd-4640-9baa-7fcdfd157225
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2730731367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2730731367
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.499821853
Short name T6
Test name
Test status
Simulation time 14416016677 ps
CPU time 105.72 seconds
Started Aug 08 06:20:06 PM PDT 24
Finished Aug 08 06:21:51 PM PDT 24
Peak memory 207832 kb
Host smart-23d3dc8b-fd38-4b93-92c0-c55290aee306
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=499821853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.499821853
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.619435767
Short name T843
Test name
Test status
Simulation time 219734724 ps
CPU time 1.02 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207544 kb
Host smart-7a1ea76f-3b32-42c5-8b82-36475d3095e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61943
5767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.619435767
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.169764293
Short name T2734
Test name
Test status
Simulation time 32917080136 ps
CPU time 53.34 seconds
Started Aug 08 06:20:03 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207852 kb
Host smart-00edae42-be22-4081-a339-81216b464c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
4293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.169764293
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2966828356
Short name T3453
Test name
Test status
Simulation time 10928092558 ps
CPU time 14.22 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:19:52 PM PDT 24
Peak memory 207832 kb
Host smart-3c37356c-3998-4f52-bc90-3e43cb0461a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668
28356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2966828356
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3382069277
Short name T2730
Test name
Test status
Simulation time 3375952598 ps
CPU time 33.72 seconds
Started Aug 08 06:19:39 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 218872 kb
Host smart-487e5a00-9ad4-4367-a8dd-4113135131a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820
69277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3382069277
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2410375333
Short name T1471
Test name
Test status
Simulation time 4278763324 ps
CPU time 40.49 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 217784 kb
Host smart-420fa711-ec94-41c3-b90b-bca608c9aab1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2410375333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2410375333
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3858133162
Short name T763
Test name
Test status
Simulation time 241133899 ps
CPU time 1.1 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207500 kb
Host smart-7a187b85-5b84-4187-a05c-2716f306d492
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3858133162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3858133162
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2559060713
Short name T2763
Test name
Test status
Simulation time 206137483 ps
CPU time 1 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 207612 kb
Host smart-cf8d526b-3bc7-430c-a483-f4b5f13b7634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25590
60713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2559060713
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1552577185
Short name T3184
Test name
Test status
Simulation time 2244837639 ps
CPU time 22.98 seconds
Started Aug 08 06:19:38 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 217532 kb
Host smart-62a92fff-c6e7-414f-9403-a898bceeb394
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1552577185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1552577185
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2361881940
Short name T2341
Test name
Test status
Simulation time 154037116 ps
CPU time 0.85 seconds
Started Aug 08 06:19:42 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207532 kb
Host smart-0801467a-5c23-484d-a1b5-265916b560ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2361881940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2361881940
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3875253693
Short name T889
Test name
Test status
Simulation time 167749334 ps
CPU time 0.84 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207508 kb
Host smart-6bbdadb8-6aaf-4b89-960e-7f81ed21941b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38752
53693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3875253693
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2666702908
Short name T140
Test name
Test status
Simulation time 233606874 ps
CPU time 0.98 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:44 PM PDT 24
Peak memory 207540 kb
Host smart-e4081220-5b34-4a3e-a4aa-e9c169a2e29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
02908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2666702908
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3372993713
Short name T681
Test name
Test status
Simulation time 190514078 ps
CPU time 0.92 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207512 kb
Host smart-34e550ea-a23c-4c8f-b2be-ab61ca49be1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
93713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3372993713
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3361852542
Short name T1544
Test name
Test status
Simulation time 160444325 ps
CPU time 0.83 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207616 kb
Host smart-d570388d-a874-4756-9135-5316572d51ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33618
52542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3361852542
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2737571993
Short name T2569
Test name
Test status
Simulation time 156728837 ps
CPU time 0.96 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207508 kb
Host smart-4d812d20-69cd-4536-a8a4-e79cf95204fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27375
71993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2737571993
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.794566344
Short name T184
Test name
Test status
Simulation time 148041246 ps
CPU time 0.89 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:44 PM PDT 24
Peak memory 207592 kb
Host smart-d56d92c2-30cf-4a22-9698-7d601cf5f179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79456
6344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.794566344
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.755630449
Short name T2187
Test name
Test status
Simulation time 215467889 ps
CPU time 1 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207604 kb
Host smart-2674f6be-f5c6-4c1d-875e-1aa15cfab10c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=755630449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.755630449
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.584038190
Short name T211
Test name
Test status
Simulation time 145791932 ps
CPU time 0.8 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207440 kb
Host smart-6aae2ac4-8306-4646-bba9-4730de42720a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58403
8190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.584038190
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.415833995
Short name T26
Test name
Test status
Simulation time 37678554 ps
CPU time 0.72 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:43 PM PDT 24
Peak memory 207512 kb
Host smart-4e65d45e-aac5-48d6-a2bb-4e7a1f034d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41583
3995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.415833995
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3416688989
Short name T2720
Test name
Test status
Simulation time 15230294746 ps
CPU time 35.36 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:20:19 PM PDT 24
Peak memory 216060 kb
Host smart-68f5155c-b9a0-4a24-9111-a0d479a749ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34166
88989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3416688989
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.507467116
Short name T916
Test name
Test status
Simulation time 162966532 ps
CPU time 0.91 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207560 kb
Host smart-4058ef83-a408-472f-bdfa-b656227bdc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50746
7116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.507467116
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3236306090
Short name T702
Test name
Test status
Simulation time 243442542 ps
CPU time 1 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207532 kb
Host smart-49f1112b-5d81-4019-91f3-73dcfb4f3253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
06090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3236306090
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2960474214
Short name T1406
Test name
Test status
Simulation time 247702641 ps
CPU time 0.97 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207564 kb
Host smart-447cb0de-e099-4cb3-8267-a7d6d211a9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29604
74214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2960474214
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1609803487
Short name T1148
Test name
Test status
Simulation time 156406536 ps
CPU time 0.86 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:45 PM PDT 24
Peak memory 207472 kb
Host smart-dd6f8650-ddd2-4b9a-a0d1-bac2c368fb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
03487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1609803487
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1065511640
Short name T1681
Test name
Test status
Simulation time 189880263 ps
CPU time 0.99 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207632 kb
Host smart-3e1fb7bd-602d-4817-a45d-8228c7ed3885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655
11640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1065511640
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1419422469
Short name T1723
Test name
Test status
Simulation time 168361188 ps
CPU time 0.87 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207568 kb
Host smart-4666c9a8-cea0-4b23-ad0a-e2e606e6318c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
22469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1419422469
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3733798933
Short name T3610
Test name
Test status
Simulation time 172512036 ps
CPU time 0.89 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207572 kb
Host smart-e504240f-1aed-4c16-a2a9-14bba87acc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337
98933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3733798933
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1449926918
Short name T2120
Test name
Test status
Simulation time 230818075 ps
CPU time 1.08 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207564 kb
Host smart-dba47a67-433b-47c7-9e78-371275f9d0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
26918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1449926918
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.695543747
Short name T3463
Test name
Test status
Simulation time 2871545518 ps
CPU time 28.87 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:20:15 PM PDT 24
Peak memory 224304 kb
Host smart-9f1e557f-163a-405a-af33-ec4d42a46837
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=695543747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.695543747
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1657880255
Short name T701
Test name
Test status
Simulation time 221782897 ps
CPU time 0.92 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207540 kb
Host smart-474bdb5f-e916-4772-a883-458480248384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578
80255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1657880255
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.332951056
Short name T1996
Test name
Test status
Simulation time 181116969 ps
CPU time 0.89 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207592 kb
Host smart-3478cb8c-72bc-486b-b52c-0d1d2938ebe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33295
1056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.332951056
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.4179054323
Short name T1429
Test name
Test status
Simulation time 775421308 ps
CPU time 2 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:09 PM PDT 24
Peak memory 207532 kb
Host smart-6e432f31-4b45-4138-9683-14878dbcdb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790
54323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.4179054323
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2624740952
Short name T1819
Test name
Test status
Simulation time 4329616335 ps
CPU time 126.2 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 217580 kb
Host smart-6134e922-fa9e-4202-b055-aba6296b492c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26247
40952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2624740952
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.1201627066
Short name T234
Test name
Test status
Simulation time 3828211528 ps
CPU time 32.63 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207852 kb
Host smart-a6c498ee-c306-4436-9f5f-a09d5b1d6b37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201627066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.1201627066
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.3944415467
Short name T2770
Test name
Test status
Simulation time 522541233 ps
CPU time 1.44 seconds
Started Aug 08 06:20:10 PM PDT 24
Finished Aug 08 06:20:12 PM PDT 24
Peak memory 207636 kb
Host smart-464a04b2-5ea0-4a17-b33e-39f107e3abae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944415467 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.3944415467
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.673960704
Short name T3604
Test name
Test status
Simulation time 467769806 ps
CPU time 1.44 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207548 kb
Host smart-d6b94ca3-947f-42aa-a789-31ecee0eceaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673960704 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.673960704
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.634508860
Short name T1536
Test name
Test status
Simulation time 432586459 ps
CPU time 1.42 seconds
Started Aug 08 06:22:40 PM PDT 24
Finished Aug 08 06:22:42 PM PDT 24
Peak memory 207572 kb
Host smart-468cb417-abdd-413e-b557-fa5387941913
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634508860 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.634508860
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.1205759982
Short name T1168
Test name
Test status
Simulation time 479911859 ps
CPU time 1.48 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:36 PM PDT 24
Peak memory 207508 kb
Host smart-432c15eb-681b-444b-8120-d14b3b9b3826
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205759982 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.1205759982
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.3725991834
Short name T1187
Test name
Test status
Simulation time 637189651 ps
CPU time 1.69 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:22:48 PM PDT 24
Peak memory 207592 kb
Host smart-5d683495-550e-4dec-8f98-a3f246a8fc00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725991834 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.3725991834
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.1158939626
Short name T1535
Test name
Test status
Simulation time 625728491 ps
CPU time 1.67 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207644 kb
Host smart-057561f5-61c4-441f-afbd-193bb96cb6c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158939626 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.1158939626
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.3754026376
Short name T165
Test name
Test status
Simulation time 594370077 ps
CPU time 1.67 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207556 kb
Host smart-d58f5ff3-43c3-4139-950d-1d4591e1c9d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754026376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.3754026376
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.3828819889
Short name T1434
Test name
Test status
Simulation time 491148570 ps
CPU time 1.56 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207520 kb
Host smart-ba2f22f8-5c54-46c3-96bf-07e94c2f7243
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828819889 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.3828819889
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.1513037738
Short name T2909
Test name
Test status
Simulation time 525174972 ps
CPU time 1.68 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207616 kb
Host smart-fe767a74-ee54-47c2-acc2-9bb2f0ae11b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513037738 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.1513037738
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.2602669372
Short name T3525
Test name
Test status
Simulation time 493489864 ps
CPU time 1.48 seconds
Started Aug 08 06:22:19 PM PDT 24
Finished Aug 08 06:22:21 PM PDT 24
Peak memory 207592 kb
Host smart-bbf539ff-7f1a-4606-8997-3e06a6cbb213
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602669372 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.2602669372
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.379960396
Short name T205
Test name
Test status
Simulation time 37081954 ps
CPU time 0.66 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207632 kb
Host smart-a3832617-46a7-429b-9f0e-d7eca319a8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=379960396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.379960396
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2299525376
Short name T2184
Test name
Test status
Simulation time 6291469408 ps
CPU time 9.73 seconds
Started Aug 08 06:19:48 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 216052 kb
Host smart-d3e66be7-408a-4a6f-81aa-ece7d7b438fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299525376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2299525376
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2325754705
Short name T3512
Test name
Test status
Simulation time 13473496422 ps
CPU time 15.89 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:20:12 PM PDT 24
Peak memory 216072 kb
Host smart-fdf1f0ee-6bbd-4d1d-9368-6cde1d61a058
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325754705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2325754705
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.982866365
Short name T2621
Test name
Test status
Simulation time 30570695764 ps
CPU time 34.67 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:39 PM PDT 24
Peak memory 207920 kb
Host smart-9503b694-8bfc-4a1c-9d93-bffb77b9b7d1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982866365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ao
n_wake_resume.982866365
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.209099116
Short name T1909
Test name
Test status
Simulation time 173848593 ps
CPU time 0.96 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207616 kb
Host smart-0cdea655-36af-4042-9209-7c6b78276298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
9116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.209099116
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3282511315
Short name T955
Test name
Test status
Simulation time 151197885 ps
CPU time 0.88 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207520 kb
Host smart-daca8995-b717-42ad-a6ae-49bf24b614b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
11315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3282511315
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3198974595
Short name T3588
Test name
Test status
Simulation time 407802753 ps
CPU time 1.49 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207544 kb
Host smart-b4e56439-b27c-4ac1-918a-086581e46d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
74595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3198974595
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.4224625876
Short name T2384
Test name
Test status
Simulation time 446165360 ps
CPU time 1.36 seconds
Started Aug 08 06:20:05 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207540 kb
Host smart-221ac4b6-a042-4067-b2b9-522a55d6de23
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4224625876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.4224625876
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1738018641
Short name T2510
Test name
Test status
Simulation time 36904530130 ps
CPU time 54.65 seconds
Started Aug 08 06:19:55 PM PDT 24
Finished Aug 08 06:20:50 PM PDT 24
Peak memory 207764 kb
Host smart-30464240-ddc9-4942-a05b-5dd1e2b0f0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380
18641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1738018641
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.4094367135
Short name T1268
Test name
Test status
Simulation time 4930844665 ps
CPU time 32.56 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:20:19 PM PDT 24
Peak memory 206664 kb
Host smart-b23c63be-fc70-47bc-8cb9-64b3eb63ebd7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094367135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.4094367135
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.354763748
Short name T2635
Test name
Test status
Simulation time 878557942 ps
CPU time 1.97 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207528 kb
Host smart-06e811ac-4bb4-4a93-84a3-be92cd9cf295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35476
3748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.354763748
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.708440726
Short name T69
Test name
Test status
Simulation time 157724380 ps
CPU time 0.82 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 206336 kb
Host smart-1001cdde-a67c-48e8-a8ad-524fb9a77ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70844
0726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.708440726
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2954172177
Short name T1472
Test name
Test status
Simulation time 55442358 ps
CPU time 0.71 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207524 kb
Host smart-d8c9ab8a-4bb9-4c06-b93f-d807f903c192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
72177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2954172177
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.625704549
Short name T501
Test name
Test status
Simulation time 887506551 ps
CPU time 2.53 seconds
Started Aug 08 06:20:03 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207748 kb
Host smart-514be51c-dbc7-43e6-8322-739687366a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62570
4549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.625704549
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3927145643
Short name T1425
Test name
Test status
Simulation time 442677462 ps
CPU time 2.69 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207780 kb
Host smart-d3f8b56f-a004-4542-af07-ef067d0ba53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
45643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3927145643
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3537594047
Short name T3460
Test name
Test status
Simulation time 228544514 ps
CPU time 1.1 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:41 PM PDT 24
Peak memory 215964 kb
Host smart-f8d79e84-e122-4774-99fb-1719d11cf889
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3537594047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3537594047
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1606670835
Short name T720
Test name
Test status
Simulation time 143300526 ps
CPU time 0.78 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 207436 kb
Host smart-dd20fa6f-d89e-43fa-95b7-77a27d6e7dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
70835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1606670835
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2759703065
Short name T2707
Test name
Test status
Simulation time 227118937 ps
CPU time 1 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207528 kb
Host smart-a4999c34-1683-47e9-8e46-294b1f7d7c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
03065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2759703065
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3657047320
Short name T2052
Test name
Test status
Simulation time 4286300089 ps
CPU time 43.43 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 218036 kb
Host smart-01c3ff40-73ea-40b2-96ce-71e58df60975
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3657047320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3657047320
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.3373605881
Short name T990
Test name
Test status
Simulation time 6947981391 ps
CPU time 47.21 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207808 kb
Host smart-60edf3e9-1cfc-4659-8f21-14aee1be0f53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3373605881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.3373605881
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.71996873
Short name T1711
Test name
Test status
Simulation time 221714755 ps
CPU time 0.99 seconds
Started Aug 08 06:19:43 PM PDT 24
Finished Aug 08 06:19:44 PM PDT 24
Peak memory 207524 kb
Host smart-8e732a12-f373-467f-9aac-ac6a376adace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71996
873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.71996873
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.761180254
Short name T210
Test name
Test status
Simulation time 30982943559 ps
CPU time 46.57 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:20:38 PM PDT 24
Peak memory 207760 kb
Host smart-9d9ef409-578f-4acd-8e81-8a26c4a2a830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76118
0254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.761180254
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.903358288
Short name T208
Test name
Test status
Simulation time 8619216800 ps
CPU time 11 seconds
Started Aug 08 06:19:44 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207836 kb
Host smart-7883dd93-d2a4-4aeb-8628-c8feb5d45da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90335
8288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.903358288
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.230458153
Short name T1423
Test name
Test status
Simulation time 6732330510 ps
CPU time 64.16 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:21:00 PM PDT 24
Peak memory 224208 kb
Host smart-8ac5b8a1-7b28-4ba9-ac53-27c9160607c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23045
8153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.230458153
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1723575383
Short name T2870
Test name
Test status
Simulation time 2069051298 ps
CPU time 57.54 seconds
Started Aug 08 06:19:49 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 215944 kb
Host smart-05eb78af-f362-4d88-927b-e3d61a400af3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1723575383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1723575383
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1504940444
Short name T2610
Test name
Test status
Simulation time 244879925 ps
CPU time 1.09 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207612 kb
Host smart-f62f432e-f39e-4fd2-91ac-e6c13c7d1573
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1504940444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1504940444
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1113843074
Short name T2336
Test name
Test status
Simulation time 209899363 ps
CPU time 0.98 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207508 kb
Host smart-8bb25d32-5c8b-4ff5-83c4-34f5c216f9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
43074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1113843074
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.695599115
Short name T169
Test name
Test status
Simulation time 2359575789 ps
CPU time 23.59 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 218048 kb
Host smart-e412b25f-8fa1-45d4-a5e7-9b577b74cb0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=695599115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.695599115
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1488784397
Short name T2425
Test name
Test status
Simulation time 166548037 ps
CPU time 0.89 seconds
Started Aug 08 06:20:05 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207788 kb
Host smart-3a99e5f3-dd60-4ffa-981b-813e4ebf53e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1488784397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1488784397
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1536172098
Short name T3497
Test name
Test status
Simulation time 178503730 ps
CPU time 0.86 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207608 kb
Host smart-f8c2b70e-1af3-4dab-9f5b-dd0a137ecddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15361
72098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1536172098
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3841491428
Short name T153
Test name
Test status
Simulation time 172675512 ps
CPU time 0.96 seconds
Started Aug 08 06:20:04 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 207540 kb
Host smart-8314e4eb-4143-472c-a695-8bd850e45be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38414
91428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3841491428
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2030604463
Short name T1054
Test name
Test status
Simulation time 218967902 ps
CPU time 1 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207536 kb
Host smart-765cbcd1-59ab-4822-beee-9293ccb2c0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
04463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2030604463
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.332680004
Short name T3195
Test name
Test status
Simulation time 148398087 ps
CPU time 0.8 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207468 kb
Host smart-594a6360-6627-448c-bbf9-2a8c9716b089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
0004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.332680004
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2099273327
Short name T1128
Test name
Test status
Simulation time 183669685 ps
CPU time 0.89 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207624 kb
Host smart-12064fcd-231a-4a4f-bc4c-6b74e52345ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20992
73327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2099273327
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1265094052
Short name T2016
Test name
Test status
Simulation time 215751642 ps
CPU time 0.91 seconds
Started Aug 08 06:19:40 PM PDT 24
Finished Aug 08 06:19:42 PM PDT 24
Peak memory 207580 kb
Host smart-37f613c0-6005-468f-bfa1-13eac1c6743e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650
94052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1265094052
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2799369067
Short name T1858
Test name
Test status
Simulation time 235294992 ps
CPU time 1.04 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:19:47 PM PDT 24
Peak memory 207532 kb
Host smart-8eb2de98-6eac-41ae-8ed7-42e663f4fdf6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2799369067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2799369067
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3496435019
Short name T1885
Test name
Test status
Simulation time 143145587 ps
CPU time 0.82 seconds
Started Aug 08 06:19:45 PM PDT 24
Finished Aug 08 06:19:46 PM PDT 24
Peak memory 207504 kb
Host smart-5de7d04e-52e0-4e55-b7aa-c318dbb87fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34964
35019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3496435019
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2865614499
Short name T2110
Test name
Test status
Simulation time 34485643 ps
CPU time 0.65 seconds
Started Aug 08 06:19:51 PM PDT 24
Finished Aug 08 06:19:52 PM PDT 24
Peak memory 207508 kb
Host smart-94996c7d-8bab-48b7-af05-044ccdc11f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28656
14499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2865614499
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3818400864
Short name T2682
Test name
Test status
Simulation time 17086128393 ps
CPU time 44.47 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 216032 kb
Host smart-7a2db8bf-633c-4d7f-b6d4-8aac1658824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38184
00864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3818400864
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.238013982
Short name T2915
Test name
Test status
Simulation time 186579916 ps
CPU time 0.94 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207532 kb
Host smart-41d962d5-54ff-4bc0-a7ab-006199133223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23801
3982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.238013982
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2174613735
Short name T2729
Test name
Test status
Simulation time 250594254 ps
CPU time 1.01 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207544 kb
Host smart-243c3b85-3c95-4cb4-ba68-9c75c169eb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21746
13735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2174613735
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3531637234
Short name T1743
Test name
Test status
Simulation time 187344040 ps
CPU time 0.92 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207656 kb
Host smart-eb769fa5-7d08-47fa-bec8-76d4784c3f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
37234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3531637234
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2952353196
Short name T1779
Test name
Test status
Simulation time 184642671 ps
CPU time 0.95 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207564 kb
Host smart-5a80d255-5f7e-4e91-81b1-b2489cc59c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
53196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2952353196
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1616560367
Short name T930
Test name
Test status
Simulation time 192840186 ps
CPU time 0.91 seconds
Started Aug 08 06:20:05 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207600 kb
Host smart-f6d67733-0aa5-4239-b14e-aed8eb2f5500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16165
60367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1616560367
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.2008875869
Short name T1156
Test name
Test status
Simulation time 376662340 ps
CPU time 1.3 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207536 kb
Host smart-5fa509b0-d593-4e2c-ba1a-0eee742eefb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
75869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.2008875869
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.426298241
Short name T1412
Test name
Test status
Simulation time 161389382 ps
CPU time 0.85 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207552 kb
Host smart-c0e64853-bc5f-4470-a0a9-77d913e21ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
8241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.426298241
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3444800634
Short name T1866
Test name
Test status
Simulation time 172970972 ps
CPU time 0.86 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207620 kb
Host smart-0d373b98-302f-4c91-995c-335ba85751f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34448
00634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3444800634
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1827779894
Short name T2712
Test name
Test status
Simulation time 263619929 ps
CPU time 1.08 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207556 kb
Host smart-95a4f813-2115-47c7-add2-18ebab7dee65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18277
79894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1827779894
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3869074436
Short name T2944
Test name
Test status
Simulation time 2611925150 ps
CPU time 19.68 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:20:16 PM PDT 24
Peak memory 224252 kb
Host smart-04042290-d07c-4fb1-a226-7996b44fe747
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3869074436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3869074436
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1672813659
Short name T1698
Test name
Test status
Simulation time 214281760 ps
CPU time 0.95 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207632 kb
Host smart-30911036-ee92-4d5c-a76b-55400c7324c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
13659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1672813659
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2888127658
Short name T3566
Test name
Test status
Simulation time 164429408 ps
CPU time 0.84 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207588 kb
Host smart-5a63026c-bd82-4bc9-aacb-6250d8913284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
27658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2888127658
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.4204286757
Short name T2231
Test name
Test status
Simulation time 1277738337 ps
CPU time 2.88 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:15 PM PDT 24
Peak memory 207712 kb
Host smart-b75bc6e3-7563-412a-a95b-0e88683e614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042
86757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.4204286757
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3513953913
Short name T1333
Test name
Test status
Simulation time 1645770331 ps
CPU time 17.31 seconds
Started Aug 08 06:20:08 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 217404 kb
Host smart-af13281d-3240-44d0-9044-947371c27e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
53913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3513953913
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1334623351
Short name T1478
Test name
Test status
Simulation time 1331472413 ps
CPU time 29.69 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207664 kb
Host smart-2156a923-6ecd-47c6-b64c-39aa23311f4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334623351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1334623351
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.3357963409
Short name T884
Test name
Test status
Simulation time 567828937 ps
CPU time 1.64 seconds
Started Aug 08 06:19:51 PM PDT 24
Finished Aug 08 06:19:53 PM PDT 24
Peak memory 207620 kb
Host smart-5ea51041-8fa2-4087-a95e-f3a9ab5a2dad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357963409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.3357963409
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.871495943
Short name T3136
Test name
Test status
Simulation time 470638105 ps
CPU time 1.41 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207560 kb
Host smart-749edf6a-54f4-4918-87df-5220632aa409
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871495943 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.871495943
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.1953740228
Short name T1777
Test name
Test status
Simulation time 513118797 ps
CPU time 1.62 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207504 kb
Host smart-f23d895f-9438-465b-a548-0cfa5b1730f0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953740228 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.1953740228
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.3965675811
Short name T2904
Test name
Test status
Simulation time 592165636 ps
CPU time 1.67 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207564 kb
Host smart-600fca12-9b46-42a5-96a4-523c08f347ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965675811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.3965675811
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.2278186427
Short name T1611
Test name
Test status
Simulation time 557910118 ps
CPU time 1.68 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:22:49 PM PDT 24
Peak memory 207516 kb
Host smart-e14f33f6-98fe-4ced-85ca-45fbabf8e399
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278186427 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2278186427
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.983636106
Short name T1311
Test name
Test status
Simulation time 587218510 ps
CPU time 1.62 seconds
Started Aug 08 06:22:21 PM PDT 24
Finished Aug 08 06:22:23 PM PDT 24
Peak memory 207548 kb
Host smart-ab310738-74d6-4691-9291-684861860262
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983636106 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.983636106
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.3725120284
Short name T2205
Test name
Test status
Simulation time 645286048 ps
CPU time 1.8 seconds
Started Aug 08 06:22:48 PM PDT 24
Finished Aug 08 06:22:55 PM PDT 24
Peak memory 207520 kb
Host smart-c0a7c949-4b36-4d41-ae69-552bca9e4697
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725120284 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.3725120284
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.2996633075
Short name T1129
Test name
Test status
Simulation time 635993880 ps
CPU time 1.69 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207604 kb
Host smart-b5336cde-01d1-4cbe-be3b-b6e5adc98e18
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996633075 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.2996633075
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.213666353
Short name T1206
Test name
Test status
Simulation time 504348730 ps
CPU time 1.55 seconds
Started Aug 08 06:22:29 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207580 kb
Host smart-6f26befe-2c20-40fc-81b3-c757de9015a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213666353 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.213666353
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.1882523545
Short name T1841
Test name
Test status
Simulation time 499170009 ps
CPU time 1.52 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207552 kb
Host smart-10d1b828-de22-46a6-9984-7ed4050412d0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882523545 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.1882523545
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.876024970
Short name T530
Test name
Test status
Simulation time 594576621 ps
CPU time 1.61 seconds
Started Aug 08 06:22:53 PM PDT 24
Finished Aug 08 06:22:55 PM PDT 24
Peak memory 207616 kb
Host smart-c6e5e0be-2327-4102-8db5-3269d15b7056
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876024970 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.876024970
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1049935470
Short name T1342
Test name
Test status
Simulation time 33852799 ps
CPU time 0.66 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207576 kb
Host smart-6b73523f-4c34-4961-b3b8-b2d0a7fc966c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1049935470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1049935470
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3615686485
Short name T3323
Test name
Test status
Simulation time 11021089860 ps
CPU time 13.99 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 207856 kb
Host smart-b7e7cf01-d62b-4c22-ae97-69c1b59a7a27
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615686485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.3615686485
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3175248531
Short name T105
Test name
Test status
Simulation time 14543473206 ps
CPU time 16.16 seconds
Started Aug 08 06:20:00 PM PDT 24
Finished Aug 08 06:20:16 PM PDT 24
Peak memory 215976 kb
Host smart-907097b4-bf43-4f43-85d8-b83384a3d927
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175248531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3175248531
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.4048427337
Short name T1837
Test name
Test status
Simulation time 23737749672 ps
CPU time 26.89 seconds
Started Aug 08 06:19:55 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 216276 kb
Host smart-9b8ecdf9-0a3d-450b-b988-7ad1493bf811
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048427337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.4048427337
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1401146448
Short name T1904
Test name
Test status
Simulation time 185616867 ps
CPU time 0.93 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207520 kb
Host smart-d30a6479-47c4-41ad-b347-7a6957e4b2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
46448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1401146448
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.230707705
Short name T1553
Test name
Test status
Simulation time 150320577 ps
CPU time 0.83 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207560 kb
Host smart-d9b90b5d-fa2b-432f-95ec-760ed553cc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23070
7705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.230707705
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1763595908
Short name T726
Test name
Test status
Simulation time 333852593 ps
CPU time 1.28 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207488 kb
Host smart-c1ce0f80-5bcf-4789-b6f9-7355035e53a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17635
95908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1763595908
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2118272117
Short name T967
Test name
Test status
Simulation time 537445910 ps
CPU time 1.53 seconds
Started Aug 08 06:19:52 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207520 kb
Host smart-07257b67-b631-4e9f-b159-af1e126b2e2c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2118272117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2118272117
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.2134786517
Short name T1439
Test name
Test status
Simulation time 4313982972 ps
CPU time 28 seconds
Started Aug 08 06:20:05 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207808 kb
Host smart-83bdb0f0-162c-4d1d-ac57-69f485481fbd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134786517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.2134786517
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.2613385789
Short name T706
Test name
Test status
Simulation time 879694548 ps
CPU time 1.97 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207540 kb
Host smart-c0f4e139-0fcf-41ca-a28c-555cf7b8e72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26133
85789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.2613385789
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.4260859880
Short name T1881
Test name
Test status
Simulation time 147032588 ps
CPU time 0.87 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207552 kb
Host smart-a434217c-33e5-4335-8c50-2a2983d5d5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
59880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.4260859880
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1940423149
Short name T3562
Test name
Test status
Simulation time 36321709 ps
CPU time 0.7 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 207544 kb
Host smart-ee260769-6602-48f6-8be4-727d7ddcd13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
23149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1940423149
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.765276068
Short name T2399
Test name
Test status
Simulation time 893818606 ps
CPU time 2.63 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207788 kb
Host smart-50b58d79-1d41-48a9-86f3-bcb3841c3b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76527
6068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.765276068
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.319939836
Short name T2882
Test name
Test status
Simulation time 316868101 ps
CPU time 1.13 seconds
Started Aug 08 06:19:47 PM PDT 24
Finished Aug 08 06:19:48 PM PDT 24
Peak memory 207496 kb
Host smart-ee311e44-fc6c-4130-a999-feb5d6f53df6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=319939836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.319939836
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1059174472
Short name T1159
Test name
Test status
Simulation time 350917323 ps
CPU time 2.53 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 207824 kb
Host smart-6f9f80df-2dc6-4bc1-bf0d-6b3b2fd3ff2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10591
74472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1059174472
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3439398845
Short name T1157
Test name
Test status
Simulation time 192404532 ps
CPU time 1.13 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 215996 kb
Host smart-6ce1f756-2b6e-47be-a327-80533b744164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3439398845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3439398845
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1843173957
Short name T1982
Test name
Test status
Simulation time 156596930 ps
CPU time 0.82 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207536 kb
Host smart-8b36be61-5801-47ef-8942-9e236579bb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1843173957
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.714958536
Short name T2152
Test name
Test status
Simulation time 197796232 ps
CPU time 0.93 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:09 PM PDT 24
Peak memory 207588 kb
Host smart-123b505d-6cb6-4db7-b470-cb76c41c7709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71495
8536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.714958536
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.4042872459
Short name T1354
Test name
Test status
Simulation time 3028353709 ps
CPU time 21.77 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:20:15 PM PDT 24
Peak memory 216132 kb
Host smart-4c8fb479-9b76-4448-964a-8289b93504ac
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4042872459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.4042872459
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.717204267
Short name T2401
Test name
Test status
Simulation time 5256559086 ps
CPU time 34.25 seconds
Started Aug 08 06:19:55 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207832 kb
Host smart-921a5a95-ad89-41f7-9f93-ae6f42f913ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=717204267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.717204267
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3880612941
Short name T711
Test name
Test status
Simulation time 219914681 ps
CPU time 0.97 seconds
Started Aug 08 06:20:03 PM PDT 24
Finished Aug 08 06:20:04 PM PDT 24
Peak memory 207560 kb
Host smart-36560509-5261-40e2-990b-575d76b6080d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
12941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3880612941
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1169908844
Short name T559
Test name
Test status
Simulation time 9127260573 ps
CPU time 12.8 seconds
Started Aug 08 06:19:50 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207792 kb
Host smart-6bba99d7-4486-4775-ad52-468dd38cc464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699
08844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1169908844
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3161734442
Short name T974
Test name
Test status
Simulation time 3646307649 ps
CPU time 5.23 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 216796 kb
Host smart-8a9223d0-5034-4b94-8272-f43a16145c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
34442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3161734442
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.258871055
Short name T3446
Test name
Test status
Simulation time 3270649631 ps
CPU time 24.94 seconds
Started Aug 08 06:20:12 PM PDT 24
Finished Aug 08 06:20:38 PM PDT 24
Peak memory 216124 kb
Host smart-5ff5ddc5-199f-431d-9f12-e96cb667c549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25887
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.258871055
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1912363621
Short name T2342
Test name
Test status
Simulation time 2471593468 ps
CPU time 18.47 seconds
Started Aug 08 06:19:46 PM PDT 24
Finished Aug 08 06:20:05 PM PDT 24
Peak memory 207912 kb
Host smart-4e0effcb-b3eb-4002-bf1a-23cfaf7dfff4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1912363621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1912363621
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1190751549
Short name T1640
Test name
Test status
Simulation time 240492311 ps
CPU time 1.06 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207540 kb
Host smart-a574f55d-8d23-4be4-abff-433ba438d786
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1190751549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1190751549
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1407360231
Short name T2172
Test name
Test status
Simulation time 196565667 ps
CPU time 1.01 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:59 PM PDT 24
Peak memory 207476 kb
Host smart-6001bffe-1ad0-47cb-abaf-b8b59822314e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
60231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1407360231
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1988179256
Short name T3515
Test name
Test status
Simulation time 2803726028 ps
CPU time 20.41 seconds
Started Aug 08 06:20:11 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 224288 kb
Host smart-9061ad78-be80-43ef-a3ae-3e60cd94e385
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1988179256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1988179256
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3139202542
Short name T3063
Test name
Test status
Simulation time 149914372 ps
CPU time 0.8 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207584 kb
Host smart-0bc3d219-a3b9-4aa8-9bae-2d59f71473f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3139202542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3139202542
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2871612356
Short name T1701
Test name
Test status
Simulation time 143371094 ps
CPU time 0.82 seconds
Started Aug 08 06:20:00 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207596 kb
Host smart-b83af725-599e-4b17-9477-6f0fac778691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28716
12356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2871612356
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.849751572
Short name T148
Test name
Test status
Simulation time 210901134 ps
CPU time 0.99 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207580 kb
Host smart-86bddb1e-d4a7-4abf-81c3-72f1a3a81d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84975
1572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.849751572
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.419129908
Short name T1388
Test name
Test status
Simulation time 171948720 ps
CPU time 0.98 seconds
Started Aug 08 06:19:51 PM PDT 24
Finished Aug 08 06:19:52 PM PDT 24
Peak memory 207612 kb
Host smart-7147f3a6-6288-4f39-9242-258d3a6e183d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
9908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.419129908
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4293095225
Short name T2714
Test name
Test status
Simulation time 193031747 ps
CPU time 0.98 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207584 kb
Host smart-4c003f36-bbf2-4f85-807c-657ee8460f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42930
95225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4293095225
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4171651195
Short name T253
Test name
Test status
Simulation time 207244680 ps
CPU time 0.93 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207580 kb
Host smart-d38da5c0-fe48-4e40-a847-f03ca27653d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41716
51195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4171651195
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2604335101
Short name T1929
Test name
Test status
Simulation time 155639627 ps
CPU time 0.83 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 207516 kb
Host smart-4b1bef04-1349-42ec-9663-e827592cacdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26043
35101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2604335101
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.637272031
Short name T2806
Test name
Test status
Simulation time 221878602 ps
CPU time 0.93 seconds
Started Aug 08 06:20:12 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 207592 kb
Host smart-732e357a-5170-4960-84ec-e4ea21cb576b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=637272031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.637272031
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.4043011245
Short name T3421
Test name
Test status
Simulation time 151917517 ps
CPU time 0.81 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:19:54 PM PDT 24
Peak memory 207532 kb
Host smart-132f536f-5478-4257-bb86-dff66eb48d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430
11245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.4043011245
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4203731080
Short name T3045
Test name
Test status
Simulation time 15823955120 ps
CPU time 40.18 seconds
Started Aug 08 06:19:53 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 220060 kb
Host smart-06e3bd0a-66c0-4386-b5ff-c3fbc88fea46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42037
31080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4203731080
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3405722833
Short name T2835
Test name
Test status
Simulation time 205516744 ps
CPU time 0.98 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207548 kb
Host smart-57768bf9-24bd-4935-8873-ab84a7fa4c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
22833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3405722833
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3041656069
Short name T1362
Test name
Test status
Simulation time 186059111 ps
CPU time 0.93 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:19:55 PM PDT 24
Peak memory 207508 kb
Host smart-0ec5d534-db2a-4613-8d27-a7dc02960060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30416
56069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3041656069
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2918183738
Short name T2586
Test name
Test status
Simulation time 213826229 ps
CPU time 0.95 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207616 kb
Host smart-410ce947-95ee-4d3a-8734-af17d7c67880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29181
83738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2918183738
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2318038977
Short name T1682
Test name
Test status
Simulation time 169453632 ps
CPU time 0.89 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:03 PM PDT 24
Peak memory 207612 kb
Host smart-1bb14785-1752-4fde-814f-3c633a07a6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
38977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2318038977
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1982059786
Short name T2771
Test name
Test status
Simulation time 196780366 ps
CPU time 1 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207508 kb
Host smart-a3b6b968-ec32-44df-a189-11b3d2f88314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19820
59786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1982059786
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.3231821408
Short name T325
Test name
Test status
Simulation time 378063849 ps
CPU time 1.22 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207548 kb
Host smart-4ec76aa3-b907-44f1-a937-94e93a20c0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
21408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3231821408
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1807664028
Short name T2268
Test name
Test status
Simulation time 159422454 ps
CPU time 0.91 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207476 kb
Host smart-823ee684-3cdd-4d14-86c7-ab4087d11504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18076
64028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1807664028
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2664384515
Short name T121
Test name
Test status
Simulation time 157523497 ps
CPU time 0.86 seconds
Started Aug 08 06:19:55 PM PDT 24
Finished Aug 08 06:19:56 PM PDT 24
Peak memory 207620 kb
Host smart-c08f88ce-5d8d-4820-acfc-569a276d7fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26643
84515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2664384515
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2357228593
Short name T1928
Test name
Test status
Simulation time 207291141 ps
CPU time 0.98 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 207496 kb
Host smart-756fbd70-639e-40bf-bda0-5a467e8df398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23572
28593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2357228593
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2126372992
Short name T2073
Test name
Test status
Simulation time 3871787769 ps
CPU time 30.4 seconds
Started Aug 08 06:20:02 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 217988 kb
Host smart-ce70deff-c5a3-46c2-9e00-c7efbdc65fa6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2126372992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2126372992
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3571699126
Short name T1820
Test name
Test status
Simulation time 174715045 ps
CPU time 0.87 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:02 PM PDT 24
Peak memory 207480 kb
Host smart-c6a6895d-06e6-4b73-a64b-f2ca107a7e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35716
99126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3571699126
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3801905235
Short name T678
Test name
Test status
Simulation time 217195443 ps
CPU time 0.93 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207500 kb
Host smart-810d5d54-5330-4a5a-86ed-4b7ac7bf9e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019
05235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3801905235
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.1851593783
Short name T2757
Test name
Test status
Simulation time 898070498 ps
CPU time 2.17 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207692 kb
Host smart-5fe1e384-efc8-4920-a086-8a61a36d0e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
93783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.1851593783
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.327999877
Short name T972
Test name
Test status
Simulation time 1777373142 ps
CPU time 13.52 seconds
Started Aug 08 06:19:54 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 217364 kb
Host smart-a7d2664c-b64e-4d91-bf18-43160a8117f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799
9877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.327999877
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.1433849189
Short name T2397
Test name
Test status
Simulation time 741568626 ps
CPU time 14.43 seconds
Started Aug 08 06:19:56 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207760 kb
Host smart-0eb0a62c-1a2b-4d44-84d3-b1f761bdc576
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433849189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.1433849189
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.2142184892
Short name T1145
Test name
Test status
Simulation time 491746417 ps
CPU time 1.58 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 207492 kb
Host smart-b909addf-97e2-4132-a9e0-007f01a79dc9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142184892 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.2142184892
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.587351541
Short name T1853
Test name
Test status
Simulation time 636353528 ps
CPU time 1.76 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207604 kb
Host smart-9a2f6b9e-7a83-4d04-8bf2-d905ddb72ebe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587351541 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.587351541
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.2184768060
Short name T579
Test name
Test status
Simulation time 452169726 ps
CPU time 1.4 seconds
Started Aug 08 06:22:50 PM PDT 24
Finished Aug 08 06:22:52 PM PDT 24
Peak memory 207592 kb
Host smart-ee30a825-7f97-4769-b357-3a61376ddab5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184768060 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.2184768060
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.3991595993
Short name T2644
Test name
Test status
Simulation time 591596067 ps
CPU time 1.72 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207556 kb
Host smart-0665b6ec-ef69-4c52-b12b-912874b05c62
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991595993 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.3991595993
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.1416770893
Short name T1355
Test name
Test status
Simulation time 584699639 ps
CPU time 1.63 seconds
Started Aug 08 06:22:26 PM PDT 24
Finished Aug 08 06:22:28 PM PDT 24
Peak memory 207572 kb
Host smart-e1910177-4369-4c57-bc6c-6388710f9e42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416770893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.1416770893
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.2863146978
Short name T168
Test name
Test status
Simulation time 475101326 ps
CPU time 1.52 seconds
Started Aug 08 06:22:27 PM PDT 24
Finished Aug 08 06:22:29 PM PDT 24
Peak memory 207556 kb
Host smart-153ba151-e948-42f2-b3a3-5d3d7b56ba5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863146978 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.2863146978
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.3404929886
Short name T3306
Test name
Test status
Simulation time 526743108 ps
CPU time 1.63 seconds
Started Aug 08 06:22:40 PM PDT 24
Finished Aug 08 06:22:42 PM PDT 24
Peak memory 207548 kb
Host smart-beadd208-0f5b-47b4-bb34-7657b7c5c806
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404929886 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3404929886
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.2892549164
Short name T2985
Test name
Test status
Simulation time 502047766 ps
CPU time 1.68 seconds
Started Aug 08 06:23:01 PM PDT 24
Finished Aug 08 06:23:02 PM PDT 24
Peak memory 207524 kb
Host smart-0c203f03-a891-408d-94aa-0612afb6b974
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892549164 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.2892549164
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.1640183899
Short name T942
Test name
Test status
Simulation time 457088299 ps
CPU time 1.48 seconds
Started Aug 08 06:22:31 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207492 kb
Host smart-2962d4d3-bdbe-4ec2-bca7-eb67dcaa8067
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640183899 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.1640183899
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.2558272478
Short name T3540
Test name
Test status
Simulation time 683071450 ps
CPU time 1.85 seconds
Started Aug 08 06:22:31 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207612 kb
Host smart-ec0ec559-75e1-4459-8293-219657b0d3ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558272478 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.2558272478
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.857396867
Short name T3164
Test name
Test status
Simulation time 501980320 ps
CPU time 1.55 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207600 kb
Host smart-8f56bdc3-745b-4bd3-8577-7176e313623a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857396867 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.857396867
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3486680174
Short name T3161
Test name
Test status
Simulation time 35586845 ps
CPU time 0.65 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207628 kb
Host smart-22192ee9-ed10-4683-ac17-b859e8ad8237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3486680174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3486680174
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3637663647
Short name T1818
Test name
Test status
Simulation time 10488847763 ps
CPU time 12.94 seconds
Started Aug 08 06:20:13 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207896 kb
Host smart-dc4def57-52ba-47df-bf32-a57b80276e9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637663647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.3637663647
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2365660112
Short name T2311
Test name
Test status
Simulation time 20180713362 ps
CPU time 23.6 seconds
Started Aug 08 06:19:59 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207816 kb
Host smart-9e8f159d-bffe-4901-bc44-b7e4bc489db5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365660112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2365660112
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.4142555950
Short name T710
Test name
Test status
Simulation time 28716769897 ps
CPU time 41 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:48 PM PDT 24
Peak memory 207856 kb
Host smart-b79e6f2f-05a7-4021-b2df-a463e00dc6e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142555950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.4142555950
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.645031557
Short name T3241
Test name
Test status
Simulation time 155993494 ps
CPU time 0.85 seconds
Started Aug 08 06:20:11 PM PDT 24
Finished Aug 08 06:20:12 PM PDT 24
Peak memory 207592 kb
Host smart-284919b2-4d38-4643-a2d8-3c4aabab4af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64503
1557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.645031557
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.635377031
Short name T1594
Test name
Test status
Simulation time 153716107 ps
CPU time 0.83 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207512 kb
Host smart-ad743e8d-1e8d-4886-bf2e-109c86cfa6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63537
7031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.635377031
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.362347140
Short name T1138
Test name
Test status
Simulation time 272534701 ps
CPU time 1.13 seconds
Started Aug 08 06:20:08 PM PDT 24
Finished Aug 08 06:20:09 PM PDT 24
Peak memory 207592 kb
Host smart-82207b4f-8ab1-4979-9cdf-d5db65007ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36234
7140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.362347140
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3373332558
Short name T2744
Test name
Test status
Simulation time 828308451 ps
CPU time 2.21 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:11 PM PDT 24
Peak memory 207748 kb
Host smart-f1390c6e-8ffa-4549-865c-3fc0d1d0e0d1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3373332558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3373332558
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2591102599
Short name T2371
Test name
Test status
Simulation time 24709937861 ps
CPU time 36.31 seconds
Started Aug 08 06:20:16 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207824 kb
Host smart-595b5446-3162-4ee8-be28-e67cbcd36aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
02599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2591102599
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.3876588119
Short name T3570
Test name
Test status
Simulation time 3871954288 ps
CPU time 34.15 seconds
Started Aug 08 06:20:01 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207808 kb
Host smart-5b356fe9-c0f2-4b77-8c41-b67c20884c29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876588119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.3876588119
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1418029545
Short name T1166
Test name
Test status
Simulation time 1198337664 ps
CPU time 2.32 seconds
Started Aug 08 06:20:10 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 207492 kb
Host smart-2c6f02e7-88a8-4867-bb1f-4ff2c36ea73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
29545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1418029545
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.122241139
Short name T2630
Test name
Test status
Simulation time 154040292 ps
CPU time 0.83 seconds
Started Aug 08 06:20:08 PM PDT 24
Finished Aug 08 06:20:09 PM PDT 24
Peak memory 207508 kb
Host smart-d10a4da4-a396-4fb9-8dc6-8b82c14b3fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12224
1139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.122241139
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3237987131
Short name T3166
Test name
Test status
Simulation time 39465272 ps
CPU time 0.68 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207484 kb
Host smart-e329cd34-1abc-42d6-808b-9cb110528bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32379
87131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3237987131
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.4200601236
Short name T1096
Test name
Test status
Simulation time 863225705 ps
CPU time 2.34 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:00 PM PDT 24
Peak memory 207844 kb
Host smart-3df8f097-3c80-4a4a-ad08-ebf662908812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42006
01236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.4200601236
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.1383782006
Short name T417
Test name
Test status
Simulation time 526987036 ps
CPU time 1.5 seconds
Started Aug 08 06:19:57 PM PDT 24
Finished Aug 08 06:19:58 PM PDT 24
Peak memory 207548 kb
Host smart-5a2f8b52-d1dc-48f4-8d43-e0f1f829c5cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1383782006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.1383782006
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1232452513
Short name T656
Test name
Test status
Simulation time 248140348 ps
CPU time 2.03 seconds
Started Aug 08 06:19:58 PM PDT 24
Finished Aug 08 06:20:01 PM PDT 24
Peak memory 207716 kb
Host smart-cf31fdd5-ae10-40d4-a392-59e0530bebdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
52513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1232452513
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2021524537
Short name T2337
Test name
Test status
Simulation time 153681784 ps
CPU time 0.85 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207528 kb
Host smart-f6dc1b03-0d2b-4cb0-8086-162cb6628079
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2021524537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2021524537
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1764466816
Short name T3206
Test name
Test status
Simulation time 145270384 ps
CPU time 0.82 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207560 kb
Host smart-50ed7991-17c3-4dbc-838a-a6513c73af66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
66816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1764466816
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1725746892
Short name T1277
Test name
Test status
Simulation time 202962504 ps
CPU time 0.96 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207564 kb
Host smart-d938f11e-fa91-469f-ab53-e38ddc35156e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17257
46892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1725746892
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.4206181211
Short name T946
Test name
Test status
Simulation time 4003879530 ps
CPU time 112.63 seconds
Started Aug 08 06:20:06 PM PDT 24
Finished Aug 08 06:21:59 PM PDT 24
Peak memory 218132 kb
Host smart-c795cd0d-d5a6-4126-a161-7b271d4ef9d7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4206181211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.4206181211
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.33195048
Short name T1761
Test name
Test status
Simulation time 10401553864 ps
CPU time 128.1 seconds
Started Aug 08 06:20:10 PM PDT 24
Finished Aug 08 06:22:18 PM PDT 24
Peak memory 207884 kb
Host smart-ad7f18c2-02b1-45a2-8ea0-a1086dde976e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=33195048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.33195048
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2103059097
Short name T1887
Test name
Test status
Simulation time 216032700 ps
CPU time 1.03 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207560 kb
Host smart-e60bbd43-9401-4d32-9aeb-868170de99f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
59097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2103059097
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.240527135
Short name T818
Test name
Test status
Simulation time 30969028010 ps
CPU time 45.4 seconds
Started Aug 08 06:20:06 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207880 kb
Host smart-af2b39e9-77d7-4d6c-b814-2490e1217fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24052
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.240527135
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3093282503
Short name T1678
Test name
Test status
Simulation time 10761069265 ps
CPU time 13.73 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:21 PM PDT 24
Peak memory 207884 kb
Host smart-88760015-6f03-4149-b867-75f7326c2abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
82503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3093282503
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3671308641
Short name T1204
Test name
Test status
Simulation time 3198117106 ps
CPU time 86.59 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 218468 kb
Host smart-392423e3-7338-4592-ba90-4aea06d081fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
08641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3671308641
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.4218552085
Short name T1111
Test name
Test status
Simulation time 2017376295 ps
CPU time 56.78 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:21:16 PM PDT 24
Peak memory 217276 kb
Host smart-545263b2-44b2-42ae-a08f-7b50f1b77fa8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4218552085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.4218552085
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1703047789
Short name T2670
Test name
Test status
Simulation time 250745379 ps
CPU time 1 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207548 kb
Host smart-d21191ac-ea32-45eb-9d9b-0632ee44860e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1703047789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1703047789
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1811244408
Short name T1537
Test name
Test status
Simulation time 199768859 ps
CPU time 1 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207568 kb
Host smart-a1ab0a0f-f9ca-4d80-ae87-5d32137ba6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
44408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1811244408
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3303829529
Short name T1686
Test name
Test status
Simulation time 2222821666 ps
CPU time 64.58 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 216156 kb
Host smart-ced71bf1-2e7a-47a0-a451-0feccf7b4356
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3303829529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3303829529
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2106419783
Short name T2270
Test name
Test status
Simulation time 147620000 ps
CPU time 0.83 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207596 kb
Host smart-72d20164-3e38-46f5-9088-85b54e4f39e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2106419783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2106419783
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.4113471945
Short name T917
Test name
Test status
Simulation time 204213510 ps
CPU time 0.96 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207532 kb
Host smart-e742156d-37e0-4a25-b60b-7fc6a0e6a089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
71945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.4113471945
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1604280341
Short name T3175
Test name
Test status
Simulation time 177546122 ps
CPU time 0.9 seconds
Started Aug 08 06:20:14 PM PDT 24
Finished Aug 08 06:20:15 PM PDT 24
Peak memory 207788 kb
Host smart-41092744-86b9-43e4-80e3-4b1b62ad4ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16042
80341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1604280341
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1983615383
Short name T1064
Test name
Test status
Simulation time 198193906 ps
CPU time 0.97 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207584 kb
Host smart-1a8d6298-ed79-490e-b790-cb84c625320c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
15383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1983615383
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1674226567
Short name T564
Test name
Test status
Simulation time 196906946 ps
CPU time 0.89 seconds
Started Aug 08 06:20:17 PM PDT 24
Finished Aug 08 06:20:18 PM PDT 24
Peak memory 207528 kb
Host smart-7df36183-7c8e-4a15-9a83-db3b59ae5172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16742
26567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1674226567
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.224647932
Short name T1179
Test name
Test status
Simulation time 161627318 ps
CPU time 0.86 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 207588 kb
Host smart-2cfe62c7-4e8a-463b-b886-01f939fc9161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464
7932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.224647932
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.362796318
Short name T3440
Test name
Test status
Simulation time 152633720 ps
CPU time 0.84 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207548 kb
Host smart-332602d9-f48b-4d47-b4d2-32ac81ed357a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.362796318
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2725583633
Short name T1455
Test name
Test status
Simulation time 189308807 ps
CPU time 0.96 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207568 kb
Host smart-7f5e4d40-dd40-42b5-90e9-52139a048626
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2725583633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2725583633
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3531623682
Short name T3275
Test name
Test status
Simulation time 138851986 ps
CPU time 0.86 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207564 kb
Host smart-3c9109c1-69fa-4441-8cd4-c0f8d25b3f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
23682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3531623682
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3225146558
Short name T1667
Test name
Test status
Simulation time 53571871 ps
CPU time 0.72 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207548 kb
Host smart-61d508e5-34a3-442a-9dc0-5ffb65e31e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32251
46558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3225146558
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.764816847
Short name T2247
Test name
Test status
Simulation time 163602847 ps
CPU time 0.87 seconds
Started Aug 08 06:20:13 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 207640 kb
Host smart-081d11e5-ff03-4b21-93ed-c252f92f1221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76481
6847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.764816847
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3183863959
Short name T3242
Test name
Test status
Simulation time 221235351 ps
CPU time 1.01 seconds
Started Aug 08 06:20:25 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207756 kb
Host smart-f6aa299b-6db1-4459-b1a8-d742123b19e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
63959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3183863959
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3081939605
Short name T1714
Test name
Test status
Simulation time 209492567 ps
CPU time 0.94 seconds
Started Aug 08 06:20:12 PM PDT 24
Finished Aug 08 06:20:13 PM PDT 24
Peak memory 207544 kb
Host smart-a633a122-fcd7-4af8-8348-9e17b4481cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30819
39605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3081939605
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3904668967
Short name T877
Test name
Test status
Simulation time 208884622 ps
CPU time 0.92 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207528 kb
Host smart-ce377f31-2361-4bc4-872e-a37e2a303e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
68967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3904668967
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3948868286
Short name T609
Test name
Test status
Simulation time 138774652 ps
CPU time 0.79 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207552 kb
Host smart-ad5f0d03-ef11-4e1a-9e05-2c0d82cc0501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
68286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3948868286
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.3066175660
Short name T2724
Test name
Test status
Simulation time 248096656 ps
CPU time 1.07 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207540 kb
Host smart-f7eb2bb5-c900-487a-a0e3-5dbc8b4edc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30661
75660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.3066175660
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3980651835
Short name T773
Test name
Test status
Simulation time 161425484 ps
CPU time 0.84 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 207508 kb
Host smart-0362d442-0b67-4aad-9343-ff63eee63a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
51835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3980651835
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2515141076
Short name T556
Test name
Test status
Simulation time 169894997 ps
CPU time 0.96 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207536 kb
Host smart-6bb76f4f-05ad-44cc-9304-d5375bb53474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
41076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2515141076
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2034255302
Short name T3254
Test name
Test status
Simulation time 232694503 ps
CPU time 1.01 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207528 kb
Host smart-54882465-b70b-4a05-9dd8-60edc6bd250c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
55302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2034255302
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1005531019
Short name T1519
Test name
Test status
Simulation time 2138962599 ps
CPU time 20.62 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:43 PM PDT 24
Peak memory 224152 kb
Host smart-445e2853-7e4d-49f9-b702-c1440a86ebaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1005531019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1005531019
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3287856775
Short name T1023
Test name
Test status
Simulation time 171696896 ps
CPU time 0.88 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207540 kb
Host smart-ed5b94c8-a515-4f3c-a46b-d66a2be21a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
56775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3287856775
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1869049221
Short name T3274
Test name
Test status
Simulation time 156924061 ps
CPU time 0.86 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207532 kb
Host smart-0265a676-29b0-46a2-b213-cf0a6fda5020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18690
49221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1869049221
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.3785509566
Short name T1236
Test name
Test status
Simulation time 726566406 ps
CPU time 2.05 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207512 kb
Host smart-be33345a-e481-4c98-8b88-9170f9fb4e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37855
09566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.3785509566
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.4054106236
Short name T3222
Test name
Test status
Simulation time 2039527840 ps
CPU time 15.67 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 224228 kb
Host smart-22b57f9f-df52-41e6-a09a-ec0ef1c6a8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
06236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.4054106236
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.2236674200
Short name T1974
Test name
Test status
Simulation time 541270911 ps
CPU time 11.76 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207708 kb
Host smart-f690809f-47c7-4249-b8e7-d825beafb6f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236674200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.2236674200
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.3976534560
Short name T618
Test name
Test status
Simulation time 483912542 ps
CPU time 1.48 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 207608 kb
Host smart-2e5e76e2-23ce-4f1c-91b8-33b11ebfe6e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976534560 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.3976534560
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.1500858841
Short name T766
Test name
Test status
Simulation time 509774470 ps
CPU time 1.66 seconds
Started Aug 08 06:22:30 PM PDT 24
Finished Aug 08 06:22:32 PM PDT 24
Peak memory 207584 kb
Host smart-d5d5cc67-427c-45e0-9593-6b23909d9e75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500858841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.1500858841
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.1213671792
Short name T2907
Test name
Test status
Simulation time 592807017 ps
CPU time 1.72 seconds
Started Aug 08 06:22:45 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207520 kb
Host smart-803145ac-4e57-4bcb-9437-9d057d5a50bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213671792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.1213671792
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.181090023
Short name T2245
Test name
Test status
Simulation time 585463127 ps
CPU time 1.65 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:39 PM PDT 24
Peak memory 207544 kb
Host smart-a16e0a2d-7087-4534-9adc-dda71daf58fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181090023 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.181090023
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.3018407041
Short name T2546
Test name
Test status
Simulation time 544904285 ps
CPU time 1.63 seconds
Started Aug 08 06:22:45 PM PDT 24
Finished Aug 08 06:22:46 PM PDT 24
Peak memory 207520 kb
Host smart-8e81626b-a7b1-40fa-a0d7-ea1128aba000
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018407041 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.3018407041
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.975006638
Short name T2468
Test name
Test status
Simulation time 585438243 ps
CPU time 1.61 seconds
Started Aug 08 06:22:59 PM PDT 24
Finished Aug 08 06:23:00 PM PDT 24
Peak memory 207600 kb
Host smart-2c738138-8ac7-408a-a557-bd079efb9cf2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975006638 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.975006638
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.2437033348
Short name T3085
Test name
Test status
Simulation time 556380751 ps
CPU time 1.57 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207544 kb
Host smart-e6ae06f2-cef7-406f-952e-bb4b90a35462
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437033348 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.2437033348
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.4231182516
Short name T2315
Test name
Test status
Simulation time 646756896 ps
CPU time 1.82 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:22:49 PM PDT 24
Peak memory 207536 kb
Host smart-abf5f108-eb3c-489e-96c9-714c1810a185
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231182516 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.4231182516
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.663252555
Short name T1124
Test name
Test status
Simulation time 671811671 ps
CPU time 1.86 seconds
Started Aug 08 06:22:40 PM PDT 24
Finished Aug 08 06:22:42 PM PDT 24
Peak memory 207616 kb
Host smart-705e7e02-2fdc-480a-9d9b-d42f8a8cd26a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663252555 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.663252555
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.1707227706
Short name T2430
Test name
Test status
Simulation time 706484273 ps
CPU time 1.86 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207588 kb
Host smart-d8b43dfa-06bd-43e7-b814-792c064e061a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707227706 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.1707227706
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.3315853351
Short name T713
Test name
Test status
Simulation time 605783088 ps
CPU time 1.67 seconds
Started Aug 08 06:22:41 PM PDT 24
Finished Aug 08 06:22:43 PM PDT 24
Peak memory 207500 kb
Host smart-263102bb-c83e-4065-b6b0-e1e68a245a6e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315853351 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.3315853351
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.316309541
Short name T1843
Test name
Test status
Simulation time 62294407 ps
CPU time 0.69 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207572 kb
Host smart-ebfa3c06-22d2-4ca8-9c21-91c3e664aabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=316309541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.316309541
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1240508847
Short name T1402
Test name
Test status
Simulation time 10094082675 ps
CPU time 12.81 seconds
Started Aug 08 06:20:25 PM PDT 24
Finished Aug 08 06:20:38 PM PDT 24
Peak memory 207828 kb
Host smart-ee92eb94-7ae7-452c-90c8-f3a7b4dbf9ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240508847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.1240508847
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.4260038614
Short name T1625
Test name
Test status
Simulation time 21112978876 ps
CPU time 26.52 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 207864 kb
Host smart-8679c436-e8f3-47a2-874b-27ca1b530dd4
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260038614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.4260038614
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2539922509
Short name T1829
Test name
Test status
Simulation time 25564296965 ps
CPU time 33.82 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 216004 kb
Host smart-5a16e1d3-898d-425e-8bad-ae57f035392b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539922509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2539922509
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1934993138
Short name T665
Test name
Test status
Simulation time 142906642 ps
CPU time 0.83 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207488 kb
Host smart-2bf675e6-fae8-46a9-b3bf-54e57b13dfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349
93138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1934993138
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1489584232
Short name T707
Test name
Test status
Simulation time 148107229 ps
CPU time 0.86 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207536 kb
Host smart-ab17ae9a-dce8-4b05-9166-a3c24825b869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
84232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1489584232
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.648425607
Short name T1378
Test name
Test status
Simulation time 353746455 ps
CPU time 1.42 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207512 kb
Host smart-fb2f349a-43d9-493b-9241-40c24dbda8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64842
5607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.648425607
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.651107627
Short name T1033
Test name
Test status
Simulation time 838765337 ps
CPU time 2.46 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207812 kb
Host smart-b259d209-825e-4122-843a-eaa32ac11454
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=651107627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.651107627
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1699265058
Short name T1780
Test name
Test status
Simulation time 35208102048 ps
CPU time 49.7 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:21:16 PM PDT 24
Peak memory 207800 kb
Host smart-1b34eca5-c415-4ed2-b778-b1bb1080df92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
65058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1699265058
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.2047398840
Short name T2877
Test name
Test status
Simulation time 771516682 ps
CPU time 15.44 seconds
Started Aug 08 06:20:38 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207744 kb
Host smart-ea5e8b24-16a6-406e-ad88-e80030d5475f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047398840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.2047398840
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2757619490
Short name T2039
Test name
Test status
Simulation time 781139365 ps
CPU time 2.02 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 207512 kb
Host smart-df4201df-a840-4c4f-b07e-5e8193004ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
19490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2757619490
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2865737630
Short name T3521
Test name
Test status
Simulation time 177224750 ps
CPU time 0.94 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207524 kb
Host smart-6c843bbc-d84b-4b77-a6d7-94c780fbcdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28657
37630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2865737630
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.598994805
Short name T2469
Test name
Test status
Simulation time 35655674 ps
CPU time 0.67 seconds
Started Aug 08 06:20:07 PM PDT 24
Finished Aug 08 06:20:08 PM PDT 24
Peak memory 207540 kb
Host smart-2b6966f2-36d5-42a4-83a1-8689edc1a93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59899
4805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.598994805
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1318469700
Short name T3174
Test name
Test status
Simulation time 879330802 ps
CPU time 2.21 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:21 PM PDT 24
Peak memory 207832 kb
Host smart-98624591-e7a2-480e-8d58-2669542e5fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13184
69700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1318469700
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.636796798
Short name T374
Test name
Test status
Simulation time 606605423 ps
CPU time 1.56 seconds
Started Aug 08 06:20:18 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207480 kb
Host smart-d2067026-e789-4b0a-8c82-7c74631187ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=636796798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.636796798
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2429910376
Short name T2869
Test name
Test status
Simulation time 179141191 ps
CPU time 1.88 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207736 kb
Host smart-002798e2-a975-43bd-aaa5-0ff3bf3f0289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24299
10376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2429910376
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1674534077
Short name T3534
Test name
Test status
Simulation time 184905196 ps
CPU time 0.91 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207556 kb
Host smart-2f3fcbbb-c92c-4b80-80fd-c4fc486d1499
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1674534077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1674534077
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2896732371
Short name T1944
Test name
Test status
Simulation time 147390326 ps
CPU time 0.85 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207584 kb
Host smart-37162bda-7aab-4c69-8f0c-0d53f42b654a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967
32371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2896732371
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3794657000
Short name T2140
Test name
Test status
Simulation time 200639653 ps
CPU time 0.94 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207536 kb
Host smart-cdebde39-b3ab-4dc9-b088-49b4c833239c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37946
57000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3794657000
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1551934252
Short name T3052
Test name
Test status
Simulation time 4192282747 ps
CPU time 125.82 seconds
Started Aug 08 06:20:15 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 218668 kb
Host smart-60e89643-f33f-4db7-adf7-3751f5c45c03
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1551934252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1551934252
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.2137682327
Short name T2365
Test name
Test status
Simulation time 7917926182 ps
CPU time 93.38 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207840 kb
Host smart-42803158-f106-4e54-853d-fc2345d95fa2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2137682327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.2137682327
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.4215541262
Short name T639
Test name
Test status
Simulation time 206215171 ps
CPU time 0.96 seconds
Started Aug 08 06:20:09 PM PDT 24
Finished Aug 08 06:20:10 PM PDT 24
Peak memory 207524 kb
Host smart-2538b2d7-ba6c-41b2-a05c-33493ed67d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155
41262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.4215541262
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1048995186
Short name T47
Test name
Test status
Simulation time 25367739267 ps
CPU time 48.08 seconds
Started Aug 08 06:20:16 PM PDT 24
Finished Aug 08 06:21:04 PM PDT 24
Peak memory 216376 kb
Host smart-7576fd5d-14c6-4c19-a15f-ed0db227406b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10489
95186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1048995186
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3811458900
Short name T1192
Test name
Test status
Simulation time 5778637222 ps
CPU time 7.19 seconds
Started Aug 08 06:20:17 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207776 kb
Host smart-74a1cead-f314-4d81-ab31-b6b7b287e3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
58900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3811458900
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.207320393
Short name T3448
Test name
Test status
Simulation time 4285145677 ps
CPU time 121.19 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 218608 kb
Host smart-61b18d74-9fa1-474f-8bdf-76a8735d88fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.207320393
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1802134819
Short name T2928
Test name
Test status
Simulation time 3956205586 ps
CPU time 111.89 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:22:20 PM PDT 24
Peak memory 217648 kb
Host smart-e2afb875-ad9c-4d8b-ac0a-fa25015f8517
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1802134819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1802134819
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.32866820
Short name T1346
Test name
Test status
Simulation time 233213795 ps
CPU time 0.93 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207608 kb
Host smart-03a9a9f2-01d2-44c4-b4dc-abe69b645845
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=32866820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.32866820
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2413428752
Short name T1903
Test name
Test status
Simulation time 196102765 ps
CPU time 0.96 seconds
Started Aug 08 06:20:05 PM PDT 24
Finished Aug 08 06:20:06 PM PDT 24
Peak memory 207528 kb
Host smart-f23feb32-00f2-46b0-a040-3a1501faccdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134
28752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2413428752
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3288268507
Short name T694
Test name
Test status
Simulation time 2980074257 ps
CPU time 27.34 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 216100 kb
Host smart-a5dc57ae-67aa-445f-89e1-951099a53688
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3288268507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3288268507
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.4037155906
Short name T1430
Test name
Test status
Simulation time 188098764 ps
CPU time 0.94 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207516 kb
Host smart-5eb21e94-36d9-4057-b414-f2a409e48637
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4037155906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.4037155906
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1066962881
Short name T613
Test name
Test status
Simulation time 143734789 ps
CPU time 0.83 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:20:40 PM PDT 24
Peak memory 207504 kb
Host smart-f4f8fdfe-da05-4fc7-af4f-22a3637e8b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10669
62881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1066962881
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2587922165
Short name T157
Test name
Test status
Simulation time 232209188 ps
CPU time 0.95 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207648 kb
Host smart-ae3b5da8-69de-4819-9128-d5ae972ef26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
22165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2587922165
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.4395611
Short name T3576
Test name
Test status
Simulation time 155672753 ps
CPU time 0.83 seconds
Started Aug 08 06:20:16 PM PDT 24
Finished Aug 08 06:20:17 PM PDT 24
Peak memory 207564 kb
Host smart-fe234e75-298d-4739-b4e8-87f3dfa34ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43956
11 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.4395611
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.900340590
Short name T1331
Test name
Test status
Simulation time 225199525 ps
CPU time 0.93 seconds
Started Aug 08 06:20:13 PM PDT 24
Finished Aug 08 06:20:14 PM PDT 24
Peak memory 207576 kb
Host smart-80641caa-f420-40fb-b154-5fcb8a82d87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90034
0590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.900340590
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.43086198
Short name T534
Test name
Test status
Simulation time 177408035 ps
CPU time 0.87 seconds
Started Aug 08 06:20:18 PM PDT 24
Finished Aug 08 06:20:19 PM PDT 24
Peak memory 207576 kb
Host smart-dde1155f-880c-4645-9179-d10e25ffa6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43086
198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.43086198
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1711653388
Short name T3023
Test name
Test status
Simulation time 165365620 ps
CPU time 0.87 seconds
Started Aug 08 06:20:16 PM PDT 24
Finished Aug 08 06:20:17 PM PDT 24
Peak memory 207656 kb
Host smart-54ff6c56-75df-44f5-83b6-e75cbd6e9a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17116
53388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1711653388
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.2876051890
Short name T2219
Test name
Test status
Simulation time 233660988 ps
CPU time 1 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:30 PM PDT 24
Peak memory 207520 kb
Host smart-850f7644-3f00-4d1a-ba8f-dfcf7b244ba0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2876051890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.2876051890
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.292620332
Short name T829
Test name
Test status
Simulation time 154437003 ps
CPU time 0.87 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207488 kb
Host smart-b1e3f9c1-5f2c-45ac-b586-0ce8e8b88f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
0332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.292620332
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4121109864
Short name T986
Test name
Test status
Simulation time 86755454 ps
CPU time 0.73 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207532 kb
Host smart-1b9dd2af-d094-4851-b44c-5a611d8803ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
09864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4121109864
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.453851052
Short name T2499
Test name
Test status
Simulation time 15657802444 ps
CPU time 39.78 seconds
Started Aug 08 06:20:12 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 216032 kb
Host smart-859ea6de-ea45-45fd-844f-f598cbfd522a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45385
1052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.453851052
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.958214321
Short name T2731
Test name
Test status
Simulation time 181400646 ps
CPU time 0.92 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207560 kb
Host smart-2cd21d79-77f0-4714-8264-0083d5b76dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95821
4321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.958214321
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1929099001
Short name T2451
Test name
Test status
Simulation time 197350540 ps
CPU time 0.98 seconds
Started Aug 08 06:20:16 PM PDT 24
Finished Aug 08 06:20:17 PM PDT 24
Peak memory 207492 kb
Host smart-4c8eeab3-8fe5-47cf-9377-efe0201f17aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19290
99001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1929099001
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.904813441
Short name T330
Test name
Test status
Simulation time 172992124 ps
CPU time 0.87 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207544 kb
Host smart-7f5498af-dadb-4af9-8643-12ea6aceab37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90481
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.904813441
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2581148180
Short name T2543
Test name
Test status
Simulation time 162319614 ps
CPU time 0.85 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207552 kb
Host smart-b0859c21-7b61-47ff-8c80-7d4db7dddc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
48180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2581148180
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.885507249
Short name T2007
Test name
Test status
Simulation time 156745224 ps
CPU time 0.86 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:20:27 PM PDT 24
Peak memory 207484 kb
Host smart-51ac474e-54dc-44eb-9efc-8026684bd87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88550
7249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.885507249
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.119082452
Short name T1210
Test name
Test status
Simulation time 280750154 ps
CPU time 1.1 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207536 kb
Host smart-4d2cbd1f-cca3-46f8-9a5c-9355b968732f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
2452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.119082452
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3612781839
Short name T1776
Test name
Test status
Simulation time 159564839 ps
CPU time 0.83 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207500 kb
Host smart-69143b91-22a6-48b7-92a3-aa06c5c0fdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
81839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3612781839
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.226718980
Short name T2209
Test name
Test status
Simulation time 181209690 ps
CPU time 0.88 seconds
Started Aug 08 06:20:22 PM PDT 24
Finished Aug 08 06:20:23 PM PDT 24
Peak memory 207648 kb
Host smart-b003a999-6f85-4a8c-b106-a431330f9774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22671
8980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.226718980
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.206387483
Short name T3506
Test name
Test status
Simulation time 220011193 ps
CPU time 0.99 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207592 kb
Host smart-2ed089c9-c81a-4a25-8c05-51738b6c85d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
7483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.206387483
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.559010996
Short name T3089
Test name
Test status
Simulation time 3226218655 ps
CPU time 23.24 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 224308 kb
Host smart-8ea702b1-fa1e-458c-8b4d-6f250fea0a9f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=559010996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.559010996
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.593100364
Short name T2942
Test name
Test status
Simulation time 179929995 ps
CPU time 0.93 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207532 kb
Host smart-080f6aab-f2f4-448c-9c36-ef6d9049550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59310
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.593100364
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.4136173279
Short name T2578
Test name
Test status
Simulation time 212426612 ps
CPU time 0.91 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207544 kb
Host smart-63d5413c-3f5f-4e95-b82b-331dfe7c641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41361
73279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.4136173279
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.92056803
Short name T1469
Test name
Test status
Simulation time 1100354107 ps
CPU time 2.79 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207648 kb
Host smart-4ee4ca3c-2754-4acb-98f8-6762fc062862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92056
803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.92056803
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.745849032
Short name T2545
Test name
Test status
Simulation time 2621361430 ps
CPU time 75.39 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:21:43 PM PDT 24
Peak memory 217436 kb
Host smart-4ca6fd31-b654-4251-af71-1997f0465faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74584
9032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.745849032
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.1230718575
Short name T3028
Test name
Test status
Simulation time 687576356 ps
CPU time 5.11 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207684 kb
Host smart-5fddb5ce-7f08-41d2-b566-d4a0c0831a74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230718575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.1230718575
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.876361030
Short name T2222
Test name
Test status
Simulation time 506737806 ps
CPU time 1.52 seconds
Started Aug 08 06:20:20 PM PDT 24
Finished Aug 08 06:20:22 PM PDT 24
Peak memory 207528 kb
Host smart-adb1b173-c691-45bc-8bf0-7380b5b5339b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876361030 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.876361030
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.573368177
Short name T2188
Test name
Test status
Simulation time 441306465 ps
CPU time 1.38 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207552 kb
Host smart-dacde6e4-0132-4474-a91d-9bf12b08e6b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573368177 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.573368177
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.1746619403
Short name T2370
Test name
Test status
Simulation time 460024576 ps
CPU time 1.46 seconds
Started Aug 08 06:22:41 PM PDT 24
Finished Aug 08 06:22:43 PM PDT 24
Peak memory 207544 kb
Host smart-c3dcc348-22ab-4a6f-a933-8238443d25f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746619403 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.1746619403
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.2784455920
Short name T32
Test name
Test status
Simulation time 504430827 ps
CPU time 1.57 seconds
Started Aug 08 06:22:51 PM PDT 24
Finished Aug 08 06:22:53 PM PDT 24
Peak memory 207556 kb
Host smart-95ce4652-be21-4216-b4a5-76340e8f43b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784455920 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.2784455920
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.83142961
Short name T719
Test name
Test status
Simulation time 547500822 ps
CPU time 1.58 seconds
Started Aug 08 06:22:41 PM PDT 24
Finished Aug 08 06:22:42 PM PDT 24
Peak memory 207572 kb
Host smart-93b35eb7-ca72-403b-8913-133108732f60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83142961 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.83142961
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.1897600262
Short name T1968
Test name
Test status
Simulation time 584747944 ps
CPU time 1.77 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:26 PM PDT 24
Peak memory 207544 kb
Host smart-faf3cbfe-839f-4294-8d3c-a4dfb0f3abeb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897600262 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.1897600262
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.615874899
Short name T2405
Test name
Test status
Simulation time 529448462 ps
CPU time 1.71 seconds
Started Aug 08 06:23:00 PM PDT 24
Finished Aug 08 06:23:02 PM PDT 24
Peak memory 207552 kb
Host smart-8bc03743-d260-40d2-944a-e3f394cc4360
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615874899 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.615874899
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.590092681
Short name T1232
Test name
Test status
Simulation time 588107317 ps
CPU time 1.72 seconds
Started Aug 08 06:23:00 PM PDT 24
Finished Aug 08 06:23:02 PM PDT 24
Peak memory 207568 kb
Host smart-a8a157e0-bffe-4772-bd79-a39595df134b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590092681 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.590092681
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.2583337071
Short name T2796
Test name
Test status
Simulation time 470449008 ps
CPU time 1.57 seconds
Started Aug 08 06:22:34 PM PDT 24
Finished Aug 08 06:22:36 PM PDT 24
Peak memory 207564 kb
Host smart-658951ad-fa4d-4e72-849c-9097a4f163c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583337071 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.2583337071
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.442115623
Short name T1276
Test name
Test status
Simulation time 626996293 ps
CPU time 1.58 seconds
Started Aug 08 06:23:02 PM PDT 24
Finished Aug 08 06:23:03 PM PDT 24
Peak memory 207580 kb
Host smart-567cad7c-b2fc-4b05-90a0-b40b9bba03f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442115623 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.442115623
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.2754778348
Short name T2128
Test name
Test status
Simulation time 588908533 ps
CPU time 1.59 seconds
Started Aug 08 06:22:31 PM PDT 24
Finished Aug 08 06:22:33 PM PDT 24
Peak memory 207584 kb
Host smart-bf8fed4f-1d4c-4cdf-a541-7180de91bd01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754778348 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.2754778348
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3219687430
Short name T1250
Test name
Test status
Simulation time 71376662 ps
CPU time 0.71 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207528 kb
Host smart-dfd25873-d02d-4913-9ebf-f6f4368a52e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3219687430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3219687430
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.625893300
Short name T2334
Test name
Test status
Simulation time 11411011335 ps
CPU time 14.61 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:39 PM PDT 24
Peak memory 207852 kb
Host smart-df72e8eb-4eb8-430c-b3de-8b4d833d8c2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625893300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ao
n_wake_disconnect.625893300
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.897360302
Short name T1337
Test name
Test status
Simulation time 15007986553 ps
CPU time 18.55 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 215980 kb
Host smart-bb6ad56a-b36e-4ef6-bb03-69aef1e7893a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=897360302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.897360302
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.144769550
Short name T3549
Test name
Test status
Simulation time 30998019884 ps
CPU time 34.18 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207800 kb
Host smart-e10acfc4-4443-4f42-b974-c3733bd4e614
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144769550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_ao
n_wake_resume.144769550
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.400338217
Short name T2130
Test name
Test status
Simulation time 159139109 ps
CPU time 0.88 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:20 PM PDT 24
Peak memory 207508 kb
Host smart-f5aa62a7-4bb1-4752-a541-688701d17321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
8217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.400338217
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2666318973
Short name T2301
Test name
Test status
Simulation time 151095185 ps
CPU time 0.84 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207544 kb
Host smart-568cc2fe-36ff-48ec-a49b-7ad11bb9acc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
18973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2666318973
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.4073696840
Short name T1171
Test name
Test status
Simulation time 560673143 ps
CPU time 1.79 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207556 kb
Host smart-045785f7-dc33-411f-9f3a-381787fa5f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40736
96840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.4073696840
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.945866629
Short name T2285
Test name
Test status
Simulation time 871776724 ps
CPU time 2.43 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207716 kb
Host smart-06695f9c-4abc-4ed8-84f9-cbd1d46edeaf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=945866629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.945866629
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1974385688
Short name T1700
Test name
Test status
Simulation time 54546467547 ps
CPU time 82.6 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 207832 kb
Host smart-c775492e-b2c4-4edb-9eb6-2a3b05c27490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743
85688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1974385688
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.3565918672
Short name T865
Test name
Test status
Simulation time 2037099995 ps
CPU time 17.11 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207696 kb
Host smart-b452e248-006b-472b-a84a-c0f38a56679a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565918672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3565918672
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1516527563
Short name T1381
Test name
Test status
Simulation time 1092130760 ps
CPU time 2.24 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207576 kb
Host smart-00a88dd8-b467-4958-b3f1-54e22a493802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15165
27563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1516527563
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2929858186
Short name T2293
Test name
Test status
Simulation time 180805902 ps
CPU time 0.93 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 207472 kb
Host smart-85b58b27-393f-4a1d-b857-918d213fe4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29298
58186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2929858186
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1259257362
Short name T1882
Test name
Test status
Simulation time 46863867 ps
CPU time 0.69 seconds
Started Aug 08 06:20:36 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 207508 kb
Host smart-74d70576-b813-4997-b86b-f989db39df26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12592
57362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1259257362
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2961800183
Short name T3115
Test name
Test status
Simulation time 923432755 ps
CPU time 2.54 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 207724 kb
Host smart-b55e403a-9679-43c2-baff-dd220636b1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
00183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2961800183
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.1748863068
Short name T495
Test name
Test status
Simulation time 395631012 ps
CPU time 1.29 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207548 kb
Host smart-9bfad4d9-74c9-4bf9-b2c5-c819ae379abc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1748863068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1748863068
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3373364524
Short name T1106
Test name
Test status
Simulation time 255916502 ps
CPU time 1.7 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207692 kb
Host smart-0ea96f8f-6db3-41e3-bd69-9d9831324bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
64524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3373364524
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.508048169
Short name T2055
Test name
Test status
Simulation time 184676885 ps
CPU time 0.97 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 215912 kb
Host smart-2fccf979-ac6e-404a-aeb1-2828358d438f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=508048169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.508048169
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1291017538
Short name T3162
Test name
Test status
Simulation time 199478718 ps
CPU time 0.89 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207532 kb
Host smart-e85a000d-e471-4528-bd1c-89f8b6c5e287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910
17538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1291017538
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1544234749
Short name T2019
Test name
Test status
Simulation time 197257582 ps
CPU time 0.92 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207596 kb
Host smart-3a46938c-4147-4fd3-81f1-8d9d0edb0af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
34749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1544234749
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.1135112245
Short name T1914
Test name
Test status
Simulation time 4747353231 ps
CPU time 48.77 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:21:16 PM PDT 24
Peak memory 224324 kb
Host smart-c1806540-d303-4c4a-834c-5e9bb7d055db
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1135112245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1135112245
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1087301023
Short name T2398
Test name
Test status
Simulation time 8594679615 ps
CPU time 106.8 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:22:16 PM PDT 24
Peak memory 207776 kb
Host smart-cb4a096b-a8af-4031-894d-8576b58ce82a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1087301023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1087301023
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2243828385
Short name T623
Test name
Test status
Simulation time 192214258 ps
CPU time 0.9 seconds
Started Aug 08 06:20:19 PM PDT 24
Finished Aug 08 06:20:21 PM PDT 24
Peak memory 207588 kb
Host smart-2c4a7052-3edd-4ae4-b615-caf619688049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
28385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2243828385
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4159301881
Short name T2500
Test name
Test status
Simulation time 28991306947 ps
CPU time 49.4 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:21:19 PM PDT 24
Peak memory 207808 kb
Host smart-ce1b8806-1ee3-40a1-af33-288227c672d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41593
01881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4159301881
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3557304169
Short name T904
Test name
Test status
Simulation time 9098210939 ps
CPU time 11.59 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:43 PM PDT 24
Peak memory 207820 kb
Host smart-23eae8fa-54c3-4837-b066-636c63e3132a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35573
04169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3557304169
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1612691720
Short name T3327
Test name
Test status
Simulation time 4451753723 ps
CPU time 43.57 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 218772 kb
Host smart-0538ab28-fbfc-4910-844d-3c42fc500ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
91720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1612691720
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1290463148
Short name T3245
Test name
Test status
Simulation time 2240800450 ps
CPU time 64.55 seconds
Started Aug 08 06:20:26 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 217652 kb
Host smart-30e6a701-f2c5-43e0-9cf0-956426754469
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1290463148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1290463148
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3230220065
Short name T630
Test name
Test status
Simulation time 253795142 ps
CPU time 1.01 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207612 kb
Host smart-f262a353-1a99-4580-af48-979c3a6fb8e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3230220065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3230220065
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1136441988
Short name T2139
Test name
Test status
Simulation time 184461737 ps
CPU time 0.94 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207596 kb
Host smart-076ceedf-d456-4104-89f9-18c33e90bb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364
41988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1136441988
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1160969402
Short name T1262
Test name
Test status
Simulation time 2613042003 ps
CPU time 24.94 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 217832 kb
Host smart-bb3d577c-1958-4e33-8186-2298f9eeeffc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1160969402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1160969402
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.644306806
Short name T2049
Test name
Test status
Simulation time 174344681 ps
CPU time 0.87 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207512 kb
Host smart-27724811-2a8a-4f88-8847-e6d32dc91731
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=644306806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.644306806
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2748883907
Short name T2761
Test name
Test status
Simulation time 147856840 ps
CPU time 0.81 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207588 kb
Host smart-880d0f20-fbe2-4d74-aa06-65b55b8f8df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
83907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2748883907
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2068202098
Short name T1852
Test name
Test status
Simulation time 176974573 ps
CPU time 0.89 seconds
Started Aug 08 06:20:27 PM PDT 24
Finished Aug 08 06:20:28 PM PDT 24
Peak memory 207536 kb
Host smart-7f870393-f556-4a8c-b0fe-db6e80ee9020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
02098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2068202098
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2378449300
Short name T778
Test name
Test status
Simulation time 232990818 ps
CPU time 0.98 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207600 kb
Host smart-e44ba711-39d3-4f25-b45f-89822ff09375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23784
49300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2378449300
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1963508480
Short name T533
Test name
Test status
Simulation time 241723811 ps
CPU time 0.95 seconds
Started Aug 08 06:20:37 PM PDT 24
Finished Aug 08 06:20:38 PM PDT 24
Peak memory 207596 kb
Host smart-cef9e42d-27f8-450a-8f84-41141345641d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635
08480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1963508480
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.702324108
Short name T1098
Test name
Test status
Simulation time 203510174 ps
CPU time 0.93 seconds
Started Aug 08 06:20:36 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 207524 kb
Host smart-c1aad6f4-9a4a-493e-ba1e-f8d104da2f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70232
4108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.702324108
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2934631463
Short name T2240
Test name
Test status
Simulation time 154704199 ps
CPU time 0.83 seconds
Started Aug 08 06:20:25 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207608 kb
Host smart-5b936fb1-794a-4ea6-84ee-ebdb95da7c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
31463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2934631463
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3065059335
Short name T1473
Test name
Test status
Simulation time 214411395 ps
CPU time 1.04 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207528 kb
Host smart-33ed6ee3-681d-488e-85e0-6ca452554b9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3065059335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3065059335
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3175046206
Short name T3547
Test name
Test status
Simulation time 148962589 ps
CPU time 0.88 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207560 kb
Host smart-b86ca19b-4549-4d6e-b015-f1339612d55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
46206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3175046206
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.857015753
Short name T2436
Test name
Test status
Simulation time 36561164 ps
CPU time 0.67 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 207508 kb
Host smart-c4645e38-a37e-4463-afec-cef19407f4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85701
5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.857015753
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1992335792
Short name T1617
Test name
Test status
Simulation time 8049600183 ps
CPU time 21.56 seconds
Started Aug 08 06:20:25 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 216068 kb
Host smart-ad93b9d4-7577-4de2-91a8-4eb45863b38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923
35792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1992335792
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4102930470
Short name T2701
Test name
Test status
Simulation time 210177987 ps
CPU time 0.97 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207588 kb
Host smart-55cbdb79-4af0-4e38-8ae5-0c68cd6e09d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
30470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4102930470
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.4179025536
Short name T3022
Test name
Test status
Simulation time 238391329 ps
CPU time 1.1 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207556 kb
Host smart-39573ccb-731e-4fd9-ab69-4a1c1ece1b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790
25536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.4179025536
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1600659737
Short name T1608
Test name
Test status
Simulation time 249594761 ps
CPU time 0.94 seconds
Started Aug 08 06:20:24 PM PDT 24
Finished Aug 08 06:20:25 PM PDT 24
Peak memory 207580 kb
Host smart-b8ebe6ce-e538-46a7-9a9f-b84fc322011f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16006
59737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1600659737
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2724323418
Short name T2791
Test name
Test status
Simulation time 181453046 ps
CPU time 0.92 seconds
Started Aug 08 06:20:25 PM PDT 24
Finished Aug 08 06:20:26 PM PDT 24
Peak memory 207580 kb
Host smart-7487d710-1157-4d72-a9a7-f2e18046a1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
23418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2724323418
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1510984240
Short name T2813
Test name
Test status
Simulation time 187834530 ps
CPU time 0.92 seconds
Started Aug 08 06:20:36 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 207576 kb
Host smart-468f11d1-5789-45be-9419-3641d3b52816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15109
84240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1510984240
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.3249089395
Short name T2805
Test name
Test status
Simulation time 394662836 ps
CPU time 1.37 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207592 kb
Host smart-d1069688-c8eb-4a42-92b6-0f2b33469cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32490
89395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.3249089395
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4240530582
Short name T1649
Test name
Test status
Simulation time 184322530 ps
CPU time 0.87 seconds
Started Aug 08 06:20:23 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 207544 kb
Host smart-c359fde8-7fe0-4c73-b27a-cf2b0ea42178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42405
30582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4240530582
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1847155971
Short name T2295
Test name
Test status
Simulation time 199494961 ps
CPU time 0.92 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207528 kb
Host smart-ff80a5f8-3e92-4cb5-ab2b-d965c82550e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18471
55971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1847155971
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3663240415
Short name T3004
Test name
Test status
Simulation time 189083317 ps
CPU time 0.98 seconds
Started Aug 08 06:20:57 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207508 kb
Host smart-d29c0421-9356-4241-a696-0cef4686cfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36632
40415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3663240415
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.780271271
Short name T2025
Test name
Test status
Simulation time 2436265627 ps
CPU time 67.39 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:21:37 PM PDT 24
Peak memory 217980 kb
Host smart-6d9a0172-a365-4d0f-8565-ffeb6d0d1b5d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=780271271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.780271271
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3591232267
Short name T1833
Test name
Test status
Simulation time 168073834 ps
CPU time 0.84 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:49 PM PDT 24
Peak memory 207588 kb
Host smart-d4d1d067-4ec7-4813-aece-2b1c6d08d06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
32267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3591232267
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4099377256
Short name T1297
Test name
Test status
Simulation time 172509457 ps
CPU time 0.91 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207604 kb
Host smart-53777d64-3f0d-44d6-b8bb-e2295db7614f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40993
77256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4099377256
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.4146697340
Short name T1068
Test name
Test status
Simulation time 1321124129 ps
CPU time 3.12 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:48 PM PDT 24
Peak memory 207764 kb
Host smart-98b12425-6a5c-4577-97df-e48dca315285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
97340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.4146697340
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2040461969
Short name T3508
Test name
Test status
Simulation time 2021429244 ps
CPU time 15.41 seconds
Started Aug 08 06:20:37 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207736 kb
Host smart-7ec667c7-75a2-493a-a609-95bc3cb0e493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404
61969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2040461969
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.3856760482
Short name T3343
Test name
Test status
Simulation time 3392178955 ps
CPU time 29.64 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207900 kb
Host smart-12f53623-2c3c-4310-af1b-a7da6cd5fff6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856760482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.3856760482
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.2009005672
Short name T2281
Test name
Test status
Simulation time 474907356 ps
CPU time 1.5 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207536 kb
Host smart-5911474a-dc70-4224-a8c6-8bcd1ee932ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009005672 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.2009005672
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.1254952447
Short name T195
Test name
Test status
Simulation time 531057493 ps
CPU time 1.62 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207616 kb
Host smart-5f097626-86fb-49c2-b1a8-87bd1a511e52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254952447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.1254952447
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.1336232951
Short name T791
Test name
Test status
Simulation time 626512419 ps
CPU time 1.76 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207548 kb
Host smart-bde87838-07ae-461b-95f4-8ea1bb79b5eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336232951 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.1336232951
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.3872218179
Short name T2221
Test name
Test status
Simulation time 506206241 ps
CPU time 1.44 seconds
Started Aug 08 06:22:33 PM PDT 24
Finished Aug 08 06:22:35 PM PDT 24
Peak memory 207640 kb
Host smart-72e792c2-cde7-46fa-a958-669598534a32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872218179 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.3872218179
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.3385125781
Short name T3616
Test name
Test status
Simulation time 663431858 ps
CPU time 1.79 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:39 PM PDT 24
Peak memory 207608 kb
Host smart-cc0b9f42-b4e6-4634-a919-1daace0295f4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385125781 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.3385125781
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.2573919737
Short name T2766
Test name
Test status
Simulation time 548025648 ps
CPU time 1.55 seconds
Started Aug 08 06:22:44 PM PDT 24
Finished Aug 08 06:22:46 PM PDT 24
Peak memory 207584 kb
Host smart-d5dab650-ac7a-4567-8817-ba28a5be45f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573919737 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.2573919737
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.2356178976
Short name T1876
Test name
Test status
Simulation time 711082075 ps
CPU time 1.95 seconds
Started Aug 08 06:22:48 PM PDT 24
Finished Aug 08 06:22:50 PM PDT 24
Peak memory 207612 kb
Host smart-e84cf96a-6106-4446-a8a4-a55d42a73ef9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356178976 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.2356178976
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.4217501663
Short name T808
Test name
Test status
Simulation time 460421985 ps
CPU time 1.4 seconds
Started Aug 08 06:22:23 PM PDT 24
Finished Aug 08 06:22:24 PM PDT 24
Peak memory 207612 kb
Host smart-d9cd2168-2cab-4bd2-84fd-85b4c371ec36
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217501663 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.4217501663
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.3270916315
Short name T1799
Test name
Test status
Simulation time 572376614 ps
CPU time 1.72 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207640 kb
Host smart-ceb2302c-1ea8-4153-8664-f3f4bf00bac3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270916315 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.3270916315
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.935444169
Short name T3144
Test name
Test status
Simulation time 514831647 ps
CPU time 1.51 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207588 kb
Host smart-392a00cb-e396-4ce9-8a4f-884dd4340f2c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935444169 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.935444169
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.2904447159
Short name T2487
Test name
Test status
Simulation time 535010398 ps
CPU time 1.7 seconds
Started Aug 08 06:22:33 PM PDT 24
Finished Aug 08 06:22:35 PM PDT 24
Peak memory 207588 kb
Host smart-c67025b2-5586-441e-aafb-f741ba97b34d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904447159 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.2904447159
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1639675187
Short name T2317
Test name
Test status
Simulation time 48499946 ps
CPU time 0.69 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207540 kb
Host smart-ab6d4f25-a562-45a6-abee-ab9ea8e09ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1639675187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1639675187
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2828273056
Short name T2125
Test name
Test status
Simulation time 6514037592 ps
CPU time 9.07 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:40 PM PDT 24
Peak memory 216048 kb
Host smart-2cba392a-e027-457e-b939-c03a7a722ccd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828273056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.2828273056
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2538738772
Short name T1142
Test name
Test status
Simulation time 15796985141 ps
CPU time 22.95 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 216060 kb
Host smart-866e1428-172b-4250-b0d3-96d450056e6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538738772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2538738772
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.4000820608
Short name T3405
Test name
Test status
Simulation time 24749744935 ps
CPU time 31.03 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 215992 kb
Host smart-02586a1b-7275-48f0-8fa5-ace525272238
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000820608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.4000820608
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3445510996
Short name T3626
Test name
Test status
Simulation time 143497095 ps
CPU time 0.8 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207592 kb
Host smart-83d6fe54-ae0b-47ea-9d17-f4bce7122988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34455
10996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3445510996
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2344677930
Short name T1146
Test name
Test status
Simulation time 161652978 ps
CPU time 0.9 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207536 kb
Host smart-c7a5071c-17d2-43f3-878f-c37404fa1595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
77930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2344677930
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.268226742
Short name T3219
Test name
Test status
Simulation time 279138056 ps
CPU time 1.09 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207580 kb
Host smart-c0abe634-0b83-4965-a5bc-cf99476f1a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26822
6742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.268226742
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1214352721
Short name T1794
Test name
Test status
Simulation time 550214768 ps
CPU time 1.66 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:20:31 PM PDT 24
Peak memory 207648 kb
Host smart-2b0997c2-363a-4426-adb9-67d677f58bfb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1214352721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1214352721
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.831780307
Short name T2891
Test name
Test status
Simulation time 61505480024 ps
CPU time 91.74 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:22:02 PM PDT 24
Peak memory 207796 kb
Host smart-f4e38807-d5bd-45be-96d0-ea7610301cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83178
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.831780307
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.2030982468
Short name T3229
Test name
Test status
Simulation time 171311375 ps
CPU time 0.91 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207524 kb
Host smart-03d4b811-e49a-4fe4-a558-2b630e8e901d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030982468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.2030982468
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4246757918
Short name T1207
Test name
Test status
Simulation time 683676184 ps
CPU time 1.69 seconds
Started Aug 08 06:20:39 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207504 kb
Host smart-19de0019-c69d-4225-9863-ab947428f686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
57918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4246757918
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2312310956
Short name T3177
Test name
Test status
Simulation time 146892680 ps
CPU time 0.84 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207508 kb
Host smart-08a32ad9-9814-4726-ae55-53ab4ce47aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
10956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2312310956
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3042655056
Short name T2911
Test name
Test status
Simulation time 37510466 ps
CPU time 0.72 seconds
Started Aug 08 06:20:42 PM PDT 24
Finished Aug 08 06:20:43 PM PDT 24
Peak memory 207504 kb
Host smart-4941370e-ab94-4cf5-8508-3c69143d4cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426
55056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3042655056
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2704263401
Short name T1975
Test name
Test status
Simulation time 852153265 ps
CPU time 2.45 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:47 PM PDT 24
Peak memory 207748 kb
Host smart-32f77eae-08e7-48ca-bbba-9153dd80398f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27042
63401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2704263401
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.1321792803
Short name T3066
Test name
Test status
Simulation time 433842069 ps
CPU time 1.44 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207536 kb
Host smart-c3a3e14d-1eac-4daa-8baa-84140a0dac41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1321792803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.1321792803
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3887516259
Short name T203
Test name
Test status
Simulation time 352763581 ps
CPU time 2.36 seconds
Started Aug 08 06:20:36 PM PDT 24
Finished Aug 08 06:20:39 PM PDT 24
Peak memory 207744 kb
Host smart-b9be5225-974c-4a08-a93d-ba895b94558a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38875
16259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3887516259
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.169267967
Short name T1323
Test name
Test status
Simulation time 208370031 ps
CPU time 1.11 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 215900 kb
Host smart-c2551f16-7c03-4f8d-9667-2bffd408be65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=169267967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.169267967
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2715949560
Short name T126
Test name
Test status
Simulation time 148883650 ps
CPU time 0.89 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207500 kb
Host smart-04b82f7c-c928-4025-9235-6e476df512e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
49560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2715949560
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2106129378
Short name T3603
Test name
Test status
Simulation time 190936998 ps
CPU time 0.91 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207584 kb
Host smart-81e59903-a98f-4d76-ab5a-0d204c103420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061
29378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2106129378
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.2969053485
Short name T2739
Test name
Test status
Simulation time 3211812278 ps
CPU time 31.04 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 224292 kb
Host smart-5aa121c1-9659-421b-b3b9-a1a03c03340f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2969053485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2969053485
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1255125312
Short name T3083
Test name
Test status
Simulation time 5599407243 ps
CPU time 39.3 seconds
Started Aug 08 06:20:47 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207744 kb
Host smart-cd4f11d9-043f-4e8c-b534-828e7e4ac51b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1255125312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1255125312
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3031279002
Short name T1041
Test name
Test status
Simulation time 230776457 ps
CPU time 0.93 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207580 kb
Host smart-20cd7b9f-9c9a-44bc-9a7e-5159743ba2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
79002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3031279002
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2814839887
Short name T2465
Test name
Test status
Simulation time 13629734160 ps
CPU time 18.06 seconds
Started Aug 08 06:20:30 PM PDT 24
Finished Aug 08 06:20:49 PM PDT 24
Peak memory 207828 kb
Host smart-2a33141a-07d7-4a7c-b21e-a21bcd7f14ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28148
39887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2814839887
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3225952645
Short name T954
Test name
Test status
Simulation time 5967147710 ps
CPU time 7.82 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:39 PM PDT 24
Peak memory 207784 kb
Host smart-cf75af28-cf49-4827-9e78-9ed23192d21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
52645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3225952645
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3841790262
Short name T3312
Test name
Test status
Simulation time 3333753225 ps
CPU time 94.96 seconds
Started Aug 08 06:20:29 PM PDT 24
Finished Aug 08 06:22:04 PM PDT 24
Peak memory 218968 kb
Host smart-b7b00a55-6245-4a82-aff3-d251a13c66d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417
90262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3841790262
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3623960315
Short name T1242
Test name
Test status
Simulation time 1841696915 ps
CPU time 51.37 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 217324 kb
Host smart-f0b3891b-4bae-4889-bbe0-ffae75e78e3f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3623960315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3623960315
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3438349975
Short name T2902
Test name
Test status
Simulation time 289166237 ps
CPU time 1.11 seconds
Started Aug 08 06:20:41 PM PDT 24
Finished Aug 08 06:20:42 PM PDT 24
Peak memory 207480 kb
Host smart-9c95e510-7b9e-473a-9967-6a2564bbd127
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3438349975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3438349975
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2393168821
Short name T1733
Test name
Test status
Simulation time 196593439 ps
CPU time 0.92 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207588 kb
Host smart-1fce68d8-342b-469a-8bb0-0fbd268cc168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
68821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2393168821
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3546715015
Short name T1038
Test name
Test status
Simulation time 1640190153 ps
CPU time 45.15 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 217364 kb
Host smart-56adb31e-6235-4939-89ad-30fd3b9ce8f7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3546715015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3546715015
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3926989543
Short name T1651
Test name
Test status
Simulation time 167665157 ps
CPU time 0.85 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207588 kb
Host smart-85a91ab3-9bbe-40f5-a43d-4dde8e083e58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3926989543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3926989543
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1505956137
Short name T1874
Test name
Test status
Simulation time 139651021 ps
CPU time 0.8 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207556 kb
Host smart-0a58daea-ffc4-4609-950c-1b9811594e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
56137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1505956137
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.439203609
Short name T3422
Test name
Test status
Simulation time 174394222 ps
CPU time 0.86 seconds
Started Aug 08 06:20:48 PM PDT 24
Finished Aug 08 06:20:49 PM PDT 24
Peak memory 207596 kb
Host smart-0089b5f4-e85f-4bcb-93f3-1d0be2712993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43920
3609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.439203609
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3837509661
Short name T3551
Test name
Test status
Simulation time 171791636 ps
CPU time 0.91 seconds
Started Aug 08 06:20:36 PM PDT 24
Finished Aug 08 06:20:37 PM PDT 24
Peak memory 207584 kb
Host smart-e58b6c6f-bdcf-4531-a4ad-f127d9f76277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
09661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3837509661
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3200299159
Short name T844
Test name
Test status
Simulation time 170740864 ps
CPU time 0.87 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207568 kb
Host smart-526124b2-cf0b-45fe-9f21-d322ccf8c082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32002
99159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3200299159
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1748863839
Short name T2353
Test name
Test status
Simulation time 177740378 ps
CPU time 0.87 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207564 kb
Host smart-3154540f-90cd-4921-97f9-5f153d930105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488
63839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1748863839
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3592462949
Short name T1287
Test name
Test status
Simulation time 141690532 ps
CPU time 0.81 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207616 kb
Host smart-d0cf26bf-994f-487f-810c-413cf9c5ff6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
62949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3592462949
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.925539492
Short name T2749
Test name
Test status
Simulation time 286245237 ps
CPU time 1.13 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207608 kb
Host smart-d004f864-5ffc-47f4-bf60-84d9cf37fc86
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=925539492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.925539492
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3289665762
Short name T3391
Test name
Test status
Simulation time 140133204 ps
CPU time 0.81 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:32 PM PDT 24
Peak memory 207516 kb
Host smart-3131e3dd-6a26-4ece-938a-9bad1aa40051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32896
65762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3289665762
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1901069240
Short name T43
Test name
Test status
Simulation time 33916879 ps
CPU time 0.68 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207504 kb
Host smart-d143ceaa-c75d-4603-994d-368393c0a7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
69240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1901069240
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4224058100
Short name T1251
Test name
Test status
Simulation time 19154619959 ps
CPU time 48.52 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 224268 kb
Host smart-65c24456-8b6d-4ace-b476-aea29c723093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
58100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4224058100
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.912610293
Short name T1636
Test name
Test status
Simulation time 194688821 ps
CPU time 0.88 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207560 kb
Host smart-d3f2e02e-7843-49fc-8b0b-a3aeaa5af429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91261
0293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.912610293
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2374257748
Short name T3053
Test name
Test status
Simulation time 169150086 ps
CPU time 0.88 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207560 kb
Host smart-ecd49d19-e258-4184-bd33-19b81c31891f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
57748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2374257748
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1210525614
Short name T517
Test name
Test status
Simulation time 178099926 ps
CPU time 0.91 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207564 kb
Host smart-bdb81758-5850-4b05-afa5-e17dc51e5d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12105
25614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1210525614
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.166692179
Short name T1345
Test name
Test status
Simulation time 219838846 ps
CPU time 0.91 seconds
Started Aug 08 06:20:35 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207600 kb
Host smart-053f1282-3314-4278-91c2-1ab0f12c2d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
2179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.166692179
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1403553066
Short name T2289
Test name
Test status
Simulation time 133967712 ps
CPU time 0.88 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207512 kb
Host smart-8b8c852b-2821-4f00-8907-a530a1f561ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14035
53066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1403553066
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.180895287
Short name T53
Test name
Test status
Simulation time 251720879 ps
CPU time 1.14 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207556 kb
Host smart-c9bbb218-ffce-418e-b6e2-7120e1264b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18089
5287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.180895287
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3196284987
Short name T3088
Test name
Test status
Simulation time 167029656 ps
CPU time 0.85 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:20:47 PM PDT 24
Peak memory 207500 kb
Host smart-86c379d4-30b9-4f43-866f-d1b19dd2c491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31962
84987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3196284987
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.606115003
Short name T1448
Test name
Test status
Simulation time 188333934 ps
CPU time 0.91 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207584 kb
Host smart-070953e8-d693-46d2-981d-0951e7f99d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60611
5003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.606115003
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.85470782
Short name T1175
Test name
Test status
Simulation time 284711604 ps
CPU time 1.09 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207544 kb
Host smart-8487f658-856c-422c-971f-cab828a28e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85470
782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.85470782
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3600356082
Short name T2828
Test name
Test status
Simulation time 2452586336 ps
CPU time 24.24 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 218128 kb
Host smart-ea9c004c-6295-4e05-9039-4ac10c4ce2e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3600356082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3600356082
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1803205078
Short name T1325
Test name
Test status
Simulation time 186763471 ps
CPU time 0.9 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207544 kb
Host smart-0c69c848-9996-4069-8e4d-bd3ccd40cb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
05078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1803205078
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.676491214
Short name T2024
Test name
Test status
Simulation time 167236385 ps
CPU time 0.86 seconds
Started Aug 08 06:20:41 PM PDT 24
Finished Aug 08 06:20:42 PM PDT 24
Peak memory 207568 kb
Host smart-f8481ee3-afb2-4a41-8e2b-69818f9728c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67649
1214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.676491214
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.1063384255
Short name T3021
Test name
Test status
Simulation time 1273005531 ps
CPU time 2.78 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:48 PM PDT 24
Peak memory 207804 kb
Host smart-6a2fc5a7-5eed-4f93-9f58-fcbe663ea44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10633
84255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.1063384255
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2176850400
Short name T2507
Test name
Test status
Simulation time 2337786996 ps
CPU time 23.39 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 217728 kb
Host smart-e082f84b-ceea-48ab-9442-a7660e072dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
50400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2176850400
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.3660853116
Short name T943
Test name
Test status
Simulation time 1529845722 ps
CPU time 13.25 seconds
Started Aug 08 06:20:48 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 207656 kb
Host smart-1e0d6331-6093-4aca-bcca-bac58c44a453
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660853116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.3660853116
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.3422981418
Short name T2059
Test name
Test status
Simulation time 585869301 ps
CPU time 1.52 seconds
Started Aug 08 06:20:34 PM PDT 24
Finished Aug 08 06:20:36 PM PDT 24
Peak memory 207552 kb
Host smart-9a9977db-7bea-45d1-b2da-003d52a4966b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422981418 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.3422981418
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.653335026
Short name T2216
Test name
Test status
Simulation time 520179289 ps
CPU time 1.57 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207548 kb
Host smart-9da27bfe-4def-48be-b0bc-0d401e2bf42b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653335026 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.653335026
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.358723375
Short name T3261
Test name
Test status
Simulation time 595518829 ps
CPU time 1.6 seconds
Started Aug 08 06:22:58 PM PDT 24
Finished Aug 08 06:22:59 PM PDT 24
Peak memory 207596 kb
Host smart-3cbe3d74-62d2-4a9f-969b-c52b38f92805
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358723375 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.358723375
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.54094603
Short name T3591
Test name
Test status
Simulation time 524727129 ps
CPU time 1.57 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207548 kb
Host smart-d453d32e-f867-4363-aa42-8b718630adda
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54094603 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.54094603
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.2528497965
Short name T36
Test name
Test status
Simulation time 489236924 ps
CPU time 1.51 seconds
Started Aug 08 06:22:40 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207552 kb
Host smart-1785f182-05eb-4128-948f-eb4a39252e77
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528497965 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.2528497965
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.2272209644
Short name T2580
Test name
Test status
Simulation time 585882386 ps
CPU time 1.79 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207620 kb
Host smart-67a7330d-e0a8-4f77-b1d2-e5034263f479
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272209644 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.2272209644
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.1149711445
Short name T811
Test name
Test status
Simulation time 431186264 ps
CPU time 1.4 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207552 kb
Host smart-be7e6a17-12d8-4de7-b64b-7da1c626e36d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149711445 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.1149711445
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.3669896204
Short name T1908
Test name
Test status
Simulation time 517168811 ps
CPU time 1.56 seconds
Started Aug 08 06:22:35 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 207600 kb
Host smart-92d0fffe-92cc-47e6-90c7-65fd562f87ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669896204 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.3669896204
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.1719730123
Short name T2380
Test name
Test status
Simulation time 542367053 ps
CPU time 1.6 seconds
Started Aug 08 06:22:50 PM PDT 24
Finished Aug 08 06:22:51 PM PDT 24
Peak memory 207572 kb
Host smart-43d9b5e8-37c0-4108-a527-f6cd60c53895
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719730123 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.1719730123
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.1971530755
Short name T2136
Test name
Test status
Simulation time 643481104 ps
CPU time 1.63 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:39 PM PDT 24
Peak memory 207596 kb
Host smart-dbb4a140-230f-4772-b2af-d948163e75f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971530755 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.1971530755
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.1149825440
Short name T3518
Test name
Test status
Simulation time 475044650 ps
CPU time 1.5 seconds
Started Aug 08 06:22:52 PM PDT 24
Finished Aug 08 06:22:53 PM PDT 24
Peak memory 207568 kb
Host smart-0fe811e7-f511-4e42-938b-4e964d3ec115
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149825440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.1149825440
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1128062380
Short name T1193
Test name
Test status
Simulation time 37025534 ps
CPU time 0.73 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207548 kb
Host smart-eaa019e3-bece-45af-93a6-c5c1055852dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1128062380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1128062380
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3198080055
Short name T716
Test name
Test status
Simulation time 6770874311 ps
CPU time 8.65 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 215972 kb
Host smart-b72b82be-848e-446f-980a-47fc2869110f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198080055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.3198080055
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.513803517
Short name T1283
Test name
Test status
Simulation time 23305887049 ps
CPU time 28.29 seconds
Started Aug 08 06:20:31 PM PDT 24
Finished Aug 08 06:20:59 PM PDT 24
Peak memory 216004 kb
Host smart-2a1a9778-67d8-481d-8b39-87f88cde6be0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513803517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_resume.513803517
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2597936696
Short name T3056
Test name
Test status
Simulation time 175276466 ps
CPU time 0.85 seconds
Started Aug 08 06:20:39 PM PDT 24
Finished Aug 08 06:20:40 PM PDT 24
Peak memory 207580 kb
Host smart-78c66179-ab64-4bc8-b6f7-83ea359711ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25979
36696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2597936696
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2081038403
Short name T1766
Test name
Test status
Simulation time 147352348 ps
CPU time 0.83 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 207568 kb
Host smart-92d10c4d-b6b2-4c0a-87ef-1d7f2b8909bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
38403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2081038403
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3409705896
Short name T666
Test name
Test status
Simulation time 356880173 ps
CPU time 1.33 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:33 PM PDT 24
Peak memory 207560 kb
Host smart-ade27589-4504-4743-a827-047211e3170f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
05896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3409705896
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1939171304
Short name T3253
Test name
Test status
Simulation time 519097426 ps
CPU time 1.82 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:35 PM PDT 24
Peak memory 207556 kb
Host smart-770ffd85-5740-4111-bf7a-8a63021716a7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1939171304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1939171304
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3758962240
Short name T2595
Test name
Test status
Simulation time 23562121302 ps
CPU time 35.41 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:21:18 PM PDT 24
Peak memory 207788 kb
Host smart-a19061a2-63b5-486e-9b4a-0eb698d6ee14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
62240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3758962240
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.1094177507
Short name T1740
Test name
Test status
Simulation time 562676604 ps
CPU time 10.97 seconds
Started Aug 08 06:20:37 PM PDT 24
Finished Aug 08 06:20:48 PM PDT 24
Peak memory 207756 kb
Host smart-7a7eb79f-9118-4860-b8ae-f6f56fdf68dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094177507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.1094177507
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1343250730
Short name T1746
Test name
Test status
Simulation time 791534166 ps
CPU time 1.87 seconds
Started Aug 08 06:20:32 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207540 kb
Host smart-cf00de9b-1bd2-4775-afa4-bcacd7646662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13432
50730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1343250730
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.4113356917
Short name T2704
Test name
Test status
Simulation time 150605014 ps
CPU time 0.82 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:50 PM PDT 24
Peak memory 207496 kb
Host smart-e48124af-9176-4a60-aa48-e507966bf1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133
56917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.4113356917
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1814841381
Short name T2447
Test name
Test status
Simulation time 33895472 ps
CPU time 0.73 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207488 kb
Host smart-36bef004-cc24-4d61-8eaf-10c93f2cf4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148
41381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1814841381
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2667033165
Short name T3313
Test name
Test status
Simulation time 993454299 ps
CPU time 2.74 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:20:59 PM PDT 24
Peak memory 207704 kb
Host smart-4ab2f42e-0eda-4728-90ba-9e5ec2f6e6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
33165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2667033165
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.722021563
Short name T448
Test name
Test status
Simulation time 634755878 ps
CPU time 1.69 seconds
Started Aug 08 06:20:37 PM PDT 24
Finished Aug 08 06:20:39 PM PDT 24
Peak memory 207512 kb
Host smart-3dd03b3d-627c-4703-975e-cf7e9a630c1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=722021563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.722021563
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3074018595
Short name T2410
Test name
Test status
Simulation time 316427153 ps
CPU time 2.23 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207672 kb
Host smart-2844b274-7396-4401-a2c2-882ec9b4f0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30740
18595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3074018595
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3642679280
Short name T1857
Test name
Test status
Simulation time 242407782 ps
CPU time 1.21 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 215916 kb
Host smart-7b376386-957c-4dd1-9f20-d8b1d1602661
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3642679280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3642679280
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.692272086
Short name T802
Test name
Test status
Simulation time 141409290 ps
CPU time 0.85 seconds
Started Aug 08 06:20:28 PM PDT 24
Finished Aug 08 06:20:29 PM PDT 24
Peak memory 207492 kb
Host smart-40e7b52f-b068-46aa-aaad-ef5a44e1d84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69227
2086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.692272086
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.158156085
Short name T2608
Test name
Test status
Simulation time 197553802 ps
CPU time 0.92 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:34 PM PDT 24
Peak memory 207512 kb
Host smart-9707a79b-0d33-46c8-8eee-599e87236175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15815
6085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.158156085
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3489579272
Short name T2548
Test name
Test status
Simulation time 4128182036 ps
CPU time 39.1 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 224248 kb
Host smart-c39c5d80-7c1c-4209-bf6e-0293f768f946
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3489579272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3489579272
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.2695744202
Short name T2102
Test name
Test status
Simulation time 8855772452 ps
CPU time 56.41 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:21:52 PM PDT 24
Peak memory 207788 kb
Host smart-aff41d4f-6948-4107-8734-2e59bcfff2e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2695744202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2695744202
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.358914746
Short name T3167
Test name
Test status
Simulation time 194442864 ps
CPU time 0.9 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207532 kb
Host smart-b7c91c76-21d5-4657-80a0-dfce2bd5bc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.358914746
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3475810984
Short name T2238
Test name
Test status
Simulation time 23911254929 ps
CPU time 46.35 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:38 PM PDT 24
Peak memory 216184 kb
Host smart-bfb7102c-208a-4438-b14e-65ac954e7d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34758
10984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3475810984
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1100947253
Short name T3225
Test name
Test status
Simulation time 5654503439 ps
CPU time 7.94 seconds
Started Aug 08 06:20:33 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207840 kb
Host smart-dde1436c-629d-428b-bc90-2e6ce689e28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
47253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1100947253
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3644030505
Short name T1925
Test name
Test status
Simulation time 3400771508 ps
CPU time 96.3 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:22:16 PM PDT 24
Peak memory 216108 kb
Host smart-6bf4bcb9-2b9a-4007-83e3-2f543ea8cdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
30505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3644030505
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3588973274
Short name T1060
Test name
Test status
Simulation time 2960487874 ps
CPU time 31.16 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 217376 kb
Host smart-6d218a4e-b677-4921-8fe2-aa45dd342f38
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3588973274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3588973274
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.573273297
Short name T1886
Test name
Test status
Simulation time 242417640 ps
CPU time 0.95 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207488 kb
Host smart-9c98c040-432d-41b9-921d-e51763b4d7f5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=573273297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.573273297
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3403979380
Short name T2655
Test name
Test status
Simulation time 219354608 ps
CPU time 1 seconds
Started Aug 08 06:20:58 PM PDT 24
Finished Aug 08 06:20:59 PM PDT 24
Peak memory 207556 kb
Host smart-018985df-d869-4892-ae50-2352307db5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
79380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3403979380
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2114374107
Short name T2767
Test name
Test status
Simulation time 3509245306 ps
CPU time 100.71 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 217584 kb
Host smart-787b29ff-8447-474c-9cc2-7e32389e52ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2114374107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2114374107
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.268523766
Short name T536
Test name
Test status
Simulation time 154307751 ps
CPU time 0.85 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:20:44 PM PDT 24
Peak memory 207568 kb
Host smart-c2bbc22e-012f-4a28-8f34-932500bc6463
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=268523766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.268523766
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.102392487
Short name T537
Test name
Test status
Simulation time 193606650 ps
CPU time 0.89 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207640 kb
Host smart-8066b527-b2bf-4a82-b7ce-1968280e4d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
2487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.102392487
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4026148235
Short name T155
Test name
Test status
Simulation time 167802778 ps
CPU time 0.89 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207592 kb
Host smart-c85a29e5-bd81-4be5-8ae0-8434f86c75fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40261
48235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4026148235
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.180513146
Short name T2794
Test name
Test status
Simulation time 161745246 ps
CPU time 0.99 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 207608 kb
Host smart-6630a72e-6ea8-4410-8933-7188163f7708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18051
3146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.180513146
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1817934965
Short name T1702
Test name
Test status
Simulation time 165590519 ps
CPU time 0.88 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207512 kb
Host smart-80f15b51-00bb-416f-95d4-209c84e9205c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
34965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1817934965
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3017474172
Short name T2723
Test name
Test status
Simulation time 158536075 ps
CPU time 0.83 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207588 kb
Host smart-2bab82b5-daf0-4af3-b3d6-7d6e98d67f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30174
74172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3017474172
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3203464570
Short name T1180
Test name
Test status
Simulation time 221407550 ps
CPU time 0.89 seconds
Started Aug 08 06:20:58 PM PDT 24
Finished Aug 08 06:20:59 PM PDT 24
Peak memory 207516 kb
Host smart-d56bfdb2-78c7-4a9e-869d-3b48f2fd5a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
64570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3203464570
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.812480543
Short name T24
Test name
Test status
Simulation time 208655584 ps
CPU time 0.99 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207576 kb
Host smart-46c4f23f-0523-4969-ac07-21f6217bdaaf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=812480543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.812480543
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2345491595
Short name T1739
Test name
Test status
Simulation time 178513834 ps
CPU time 0.87 seconds
Started Aug 08 06:20:57 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207536 kb
Host smart-2d7fce36-0fbf-4548-ab94-e89d56091e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
91595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2345491595
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2362523012
Short name T1462
Test name
Test status
Simulation time 49521981 ps
CPU time 0.71 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:50 PM PDT 24
Peak memory 207472 kb
Host smart-bde78384-7f84-4716-835e-19ed89a418a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
23012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2362523012
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3494587557
Short name T1052
Test name
Test status
Simulation time 7306263503 ps
CPU time 20.19 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 216016 kb
Host smart-af4e06a3-4e3a-4cac-909a-f39f67a1b1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
87557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3494587557
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2598015301
Short name T1524
Test name
Test status
Simulation time 163633861 ps
CPU time 0.88 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207552 kb
Host smart-3b71392d-d37d-4882-bd61-78d3930b0262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
15301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2598015301
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2444015495
Short name T807
Test name
Test status
Simulation time 187504805 ps
CPU time 0.94 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207488 kb
Host smart-3d5865c7-c7c8-451d-98f0-9a29f6942527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24440
15495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2444015495
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.341283358
Short name T3410
Test name
Test status
Simulation time 280222779 ps
CPU time 1.02 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207572 kb
Host smart-b5d317cd-030e-4094-9109-79abb3952085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
3358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.341283358
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3546772589
Short name T1063
Test name
Test status
Simulation time 166628353 ps
CPU time 0.92 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207520 kb
Host smart-d44e07d7-eda1-4b74-8ed3-b6fe6d509278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35467
72589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3546772589
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.540268453
Short name T2303
Test name
Test status
Simulation time 240430586 ps
CPU time 0.94 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207544 kb
Host smart-f789c56a-074b-4bf8-a375-db20c42b86ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54026
8453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.540268453
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.3501636441
Short name T2034
Test name
Test status
Simulation time 438454271 ps
CPU time 1.38 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:20:47 PM PDT 24
Peak memory 207532 kb
Host smart-9f3e6723-14d6-460f-bcda-fa5734b36935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
36441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.3501636441
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.617691416
Short name T2818
Test name
Test status
Simulation time 153505038 ps
CPU time 0.82 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:50 PM PDT 24
Peak memory 207436 kb
Host smart-918c1ebd-b97f-4872-8c6f-f8df80ff2e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61769
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.617691416
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.418584176
Short name T2900
Test name
Test status
Simulation time 157141234 ps
CPU time 0.86 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207612 kb
Host smart-3f41b038-d746-4b97-ae88-307d04c7f67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
4176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.418584176
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.875296979
Short name T3278
Test name
Test status
Simulation time 222176728 ps
CPU time 0.97 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:20:47 PM PDT 24
Peak memory 207536 kb
Host smart-1a6c8244-14e4-47a8-bd0a-60fa3631dde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87529
6979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.875296979
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.4050354572
Short name T3048
Test name
Test status
Simulation time 2734168050 ps
CPU time 21.1 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 218136 kb
Host smart-6cd185dd-b655-4273-89a5-81b9396e3a99
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4050354572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.4050354572
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1620178421
Short name T487
Test name
Test status
Simulation time 147609495 ps
CPU time 0.8 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207584 kb
Host smart-2a6d182e-d45e-4f27-aa63-59543d80c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
78421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1620178421
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3417793808
Short name T2190
Test name
Test status
Simulation time 206367250 ps
CPU time 0.89 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207624 kb
Host smart-00add720-f5e7-495f-a493-e1b94715247a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34177
93808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3417793808
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.2036728548
Short name T328
Test name
Test status
Simulation time 446066618 ps
CPU time 1.39 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207476 kb
Host smart-7654a06d-405b-475d-97d6-36eede4213aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20367
28548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.2036728548
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3207307923
Short name T3568
Test name
Test status
Simulation time 2243168306 ps
CPU time 16.02 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:21:07 PM PDT 24
Peak memory 217540 kb
Host smart-d0e6b284-0da1-4969-b0a2-ac46d82d83da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
07923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3207307923
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.1055309072
Short name T2312
Test name
Test status
Simulation time 2458217854 ps
CPU time 22.24 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 207780 kb
Host smart-6d5fee1e-81b1-4df8-8045-23123bad18b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055309072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.1055309072
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.3091970366
Short name T3212
Test name
Test status
Simulation time 561029340 ps
CPU time 1.65 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:20:44 PM PDT 24
Peak memory 207624 kb
Host smart-2add90f2-818c-40b8-b7e6-0df9c4e977ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091970366 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.3091970366
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.2199844414
Short name T2643
Test name
Test status
Simulation time 610453721 ps
CPU time 1.63 seconds
Started Aug 08 06:22:48 PM PDT 24
Finished Aug 08 06:22:50 PM PDT 24
Peak memory 207572 kb
Host smart-84e9eef3-47ec-4a16-8234-8c7c886e1259
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199844414 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.2199844414
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.2852915275
Short name T2506
Test name
Test status
Simulation time 580150614 ps
CPU time 1.89 seconds
Started Aug 08 06:22:59 PM PDT 24
Finished Aug 08 06:23:01 PM PDT 24
Peak memory 207572 kb
Host smart-035979a0-94f3-408b-a9dd-63944b3369eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852915275 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.2852915275
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.142470214
Short name T1062
Test name
Test status
Simulation time 548945697 ps
CPU time 1.68 seconds
Started Aug 08 06:22:49 PM PDT 24
Finished Aug 08 06:22:51 PM PDT 24
Peak memory 207516 kb
Host smart-42c670b4-cf27-40dd-ab45-770e247e1cf6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142470214 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.142470214
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.2286703893
Short name T2014
Test name
Test status
Simulation time 558137764 ps
CPU time 1.64 seconds
Started Aug 08 06:22:54 PM PDT 24
Finished Aug 08 06:22:56 PM PDT 24
Peak memory 207516 kb
Host smart-0d813a04-4d9c-4d0f-b062-619e7751acf4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286703893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.2286703893
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.3803679866
Short name T2789
Test name
Test status
Simulation time 509464078 ps
CPU time 1.54 seconds
Started Aug 08 06:22:41 PM PDT 24
Finished Aug 08 06:22:43 PM PDT 24
Peak memory 207516 kb
Host smart-5685cffa-d187-447d-b96b-e5ca3f064b1d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803679866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.3803679866
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.121310586
Short name T1863
Test name
Test status
Simulation time 484402957 ps
CPU time 1.53 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207548 kb
Host smart-126c6531-c801-4076-9510-eb9ab499fb14
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121310586 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.121310586
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.4125804058
Short name T3287
Test name
Test status
Simulation time 570351468 ps
CPU time 1.47 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207588 kb
Host smart-6ce2cdbf-ce2a-4d2a-b1e6-af2c63a8b4e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125804058 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.4125804058
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.3540538253
Short name T864
Test name
Test status
Simulation time 623102173 ps
CPU time 1.61 seconds
Started Aug 08 06:22:52 PM PDT 24
Finished Aug 08 06:22:54 PM PDT 24
Peak memory 207516 kb
Host smart-3d2fef4d-a996-4644-a9cb-fa0401e08eff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540538253 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.3540538253
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.52216107
Short name T3511
Test name
Test status
Simulation time 494621803 ps
CPU time 1.5 seconds
Started Aug 08 06:23:02 PM PDT 24
Finished Aug 08 06:23:04 PM PDT 24
Peak memory 207516 kb
Host smart-83151421-f17e-4b08-a0bb-ea4f60df035d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52216107 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.52216107
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.990859012
Short name T725
Test name
Test status
Simulation time 635826558 ps
CPU time 1.58 seconds
Started Aug 08 06:22:53 PM PDT 24
Finished Aug 08 06:22:55 PM PDT 24
Peak memory 207512 kb
Host smart-6c113d6a-3e21-45ed-9bae-4445475ff91d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990859012 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.990859012
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.518408016
Short name T206
Test name
Test status
Simulation time 32760608 ps
CPU time 0.66 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207568 kb
Host smart-86cf53c3-278d-47b5-aa2f-8bc6e3acf732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=518408016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.518408016
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1854901698
Short name T2648
Test name
Test status
Simulation time 8799145665 ps
CPU time 12.47 seconds
Started Aug 08 06:20:42 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207852 kb
Host smart-fe88f8c0-1a7f-4456-92a3-95768656e9f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854901698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1854901698
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.848645368
Short name T2282
Test name
Test status
Simulation time 19431252262 ps
CPU time 22.45 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207892 kb
Host smart-665dcc57-ee62-4828-8588-4abc2ce28419
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848645368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.848645368
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3358589150
Short name T822
Test name
Test status
Simulation time 23647906593 ps
CPU time 34.12 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 216004 kb
Host smart-d474d091-98cc-4c10-9b8f-2c0ff8ec00e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358589150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.3358589150
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1246825926
Short name T2594
Test name
Test status
Simulation time 169509227 ps
CPU time 0.87 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:20:50 PM PDT 24
Peak memory 207540 kb
Host smart-ce5f0f88-9208-4f52-8912-c341f2422662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468
25926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1246825926
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2743262898
Short name T1494
Test name
Test status
Simulation time 167302278 ps
CPU time 0.86 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207472 kb
Host smart-68b0b5d6-6972-41c4-82cb-b8a88bc28ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27432
62898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2743262898
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2358151124
Short name T2625
Test name
Test status
Simulation time 199130049 ps
CPU time 0.91 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207540 kb
Host smart-e4e02810-c751-43b9-95b9-53275b2ca49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23581
51124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2358151124
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1556971077
Short name T1074
Test name
Test status
Simulation time 974490589 ps
CPU time 2.81 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207760 kb
Host smart-af61108c-9a99-40ea-b77a-8bf59ef80bff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1556971077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1556971077
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2241707485
Short name T3157
Test name
Test status
Simulation time 37653316433 ps
CPU time 67.53 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:21:53 PM PDT 24
Peak memory 207780 kb
Host smart-78d5cec2-219d-4beb-bef9-28b53cd4051d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417
07485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2241707485
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.634758669
Short name T2421
Test name
Test status
Simulation time 4980665271 ps
CPU time 32.39 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207864 kb
Host smart-8d502df1-6731-4a81-84cb-09829b67b887
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634758669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.634758669
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2626165418
Short name T3456
Test name
Test status
Simulation time 1583417491 ps
CPU time 3.09 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207528 kb
Host smart-7fde8ac3-6971-4848-bd3f-d2de06f4ce58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
65418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2626165418
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1423058634
Short name T1785
Test name
Test status
Simulation time 147981231 ps
CPU time 0.83 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207488 kb
Host smart-25e7a925-a8a7-4ed9-9f17-8c5da4c5ff19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
58634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1423058634
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.494077829
Short name T2960
Test name
Test status
Simulation time 39881394 ps
CPU time 0.7 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207520 kb
Host smart-ecbf2f1b-0caa-4558-91df-43954319d701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49407
7829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.494077829
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2726754889
Short name T1091
Test name
Test status
Simulation time 1004009768 ps
CPU time 2.51 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207804 kb
Host smart-56043eae-8476-45fb-8601-79c31916b36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27267
54889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2726754889
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.1209343791
Short name T3467
Test name
Test status
Simulation time 322551415 ps
CPU time 1.08 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207536 kb
Host smart-d1ae24bb-2b7f-4123-9755-9c89cb80ed1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1209343791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1209343791
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2980520593
Short name T1734
Test name
Test status
Simulation time 225097299 ps
CPU time 1.67 seconds
Started Aug 08 06:20:42 PM PDT 24
Finished Aug 08 06:20:44 PM PDT 24
Peak memory 207668 kb
Host smart-78cd195c-f17c-4f3a-a1d7-d646cee71d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29805
20593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2980520593
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3885092392
Short name T2903
Test name
Test status
Simulation time 220414890 ps
CPU time 1.17 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 215896 kb
Host smart-69d458a8-7b9a-4a98-93ea-f111b9dbd90f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3885092392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3885092392
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.599710103
Short name T2349
Test name
Test status
Simulation time 142312423 ps
CPU time 0.83 seconds
Started Aug 08 06:20:48 PM PDT 24
Finished Aug 08 06:20:49 PM PDT 24
Peak memory 207492 kb
Host smart-2d855cf0-ddf0-4960-89e4-1a1c3cfdc4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59971
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.599710103
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3696624394
Short name T1899
Test name
Test status
Simulation time 245007972 ps
CPU time 1.13 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:20:45 PM PDT 24
Peak memory 207636 kb
Host smart-04364ee9-b4b7-41b0-88a7-d418017920f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36966
24394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3696624394
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2478184386
Short name T816
Test name
Test status
Simulation time 2906931648 ps
CPU time 85.18 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:22:15 PM PDT 24
Peak memory 218004 kb
Host smart-375f0612-9b78-4027-a785-90cace53d2d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2478184386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2478184386
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.41833538
Short name T3205
Test name
Test status
Simulation time 5004141410 ps
CPU time 64.32 seconds
Started Aug 08 06:20:44 PM PDT 24
Finished Aug 08 06:21:49 PM PDT 24
Peak memory 207756 kb
Host smart-f28f3e51-74ef-4f4e-baa2-a774e36019e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=41833538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.41833538
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1830314640
Short name T2271
Test name
Test status
Simulation time 179794746 ps
CPU time 0.94 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207544 kb
Host smart-c3def436-1e00-432d-9b08-ecda4fcd4772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
14640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1830314640
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.594076492
Short name T1076
Test name
Test status
Simulation time 23326461763 ps
CPU time 29.42 seconds
Started Aug 08 06:20:49 PM PDT 24
Finished Aug 08 06:21:18 PM PDT 24
Peak memory 216052 kb
Host smart-28eb6c30-4fde-4f5e-b43c-9ed2a1e88084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59407
6492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.594076492
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.428391245
Short name T2785
Test name
Test status
Simulation time 10666708768 ps
CPU time 12.37 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:04 PM PDT 24
Peak memory 207912 kb
Host smart-6e7b7786-7d82-478e-a68c-635ea6c75f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42839
1245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.428391245
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1112843692
Short name T1045
Test name
Test status
Simulation time 2577911284 ps
CPU time 18.32 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 218828 kb
Host smart-d5243e6b-4e0f-4092-8d68-790c9acc917a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
43692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1112843692
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1509202902
Short name T2148
Test name
Test status
Simulation time 3922819924 ps
CPU time 110.56 seconds
Started Aug 08 06:20:46 PM PDT 24
Finished Aug 08 06:22:37 PM PDT 24
Peak memory 216140 kb
Host smart-efc94fc0-3d1e-4b17-baeb-2e43df9ddcc3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1509202902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1509202902
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3174319193
Short name T2920
Test name
Test status
Simulation time 238325291 ps
CPU time 1 seconds
Started Aug 08 06:20:47 PM PDT 24
Finished Aug 08 06:20:48 PM PDT 24
Peak memory 207512 kb
Host smart-eaf38187-8621-4092-afae-27c23c764551
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3174319193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3174319193
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3236277097
Short name T2381
Test name
Test status
Simulation time 194754616 ps
CPU time 0.98 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207576 kb
Host smart-7c310285-0fff-49b6-98cc-7a7cc3201769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32362
77097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3236277097
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.1663404721
Short name T1826
Test name
Test status
Simulation time 2327846129 ps
CPU time 66.01 seconds
Started Aug 08 06:20:47 PM PDT 24
Finished Aug 08 06:21:56 PM PDT 24
Peak memory 217584 kb
Host smart-f70c21ad-6421-485b-9a51-8edd5b8d01d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1663404721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.1663404721
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.434262165
Short name T2389
Test name
Test status
Simulation time 162836888 ps
CPU time 0.88 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207576 kb
Host smart-cbe30a3d-40e7-417b-a5d9-b5940c6a9761
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=434262165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.434262165
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.443688584
Short name T2395
Test name
Test status
Simulation time 140447546 ps
CPU time 0.83 seconds
Started Aug 08 06:20:42 PM PDT 24
Finished Aug 08 06:20:43 PM PDT 24
Peak memory 207500 kb
Host smart-dd84aad2-3c79-42d4-9c45-07ab4707e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44368
8584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.443688584
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.405533625
Short name T135
Test name
Test status
Simulation time 216209432 ps
CPU time 1 seconds
Started Aug 08 06:20:40 PM PDT 24
Finished Aug 08 06:20:41 PM PDT 24
Peak memory 207620 kb
Host smart-fd25fcad-b83a-4fe4-accc-1feccc60094a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40553
3625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.405533625
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2669731637
Short name T1588
Test name
Test status
Simulation time 159104413 ps
CPU time 0.86 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:20:51 PM PDT 24
Peak memory 207592 kb
Host smart-30961374-7452-4c54-89dd-e2562f70fb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
31637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2669731637
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3561221228
Short name T2396
Test name
Test status
Simulation time 178379811 ps
CPU time 0.85 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207620 kb
Host smart-43c675be-b9a8-4900-bbde-faec9224f7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35612
21228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3561221228
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2001831951
Short name T254
Test name
Test status
Simulation time 255880232 ps
CPU time 0.93 seconds
Started Aug 08 06:20:43 PM PDT 24
Finished Aug 08 06:20:44 PM PDT 24
Peak memory 207560 kb
Host smart-4d27c9b3-3bf0-42a1-9c6b-f1428581810b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
31951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2001831951
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.585926308
Short name T2640
Test name
Test status
Simulation time 175848156 ps
CPU time 0.86 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207520 kb
Host smart-7ce60c24-618f-4ebb-9aa1-a53bd3e70ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58592
6308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.585926308
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3205641813
Short name T2383
Test name
Test status
Simulation time 202700268 ps
CPU time 0.98 seconds
Started Aug 08 06:20:45 PM PDT 24
Finished Aug 08 06:20:46 PM PDT 24
Peak memory 207624 kb
Host smart-b94bded0-8f95-4284-a0fc-2e072b19d7aa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3205641813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3205641813
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4245666732
Short name T213
Test name
Test status
Simulation time 153083595 ps
CPU time 0.86 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207540 kb
Host smart-93ac3e55-f653-4722-b803-c52b37cdc757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
66732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4245666732
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3170110972
Short name T1386
Test name
Test status
Simulation time 64365670 ps
CPU time 0.75 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 207492 kb
Host smart-528a897e-e6cb-48ae-860e-fd011f7d9c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
10972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3170110972
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.267246284
Short name T3002
Test name
Test status
Simulation time 19018189843 ps
CPU time 54.8 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:21:45 PM PDT 24
Peak memory 216068 kb
Host smart-abe1ac0d-bcbc-4800-8e4b-951dd323c8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
6284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.267246284
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2141504471
Short name T237
Test name
Test status
Simulation time 178132204 ps
CPU time 0.95 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207508 kb
Host smart-a88c8943-5283-4cd5-89a8-553ff25672c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415
04471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2141504471
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.4286974680
Short name T1890
Test name
Test status
Simulation time 231971351 ps
CPU time 0.98 seconds
Started Aug 08 06:20:51 PM PDT 24
Finished Aug 08 06:20:52 PM PDT 24
Peak memory 207508 kb
Host smart-9437da03-134b-4345-a982-a0b740f01be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42869
74680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.4286974680
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3722312637
Short name T1137
Test name
Test status
Simulation time 236155271 ps
CPU time 0.99 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:02 PM PDT 24
Peak memory 207516 kb
Host smart-afdeb3d5-1cfc-4593-89db-2dacd34533e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37223
12637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3722312637
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.882247149
Short name T1396
Test name
Test status
Simulation time 174260733 ps
CPU time 0.94 seconds
Started Aug 08 06:21:01 PM PDT 24
Finished Aug 08 06:21:02 PM PDT 24
Peak memory 207604 kb
Host smart-470d7aea-f8a6-4112-a39c-e2315b0fce06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88224
7149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.882247149
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.587628609
Short name T1050
Test name
Test status
Simulation time 251646521 ps
CPU time 1.01 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207792 kb
Host smart-f87d87a5-a2d7-4a02-aa00-aeb224d29a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58762
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.587628609
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.2445210585
Short name T51
Test name
Test status
Simulation time 260605648 ps
CPU time 1.23 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207584 kb
Host smart-751499cf-375f-4160-881e-377401cc5483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
10585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2445210585
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3076240121
Short name T2505
Test name
Test status
Simulation time 154077208 ps
CPU time 0.88 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207548 kb
Host smart-764b47fd-8602-4b0d-b3c5-03f93c52f4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30762
40121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3076240121
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2753294587
Short name T2434
Test name
Test status
Simulation time 153964327 ps
CPU time 0.84 seconds
Started Aug 08 06:21:02 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207564 kb
Host smart-a99e36c7-86ad-4498-b2d9-29ee094072c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
94587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2753294587
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1899586027
Short name T647
Test name
Test status
Simulation time 230210935 ps
CPU time 1 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207576 kb
Host smart-7b4adf42-0d28-44a1-b8fb-4aee43f55a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
86027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1899586027
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1117089333
Short name T3412
Test name
Test status
Simulation time 2026610335 ps
CPU time 15.47 seconds
Started Aug 08 06:21:07 PM PDT 24
Finished Aug 08 06:21:22 PM PDT 24
Peak memory 216036 kb
Host smart-7c33eb3b-549e-4f71-8c51-8505fb445195
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1117089333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1117089333
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.273670109
Short name T2111
Test name
Test status
Simulation time 183051176 ps
CPU time 0.86 seconds
Started Aug 08 06:21:05 PM PDT 24
Finished Aug 08 06:21:06 PM PDT 24
Peak memory 207596 kb
Host smart-c6d1ebcc-9561-436a-bbfa-bd989b4a0010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
0109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.273670109
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3113910619
Short name T535
Test name
Test status
Simulation time 152766736 ps
CPU time 0.88 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207544 kb
Host smart-d2fe83e7-fe4d-4f0e-acf1-3d784c0c5791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31139
10619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3113910619
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3737555200
Short name T2286
Test name
Test status
Simulation time 680058211 ps
CPU time 1.8 seconds
Started Aug 08 06:21:04 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207532 kb
Host smart-9ac37f50-aa64-4b05-a7f8-7a21f9874351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
55200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3737555200
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3948516922
Short name T2185
Test name
Test status
Simulation time 2651534284 ps
CPU time 19.71 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 216144 kb
Host smart-90158f0a-8629-4e36-a05d-df763f28a241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
16922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3948516922
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2115774023
Short name T1117
Test name
Test status
Simulation time 1505999590 ps
CPU time 12.48 seconds
Started Aug 08 06:20:50 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207708 kb
Host smart-ade9dd41-6017-49e1-a8ef-10f19b94484c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115774023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2115774023
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.3430920591
Short name T1997
Test name
Test status
Simulation time 622475145 ps
CPU time 1.94 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207568 kb
Host smart-822fca4d-67a1-4490-a755-cb68463a2cc2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430920591 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.3430920591
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.2424362404
Short name T3037
Test name
Test status
Simulation time 602147518 ps
CPU time 1.7 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207576 kb
Host smart-e921b326-683d-4119-8e13-775649e2912e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424362404 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.2424362404
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.750768627
Short name T188
Test name
Test status
Simulation time 601740820 ps
CPU time 1.54 seconds
Started Aug 08 06:22:28 PM PDT 24
Finished Aug 08 06:22:30 PM PDT 24
Peak memory 207572 kb
Host smart-fb5a37c9-fc7c-48bb-ad23-319818bbc01a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750768627 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.750768627
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.2502930100
Short name T3523
Test name
Test status
Simulation time 496594946 ps
CPU time 1.51 seconds
Started Aug 08 06:22:49 PM PDT 24
Finished Aug 08 06:22:50 PM PDT 24
Peak memory 207516 kb
Host smart-855f427b-3130-4380-8239-52f312dbc12e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502930100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.2502930100
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.3017440997
Short name T3277
Test name
Test status
Simulation time 577447309 ps
CPU time 1.54 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207524 kb
Host smart-1a3d3578-136b-43fa-b343-d300b4e9be78
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017440997 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.3017440997
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.1953176077
Short name T3203
Test name
Test status
Simulation time 445914421 ps
CPU time 1.47 seconds
Started Aug 08 06:22:39 PM PDT 24
Finished Aug 08 06:22:41 PM PDT 24
Peak memory 207576 kb
Host smart-6d2a6759-8575-46b7-9fed-2bc592d11382
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953176077 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.1953176077
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.1075861196
Short name T3491
Test name
Test status
Simulation time 491359721 ps
CPU time 1.46 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207600 kb
Host smart-af000030-0e50-459e-9001-a00ec4952be0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075861196 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.1075861196
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.4151175841
Short name T1539
Test name
Test status
Simulation time 467779469 ps
CPU time 1.45 seconds
Started Aug 08 06:22:37 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207576 kb
Host smart-504b1c52-10ba-4d8c-a485-4e97a8425693
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151175841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.4151175841
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.2907645516
Short name T2846
Test name
Test status
Simulation time 588189600 ps
CPU time 1.59 seconds
Started Aug 08 06:23:00 PM PDT 24
Finished Aug 08 06:23:01 PM PDT 24
Peak memory 207528 kb
Host smart-74e3032b-18fb-4e5a-b16f-8aaa71301346
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907645516 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.2907645516
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.2125564456
Short name T1676
Test name
Test status
Simulation time 645613733 ps
CPU time 1.81 seconds
Started Aug 08 06:22:56 PM PDT 24
Finished Aug 08 06:22:58 PM PDT 24
Peak memory 207528 kb
Host smart-909a6f4c-b570-46ec-b866-4ee200a7178f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125564456 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.2125564456
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.423466879
Short name T2443
Test name
Test status
Simulation time 518071372 ps
CPU time 1.53 seconds
Started Aug 08 06:22:53 PM PDT 24
Finished Aug 08 06:22:55 PM PDT 24
Peak memory 207516 kb
Host smart-223fb844-137d-4601-9981-43d970ac7f74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423466879 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.423466879
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2505442396
Short name T2521
Test name
Test status
Simulation time 57258705 ps
CPU time 0.66 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:00 PM PDT 24
Peak memory 207632 kb
Host smart-5f385027-bca1-482f-b3ec-34f486b4fa31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2505442396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2505442396
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.929916230
Short name T2056
Test name
Test status
Simulation time 10218743522 ps
CPU time 13.66 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:21:07 PM PDT 24
Peak memory 207816 kb
Host smart-f41c1e94-ba0f-4b4d-9113-38d2085aad22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929916230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.929916230
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1470550640
Short name T1725
Test name
Test status
Simulation time 20616514451 ps
CPU time 25.8 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:32 PM PDT 24
Peak memory 207844 kb
Host smart-7a30e8f0-d869-439b-b0f5-9dbcc12458e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470550640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1470550640
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2844509463
Short name T2824
Test name
Test status
Simulation time 29518803446 ps
CPU time 35.89 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:47 PM PDT 24
Peak memory 207816 kb
Host smart-f4aae2a6-7b32-40b4-838a-bef9bc14b171
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844509463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.2844509463
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2222847173
Short name T2088
Test name
Test status
Simulation time 184394402 ps
CPU time 0.93 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:11 PM PDT 24
Peak memory 207508 kb
Host smart-726ec5cb-73fc-44cb-b2c9-48c66d429b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22228
47173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2222847173
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3807598688
Short name T3119
Test name
Test status
Simulation time 195956366 ps
CPU time 0.87 seconds
Started Aug 08 06:21:03 PM PDT 24
Finished Aug 08 06:21:04 PM PDT 24
Peak memory 207516 kb
Host smart-e879ec30-4e7d-4ea7-99d8-3ce4df388735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38075
98688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3807598688
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.62394633
Short name T1056
Test name
Test status
Simulation time 172189413 ps
CPU time 0.87 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 207524 kb
Host smart-dd53fb40-b3d5-4efe-bfe8-3658a9e2c9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62394
633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.62394633
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2802684839
Short name T3135
Test name
Test status
Simulation time 1072974449 ps
CPU time 2.71 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207788 kb
Host smart-17b35068-f5d6-4ccd-8bd8-2811dc4d68bc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2802684839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2802684839
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2754782266
Short name T3276
Test name
Test status
Simulation time 2365921317 ps
CPU time 14.43 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 208084 kb
Host smart-e36fb711-63eb-41d0-bd38-eb8d7815fe43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754782266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2754782266
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1320381425
Short name T693
Test name
Test status
Simulation time 625714717 ps
CPU time 1.66 seconds
Started Aug 08 06:21:03 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207596 kb
Host smart-af6e6486-671a-45d6-8230-95dfa3589f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13203
81425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1320381425
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.853163112
Short name T1838
Test name
Test status
Simulation time 146577077 ps
CPU time 0.87 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207580 kb
Host smart-3c7b711a-6b45-43c8-b26a-bf29a794c5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85316
3112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.853163112
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1789207250
Short name T1443
Test name
Test status
Simulation time 42480373 ps
CPU time 0.71 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207504 kb
Host smart-64279e8b-e1e1-42cd-9ef1-5263e7cf2a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
07250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1789207250
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1424557631
Short name T846
Test name
Test status
Simulation time 788032062 ps
CPU time 2.19 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207772 kb
Host smart-c0f4d285-19c7-43b3-8369-e6582380d72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
57631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1424557631
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.171662105
Short name T400
Test name
Test status
Simulation time 226064225 ps
CPU time 0.96 seconds
Started Aug 08 06:20:57 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207544 kb
Host smart-b7887393-ccdf-4a16-a8a9-95047b5b078b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=171662105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.171662105
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.823373232
Short name T2708
Test name
Test status
Simulation time 180215926 ps
CPU time 1.68 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207764 kb
Host smart-fc9eec5f-44a7-4411-b823-4dd314bc5ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82337
3232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.823373232
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1154508774
Short name T1645
Test name
Test status
Simulation time 262341569 ps
CPU time 1.24 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 215888 kb
Host smart-76d66272-87cd-4de8-b595-755d8be22839
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1154508774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1154508774
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1524323412
Short name T2258
Test name
Test status
Simulation time 217886634 ps
CPU time 0.96 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207560 kb
Host smart-883c392e-e20f-4828-b23f-3f66f7091b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
23412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1524323412
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.302312649
Short name T1950
Test name
Test status
Simulation time 248063433 ps
CPU time 0.99 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:11 PM PDT 24
Peak memory 207588 kb
Host smart-88119fcf-64a1-46f8-af49-fc08171f1ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
2649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.302312649
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3393652839
Short name T831
Test name
Test status
Simulation time 3610123557 ps
CPU time 29.54 seconds
Started Aug 08 06:20:59 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 216176 kb
Host smart-d6a45c0c-e4cf-4705-9ef2-e11fa089d3d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3393652839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3393652839
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3860397271
Short name T786
Test name
Test status
Simulation time 10573624018 ps
CPU time 67.84 seconds
Started Aug 08 06:21:05 PM PDT 24
Finished Aug 08 06:22:13 PM PDT 24
Peak memory 207776 kb
Host smart-1e19df84-f7bd-4748-9aa8-024650b64aeb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3860397271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3860397271
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2872543469
Short name T828
Test name
Test status
Simulation time 258038491 ps
CPU time 0.99 seconds
Started Aug 08 06:20:58 PM PDT 24
Finished Aug 08 06:21:04 PM PDT 24
Peak memory 207580 kb
Host smart-f870c255-b263-4c5c-9f9e-d5aa17c00022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
43469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2872543469
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1407229339
Short name T2779
Test name
Test status
Simulation time 12943156527 ps
CPU time 17.22 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:21:11 PM PDT 24
Peak memory 207832 kb
Host smart-43c31327-01bc-46eb-8c36-f183f1966b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14072
29339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1407229339
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3681369489
Short name T1906
Test name
Test status
Simulation time 5775216657 ps
CPU time 7.65 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 216232 kb
Host smart-90c021d3-c459-4d25-a8dd-4841d0566658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36813
69489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3681369489
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2452906705
Short name T331
Test name
Test status
Simulation time 2834948992 ps
CPU time 79.76 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:22:14 PM PDT 24
Peak memory 216044 kb
Host smart-ae07600b-5ce4-47cb-952b-9c1ddd870ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
06705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2452906705
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3504758451
Short name T1286
Test name
Test status
Simulation time 1889175931 ps
CPU time 14.38 seconds
Started Aug 08 06:20:58 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 217468 kb
Host smart-fbcfc8b8-2b60-440e-9c7b-5f07566eb33d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3504758451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3504758451
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2874274674
Short name T3614
Test name
Test status
Simulation time 236962657 ps
CPU time 1.01 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207500 kb
Host smart-9cdf09ed-a2ac-4284-8fb4-d559c422c197
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2874274674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2874274674
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2852843319
Short name T1715
Test name
Test status
Simulation time 186949624 ps
CPU time 0.89 seconds
Started Aug 08 06:21:02 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207572 kb
Host smart-7f47c780-9fac-4f41-ba92-a9443189c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28528
43319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2852843319
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2990637150
Short name T596
Test name
Test status
Simulation time 2282719306 ps
CPU time 16.85 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 216068 kb
Host smart-053ae6d0-1c9e-42ce-b632-5be26d09c7f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2990637150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2990637150
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3106104581
Short name T1940
Test name
Test status
Simulation time 151824914 ps
CPU time 0.83 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207616 kb
Host smart-95635d84-4ae3-4aca-9df9-31d541f81323
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3106104581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3106104581
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2019211360
Short name T3404
Test name
Test status
Simulation time 148445265 ps
CPU time 0.84 seconds
Started Aug 08 06:21:07 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207500 kb
Host smart-b6e3b421-f25c-4285-896e-2ac569e4fcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20192
11360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2019211360
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4183681459
Short name T3067
Test name
Test status
Simulation time 197804993 ps
CPU time 0.91 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207524 kb
Host smart-96f237b1-0ca6-414e-9a6b-3f9cf09ec2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41836
81459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4183681459
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3298348349
Short name T2530
Test name
Test status
Simulation time 201216120 ps
CPU time 0.94 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207512 kb
Host smart-a75b2bcc-e599-4739-b3e8-29d29cf5dab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983
48349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3298348349
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2293944269
Short name T1238
Test name
Test status
Simulation time 179051609 ps
CPU time 0.89 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207544 kb
Host smart-14d038b1-9412-4107-b83f-ae6eb70e2d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
44269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2293944269
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.153527677
Short name T2633
Test name
Test status
Simulation time 207802829 ps
CPU time 0.94 seconds
Started Aug 08 06:21:02 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207544 kb
Host smart-f5be0888-65fe-4194-b24c-c5a332c2414a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15352
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.153527677
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2745448521
Short name T3434
Test name
Test status
Simulation time 161226058 ps
CPU time 0.86 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207540 kb
Host smart-7ba42a16-5ac8-442b-bb79-a05f6e387a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
48521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2745448521
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1338862536
Short name T947
Test name
Test status
Simulation time 193265712 ps
CPU time 0.95 seconds
Started Aug 08 06:20:53 PM PDT 24
Finished Aug 08 06:20:54 PM PDT 24
Peak memory 207564 kb
Host smart-19fefb78-098f-4181-be6e-09eb8e0b8b1a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1338862536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1338862536
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.4092735657
Short name T1630
Test name
Test status
Simulation time 185204967 ps
CPU time 0.89 seconds
Started Aug 08 06:20:57 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207484 kb
Host smart-c3daa498-6e78-4456-a678-7e1c9a5f0f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40927
35657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.4092735657
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1605359799
Short name T940
Test name
Test status
Simulation time 75157046 ps
CPU time 0.73 seconds
Started Aug 08 06:21:09 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207592 kb
Host smart-03d7c61b-e751-43b6-9e3f-a8a310f961bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16053
59799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1605359799
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2005569338
Short name T1722
Test name
Test status
Simulation time 17262183609 ps
CPU time 46.37 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:21:41 PM PDT 24
Peak memory 216032 kb
Host smart-c2c67cf5-6da6-47de-83d2-6d110c5b7b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20055
69338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2005569338
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2007553195
Short name T2539
Test name
Test status
Simulation time 224272160 ps
CPU time 0.98 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207556 kb
Host smart-c8263ff6-c3fa-4a56-80f2-641dca7a09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
53195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2007553195
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.879803703
Short name T2445
Test name
Test status
Simulation time 164589142 ps
CPU time 0.9 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207552 kb
Host smart-faa5437f-6fe9-4b56-aa8f-cf16f8884d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87980
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.879803703
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1854980423
Short name T3170
Test name
Test status
Simulation time 219451909 ps
CPU time 0.92 seconds
Started Aug 08 06:21:07 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207484 kb
Host smart-d878c63f-e48f-4a41-af2e-02caf44f6337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18549
80423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1854980423
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2818106701
Short name T2116
Test name
Test status
Simulation time 183445131 ps
CPU time 0.88 seconds
Started Aug 08 06:20:57 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207576 kb
Host smart-541bdd09-8c17-4403-9aa3-c254522c6b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
06701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2818106701
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.357310087
Short name T1308
Test name
Test status
Simulation time 201810906 ps
CPU time 0.91 seconds
Started Aug 08 06:20:59 PM PDT 24
Finished Aug 08 06:21:00 PM PDT 24
Peak memory 207560 kb
Host smart-58c788d0-2eff-4a59-bcbd-d4f1a80ac464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35731
0087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.357310087
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.54398374
Short name T1969
Test name
Test status
Simulation time 244368141 ps
CPU time 1.09 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207508 kb
Host smart-316e3446-67d7-4cea-821e-9dfb4ff57c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54398
374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.54398374
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1377020149
Short name T2045
Test name
Test status
Simulation time 168977718 ps
CPU time 0.83 seconds
Started Aug 08 06:20:58 PM PDT 24
Finished Aug 08 06:20:59 PM PDT 24
Peak memory 207448 kb
Host smart-92cd733a-b141-4a26-bd9a-5f780f95080c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
20149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1377020149
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1036158595
Short name T3079
Test name
Test status
Simulation time 172100490 ps
CPU time 0.88 seconds
Started Aug 08 06:21:19 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207616 kb
Host smart-fb82c01d-9f33-4e9b-a9ac-e8c045a65390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361
58595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1036158595
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3994479573
Short name T695
Test name
Test status
Simulation time 281080806 ps
CPU time 1.15 seconds
Started Aug 08 06:21:21 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207472 kb
Host smart-d37a94bd-c2ab-4561-b2d6-02a14a77db2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39944
79573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3994479573
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2057149656
Short name T3036
Test name
Test status
Simulation time 1697431559 ps
CPU time 47.4 seconds
Started Aug 08 06:21:16 PM PDT 24
Finished Aug 08 06:22:03 PM PDT 24
Peak memory 216024 kb
Host smart-55b9a26a-3bae-4a78-82bd-72841125127d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2057149656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2057149656
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4040365263
Short name T1211
Test name
Test status
Simulation time 176646725 ps
CPU time 0.87 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207564 kb
Host smart-5d714d4f-109f-45d6-a55a-94a02fbffd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40403
65263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4040365263
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1051178778
Short name T1266
Test name
Test status
Simulation time 185270016 ps
CPU time 0.9 seconds
Started Aug 08 06:20:52 PM PDT 24
Finished Aug 08 06:20:53 PM PDT 24
Peak memory 207620 kb
Host smart-d179abb7-80dd-4a43-96a5-3481fc475308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
78778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1051178778
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2661031445
Short name T1774
Test name
Test status
Simulation time 700587687 ps
CPU time 1.81 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207464 kb
Host smart-ed76b5b0-1854-4e51-9979-be41b9637530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
31445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2661031445
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1392400554
Short name T3051
Test name
Test status
Simulation time 3322715968 ps
CPU time 25.12 seconds
Started Aug 08 06:21:17 PM PDT 24
Finished Aug 08 06:21:42 PM PDT 24
Peak memory 216064 kb
Host smart-c7ccf8d8-bc50-4e38-887c-2f5b864efdaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13924
00554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1392400554
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2024474825
Short name T2494
Test name
Test status
Simulation time 191905456 ps
CPU time 0.92 seconds
Started Aug 08 06:20:59 PM PDT 24
Finished Aug 08 06:21:00 PM PDT 24
Peak memory 207504 kb
Host smart-55f91ead-8875-4f3f-b27b-ea5f7f440ab7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024474825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2024474825
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.1841323443
Short name T2788
Test name
Test status
Simulation time 510982017 ps
CPU time 1.45 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207516 kb
Host smart-1b23e8f9-4527-47cb-8416-700fd67c3706
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841323443 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.1841323443
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.2443775309
Short name T1708
Test name
Test status
Simulation time 493408718 ps
CPU time 1.54 seconds
Started Aug 08 06:22:51 PM PDT 24
Finished Aug 08 06:22:53 PM PDT 24
Peak memory 207620 kb
Host smart-cc698afa-617a-4861-a8aa-87dc7b05469a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443775309 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.2443775309
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.3421926067
Short name T3150
Test name
Test status
Simulation time 499228944 ps
CPU time 1.6 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:22:49 PM PDT 24
Peak memory 207596 kb
Host smart-69d0a414-38e5-42a7-8ab6-83544865d95f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421926067 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.3421926067
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.3371560126
Short name T1010
Test name
Test status
Simulation time 501910309 ps
CPU time 1.44 seconds
Started Aug 08 06:22:38 PM PDT 24
Finished Aug 08 06:22:40 PM PDT 24
Peak memory 207500 kb
Host smart-893f7b66-22fb-4829-8d16-058e0b437f19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371560126 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.3371560126
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.3441652436
Short name T255
Test name
Test status
Simulation time 606459439 ps
CPU time 1.57 seconds
Started Aug 08 06:22:36 PM PDT 24
Finished Aug 08 06:22:38 PM PDT 24
Peak memory 207540 kb
Host smart-34ffbc4a-4664-4e33-a26d-a53b5c8dc429
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441652436 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.3441652436
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.1416431321
Short name T3475
Test name
Test status
Simulation time 518894894 ps
CPU time 1.62 seconds
Started Aug 08 06:22:43 PM PDT 24
Finished Aug 08 06:22:45 PM PDT 24
Peak memory 207540 kb
Host smart-69ad689a-5204-488b-8d44-e11bc2cedb0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416431321 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.1416431321
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.1490578509
Short name T1320
Test name
Test status
Simulation time 498212154 ps
CPU time 1.64 seconds
Started Aug 08 06:22:47 PM PDT 24
Finished Aug 08 06:22:48 PM PDT 24
Peak memory 207540 kb
Host smart-c1c37366-9155-43e8-a782-d06915041eb7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490578509 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.1490578509
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.440458843
Short name T1951
Test name
Test status
Simulation time 590822224 ps
CPU time 1.6 seconds
Started Aug 08 06:22:46 PM PDT 24
Finished Aug 08 06:22:48 PM PDT 24
Peak memory 207568 kb
Host smart-c2b75a17-45d0-4d79-aac8-38ded026972b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440458843 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.440458843
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.3616051824
Short name T2356
Test name
Test status
Simulation time 671240677 ps
CPU time 1.75 seconds
Started Aug 08 06:22:41 PM PDT 24
Finished Aug 08 06:22:43 PM PDT 24
Peak memory 207540 kb
Host smart-35bb5747-82bd-4411-8aec-67ffc2efcdba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616051824 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.3616051824
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.197348794
Short name T192
Test name
Test status
Simulation time 679479788 ps
CPU time 1.67 seconds
Started Aug 08 06:22:45 PM PDT 24
Finished Aug 08 06:22:47 PM PDT 24
Peak memory 207608 kb
Host smart-5104fa6a-ecfd-4794-80e1-0acb4fbb6992
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197348794 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.197348794
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.3610096849
Short name T2177
Test name
Test status
Simulation time 444426505 ps
CPU time 1.37 seconds
Started Aug 08 06:22:24 PM PDT 24
Finished Aug 08 06:22:25 PM PDT 24
Peak memory 207548 kb
Host smart-8dccab53-489c-4a92-9d7b-aa279b3fed86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610096849 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.3610096849
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1008384927
Short name T1459
Test name
Test status
Simulation time 48401491 ps
CPU time 0.64 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207552 kb
Host smart-f5c3316d-a02a-48a0-8fd5-9a1139caf01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1008384927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1008384927
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.646736437
Short name T696
Test name
Test status
Simulation time 11576627700 ps
CPU time 14.14 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207964 kb
Host smart-474edce7-c4ce-40e0-ab16-f7fcf2a1d7aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646736437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon
_wake_disconnect.646736437
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2254925197
Short name T1301
Test name
Test status
Simulation time 20248868950 ps
CPU time 23.73 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207848 kb
Host smart-3122a124-fd93-42ca-97ef-0c8edd3cba5e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254925197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2254925197
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3150757949
Short name T2858
Test name
Test status
Simulation time 24057104137 ps
CPU time 36.06 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 215980 kb
Host smart-cca799a2-b0a8-4a4f-a5b4-3d2c63686b77
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150757949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.3150757949
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1514352671
Short name T3556
Test name
Test status
Simulation time 163084193 ps
CPU time 0.89 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207500 kb
Host smart-c0860eb2-d90c-4633-ac65-7d24e3318ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
52671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1514352671
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.249353205
Short name T2847
Test name
Test status
Simulation time 157720701 ps
CPU time 0.89 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207608 kb
Host smart-ada25bdf-5c6d-4e66-803a-c4ed5710dd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24935
3205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.249353205
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.273228838
Short name T2417
Test name
Test status
Simulation time 282279395 ps
CPU time 1.22 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:18 PM PDT 24
Peak memory 207592 kb
Host smart-33faf1c6-a55f-4b85-8916-e04b9622fd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27322
8838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.273228838
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1200447468
Short name T500
Test name
Test status
Simulation time 734868285 ps
CPU time 2.08 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207816 kb
Host smart-786cb54c-7662-43a7-bed8-ba8565184fc0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1200447468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1200447468
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.137731774
Short name T2489
Test name
Test status
Simulation time 29274572270 ps
CPU time 45.14 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207828 kb
Host smart-0c1e49f7-4969-45b7-8a80-9b39220bfacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13773
1774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.137731774
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.2028673527
Short name T1176
Test name
Test status
Simulation time 2906226559 ps
CPU time 26.1 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207828 kb
Host smart-4374961a-7b20-4da8-9769-df7e0bd86be7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028673527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2028673527
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.2365080926
Short name T644
Test name
Test status
Simulation time 708851259 ps
CPU time 2.03 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207504 kb
Host smart-5b0afed7-75fb-4b9b-8eb6-bee7adc3df4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23650
80926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.2365080926
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3546590624
Short name T1514
Test name
Test status
Simulation time 160742451 ps
CPU time 0.86 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207612 kb
Host smart-29e56214-feec-4d73-ba54-d30a26c133b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465
90624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3546590624
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1705332477
Short name T2542
Test name
Test status
Simulation time 31803089 ps
CPU time 0.68 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207612 kb
Host smart-2df2a575-0d59-4960-83e2-8416da36d64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
32477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1705332477
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3419840226
Short name T2086
Test name
Test status
Simulation time 1000016588 ps
CPU time 2.75 seconds
Started Aug 08 06:14:18 PM PDT 24
Finished Aug 08 06:14:21 PM PDT 24
Peak memory 207748 kb
Host smart-34a51907-f9a2-403e-a3fb-b78fd026ad4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
40226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3419840226
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.1255891273
Short name T2144
Test name
Test status
Simulation time 240123127 ps
CPU time 1.12 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207520 kb
Host smart-e9a1bd6c-db91-4f26-8371-5ca5095852c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1255891273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.1255891273
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.93073098
Short name T3232
Test name
Test status
Simulation time 206824769 ps
CPU time 2.07 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:18 PM PDT 24
Peak memory 207648 kb
Host smart-91239d37-388b-4b2f-a8cf-911e3293faaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93073
098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.93073098
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3134157065
Short name T1178
Test name
Test status
Simulation time 203485619 ps
CPU time 1.07 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 216004 kb
Host smart-f12c7d5a-84de-4abc-82d7-4ed9cde2f743
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3134157065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3134157065
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3445363948
Short name T2012
Test name
Test status
Simulation time 141077376 ps
CPU time 0.89 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207748 kb
Host smart-195c2b1d-8401-4981-b887-5875e89fe543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34453
63948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3445363948
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1451718444
Short name T1848
Test name
Test status
Simulation time 191596924 ps
CPU time 0.86 seconds
Started Aug 08 06:14:16 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207576 kb
Host smart-51483049-3f21-4221-bc80-634575444cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14517
18444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1451718444
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1075112819
Short name T890
Test name
Test status
Simulation time 3933223296 ps
CPU time 115.43 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:16:12 PM PDT 24
Peak memory 217784 kb
Host smart-b01d6ead-3994-4e9e-975b-e43ed4264373
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1075112819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1075112819
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1644520576
Short name T3110
Test name
Test status
Simulation time 6106637208 ps
CPU time 50.4 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:15:06 PM PDT 24
Peak memory 207872 kb
Host smart-a9af3f0b-02ae-4ff2-a278-f779f864a939
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1644520576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1644520576
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2953518919
Short name T1566
Test name
Test status
Simulation time 238551572 ps
CPU time 1.1 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207524 kb
Host smart-09298d46-db39-48b1-b3c8-9413d6949bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29535
18919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2953518919
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1396862128
Short name T3029
Test name
Test status
Simulation time 26584514338 ps
CPU time 43.24 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:56 PM PDT 24
Peak memory 216024 kb
Host smart-5cf201d6-edbe-4a92-ab94-47c01dc6170f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968
62128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1396862128
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3920522870
Short name T606
Test name
Test status
Simulation time 5401170406 ps
CPU time 7.7 seconds
Started Aug 08 06:14:20 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 216228 kb
Host smart-8794fc45-5dc5-4427-a199-2a830247a56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
22870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3920522870
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.152473587
Short name T3041
Test name
Test status
Simulation time 4464789928 ps
CPU time 41.85 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 224220 kb
Host smart-8605f0ef-dbe1-4b91-ae7a-ee18ac223963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
3587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.152473587
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3882245473
Short name T4
Test name
Test status
Simulation time 2789811937 ps
CPU time 20.05 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 217840 kb
Host smart-4e6cf55e-476b-41e4-bbb3-e437375405d7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3882245473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3882245473
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.193075783
Short name T2826
Test name
Test status
Simulation time 296752318 ps
CPU time 1.06 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207556 kb
Host smart-60ff7a05-d9af-4897-b1c4-ec49bd36edc4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=193075783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.193075783
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3204704759
Short name T1916
Test name
Test status
Simulation time 208217175 ps
CPU time 1.01 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207572 kb
Host smart-f94a23c5-62b7-4356-845d-d405b701147f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
04759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3204704759
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.3527149939
Short name T646
Test name
Test status
Simulation time 2634594363 ps
CPU time 18.24 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:35 PM PDT 24
Peak memory 218096 kb
Host smart-83e7fda6-a5ba-4bfb-a0a4-d5c5916e2c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
49939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.3527149939
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2275191226
Short name T243
Test name
Test status
Simulation time 1726842035 ps
CPU time 15.48 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 224144 kb
Host smart-87435131-a68e-423c-b9e6-24381723658b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2275191226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2275191226
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3447974753
Short name T1080
Test name
Test status
Simulation time 1610693310 ps
CPU time 15.77 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:32 PM PDT 24
Peak memory 216520 kb
Host smart-5b83b33a-6f81-4bb2-adc8-a44eaac8b6ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3447974753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3447974753
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.268476861
Short name T2035
Test name
Test status
Simulation time 166574310 ps
CPU time 0.86 seconds
Started Aug 08 06:14:16 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207512 kb
Host smart-451ba24e-3eac-4b51-97e6-ea353f3562d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=268476861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.268476861
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.11986662
Short name T2803
Test name
Test status
Simulation time 141504820 ps
CPU time 0.92 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207528 kb
Host smart-a0fadaf0-1b22-48ac-b6ed-ed078ed074e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.11986662
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1192433823
Short name T128
Test name
Test status
Simulation time 230926675 ps
CPU time 1.07 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207512 kb
Host smart-00a364ff-2fa1-48fe-a8c1-c31b00c6417c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
33823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1192433823
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1607090116
Short name T1851
Test name
Test status
Simulation time 159994358 ps
CPU time 0.9 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207540 kb
Host smart-a2b12127-dd9b-419a-9aec-f84d2b06b689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16070
90116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1607090116
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1497972830
Short name T2348
Test name
Test status
Simulation time 172554406 ps
CPU time 0.86 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207512 kb
Host smart-f1a1f59e-b556-4353-95c1-8b4ba5a84a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14979
72830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1497972830
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4289470934
Short name T543
Test name
Test status
Simulation time 154841901 ps
CPU time 0.86 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207556 kb
Host smart-dff91cc3-876e-4da3-af28-0a5a09a6b6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
70934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4289470934
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.246102743
Short name T2196
Test name
Test status
Simulation time 150793142 ps
CPU time 0.91 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207512 kb
Host smart-7a9c6e0d-fc2b-40d1-9c3c-6b3d7f64157f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.246102743
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3540839712
Short name T629
Test name
Test status
Simulation time 236913076 ps
CPU time 1.19 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207588 kb
Host smart-2a1fd683-0146-4a56-9952-7dee214039bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3540839712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3540839712
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2624552143
Short name T1966
Test name
Test status
Simulation time 148938818 ps
CPU time 0.88 seconds
Started Aug 08 06:14:13 PM PDT 24
Finished Aug 08 06:14:14 PM PDT 24
Peak memory 207532 kb
Host smart-48ddb54f-9fa8-4a59-9614-9e2164381cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245
52143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2624552143
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3035151742
Short name T3108
Test name
Test status
Simulation time 57660533 ps
CPU time 0.7 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207460 kb
Host smart-019f1a90-4845-4fb8-a805-2e55743c15c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30351
51742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3035151742
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1427710343
Short name T2470
Test name
Test status
Simulation time 5856295355 ps
CPU time 16.06 seconds
Started Aug 08 06:14:17 PM PDT 24
Finished Aug 08 06:14:33 PM PDT 24
Peak memory 216144 kb
Host smart-c46b8c3b-0261-4264-ab6c-af460a785bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
10343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1427710343
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3419992402
Short name T1256
Test name
Test status
Simulation time 237217641 ps
CPU time 0.97 seconds
Started Aug 08 06:14:18 PM PDT 24
Finished Aug 08 06:14:19 PM PDT 24
Peak memory 207564 kb
Host smart-ac2df6f1-31df-4792-8493-14bb2bc760d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34199
92402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3419992402
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2752029708
Short name T2133
Test name
Test status
Simulation time 192416758 ps
CPU time 0.94 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:16 PM PDT 24
Peak memory 207440 kb
Host smart-8c969bb1-ab73-44e2-bf20-f70e395ff1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27520
29708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2752029708
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.34215600
Short name T728
Test name
Test status
Simulation time 7093124027 ps
CPU time 36.29 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 224248 kb
Host smart-d1847aad-094d-4c9e-a44b-4bdeed6e653e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.34215600
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2467890763
Short name T1420
Test name
Test status
Simulation time 4526673061 ps
CPU time 108.33 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 224180 kb
Host smart-23e457a7-8823-4111-9383-0fb1c4bc4495
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2467890763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2467890763
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2156076457
Short name T689
Test name
Test status
Simulation time 9521584549 ps
CPU time 48.63 seconds
Started Aug 08 06:14:18 PM PDT 24
Finished Aug 08 06:15:07 PM PDT 24
Peak memory 218252 kb
Host smart-a92b627b-1a82-4ce9-9e7f-03c1fa59bab5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156076457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2156076457
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2093748097
Short name T1326
Test name
Test status
Simulation time 235945797 ps
CPU time 0.96 seconds
Started Aug 08 06:14:16 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207584 kb
Host smart-34207d91-7f80-4d58-a8b8-61f4be9bec6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
48097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2093748097
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2680726272
Short name T2459
Test name
Test status
Simulation time 157592856 ps
CPU time 0.85 seconds
Started Aug 08 06:14:14 PM PDT 24
Finished Aug 08 06:14:15 PM PDT 24
Peak memory 207532 kb
Host smart-3e813a85-060e-44dc-a4c0-750b9697a5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26807
26272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2680726272
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.3729158384
Short name T883
Test name
Test status
Simulation time 20187028907 ps
CPU time 25.19 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207592 kb
Host smart-a08165ed-e8af-4fbf-866e-4e2cd81e8034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
58384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.3729158384
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2827718409
Short name T2906
Test name
Test status
Simulation time 153206418 ps
CPU time 0.82 seconds
Started Aug 08 06:14:19 PM PDT 24
Finished Aug 08 06:14:20 PM PDT 24
Peak memory 207564 kb
Host smart-608857fa-1750-4375-8795-90c994cf222a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
18409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2827718409
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.3403199821
Short name T1237
Test name
Test status
Simulation time 335321431 ps
CPU time 1.34 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:17 PM PDT 24
Peak memory 207564 kb
Host smart-b6f8a17c-1846-4b27-a96f-76efe77c14cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031
99821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.3403199821
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2600794068
Short name T654
Test name
Test status
Simulation time 160420382 ps
CPU time 0.85 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207568 kb
Host smart-74a3bee3-5854-4676-bc84-da35ab1212ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26007
94068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2600794068
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1215606113
Short name T1365
Test name
Test status
Simulation time 148222771 ps
CPU time 0.81 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 207536 kb
Host smart-c9dc3f85-fd37-4b67-94d9-888f880095f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12156
06113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1215606113
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3423993254
Short name T642
Test name
Test status
Simulation time 214414955 ps
CPU time 0.96 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207564 kb
Host smart-c1e90a6d-c2d2-4afb-b42d-3861c87bb4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34239
93254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3423993254
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.4123805737
Short name T3543
Test name
Test status
Simulation time 2945047269 ps
CPU time 27.76 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 217300 kb
Host smart-e7abddea-cd34-4b62-adf5-81443dd2c378
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4123805737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.4123805737
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1421086621
Short name T3040
Test name
Test status
Simulation time 179269839 ps
CPU time 0.89 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207576 kb
Host smart-f91b669a-f788-4b5a-9870-7c1907e98e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14210
86621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1421086621
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.355915318
Short name T1529
Test name
Test status
Simulation time 190262985 ps
CPU time 0.91 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207584 kb
Host smart-4fffcfb8-32ae-4cae-87e1-bc9f63f772b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35591
5318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.355915318
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2004453996
Short name T1011
Test name
Test status
Simulation time 1106661627 ps
CPU time 2.62 seconds
Started Aug 08 06:14:32 PM PDT 24
Finished Aug 08 06:14:34 PM PDT 24
Peak memory 207744 kb
Host smart-3a3c9cd6-cbfb-49a3-9f21-bb2db3a19a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
53996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2004453996
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2205286650
Short name T560
Test name
Test status
Simulation time 1750242360 ps
CPU time 50.06 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:15:17 PM PDT 24
Peak memory 215980 kb
Host smart-0e8f1837-0d9d-4da8-b335-caee7a2c2493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
86650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2205286650
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.308277957
Short name T1952
Test name
Test status
Simulation time 850082545 ps
CPU time 18.75 seconds
Started Aug 08 06:14:15 PM PDT 24
Finished Aug 08 06:14:34 PM PDT 24
Peak memory 207728 kb
Host smart-ca025647-44f5-4954-9387-5ee91f9615ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308277957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_
handshake.308277957
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.1358363893
Short name T1282
Test name
Test status
Simulation time 568219045 ps
CPU time 1.55 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207532 kb
Host smart-d55e4eb1-540e-4677-a803-2a626b62bf8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358363893 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.1358363893
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.48905205
Short name T2953
Test name
Test status
Simulation time 475599930 ps
CPU time 1.39 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 207516 kb
Host smart-9fec5103-1965-4341-8030-d857892bbeac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48905205 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.48905205
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.2361675875
Short name T493
Test name
Test status
Simulation time 213935628 ps
CPU time 1.01 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:07 PM PDT 24
Peak memory 207468 kb
Host smart-f457fd21-8d8d-4d92-bd43-decbcd2ef0d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2361675875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.2361675875
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.1700083116
Short name T1648
Test name
Test status
Simulation time 448494311 ps
CPU time 1.52 seconds
Started Aug 08 06:21:05 PM PDT 24
Finished Aug 08 06:21:07 PM PDT 24
Peak memory 207560 kb
Host smart-786ff291-39f1-4336-bd35-c1c8a382a100
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700083116 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.1700083116
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.1244554649
Short name T418
Test name
Test status
Simulation time 305734114 ps
CPU time 1.1 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207468 kb
Host smart-2ebdb31c-b8e4-4aab-83c3-fb40c188cb36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1244554649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.1244554649
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.1482058883
Short name T1562
Test name
Test status
Simulation time 502406451 ps
CPU time 1.51 seconds
Started Aug 08 06:21:01 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207560 kb
Host smart-2b76c15d-7ec9-4e12-b065-7f936ea4bef7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482058883 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.1482058883
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.504489230
Short name T392
Test name
Test status
Simulation time 789692253 ps
CPU time 1.72 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:07 PM PDT 24
Peak memory 207568 kb
Host smart-b1b9d950-116d-4fbb-a18e-c563f4b627d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=504489230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.504489230
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.4292729093
Short name T2021
Test name
Test status
Simulation time 663436059 ps
CPU time 1.7 seconds
Started Aug 08 06:21:05 PM PDT 24
Finished Aug 08 06:21:06 PM PDT 24
Peak memory 207560 kb
Host smart-6aaa58c4-091a-4278-93aa-907d28cba423
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292729093 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.4292729093
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.2359141744
Short name T3490
Test name
Test status
Simulation time 848542577 ps
CPU time 1.83 seconds
Started Aug 08 06:21:19 PM PDT 24
Finished Aug 08 06:21:21 PM PDT 24
Peak memory 207588 kb
Host smart-faeac0fb-54a5-40fd-97a2-4adc5e72082d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2359141744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.2359141744
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.839474094
Short name T1883
Test name
Test status
Simulation time 587732665 ps
CPU time 1.59 seconds
Started Aug 08 06:21:03 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207564 kb
Host smart-72edac01-881b-481c-9f7b-fcd0804eac64
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839474094 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.839474094
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.4039121992
Short name T3414
Test name
Test status
Simulation time 697140527 ps
CPU time 1.87 seconds
Started Aug 08 06:21:01 PM PDT 24
Finished Aug 08 06:21:03 PM PDT 24
Peak memory 207520 kb
Host smart-a28ba555-a8a0-4266-86fd-37f293827952
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4039121992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.4039121992
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.309373466
Short name T1191
Test name
Test status
Simulation time 514017815 ps
CPU time 1.63 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207620 kb
Host smart-8e1ab702-5c27-4323-bf92-79e49f8940d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309373466 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.309373466
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.2530443521
Short name T18
Test name
Test status
Simulation time 616310126 ps
CPU time 1.82 seconds
Started Aug 08 06:21:03 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207560 kb
Host smart-b4553977-40ee-4d0e-ad85-c6cab6df701b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530443521 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.2530443521
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.1341844876
Short name T2955
Test name
Test status
Simulation time 478814224 ps
CPU time 1.34 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207608 kb
Host smart-b76be2a7-b08a-4080-a7ba-e65c2004b9ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1341844876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.1341844876
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.2398923593
Short name T2036
Test name
Test status
Simulation time 671720277 ps
CPU time 1.82 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207620 kb
Host smart-2e1d720f-434b-4147-9be4-475f413f128a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398923593 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.2398923593
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.1781852533
Short name T389
Test name
Test status
Simulation time 539824967 ps
CPU time 1.47 seconds
Started Aug 08 06:20:59 PM PDT 24
Finished Aug 08 06:21:01 PM PDT 24
Peak memory 207496 kb
Host smart-e3d2e466-8825-4aba-bf3d-224545aaa2f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1781852533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.1781852533
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.4173857294
Short name T584
Test name
Test status
Simulation time 631115691 ps
CPU time 1.68 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207572 kb
Host smart-173139ed-f1a8-4545-b7aa-e7cd2c2b98d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173857294 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.4173857294
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.290427929
Short name T365
Test name
Test status
Simulation time 577678140 ps
CPU time 1.53 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207548 kb
Host smart-67ea3103-8ada-4e67-b5af-47c4b7f575ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=290427929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.290427929
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.811065034
Short name T2304
Test name
Test status
Simulation time 463204844 ps
CPU time 1.43 seconds
Started Aug 08 06:21:18 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207816 kb
Host smart-43f3baae-34de-4563-b301-b13ec7883fe5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811065034 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.811065034
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1514014897
Short name T207
Test name
Test status
Simulation time 41009226 ps
CPU time 0.67 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207624 kb
Host smart-71460bf1-573d-4366-807d-a7a3501da121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1514014897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1514014897
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1916403949
Short name T2200
Test name
Test status
Simulation time 9645644847 ps
CPU time 14.95 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:43 PM PDT 24
Peak memory 207812 kb
Host smart-d82625c7-e106-4e07-8a3a-0249c781a55f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916403949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.1916403949
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4260975222
Short name T14
Test name
Test status
Simulation time 14091399107 ps
CPU time 17.39 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 215992 kb
Host smart-f762f1a7-bd0c-4ac8-b470-ab7ebfd073c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260975222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4260975222
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2250773078
Short name T2486
Test name
Test status
Simulation time 29256562261 ps
CPU time 32.87 seconds
Started Aug 08 06:14:24 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207844 kb
Host smart-28ec406f-cf45-4c9f-b61f-d96c18a01cf8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250773078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.2250773078
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1519201998
Short name T664
Test name
Test status
Simulation time 150683262 ps
CPU time 0.88 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207636 kb
Host smart-a205a04e-ff12-41b0-882a-3805b3fe74c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
01998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1519201998
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1295175681
Short name T1788
Test name
Test status
Simulation time 141147777 ps
CPU time 0.82 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207564 kb
Host smart-73fedc91-42c8-407c-a9f6-a026e7ca4ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12951
75681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1295175681
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3003657913
Short name T1606
Test name
Test status
Simulation time 184110357 ps
CPU time 0.88 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207512 kb
Host smart-b63749fc-85c6-4d59-a112-0fb1fe41c1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
57913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3003657913
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1807706114
Short name T2775
Test name
Test status
Simulation time 1260391482 ps
CPU time 2.96 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207712 kb
Host smart-3aad8a4e-140b-4a61-a737-427ffe751c5b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1807706114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1807706114
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.261537061
Short name T3495
Test name
Test status
Simulation time 45395000950 ps
CPU time 82.69 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 207868 kb
Host smart-ce57c282-85e5-4221-9407-2a496b5f7296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153
7061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.261537061
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2902556441
Short name T2706
Test name
Test status
Simulation time 4932263489 ps
CPU time 31.42 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:58 PM PDT 24
Peak memory 207852 kb
Host smart-d07eefd8-1d7d-4925-b577-88d60cfc1c82
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902556441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2902556441
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2554442838
Short name T334
Test name
Test status
Simulation time 627288684 ps
CPU time 1.78 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207516 kb
Host smart-51cee310-9392-4129-9f96-9bfccd75ff1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25544
42838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2554442838
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3475354710
Short name T2862
Test name
Test status
Simulation time 156883751 ps
CPU time 0.82 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207484 kb
Host smart-f6fe2a03-4579-4111-8ff9-b0f089bff275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34753
54710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3475354710
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1404184786
Short name T1540
Test name
Test status
Simulation time 39246972 ps
CPU time 0.72 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207520 kb
Host smart-9e928455-1b9e-427e-b0e4-147c7ec0079c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14041
84786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1404184786
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.840238741
Short name T1349
Test name
Test status
Simulation time 976076323 ps
CPU time 2.81 seconds
Started Aug 08 06:14:31 PM PDT 24
Finished Aug 08 06:14:34 PM PDT 24
Peak memory 207684 kb
Host smart-1a96cd94-710a-4404-bb79-515c3a7f436b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84023
8741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.840238741
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.677182127
Short name T413
Test name
Test status
Simulation time 662335409 ps
CPU time 1.67 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207540 kb
Host smart-408db789-007b-4412-b22b-89d3846a21c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=677182127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.677182127
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.640485851
Short name T1057
Test name
Test status
Simulation time 184877033 ps
CPU time 2.5 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207680 kb
Host smart-26ef1d99-dca7-4fb6-a21f-91a93e329ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64048
5851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.640485851
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1474796133
Short name T1328
Test name
Test status
Simulation time 221624699 ps
CPU time 1.24 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 215476 kb
Host smart-d2d0506f-0824-4ee4-95e8-51926e096b33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1474796133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1474796133
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2872886063
Short name T2529
Test name
Test status
Simulation time 146074605 ps
CPU time 0.8 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207568 kb
Host smart-0b70c618-0366-4efc-afd9-26affe628d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
86063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2872886063
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.236419993
Short name T2107
Test name
Test status
Simulation time 275268075 ps
CPU time 1.05 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207584 kb
Host smart-eb21b4aa-14ed-4ae5-a5ac-f4314a2751ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23641
9993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.236419993
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3190301004
Short name T1085
Test name
Test status
Simulation time 4688389078 ps
CPU time 47.25 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:15:16 PM PDT 24
Peak memory 218048 kb
Host smart-e25d2509-65e1-46ec-a8b5-4e796fae40c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3190301004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3190301004
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2191620879
Short name T1059
Test name
Test status
Simulation time 8329407700 ps
CPU time 54.48 seconds
Started Aug 08 06:14:32 PM PDT 24
Finished Aug 08 06:15:26 PM PDT 24
Peak memory 207868 kb
Host smart-755e8f2e-635b-4c21-b085-3934ffa17c55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2191620879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2191620879
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.40377677
Short name T2728
Test name
Test status
Simulation time 215006670 ps
CPU time 0.98 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207556 kb
Host smart-d34c32c6-d334-48b4-8574-5373e92f5f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.40377677
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2858600106
Short name T2600
Test name
Test status
Simulation time 27720252673 ps
CPU time 49.53 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:15:18 PM PDT 24
Peak memory 216768 kb
Host smart-a5edb4ba-37b7-4e53-9b3e-ddaede5d848a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
00106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2858600106
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.713919237
Short name T2193
Test name
Test status
Simulation time 11344327579 ps
CPU time 12.91 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207900 kb
Host smart-c0fc02e3-6a19-4358-a70c-db4e2ff8ae61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71391
9237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.713919237
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.588998976
Short name T3541
Test name
Test status
Simulation time 4798422025 ps
CPU time 48.88 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:15:19 PM PDT 24
Peak memory 218996 kb
Host smart-24b706fd-cca5-4181-a313-78cb554e94cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58899
8976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.588998976
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1904900214
Short name T3086
Test name
Test status
Simulation time 3859370814 ps
CPU time 37.89 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:15:04 PM PDT 24
Peak memory 216168 kb
Host smart-8f55529b-219a-475a-95ee-c4ee763f6e8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1904900214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1904900214
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2788350822
Short name T3054
Test name
Test status
Simulation time 253747961 ps
CPU time 1.05 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207588 kb
Host smart-ebb3bef6-209d-49e2-86fc-c635d085fd6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2788350822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2788350822
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.587266800
Short name T2164
Test name
Test status
Simulation time 183399443 ps
CPU time 0.87 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207536 kb
Host smart-c9273914-07e1-402c-82c7-91024a795e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58726
6800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.587266800
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.2527737973
Short name T1506
Test name
Test status
Simulation time 2316159562 ps
CPU time 22.15 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 216112 kb
Host smart-3458ba25-d63e-4661-9ef1-de9b1bbc7e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25277
37973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.2527737973
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3214983679
Short name T2318
Test name
Test status
Simulation time 2166796147 ps
CPU time 59.21 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:15:25 PM PDT 24
Peak memory 216040 kb
Host smart-d348c80a-71ce-4c83-be1a-edd71b4e2d73
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3214983679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3214983679
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2389556586
Short name T2581
Test name
Test status
Simulation time 165567696 ps
CPU time 0.91 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207580 kb
Host smart-77fa204b-77c5-47c0-8580-dc6f03ad8ebd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2389556586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2389556586
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.107765480
Short name T896
Test name
Test status
Simulation time 161166299 ps
CPU time 0.87 seconds
Started Aug 08 06:14:31 PM PDT 24
Finished Aug 08 06:14:32 PM PDT 24
Peak memory 207540 kb
Host smart-5e049745-3293-4d8a-995f-e1a27eeee627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10776
5480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.107765480
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1043759873
Short name T138
Test name
Test status
Simulation time 222110495 ps
CPU time 1 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 207596 kb
Host smart-7e7136e5-f7a8-47e8-a1a9-fba37ddfde8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
59873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1043759873
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1829069232
Short name T2122
Test name
Test status
Simulation time 174442336 ps
CPU time 0.97 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207532 kb
Host smart-a44d9f33-5c6c-4967-9553-0d2861e1acb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18290
69232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1829069232
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2378663304
Short name T839
Test name
Test status
Simulation time 204565680 ps
CPU time 0.95 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207532 kb
Host smart-fa79c374-6210-448a-aa37-d857da67aa8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
63304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2378663304
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2997912940
Short name T1141
Test name
Test status
Simulation time 203634118 ps
CPU time 0.92 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207560 kb
Host smart-3e8091ec-8827-48f0-af74-c8bba43978eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
12940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2997912940
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1285606773
Short name T3565
Test name
Test status
Simulation time 176265118 ps
CPU time 0.95 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207052 kb
Host smart-9170557f-7f30-45fc-83e5-e2d17573c359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
06773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1285606773
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3843588528
Short name T911
Test name
Test status
Simulation time 238485166 ps
CPU time 1.09 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207604 kb
Host smart-92d2fdfd-3100-4482-a721-3d8ddfc294c1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3843588528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3843588528
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2798491573
Short name T1992
Test name
Test status
Simulation time 150107820 ps
CPU time 0.84 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:28 PM PDT 24
Peak memory 207548 kb
Host smart-113ef17e-ea07-49c2-9195-cc185028ef91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27984
91573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2798491573
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.958909935
Short name T3060
Test name
Test status
Simulation time 39399375 ps
CPU time 0.67 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207504 kb
Host smart-8e44d469-4cdc-478a-be17-56c80397ce7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95890
9935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.958909935
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1909665780
Short name T2620
Test name
Test status
Simulation time 20615844122 ps
CPU time 53.11 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:15:19 PM PDT 24
Peak memory 216016 kb
Host smart-4453e986-c0e3-42fb-bb7d-fd0f21b1a8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
65780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1909665780
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4220726402
Short name T2264
Test name
Test status
Simulation time 170131088 ps
CPU time 0.84 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207540 kb
Host smart-ee8904fc-1cc8-4421-8572-65ab38e291c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42207
26402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4220726402
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.631055249
Short name T2251
Test name
Test status
Simulation time 166315025 ps
CPU time 0.88 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 207560 kb
Host smart-b8f886e9-68cb-4d2d-bce7-032ad28603cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63105
5249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.631055249
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1605907077
Short name T675
Test name
Test status
Simulation time 3248411885 ps
CPU time 88.37 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:15:55 PM PDT 24
Peak memory 216148 kb
Host smart-9bdef626-d086-4ed9-b374-ac4b6e0b7db0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605907077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1605907077
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3647595621
Short name T1902
Test name
Test status
Simulation time 3104738659 ps
CPU time 20.6 seconds
Started Aug 08 06:14:32 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 217256 kb
Host smart-aeadeb63-4cb9-4db8-a0e2-3a8568d34080
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3647595621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3647595621
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2576942392
Short name T5
Test name
Test status
Simulation time 6212632365 ps
CPU time 22.62 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 224288 kb
Host smart-b0ce42a4-46e3-4c67-8b9f-3ca95aa982c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576942392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2576942392
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1627754618
Short name T2943
Test name
Test status
Simulation time 182563317 ps
CPU time 0.9 seconds
Started Aug 08 06:14:26 PM PDT 24
Finished Aug 08 06:14:27 PM PDT 24
Peak memory 207588 kb
Host smart-96aa17ae-e8ee-47c8-8236-6bd8fc13fbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
54618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1627754618
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.63331141
Short name T3132
Test name
Test status
Simulation time 187923864 ps
CPU time 0.9 seconds
Started Aug 08 06:14:31 PM PDT 24
Finished Aug 08 06:14:32 PM PDT 24
Peak memory 207572 kb
Host smart-52128b81-1593-47e8-8505-9a79130ac14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63331
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.63331141
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.1879759317
Short name T102
Test name
Test status
Simulation time 20220964725 ps
CPU time 23.08 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 207672 kb
Host smart-ebe8e0bd-1519-44a9-8cfb-c82e670acf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
59317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.1879759317
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1469633439
Short name T832
Test name
Test status
Simulation time 151778454 ps
CPU time 0.79 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207556 kb
Host smart-05c1c804-8274-4597-b9c7-a91f52790d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14696
33439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1469633439
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.79391730
Short name T3365
Test name
Test status
Simulation time 255565514 ps
CPU time 1.06 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207596 kb
Host smart-5287c839-08b8-42f2-b25e-462fe2270529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79391
730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.79391730
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.973311087
Short name T2751
Test name
Test status
Simulation time 223553749 ps
CPU time 0.96 seconds
Started Aug 08 06:14:33 PM PDT 24
Finished Aug 08 06:14:34 PM PDT 24
Peak memory 207504 kb
Host smart-6c7f9a8f-9ae1-4fe3-870e-bd64fec6024b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97331
1087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.973311087
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1168221180
Short name T1483
Test name
Test status
Simulation time 156424045 ps
CPU time 0.83 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:29 PM PDT 24
Peak memory 207792 kb
Host smart-31ea1a4b-41c9-47c8-83f8-9d73878103ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
21180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1168221180
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.4265116561
Short name T648
Test name
Test status
Simulation time 200966449 ps
CPU time 1.01 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207568 kb
Host smart-d6022c08-d992-449c-9896-a6423cdd686e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42651
16561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.4265116561
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.899890853
Short name T3210
Test name
Test status
Simulation time 2856843865 ps
CPU time 79.35 seconds
Started Aug 08 06:14:32 PM PDT 24
Finished Aug 08 06:15:51 PM PDT 24
Peak memory 224208 kb
Host smart-38202550-9753-4645-a1ec-e2ab6ce555c7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=899890853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.899890853
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2565763565
Short name T562
Test name
Test status
Simulation time 188825668 ps
CPU time 0.92 seconds
Started Aug 08 06:14:30 PM PDT 24
Finished Aug 08 06:14:31 PM PDT 24
Peak memory 207560 kb
Host smart-0a91a3f9-fc2b-44ed-8fd8-74457ff44939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
63565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2565763565
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2457000570
Short name T2812
Test name
Test status
Simulation time 196064407 ps
CPU time 0.94 seconds
Started Aug 08 06:14:29 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207552 kb
Host smart-fc1fa9fe-cd99-4f3e-900d-02581ca8276e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
00570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2457000570
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.596718821
Short name T730
Test name
Test status
Simulation time 842746065 ps
CPU time 2.17 seconds
Started Aug 08 06:14:28 PM PDT 24
Finished Aug 08 06:14:30 PM PDT 24
Peak memory 207728 kb
Host smart-8dffca7c-9436-42d1-9f29-76b98a96c2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59671
8821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.596718821
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3849747990
Short name T2782
Test name
Test status
Simulation time 1621201736 ps
CPU time 43.39 seconds
Started Aug 08 06:14:31 PM PDT 24
Finished Aug 08 06:15:15 PM PDT 24
Peak memory 217560 kb
Host smart-59857df2-c248-4e5a-b82c-6a04ed2ba38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38497
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3849747990
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.1627392333
Short name T632
Test name
Test status
Simulation time 571737868 ps
CPU time 11.72 seconds
Started Aug 08 06:14:27 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207724 kb
Host smart-a7746c3b-77fe-488e-be2e-c1d02f1ea246
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627392333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.1627392333
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.799725109
Short name T1493
Test name
Test status
Simulation time 476595509 ps
CPU time 1.53 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207544 kb
Host smart-4c1f0807-2640-437b-9c07-57db2adb8d80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799725109 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.799725109
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.454205273
Short name T474
Test name
Test status
Simulation time 303089081 ps
CPU time 1.01 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207508 kb
Host smart-f7199153-e841-4f2a-a7f6-e7489a3073c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=454205273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.454205273
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.1444032848
Short name T1620
Test name
Test status
Simulation time 612277165 ps
CPU time 1.72 seconds
Started Aug 08 06:21:17 PM PDT 24
Finished Aug 08 06:21:19 PM PDT 24
Peak memory 207576 kb
Host smart-bb4f3ac8-c312-43f1-8ed5-845b93f4fb32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444032848 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.1444032848
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.429903169
Short name T395
Test name
Test status
Simulation time 270389556 ps
CPU time 1.06 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:56 PM PDT 24
Peak memory 207540 kb
Host smart-cc5f611c-bed2-46a5-96d1-932dcff25a00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=429903169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.429903169
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.703016128
Short name T1937
Test name
Test status
Simulation time 650790891 ps
CPU time 1.71 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207516 kb
Host smart-d94331fc-8e58-408b-b88d-a59b84b291f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703016128 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.703016128
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.76093573
Short name T248
Test name
Test status
Simulation time 679336878 ps
CPU time 1.54 seconds
Started Aug 08 06:21:03 PM PDT 24
Finished Aug 08 06:21:05 PM PDT 24
Peak memory 207540 kb
Host smart-9eb31ada-095d-48f7-b499-71c75f10a585
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=76093573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.76093573
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.2759920794
Short name T2690
Test name
Test status
Simulation time 578143046 ps
CPU time 1.69 seconds
Started Aug 08 06:20:56 PM PDT 24
Finished Aug 08 06:20:58 PM PDT 24
Peak memory 207492 kb
Host smart-9fd1b46a-972d-404a-9a22-4e4a32251588
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759920794 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.2759920794
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.553961061
Short name T475
Test name
Test status
Simulation time 475296404 ps
CPU time 1.41 seconds
Started Aug 08 06:21:04 PM PDT 24
Finished Aug 08 06:21:06 PM PDT 24
Peak memory 207500 kb
Host smart-94303ced-3120-440c-9339-2687fa4d0e1a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=553961061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.553961061
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.3961567961
Short name T2587
Test name
Test status
Simulation time 535814899 ps
CPU time 1.55 seconds
Started Aug 08 06:21:09 PM PDT 24
Finished Aug 08 06:21:10 PM PDT 24
Peak memory 207636 kb
Host smart-d1a83fdb-1d18-480a-aa04-2381ef95ab31
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961567961 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.3961567961
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.643824863
Short name T377
Test name
Test status
Simulation time 828547843 ps
CPU time 1.91 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:10 PM PDT 24
Peak memory 207484 kb
Host smart-b2f6b412-96f1-40ad-b31f-4102ec4eb801
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=643824863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.643824863
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.325757606
Short name T1977
Test name
Test status
Simulation time 517407880 ps
CPU time 1.66 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207536 kb
Host smart-910fecdf-7bbd-4aab-a8dc-c04fa55dc8a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325757606 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.325757606
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.2775215711
Short name T2941
Test name
Test status
Simulation time 511720798 ps
CPU time 1.59 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207636 kb
Host smart-008d11f5-563a-4229-bbde-2a9358fbfd5a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775215711 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.2775215711
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.695483779
Short name T465
Test name
Test status
Simulation time 572753746 ps
CPU time 1.54 seconds
Started Aug 08 06:21:09 PM PDT 24
Finished Aug 08 06:21:10 PM PDT 24
Peak memory 207588 kb
Host smart-06a1fbb6-2e10-4bcf-a887-c92a3f4964ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=695483779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.695483779
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.4091053142
Short name T799
Test name
Test status
Simulation time 449336339 ps
CPU time 1.46 seconds
Started Aug 08 06:20:54 PM PDT 24
Finished Aug 08 06:20:55 PM PDT 24
Peak memory 207568 kb
Host smart-d3913b52-8843-4cb9-b9cd-fd0199f0fa37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091053142 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.4091053142
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.3069908779
Short name T480
Test name
Test status
Simulation time 626574002 ps
CPU time 1.7 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207524 kb
Host smart-cf6d9b36-134d-4668-a7d2-68f94a03b5d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3069908779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.3069908779
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.860491936
Short name T1415
Test name
Test status
Simulation time 582136175 ps
CPU time 1.54 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207584 kb
Host smart-b0daaf58-7e9a-4dc3-8a96-252a6e190b67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860491936 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.860491936
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.1418793517
Short name T490
Test name
Test status
Simulation time 544096086 ps
CPU time 1.67 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207536 kb
Host smart-6c21e0c4-5e70-4551-be07-334b0e466d70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1418793517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.1418793517
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.137200881
Short name T3062
Test name
Test status
Simulation time 555593094 ps
CPU time 1.54 seconds
Started Aug 08 06:21:22 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 207584 kb
Host smart-299fd63e-721c-48c8-9fbd-edc13f7a4228
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137200881 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.137200881
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1901792705
Short name T1272
Test name
Test status
Simulation time 39773103 ps
CPU time 0.68 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:14:47 PM PDT 24
Peak memory 207584 kb
Host smart-39c1652a-60b1-4be0-980b-b6ea162796ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1901792705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1901792705
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3234693347
Short name T2517
Test name
Test status
Simulation time 7063532768 ps
CPU time 10 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 215992 kb
Host smart-bc320a93-2ba6-4d98-ac54-ef6d37814a70
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234693347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3234693347
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.757409940
Short name T1300
Test name
Test status
Simulation time 31430794592 ps
CPU time 40.95 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:15:19 PM PDT 24
Peak memory 207812 kb
Host smart-e5a6e5a8-c9c9-47a0-9c32-e712c4f8061c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757409940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_resume.757409940
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2713048461
Short name T554
Test name
Test status
Simulation time 184234342 ps
CPU time 0.94 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 207512 kb
Host smart-06a1d5bd-1215-4cbc-8282-9857c23f8132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
48461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2713048461
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1514297207
Short name T2584
Test name
Test status
Simulation time 151185598 ps
CPU time 0.85 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207488 kb
Host smart-1ae5fb38-82d7-4284-812e-b1a414ae5d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15142
97207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1514297207
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1053697844
Short name T3178
Test name
Test status
Simulation time 544429524 ps
CPU time 1.79 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 207508 kb
Host smart-aed1d8be-5905-4c40-b827-27cf9e6832b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10536
97844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1053697844
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.554670460
Short name T3165
Test name
Test status
Simulation time 703096122 ps
CPU time 2.16 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:43 PM PDT 24
Peak memory 207564 kb
Host smart-7c37afb8-52af-4d82-aad9-fdcee1449e4c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=554670460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.554670460
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3478741276
Short name T180
Test name
Test status
Simulation time 30701142051 ps
CPU time 48.94 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:15:27 PM PDT 24
Peak memory 207800 kb
Host smart-395a72a6-489b-43d9-9a81-c3774c51f400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
41276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3478741276
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.554139548
Short name T1136
Test name
Test status
Simulation time 2003244238 ps
CPU time 17.16 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:56 PM PDT 24
Peak memory 207736 kb
Host smart-16a76988-602b-4f2b-a670-3212d11d8f02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554139548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.554139548
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4054369764
Short name T2745
Test name
Test status
Simulation time 1136124877 ps
CPU time 2.28 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207560 kb
Host smart-0e781ecb-f424-44eb-9d2a-7cd25127fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40543
69764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4054369764
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.866376408
Short name T2939
Test name
Test status
Simulation time 143005454 ps
CPU time 0.87 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207596 kb
Host smart-0cf06b29-bd5c-466c-ac5b-90b711acbce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86637
6408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.866376408
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.4207759542
Short name T3451
Test name
Test status
Simulation time 47602391 ps
CPU time 0.7 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207520 kb
Host smart-12bfc2d0-aca5-4d8b-92c3-7268c9a5e5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
59542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.4207759542
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3745306884
Short name T2901
Test name
Test status
Simulation time 929307760 ps
CPU time 2.37 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207752 kb
Host smart-a2a73f28-154f-45b3-8794-c4aeb15a35d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37453
06884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3745306884
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.970082923
Short name T458
Test name
Test status
Simulation time 461861896 ps
CPU time 1.27 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 207548 kb
Host smart-a2d2232b-ce77-4a8f-8de8-4c6c32da9b9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=970082923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.970082923
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1094034991
Short name T3433
Test name
Test status
Simulation time 451420405 ps
CPU time 2.6 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 207728 kb
Host smart-368f61c6-e806-4475-b185-f3a38111d1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
34991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1094034991
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.471704973
Short name T1321
Test name
Test status
Simulation time 223061775 ps
CPU time 1.12 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 215992 kb
Host smart-a8cc313c-8da4-4c85-8208-c203c400ca13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=471704973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.471704973
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3790271567
Short name T862
Test name
Test status
Simulation time 208109735 ps
CPU time 0.9 seconds
Started Aug 08 06:14:36 PM PDT 24
Finished Aug 08 06:14:37 PM PDT 24
Peak memory 207484 kb
Host smart-a40e158c-db48-4d71-9a27-af101e59dc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
71567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3790271567
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3377244904
Short name T998
Test name
Test status
Simulation time 189868520 ps
CPU time 0.95 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 207584 kb
Host smart-19133257-36c5-4de2-ac7d-0ed6636df12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33772
44904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3377244904
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.2112253334
Short name T3329
Test name
Test status
Simulation time 4492360893 ps
CPU time 129.78 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:16:51 PM PDT 24
Peak memory 217892 kb
Host smart-595ea624-1c76-437d-ae06-75a90a302f9c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2112253334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2112253334
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1707741794
Short name T3194
Test name
Test status
Simulation time 12175589439 ps
CPU time 81.58 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 207788 kb
Host smart-67fa02db-a92d-4680-ba63-dc7c00e94fb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1707741794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1707741794
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.864614408
Short name T1164
Test name
Test status
Simulation time 170900656 ps
CPU time 0.87 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:14:42 PM PDT 24
Peak memory 207604 kb
Host smart-607976d5-5719-4b9e-b222-06f487ee1d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86461
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.864614408
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2458061335
Short name T1836
Test name
Test status
Simulation time 31977524966 ps
CPU time 47.54 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:15:28 PM PDT 24
Peak memory 207880 kb
Host smart-e7a09783-eb3e-4edc-b290-ed63b42bc306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24580
61335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2458061335
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.416740269
Short name T2809
Test name
Test status
Simulation time 4032338675 ps
CPU time 6.45 seconds
Started Aug 08 06:14:44 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 216028 kb
Host smart-c51eda7f-9fa2-474b-98ad-822718d2fe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
0269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.416740269
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.413422708
Short name T1867
Test name
Test status
Simulation time 3555613600 ps
CPU time 36.13 seconds
Started Aug 08 06:14:42 PM PDT 24
Finished Aug 08 06:15:18 PM PDT 24
Peak memory 218860 kb
Host smart-b50b81e6-6ac4-46d1-a6e2-b8d33e7fb6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
2708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.413422708
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3699688669
Short name T2482
Test name
Test status
Simulation time 1527112005 ps
CPU time 15.67 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 217664 kb
Host smart-35457a17-3bae-4772-a57e-e79d21979817
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3699688669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3699688669
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.4041252925
Short name T532
Test name
Test status
Simulation time 251990194 ps
CPU time 1 seconds
Started Aug 08 06:14:56 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207568 kb
Host smart-111c205d-ea5c-4eb5-ad3c-2573e0faaf92
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4041252925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.4041252925
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3126893860
Short name T3282
Test name
Test status
Simulation time 201559557 ps
CPU time 1.02 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207548 kb
Host smart-1fa0ebcf-df27-44cc-969c-6bd4ca6a8770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31268
93860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3126893860
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.1902382427
Short name T3009
Test name
Test status
Simulation time 2446524979 ps
CPU time 24.56 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 224508 kb
Host smart-a3b1755d-2399-4836-90de-dca0a373a720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19023
82427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.1902382427
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.587922466
Short name T244
Test name
Test status
Simulation time 3136980854 ps
CPU time 24.08 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 224288 kb
Host smart-781ec340-bd94-462f-988b-af129131d97b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=587922466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.587922466
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1693658889
Short name T935
Test name
Test status
Simulation time 2243554544 ps
CPU time 16.46 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 217420 kb
Host smart-7d81f8b9-b75d-4ece-8445-cea2d0203cc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1693658889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1693658889
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1941502059
Short name T3234
Test name
Test status
Simulation time 190692733 ps
CPU time 0.97 seconds
Started Aug 08 06:14:36 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 207552 kb
Host smart-a1120e8d-7f26-4ee0-a4fc-fe4f57f32c37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1941502059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1941502059
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2510572160
Short name T841
Test name
Test status
Simulation time 143004094 ps
CPU time 0.84 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 207584 kb
Host smart-88f49787-fd03-4468-89b6-3db8b725e1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25105
72160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2510572160
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1631436815
Short name T144
Test name
Test status
Simulation time 200046866 ps
CPU time 0.92 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207644 kb
Host smart-6f966395-602f-4d90-b4b0-1a9b81bfcfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16314
36815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1631436815
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2994034304
Short name T245
Test name
Test status
Simulation time 146378010 ps
CPU time 0.87 seconds
Started Aug 08 06:14:37 PM PDT 24
Finished Aug 08 06:14:38 PM PDT 24
Peak memory 207648 kb
Host smart-7f655df2-917c-4b81-86fd-52260ef64cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
34304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2994034304
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4074504950
Short name T1521
Test name
Test status
Simulation time 164148592 ps
CPU time 0.88 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207432 kb
Host smart-af9f8e4e-69bd-4349-b068-f2d676190285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745
04950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4074504950
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2251376583
Short name T3121
Test name
Test status
Simulation time 196488702 ps
CPU time 0.91 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207580 kb
Host smart-189a3cab-8f4c-4a27-9d2b-8821622dc0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
76583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2251376583
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3354301604
Short name T1898
Test name
Test status
Simulation time 171108367 ps
CPU time 0.91 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207572 kb
Host smart-e3c182dc-d08b-4034-a33a-2db9585df31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33543
01604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3354301604
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.4164818074
Short name T2590
Test name
Test status
Simulation time 232848741 ps
CPU time 0.98 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207556 kb
Host smart-bba4aff8-4b7e-481f-a30c-37fbad7a1b32
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4164818074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.4164818074
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1386976271
Short name T752
Test name
Test status
Simulation time 149092926 ps
CPU time 0.85 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 207536 kb
Host smart-c197bd15-5be5-41ac-bd5c-450e4132a492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
76271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1386976271
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3184081199
Short name T1073
Test name
Test status
Simulation time 39094836 ps
CPU time 0.71 seconds
Started Aug 08 06:14:44 PM PDT 24
Finished Aug 08 06:14:44 PM PDT 24
Peak memory 207492 kb
Host smart-acbde31a-8483-4f49-9f95-48df7e7b3ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
81199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3184081199
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2969603023
Short name T294
Test name
Test status
Simulation time 14532388297 ps
CPU time 35.79 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:15:16 PM PDT 24
Peak memory 215944 kb
Host smart-47c55efe-4f38-41fa-9755-1aa42e0dbcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29696
03023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2969603023
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.612851095
Short name T3103
Test name
Test status
Simulation time 183561975 ps
CPU time 0.93 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 207540 kb
Host smart-266a99a7-9d4d-4dbd-be42-a353f2f6e6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61285
1095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.612851095
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1859318489
Short name T37
Test name
Test status
Simulation time 192829839 ps
CPU time 0.97 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:39 PM PDT 24
Peak memory 207524 kb
Host smart-4dadefc9-1494-40d2-bd8c-e368f2db6457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
18489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1859318489
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2535727204
Short name T2703
Test name
Test status
Simulation time 7558897935 ps
CPU time 51.66 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:15:33 PM PDT 24
Peak memory 224288 kb
Host smart-8fb61ece-d61a-44a8-9a5c-3ef78134fc6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535727204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2535727204
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1329575163
Short name T1120
Test name
Test status
Simulation time 1971581971 ps
CPU time 18.23 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:56 PM PDT 24
Peak memory 224204 kb
Host smart-4f20c3d4-cf35-4456-8a11-4a33eadde2e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1329575163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1329575163
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2885419123
Short name T1177
Test name
Test status
Simulation time 10562606303 ps
CPU time 58.21 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:15:38 PM PDT 24
Peak memory 216088 kb
Host smart-6bfde445-4c77-4bbc-b035-f09c0be993b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885419123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2885419123
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.429467418
Short name T2359
Test name
Test status
Simulation time 236406049 ps
CPU time 0.99 seconds
Started Aug 08 06:14:45 PM PDT 24
Finished Aug 08 06:14:46 PM PDT 24
Peak memory 207532 kb
Host smart-e4d1f9b9-658e-48b4-84a6-921c25e6eb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
7418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.429467418
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1652395180
Short name T1736
Test name
Test status
Simulation time 196688153 ps
CPU time 0.97 seconds
Started Aug 08 06:14:40 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207508 kb
Host smart-7064be42-c6af-4492-9183-91f5c51b6a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
95180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1652395180
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.2938703324
Short name T1987
Test name
Test status
Simulation time 20164917196 ps
CPU time 23.85 seconds
Started Aug 08 06:14:41 PM PDT 24
Finished Aug 08 06:15:05 PM PDT 24
Peak memory 207624 kb
Host smart-f79bcf1c-86ff-485a-bfec-691a6aad7663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29387
03324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.2938703324
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2387801532
Short name T2391
Test name
Test status
Simulation time 217359161 ps
CPU time 0.93 seconds
Started Aug 08 06:14:45 PM PDT 24
Finished Aug 08 06:14:46 PM PDT 24
Peak memory 207532 kb
Host smart-e03196f1-11cf-4f95-9746-66a435b1bb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
01532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2387801532
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.991011598
Short name T2636
Test name
Test status
Simulation time 408004828 ps
CPU time 1.4 seconds
Started Aug 08 06:14:44 PM PDT 24
Finished Aug 08 06:14:46 PM PDT 24
Peak memory 207540 kb
Host smart-1d659618-0efe-4540-9804-adb2e4f3e71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99101
1598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.991011598
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2646114209
Short name T1959
Test name
Test status
Simulation time 155542244 ps
CPU time 0.87 seconds
Started Aug 08 06:14:44 PM PDT 24
Finished Aug 08 06:14:45 PM PDT 24
Peak memory 207432 kb
Host smart-4ea11676-65a7-4469-a810-1b59ff3e4c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
14209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2646114209
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1404711828
Short name T242
Test name
Test status
Simulation time 150667365 ps
CPU time 0.82 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:40 PM PDT 24
Peak memory 206364 kb
Host smart-fc86603c-9ede-4b3f-a677-ccff3afa5423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
11828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1404711828
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1976438500
Short name T796
Test name
Test status
Simulation time 219742746 ps
CPU time 1.03 seconds
Started Aug 08 06:14:45 PM PDT 24
Finished Aug 08 06:14:46 PM PDT 24
Peak memory 207532 kb
Host smart-e359d9e5-6798-4fd0-ba31-ee2cb3363449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
38500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1976438500
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3902108706
Short name T2895
Test name
Test status
Simulation time 2656202015 ps
CPU time 20.82 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:15:07 PM PDT 24
Peak memory 216084 kb
Host smart-6d488603-45dd-45e5-86df-97f8e34d87a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3902108706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3902108706
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3029764524
Short name T838
Test name
Test status
Simulation time 155161367 ps
CPU time 0.85 seconds
Started Aug 08 06:14:42 PM PDT 24
Finished Aug 08 06:14:43 PM PDT 24
Peak memory 207536 kb
Host smart-822156cd-77c5-4596-8adc-0c1a32b93065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30297
64524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3029764524
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.273486857
Short name T1132
Test name
Test status
Simulation time 186942492 ps
CPU time 0.89 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:53 PM PDT 24
Peak memory 207568 kb
Host smart-03516c97-5d79-4a5e-99de-73a186fa8d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
6857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.273486857
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2334972071
Short name T3134
Test name
Test status
Simulation time 1319051501 ps
CPU time 3.78 seconds
Started Aug 08 06:14:38 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207688 kb
Host smart-b8b8e7cb-281f-4564-88b3-81be943ac47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23349
72071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2334972071
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1094569504
Short name T3586
Test name
Test status
Simulation time 2643948163 ps
CPU time 78.23 seconds
Started Aug 08 06:14:42 PM PDT 24
Finished Aug 08 06:16:00 PM PDT 24
Peak memory 217436 kb
Host smart-81a95060-2c11-4bcc-b502-6c56c2a7a59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
69504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1094569504
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.3247600555
Short name T729
Test name
Test status
Simulation time 696910985 ps
CPU time 14.75 seconds
Started Aug 08 06:14:54 PM PDT 24
Finished Aug 08 06:15:09 PM PDT 24
Peak memory 207748 kb
Host smart-61422048-8bac-4fb9-a63d-e1685dbe551a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247600555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.3247600555
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.2430885053
Short name T1418
Test name
Test status
Simulation time 650100138 ps
CPU time 1.77 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207596 kb
Host smart-87322c7b-5bcf-42a0-9c81-75e60fb23007
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430885053 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.2430885053
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.345215480
Short name T477
Test name
Test status
Simulation time 426897075 ps
CPU time 1.43 seconds
Started Aug 08 06:21:00 PM PDT 24
Finished Aug 08 06:21:02 PM PDT 24
Peak memory 207536 kb
Host smart-427ebcf7-3662-484a-81de-671abcfc71cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=345215480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.345215480
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.2824202661
Short name T645
Test name
Test status
Simulation time 587745800 ps
CPU time 1.6 seconds
Started Aug 08 06:21:06 PM PDT 24
Finished Aug 08 06:21:08 PM PDT 24
Peak memory 207600 kb
Host smart-5fae215f-8e27-400f-9897-076d1fc34b1f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824202661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.2824202661
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.1769309212
Short name T464
Test name
Test status
Simulation time 752079575 ps
CPU time 1.75 seconds
Started Aug 08 06:20:55 PM PDT 24
Finished Aug 08 06:20:57 PM PDT 24
Peak memory 207452 kb
Host smart-dd242c60-594f-4fe3-a293-3167a04210a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1769309212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.1769309212
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.4204040338
Short name T1864
Test name
Test status
Simulation time 578928840 ps
CPU time 1.65 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207516 kb
Host smart-da2731f4-accb-4f45-88e1-b79c120a9238
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204040338 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.4204040338
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.2723057381
Short name T384
Test name
Test status
Simulation time 661472363 ps
CPU time 1.55 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207480 kb
Host smart-57bccb22-4e6a-467b-b3a2-4bf58576e5c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2723057381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.2723057381
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.3596321603
Short name T1025
Test name
Test status
Simulation time 481614193 ps
CPU time 1.44 seconds
Started Aug 08 06:21:38 PM PDT 24
Finished Aug 08 06:21:39 PM PDT 24
Peak memory 207496 kb
Host smart-d765a0e2-cff9-41a7-b6d4-5b1df78fd9b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596321603 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.3596321603
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.2786974899
Short name T447
Test name
Test status
Simulation time 474686600 ps
CPU time 1.4 seconds
Started Aug 08 06:21:19 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207528 kb
Host smart-14e0bb9b-2672-4729-9e89-32a21d9ec389
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2786974899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.2786974899
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.3620580065
Short name T3557
Test name
Test status
Simulation time 487857747 ps
CPU time 1.53 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207608 kb
Host smart-21d79a3d-1850-4d9e-abda-56fad68e7f40
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620580065 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.3620580065
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.1165834509
Short name T2996
Test name
Test status
Simulation time 271950794 ps
CPU time 1.11 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207480 kb
Host smart-4c9d92df-97eb-4520-b32d-0611e98f6ee7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1165834509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.1165834509
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.2125162520
Short name T1334
Test name
Test status
Simulation time 477218225 ps
CPU time 1.64 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207820 kb
Host smart-458c33dc-7dc8-4594-922c-ebc2598c04d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125162520 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.2125162520
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.3556252432
Short name T368
Test name
Test status
Simulation time 373965537 ps
CPU time 1.29 seconds
Started Aug 08 06:21:22 PM PDT 24
Finished Aug 08 06:21:23 PM PDT 24
Peak memory 207536 kb
Host smart-56366c97-ce60-4a45-873d-d366716592bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3556252432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.3556252432
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.1795257153
Short name T1382
Test name
Test status
Simulation time 568395848 ps
CPU time 1.63 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207548 kb
Host smart-5439a836-e3ee-406d-89b3-96dda1c7fad7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795257153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.1795257153
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.1944800109
Short name T412
Test name
Test status
Simulation time 743165175 ps
CPU time 1.66 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207604 kb
Host smart-5427ae3a-54a3-4fa2-8e75-22f93dbc5049
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1944800109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.1944800109
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.1247078536
Short name T2654
Test name
Test status
Simulation time 655441676 ps
CPU time 1.82 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207512 kb
Host smart-c28cd468-1be0-4cdc-aa0c-54d54e934e55
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247078536 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.1247078536
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.2059398987
Short name T423
Test name
Test status
Simulation time 422828339 ps
CPU time 1.4 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207500 kb
Host smart-9c646b4c-e165-496d-8a0f-b4ddacbe4c56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2059398987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.2059398987
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.3022138163
Short name T2291
Test name
Test status
Simulation time 599308949 ps
CPU time 1.63 seconds
Started Aug 08 06:21:07 PM PDT 24
Finished Aug 08 06:21:19 PM PDT 24
Peak memory 207568 kb
Host smart-6a6cece8-7959-46a2-8af4-b9e776a936ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022138163 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.3022138163
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.2892530078
Short name T414
Test name
Test status
Simulation time 814383693 ps
CPU time 1.82 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207520 kb
Host smart-6681d353-6c91-44e5-a074-30ccbbbb31d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2892530078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.2892530078
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.704022353
Short name T2173
Test name
Test status
Simulation time 607300373 ps
CPU time 1.65 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:28 PM PDT 24
Peak memory 207540 kb
Host smart-3d7e91a1-dfaa-45c3-aadf-d4a9d0d99abe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704022353 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.704022353
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.4256188692
Short name T385
Test name
Test status
Simulation time 539978341 ps
CPU time 1.49 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207544 kb
Host smart-09d3e358-d27e-4eaf-a776-0f3c5a0c30d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4256188692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.4256188692
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.337874430
Short name T1834
Test name
Test status
Simulation time 485363629 ps
CPU time 1.51 seconds
Started Aug 08 06:21:19 PM PDT 24
Finished Aug 08 06:21:21 PM PDT 24
Peak memory 207568 kb
Host smart-9d47b531-af1c-4236-bafa-084966666aaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337874430 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.337874430
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2944793036
Short name T3268
Test name
Test status
Simulation time 35845358 ps
CPU time 0.65 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 207612 kb
Host smart-d57d059d-0fbd-4ff5-8095-2beb52d9bd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2944793036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2944793036
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1086055449
Short name T851
Test name
Test status
Simulation time 5669521379 ps
CPU time 7.71 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 216008 kb
Host smart-d93a5fd9-5587-48df-b576-467c2660163a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086055449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.1086055449
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3207066926
Short name T3484
Test name
Test status
Simulation time 18660387647 ps
CPU time 20.42 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:19 PM PDT 24
Peak memory 207860 kb
Host smart-0de800dd-2c72-45a1-a996-124a60e02bab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207066926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3207066926
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2482617962
Short name T15
Test name
Test status
Simulation time 24867010636 ps
CPU time 31.76 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:15:18 PM PDT 24
Peak memory 216024 kb
Host smart-e92044b4-054c-45f8-9502-2c8349aecfb5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482617962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.2482617962
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.494484660
Short name T3211
Test name
Test status
Simulation time 153881612 ps
CPU time 0.84 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:53 PM PDT 24
Peak memory 207568 kb
Host smart-56ef657b-f42d-4b00-9972-a50175a91696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49448
4660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.494484660
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2648881176
Short name T2721
Test name
Test status
Simulation time 149587901 ps
CPU time 0.85 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:53 PM PDT 24
Peak memory 207564 kb
Host smart-54650e84-6f47-4874-a561-a863c9bf5dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26488
81176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2648881176
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3406500169
Short name T1389
Test name
Test status
Simulation time 484767592 ps
CPU time 1.49 seconds
Started Aug 08 06:14:39 PM PDT 24
Finished Aug 08 06:14:41 PM PDT 24
Peak memory 207592 kb
Host smart-0bb6e685-c011-4c2e-b880-52fa3399f338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
00169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3406500169
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2897161459
Short name T3338
Test name
Test status
Simulation time 573167882 ps
CPU time 1.84 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 207556 kb
Host smart-818fcb4a-0e86-48a8-aef4-d952db7cad37
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2897161459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2897161459
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2556761590
Short name T1526
Test name
Test status
Simulation time 47488078259 ps
CPU time 71.83 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:16:04 PM PDT 24
Peak memory 207836 kb
Host smart-a41fdbe0-e111-4335-b604-ac51e9292e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25567
61590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2556761590
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.1828624228
Short name T166
Test name
Test status
Simulation time 875185126 ps
CPU time 5.45 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 207772 kb
Host smart-ff901418-e52a-40ca-aa47-05a432c12a60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828624228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1828624228
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2982919872
Short name T2010
Test name
Test status
Simulation time 917769689 ps
CPU time 2.14 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207568 kb
Host smart-0b891889-fc5b-4835-b230-3452d596114d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829
19872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2982919872
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.4204619873
Short name T2153
Test name
Test status
Simulation time 164584598 ps
CPU time 0.89 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207544 kb
Host smart-b6415939-cfd9-497a-bcfd-5e62f2fa7c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
19873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.4204619873
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3277590914
Short name T671
Test name
Test status
Simulation time 74634343 ps
CPU time 0.7 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 207556 kb
Host smart-4f8613b8-380b-455c-8b38-8a8c21f2eed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32775
90914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3277590914
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.866792747
Short name T2756
Test name
Test status
Simulation time 1046731877 ps
CPU time 2.73 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 207792 kb
Host smart-c7eb686e-22ce-4902-8e5b-88cc7fccbe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86679
2747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.866792747
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.2789983414
Short name T3398
Test name
Test status
Simulation time 329626485 ps
CPU time 1.08 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207476 kb
Host smart-522fdedc-6270-4ae2-92ff-9a701ab9c985
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2789983414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.2789983414
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1635461601
Short name T3280
Test name
Test status
Simulation time 413728601 ps
CPU time 2.66 seconds
Started Aug 08 06:14:57 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207664 kb
Host smart-2980a0f9-3d69-4b9d-8dc1-d6b3fad89084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354
61601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1635461601
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.681332166
Short name T2
Test name
Test status
Simulation time 184920939 ps
CPU time 1.04 seconds
Started Aug 08 06:14:50 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 215964 kb
Host smart-00015d5c-32f0-4ce3-8f11-fac8d3361421
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=681332166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.681332166
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3115418383
Short name T527
Test name
Test status
Simulation time 203988447 ps
CPU time 0.88 seconds
Started Aug 08 06:14:46 PM PDT 24
Finished Aug 08 06:14:47 PM PDT 24
Peak memory 207532 kb
Host smart-f16980e5-008d-40fb-a2a1-192e8963bdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31154
18383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3115418383
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.619902737
Short name T2924
Test name
Test status
Simulation time 198977391 ps
CPU time 0.94 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:14:49 PM PDT 24
Peak memory 207556 kb
Host smart-c144d0f6-f768-4e86-b8c9-a6ab8dd51632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61990
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.619902737
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2754730420
Short name T958
Test name
Test status
Simulation time 4268309832 ps
CPU time 33.58 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:15:22 PM PDT 24
Peak memory 218656 kb
Host smart-f030fd9c-aa78-4e17-b105-846b19ac5e29
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2754730420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2754730420
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.4068848390
Short name T2746
Test name
Test status
Simulation time 10601201760 ps
CPU time 129.63 seconds
Started Aug 08 06:14:50 PM PDT 24
Finished Aug 08 06:17:00 PM PDT 24
Peak memory 207784 kb
Host smart-fdc030dd-1bf9-457b-ac3c-812e8db4024e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4068848390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.4068848390
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.4291258574
Short name T2299
Test name
Test status
Simulation time 215046682 ps
CPU time 0.96 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207584 kb
Host smart-40a381e4-78d0-4ea6-8391-666160e0ffdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42912
58574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.4291258574
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3938705255
Short name T953
Test name
Test status
Simulation time 23669121446 ps
CPU time 28.23 seconds
Started Aug 08 06:14:57 PM PDT 24
Finished Aug 08 06:15:25 PM PDT 24
Peak memory 207828 kb
Host smart-b097db90-0630-425b-90c6-ba0bc2fa6d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
05255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3938705255
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2043817293
Short name T2671
Test name
Test status
Simulation time 9640262175 ps
CPU time 11.73 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207880 kb
Host smart-e21681c1-dad4-451a-8367-c72fd9e9005d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
17293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2043817293
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3182845848
Short name T1246
Test name
Test status
Simulation time 3993891814 ps
CPU time 109.2 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:16:49 PM PDT 24
Peak memory 224256 kb
Host smart-b9d3574e-5715-4521-aa1d-427cf4a69425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31828
45848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3182845848
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1776366539
Short name T878
Test name
Test status
Simulation time 2401958821 ps
CPU time 69.17 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:15:57 PM PDT 24
Peak memory 217764 kb
Host smart-5ac3ff99-fcd8-43e4-b513-8b579acea79f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1776366539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1776366539
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1055830025
Short name T2208
Test name
Test status
Simulation time 279802483 ps
CPU time 0.97 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 207564 kb
Host smart-cf1aaedf-657e-4723-a37e-261a6e3d3dce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1055830025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1055830025
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.897856480
Short name T1567
Test name
Test status
Simulation time 222621182 ps
CPU time 0.96 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207496 kb
Host smart-620dca16-1dc3-4644-b94b-c24b2ab0da0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89785
6480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.897856480
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.1219210791
Short name T1912
Test name
Test status
Simulation time 2611831806 ps
CPU time 20.5 seconds
Started Aug 08 06:14:50 PM PDT 24
Finished Aug 08 06:15:10 PM PDT 24
Peak memory 207984 kb
Host smart-72532c17-316e-4dc8-ac89-f24b1638c5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12192
10791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.1219210791
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1771899111
Short name T1058
Test name
Test status
Simulation time 1651664038 ps
CPU time 12.04 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 224104 kb
Host smart-2d4309e8-974b-47ad-abb4-0ea5a91cdf57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1771899111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1771899111
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1660176158
Short name T2710
Test name
Test status
Simulation time 2591806184 ps
CPU time 26.82 seconds
Started Aug 08 06:14:48 PM PDT 24
Finished Aug 08 06:15:15 PM PDT 24
Peak memory 217572 kb
Host smart-8b36dbe9-9269-4614-b128-5da4e99c0491
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1660176158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1660176158
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.662341808
Short name T1888
Test name
Test status
Simulation time 161590480 ps
CPU time 0.86 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:14:52 PM PDT 24
Peak memory 206372 kb
Host smart-9f49020b-89c9-4890-94ae-e03d32df0c58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=662341808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.662341808
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.4063647942
Short name T1490
Test name
Test status
Simulation time 159970137 ps
CPU time 0.86 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 207516 kb
Host smart-300c920b-290a-43f2-9072-55675a741cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636
47942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.4063647942
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.525178210
Short name T133
Test name
Test status
Simulation time 203394253 ps
CPU time 0.97 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:14:48 PM PDT 24
Peak memory 207516 kb
Host smart-bdd734b2-db5f-4bdb-8d92-03c3b756bfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52517
8210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.525178210
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2034261064
Short name T1481
Test name
Test status
Simulation time 191599500 ps
CPU time 0.88 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207528 kb
Host smart-d7258a61-941d-4a78-958f-69186470a7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
61064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2034261064
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3515141864
Short name T3550
Test name
Test status
Simulation time 143734043 ps
CPU time 0.82 seconds
Started Aug 08 06:14:53 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 207536 kb
Host smart-fba2894a-8215-4f03-afaf-64e0114e4ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
41864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3515141864
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.663935990
Short name T2199
Test name
Test status
Simulation time 154659102 ps
CPU time 0.83 seconds
Started Aug 08 06:14:56 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207512 kb
Host smart-127317d0-7a8e-4ee1-a924-cc132b1924d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66393
5990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.663935990
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.93739587
Short name T2930
Test name
Test status
Simulation time 165612062 ps
CPU time 0.82 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207580 kb
Host smart-c26f7c99-ceb6-48df-876d-7e42c81f22bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93739
587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.93739587
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.290383972
Short name T650
Test name
Test status
Simulation time 208675090 ps
CPU time 0.97 seconds
Started Aug 08 06:14:50 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 207548 kb
Host smart-5ac9d0d8-a99f-4ac8-9487-7448e8cbf479
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=290383972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.290383972
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3230206680
Short name T1067
Test name
Test status
Simulation time 145895212 ps
CPU time 0.86 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207552 kb
Host smart-70450cde-9c4d-4f58-b756-17d803f2adcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
06680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3230206680
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4092684351
Short name T2995
Test name
Test status
Simulation time 40028610 ps
CPU time 0.67 seconds
Started Aug 08 06:14:53 PM PDT 24
Finished Aug 08 06:14:53 PM PDT 24
Peak memory 207500 kb
Host smart-d54e9ba7-c8ca-41f8-9cd8-ee4d0129921c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
84351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4092684351
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3013716156
Short name T1026
Test name
Test status
Simulation time 16838642867 ps
CPU time 38.79 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:15:26 PM PDT 24
Peak memory 216044 kb
Host smart-58424efb-209c-4d05-8217-8e2530402015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137
16156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3013716156
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3765564936
Short name T355
Test name
Test status
Simulation time 182634420 ps
CPU time 0.94 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207588 kb
Host smart-1c7caccf-275b-4184-9c07-e051a7397fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37655
64936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3765564936
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1772281750
Short name T691
Test name
Test status
Simulation time 193522182 ps
CPU time 0.88 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207440 kb
Host smart-cb3b7114-e39e-43c4-ab39-66ccd1147aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17722
81750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1772281750
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1212103814
Short name T171
Test name
Test status
Simulation time 7035053640 ps
CPU time 105.36 seconds
Started Aug 08 06:14:47 PM PDT 24
Finished Aug 08 06:16:33 PM PDT 24
Peak memory 219192 kb
Host smart-63e02da3-56bb-4590-877c-fc333991efee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212103814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1212103814
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2144010191
Short name T1948
Test name
Test status
Simulation time 4782987808 ps
CPU time 41.55 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:15:30 PM PDT 24
Peak memory 216084 kb
Host smart-3617349d-c58b-429e-9b5f-d5d92f3b8b1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2144010191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2144010191
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.224775424
Short name T1126
Test name
Test status
Simulation time 5413452295 ps
CPU time 54.77 seconds
Started Aug 08 06:14:53 PM PDT 24
Finished Aug 08 06:15:48 PM PDT 24
Peak memory 219312 kb
Host smart-096cd9df-506d-406c-a27b-eb2a00800a6e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=224775424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.224775424
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1506172275
Short name T3378
Test name
Test status
Simulation time 204025663 ps
CPU time 0.91 seconds
Started Aug 08 06:14:56 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207492 kb
Host smart-0c6f3a0d-6f08-43a7-b1ea-2c93c0e00774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15061
72275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1506172275
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1199710519
Short name T814
Test name
Test status
Simulation time 176757949 ps
CPU time 0.83 seconds
Started Aug 08 06:14:52 PM PDT 24
Finished Aug 08 06:14:53 PM PDT 24
Peak memory 207532 kb
Host smart-6699212e-4c8b-477f-a379-04d08a363d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997
10519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1199710519
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.1702153085
Short name T3630
Test name
Test status
Simulation time 20247499274 ps
CPU time 27.16 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:15:16 PM PDT 24
Peak memory 207696 kb
Host smart-b469401b-9177-4be6-be75-1769b3f59ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
53085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.1702153085
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1055251506
Short name T767
Test name
Test status
Simulation time 142110369 ps
CPU time 0.85 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 207476 kb
Host smart-08ec6224-b0de-4ded-8926-77bae577926a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10552
51506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1055251506
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.3318413216
Short name T324
Test name
Test status
Simulation time 324155273 ps
CPU time 1.11 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:14:50 PM PDT 24
Peak memory 207464 kb
Host smart-18126e7b-b597-49d1-b9a7-bd220cb44bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33184
13216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.3318413216
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.319354524
Short name T1762
Test name
Test status
Simulation time 144239369 ps
CPU time 0.81 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 207480 kb
Host smart-de3bfaa6-d9c3-42b9-ab16-cfe1ff399971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
4524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.319354524
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1685083853
Short name T2984
Test name
Test status
Simulation time 154190829 ps
CPU time 0.83 seconds
Started Aug 08 06:14:56 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207584 kb
Host smart-c4cd0caa-a640-4a5d-8dc6-2c38b5d9c766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850
83853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1685083853
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.272154043
Short name T2665
Test name
Test status
Simulation time 251393412 ps
CPU time 1.03 seconds
Started Aug 08 06:14:56 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207576 kb
Host smart-3c5f33b0-2938-452b-9d91-131b95e1ffed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.272154043
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.975703778
Short name T2262
Test name
Test status
Simulation time 3080853519 ps
CPU time 88.02 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:16:19 PM PDT 24
Peak memory 216592 kb
Host smart-4012c443-7fae-4366-b639-43c38feccd51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=975703778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.975703778
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1592576473
Short name T1009
Test name
Test status
Simulation time 201092436 ps
CPU time 0.91 seconds
Started Aug 08 06:14:55 PM PDT 24
Finished Aug 08 06:14:56 PM PDT 24
Peak memory 207508 kb
Host smart-fb75e893-0cde-442b-a014-005106aadec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
76473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1592576473
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2876806481
Short name T2085
Test name
Test status
Simulation time 166487787 ps
CPU time 0.81 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:14:51 PM PDT 24
Peak memory 207588 kb
Host smart-d568a407-8436-4ea6-92f5-1e65ef9e7148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
06481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2876806481
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.864176270
Short name T704
Test name
Test status
Simulation time 1198623013 ps
CPU time 3.21 seconds
Started Aug 08 06:14:51 PM PDT 24
Finished Aug 08 06:14:54 PM PDT 24
Peak memory 206536 kb
Host smart-c9172af7-05d4-4e7c-adc6-27db10562972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86417
6270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.864176270
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3220119384
Short name T1718
Test name
Test status
Simulation time 1770392668 ps
CPU time 50.64 seconds
Started Aug 08 06:14:50 PM PDT 24
Finished Aug 08 06:15:40 PM PDT 24
Peak memory 216012 kb
Host smart-11fb9ed6-d650-4d06-a9af-53714782b59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
19384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3220119384
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.1625638772
Short name T973
Test name
Test status
Simulation time 1312352892 ps
CPU time 31.45 seconds
Started Aug 08 06:14:49 PM PDT 24
Finished Aug 08 06:15:20 PM PDT 24
Peak memory 207744 kb
Host smart-93d628fa-650f-4bcb-85d8-3f27ee644894
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625638772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.1625638772
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.2495766377
Short name T2491
Test name
Test status
Simulation time 554249718 ps
CPU time 1.5 seconds
Started Aug 08 06:14:55 PM PDT 24
Finished Aug 08 06:14:57 PM PDT 24
Peak memory 207548 kb
Host smart-3737e8c9-830e-411c-b640-8a1a75173a88
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495766377 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.2495766377
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.1969805745
Short name T421
Test name
Test status
Simulation time 364992919 ps
CPU time 1.29 seconds
Started Aug 08 06:21:30 PM PDT 24
Finished Aug 08 06:21:31 PM PDT 24
Peak memory 207568 kb
Host smart-ac937814-b9eb-4f65-b29b-a3b5457ee19b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1969805745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.1969805745
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.2010823636
Short name T3319
Test name
Test status
Simulation time 582498692 ps
CPU time 1.62 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:10 PM PDT 24
Peak memory 207644 kb
Host smart-9b6304f7-66ff-424b-bb04-ff29ee27ea38
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010823636 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.2010823636
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.2572058407
Short name T361
Test name
Test status
Simulation time 722273922 ps
CPU time 1.77 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:30 PM PDT 24
Peak memory 207508 kb
Host smart-472ed73e-94e4-48e6-ad61-99622ab46121
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2572058407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.2572058407
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.3102326561
Short name T3143
Test name
Test status
Simulation time 483151032 ps
CPU time 1.59 seconds
Started Aug 08 06:21:18 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207536 kb
Host smart-d84a91e2-3bbe-481e-9c82-920a2a128906
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102326561 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.3102326561
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.4200178752
Short name T432
Test name
Test status
Simulation time 304859215 ps
CPU time 1.15 seconds
Started Aug 08 06:21:20 PM PDT 24
Finished Aug 08 06:21:21 PM PDT 24
Peak memory 207544 kb
Host smart-0eb80814-a710-417b-a26d-102f477f761c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4200178752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.4200178752
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.238353716
Short name T1793
Test name
Test status
Simulation time 545318808 ps
CPU time 1.52 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:26 PM PDT 24
Peak memory 207524 kb
Host smart-1dfa0da2-c58c-4371-b3e6-35a042c7b382
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238353716 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.238353716
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.1978325458
Short name T484
Test name
Test status
Simulation time 296972471 ps
CPU time 1.17 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:12 PM PDT 24
Peak memory 207588 kb
Host smart-80a8e113-7698-41ee-bb9f-28e9faafbba5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1978325458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.1978325458
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.1825873392
Short name T214
Test name
Test status
Simulation time 677578394 ps
CPU time 1.97 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207588 kb
Host smart-13340bfe-e3e2-4b0d-9a9d-3b5267d690f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825873392 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1825873392
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.62695081
Short name T3339
Test name
Test status
Simulation time 317522896 ps
CPU time 1.12 seconds
Started Aug 08 06:21:26 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207500 kb
Host smart-7fc3a931-66a2-41f8-bc26-93fa38c724a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=62695081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.62695081
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.3362513222
Short name T1796
Test name
Test status
Simulation time 477310620 ps
CPU time 1.51 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207540 kb
Host smart-30b14115-60d6-44d2-9069-0a2e0f113d0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362513222 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.3362513222
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.2469340966
Short name T369
Test name
Test status
Simulation time 681832069 ps
CPU time 1.54 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207568 kb
Host smart-f07dedd5-a910-46ad-9092-799aa28196f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2469340966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.2469340966
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.645706334
Short name T1172
Test name
Test status
Simulation time 203784044 ps
CPU time 0.92 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:16 PM PDT 24
Peak memory 207516 kb
Host smart-08ac827c-ce17-49dc-82b6-26c8529dc3cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=645706334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.645706334
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.2577682811
Short name T3098
Test name
Test status
Simulation time 459473159 ps
CPU time 1.34 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207636 kb
Host smart-9b9694bc-1a4a-4880-925d-29f2c62db447
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577682811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.2577682811
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.403339451
Short name T3389
Test name
Test status
Simulation time 976081569 ps
CPU time 2.14 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207536 kb
Host smart-c239f954-0972-4a47-af55-2a7d92525107
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=403339451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.403339451
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.2856375440
Short name T3307
Test name
Test status
Simulation time 586090088 ps
CPU time 1.51 seconds
Started Aug 08 06:21:24 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207584 kb
Host smart-9abdfdf1-31d8-4fb7-946e-979a8b66dad2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856375440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.2856375440
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.3638334628
Short name T581
Test name
Test status
Simulation time 359847099 ps
CPU time 1.14 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207748 kb
Host smart-c7657664-15b4-4b1f-b5d5-841a6ac4a7d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3638334628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.3638334628
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.845527517
Short name T3299
Test name
Test status
Simulation time 592252593 ps
CPU time 1.63 seconds
Started Aug 08 06:21:28 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207608 kb
Host smart-4761fafb-6d32-4316-a092-f9df5c482811
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845527517 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.845527517
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.1211788636
Short name T1299
Test name
Test status
Simulation time 646878944 ps
CPU time 1.71 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207584 kb
Host smart-da368935-1abb-4d02-8127-01aeeefb79af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211788636 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.1211788636
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3038860124
Short name T1786
Test name
Test status
Simulation time 87625870 ps
CPU time 0.7 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207560 kb
Host smart-712114b3-f906-4d87-abe9-f01bc6632eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3038860124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3038860124
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1312763400
Short name T2250
Test name
Test status
Simulation time 11434415401 ps
CPU time 13.97 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:14 PM PDT 24
Peak memory 207868 kb
Host smart-08100dbb-ace8-46b6-90a3-0350c0d0f483
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312763400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1312763400
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3114298307
Short name T3096
Test name
Test status
Simulation time 19986372996 ps
CPU time 24.84 seconds
Started Aug 08 06:15:04 PM PDT 24
Finished Aug 08 06:15:29 PM PDT 24
Peak memory 207860 kb
Host smart-64a159c9-fc40-4f35-ad00-6c36e1e06e4e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114298307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3114298307
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3746717187
Short name T756
Test name
Test status
Simulation time 30594648708 ps
CPU time 36.62 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:15:35 PM PDT 24
Peak memory 207864 kb
Host smart-7dec2ffd-81a6-4452-8a66-8473b7fae865
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746717187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.3746717187
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2252943726
Short name T1500
Test name
Test status
Simulation time 162851906 ps
CPU time 0.87 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207492 kb
Host smart-990c59a1-ed55-4d78-818c-0ffa14a93720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
43726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2252943726
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.994651272
Short name T1450
Test name
Test status
Simulation time 159429765 ps
CPU time 0.85 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 207520 kb
Host smart-886f7c09-c0f4-4520-a918-33fe1ab8e6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99465
1272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.994651272
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.275891705
Short name T2544
Test name
Test status
Simulation time 541917226 ps
CPU time 1.79 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207552 kb
Host smart-8ab63b8a-c7a5-41f3-ac1e-09fba11290ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27589
1705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.275891705
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.66496662
Short name T1263
Test name
Test status
Simulation time 1396061796 ps
CPU time 3.4 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207840 kb
Host smart-f6b1694c-03c4-4d18-a387-ae5ff52f5d82
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=66496662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.66496662
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2042430680
Short name T2583
Test name
Test status
Simulation time 51921513856 ps
CPU time 77.01 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:16:16 PM PDT 24
Peak memory 207816 kb
Host smart-740c9ccf-00cd-4a66-a983-f4b1a347da12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
30680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2042430680
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.2187840943
Short name T3415
Test name
Test status
Simulation time 2436066481 ps
CPU time 21.17 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:22 PM PDT 24
Peak memory 207836 kb
Host smart-e0b43695-0268-45d7-b70f-c3abba7823d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187840943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.2187840943
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1203368361
Short name T3533
Test name
Test status
Simulation time 901708743 ps
CPU time 1.79 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207532 kb
Host smart-ed07bdcf-49f7-4918-841e-784d118d245b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12033
68361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1203368361
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.414169608
Short name T1348
Test name
Test status
Simulation time 207191219 ps
CPU time 0.85 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207508 kb
Host smart-0891a28f-83f0-40c4-a9ab-83fd4aecf969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
9608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.414169608
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2747092881
Short name T2327
Test name
Test status
Simulation time 42216948 ps
CPU time 0.68 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207468 kb
Host smart-982bb806-249c-4969-9a47-82280ab886e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
92881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2747092881
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.136807962
Short name T3578
Test name
Test status
Simulation time 869962717 ps
CPU time 2.41 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:04 PM PDT 24
Peak memory 207780 kb
Host smart-bbe3857a-9994-40bc-9118-5486b9d1d2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13680
7962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.136807962
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.2108893010
Short name T476
Test name
Test status
Simulation time 726316306 ps
CPU time 1.71 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207524 kb
Host smart-67675b74-0d14-4e87-864b-69c25df27d87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108893010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.2108893010
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.660029397
Short name T3200
Test name
Test status
Simulation time 385933577 ps
CPU time 2.66 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207704 kb
Host smart-9869914c-28f4-405c-83e9-de40c3368671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66002
9397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.660029397
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.157740581
Short name T2859
Test name
Test status
Simulation time 224764659 ps
CPU time 1.16 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 216024 kb
Host smart-06ba0004-652e-417a-9d05-f9a3828f8af3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=157740581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.157740581
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2019380182
Short name T3438
Test name
Test status
Simulation time 155146333 ps
CPU time 0.83 seconds
Started Aug 08 06:15:04 PM PDT 24
Finished Aug 08 06:15:05 PM PDT 24
Peak memory 207556 kb
Host smart-23ca68bd-356c-404f-b84b-c4e3365759cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
80182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2019380182
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3676025254
Short name T3408
Test name
Test status
Simulation time 204625454 ps
CPU time 0.92 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207600 kb
Host smart-9fa2b134-0a9f-40df-86c2-da2f69b9f1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36760
25254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3676025254
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3022423828
Short name T2412
Test name
Test status
Simulation time 4425660443 ps
CPU time 42.91 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:43 PM PDT 24
Peak memory 224260 kb
Host smart-7760b1e3-40ad-45b5-aaf8-b67a6c26cb07
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3022423828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3022423828
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.654523436
Short name T2512
Test name
Test status
Simulation time 11616024277 ps
CPU time 149.01 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:17:32 PM PDT 24
Peak memory 207860 kb
Host smart-37098bf3-cb6f-405d-b616-1fcb3df2d4c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=654523436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.654523436
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2199317948
Short name T567
Test name
Test status
Simulation time 297127178 ps
CPU time 1.01 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207464 kb
Host smart-aa4a2c4d-6abd-4b65-957b-890810de912b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21993
17948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2199317948
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.491187303
Short name T2593
Test name
Test status
Simulation time 26874982077 ps
CPU time 36.78 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:39 PM PDT 24
Peak memory 216108 kb
Host smart-b23a39e0-5ca4-4cfb-9bd3-3531dbb4b4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49118
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.491187303
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2460071902
Short name T101
Test name
Test status
Simulation time 11010524215 ps
CPU time 12.73 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:15:16 PM PDT 24
Peak memory 207832 kb
Host smart-ac27b2db-ec7b-41c4-86a6-ceef806154bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
71902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2460071902
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.4013188447
Short name T508
Test name
Test status
Simulation time 5008520478 ps
CPU time 143.21 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:17:21 PM PDT 24
Peak memory 224184 kb
Host smart-58e67c5b-c76e-4534-8822-9c9710519812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40131
88447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.4013188447
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2202152565
Short name T2845
Test name
Test status
Simulation time 1591160573 ps
CPU time 43.24 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:15:41 PM PDT 24
Peak memory 215980 kb
Host smart-6b41f1b5-93e1-4fd5-aab2-8a7c63139e34
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2202152565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2202152565
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3851277790
Short name T1998
Test name
Test status
Simulation time 247163230 ps
CPU time 1.02 seconds
Started Aug 08 06:14:58 PM PDT 24
Finished Aug 08 06:14:59 PM PDT 24
Peak memory 207788 kb
Host smart-5459ab56-7f14-4d87-882a-fa683e4dd398
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3851277790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3851277790
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2603430242
Short name T2141
Test name
Test status
Simulation time 207583988 ps
CPU time 0.92 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207596 kb
Host smart-06feb0e3-86cc-4f63-b917-efcd3599d45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26034
30242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2603430242
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.2363340630
Short name T2297
Test name
Test status
Simulation time 2635254625 ps
CPU time 77.01 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:16:16 PM PDT 24
Peak memory 218056 kb
Host smart-aeb1283b-4dfd-4a19-9406-8318c3dac216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23633
40630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.2363340630
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3120578388
Short name T2406
Test name
Test status
Simulation time 2238128602 ps
CPU time 66.29 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:16:06 PM PDT 24
Peak memory 217956 kb
Host smart-69d59bc9-7095-4e0c-9439-2e0d37af5aab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3120578388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3120578388
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1215637523
Short name T3532
Test name
Test status
Simulation time 2339438785 ps
CPU time 21.36 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:22 PM PDT 24
Peak memory 217040 kb
Host smart-8241bfe3-8ac7-49d7-9ef5-bf3b6638539b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1215637523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1215637523
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2563393476
Short name T3228
Test name
Test status
Simulation time 165429241 ps
CPU time 0.87 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207612 kb
Host smart-2cddbd50-ed56-4bf1-9e7a-39900843d858
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2563393476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2563393476
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.514812151
Short name T2735
Test name
Test status
Simulation time 147970768 ps
CPU time 0.83 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207532 kb
Host smart-79579fa9-af66-48d3-9a4e-befa2f8a34f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51481
2151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.514812151
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.310804222
Short name T151
Test name
Test status
Simulation time 194184065 ps
CPU time 0.94 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207504 kb
Host smart-0171fba3-02e5-47de-a88a-94ba7c145883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
4222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.310804222
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.191122638
Short name T641
Test name
Test status
Simulation time 169336068 ps
CPU time 0.91 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207648 kb
Host smart-af8fa7fe-e8db-4990-803b-6b52d652b873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
2638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.191122638
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2653367680
Short name T2385
Test name
Test status
Simulation time 227535331 ps
CPU time 1.01 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207564 kb
Host smart-f159a780-5d05-44e6-9a81-144b74695b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
67680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2653367680
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3577942447
Short name T1652
Test name
Test status
Simulation time 177270700 ps
CPU time 0.89 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207628 kb
Host smart-7cbe19e4-6158-4852-9e66-56dcffff40cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
42447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3577942447
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.427784232
Short name T1332
Test name
Test status
Simulation time 159348659 ps
CPU time 0.84 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:15:04 PM PDT 24
Peak memory 207548 kb
Host smart-f5ef874d-7a06-4b25-b3d0-78f774bd6e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
4232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.427784232
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2656189534
Short name T1564
Test name
Test status
Simulation time 281060875 ps
CPU time 1.07 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207544 kb
Host smart-b4e89bcb-650f-4c5f-bdd0-30b29852bde4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2656189534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2656189534
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2020626166
Short name T968
Test name
Test status
Simulation time 161758650 ps
CPU time 0.86 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207520 kb
Host smart-7cbd1ff7-ee56-4e45-b369-69d94db9358d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
26166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2020626166
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.433032100
Short name T3116
Test name
Test status
Simulation time 6071204371 ps
CPU time 15.98 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:17 PM PDT 24
Peak memory 216080 kb
Host smart-2bf06d47-a22f-4551-9cb1-613f3d6dae92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43303
2100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.433032100
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.957131232
Short name T354
Test name
Test status
Simulation time 160094152 ps
CPU time 0.91 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:15:04 PM PDT 24
Peak memory 207588 kb
Host smart-9c81b605-4a31-4e47-8997-d9d338073a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95713
1232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.957131232
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.4212970333
Short name T1600
Test name
Test status
Simulation time 244970426 ps
CPU time 1.05 seconds
Started Aug 08 06:15:04 PM PDT 24
Finished Aug 08 06:15:05 PM PDT 24
Peak memory 207576 kb
Host smart-a2a24be7-d3ee-41c3-aa48-004bd6290b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129
70333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.4212970333
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.984319584
Short name T1224
Test name
Test status
Simulation time 6325497609 ps
CPU time 73.14 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:16:13 PM PDT 24
Peak memory 216100 kb
Host smart-98a8f930-bb8a-4f46-9404-0a39a49898da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=984319584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.984319584
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.516757178
Short name T2711
Test name
Test status
Simulation time 8457306418 ps
CPU time 218.96 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:18:40 PM PDT 24
Peak memory 218552 kb
Host smart-73b10664-81d4-4bda-a2f3-aa95b77b4a58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=516757178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.516757178
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.758934802
Short name T2411
Test name
Test status
Simulation time 5886850296 ps
CPU time 71.3 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:16:11 PM PDT 24
Peak memory 219092 kb
Host smart-5e9bfae2-df2b-4177-a66b-a8878b5d5f85
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=758934802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.758934802
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.833361098
Short name T1958
Test name
Test status
Simulation time 234881977 ps
CPU time 0.97 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207540 kb
Host smart-feffb901-b757-4233-a8b9-1baa52d55621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83336
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.833361098
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1597951671
Short name T1679
Test name
Test status
Simulation time 186291683 ps
CPU time 0.88 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:00 PM PDT 24
Peak memory 207628 kb
Host smart-89a9fea2-8f3a-4808-9df1-7d0272569d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
51671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1597951671
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.4208101994
Short name T1871
Test name
Test status
Simulation time 20164857461 ps
CPU time 25.18 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:25 PM PDT 24
Peak memory 207644 kb
Host smart-83e4da01-12b4-44e5-9562-74fbaac373b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
01994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.4208101994
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2128051832
Short name T885
Test name
Test status
Simulation time 184645046 ps
CPU time 0.9 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207552 kb
Host smart-2753e678-0997-472c-a5a6-8c8ba2b614d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21280
51832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2128051832
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.1166824050
Short name T2232
Test name
Test status
Simulation time 362693211 ps
CPU time 1.34 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207620 kb
Host smart-359f2880-b5aa-449c-834f-59af731e6cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11668
24050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.1166824050
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.663243413
Short name T2738
Test name
Test status
Simulation time 164937046 ps
CPU time 0.84 seconds
Started Aug 08 06:15:01 PM PDT 24
Finished Aug 08 06:15:02 PM PDT 24
Peak memory 207512 kb
Host smart-4cca07e6-ad6c-4f63-bdc4-10cf0f79a300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66324
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.663243413
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2588289227
Short name T2157
Test name
Test status
Simulation time 148007892 ps
CPU time 0.79 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207576 kb
Host smart-b79b38e3-21b5-498d-a630-a1f160246e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882
89227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2588289227
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.8944581
Short name T3291
Test name
Test status
Simulation time 246151035 ps
CPU time 1.11 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207588 kb
Host smart-da5656c0-bcb6-46e8-bef4-7243e4ccdede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89445
81 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.8944581
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.84918928
Short name T2097
Test name
Test status
Simulation time 3548999610 ps
CPU time 27.95 seconds
Started Aug 08 06:15:03 PM PDT 24
Finished Aug 08 06:15:31 PM PDT 24
Peak memory 224280 kb
Host smart-0b2ce6e4-2808-468e-8488-64a0c9a8831b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=84918928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.84918928
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3811871653
Short name T661
Test name
Test status
Simulation time 192379750 ps
CPU time 0.93 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207588 kb
Host smart-ba9d4b0d-180b-4e93-9fca-2ecd9f83c2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38118
71653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3811871653
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3986702364
Short name T3258
Test name
Test status
Simulation time 150510583 ps
CPU time 0.84 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:03 PM PDT 24
Peak memory 207588 kb
Host smart-a5994279-7007-49a7-a330-cc36ab11f45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39867
02364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3986702364
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.3216796516
Short name T3569
Test name
Test status
Simulation time 1304477634 ps
CPU time 3.09 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:06 PM PDT 24
Peak memory 207744 kb
Host smart-6d33aa5b-4ac6-4e85-b6a9-f3256205cfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
96516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3216796516
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1671965464
Short name T1484
Test name
Test status
Simulation time 2400212066 ps
CPU time 22.98 seconds
Started Aug 08 06:15:02 PM PDT 24
Finished Aug 08 06:15:25 PM PDT 24
Peak memory 216076 kb
Host smart-0391aadc-8ffd-4998-982f-16e91c5d8df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
65464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1671965464
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.995840532
Short name T2626
Test name
Test status
Simulation time 1278595708 ps
CPU time 29.78 seconds
Started Aug 08 06:14:59 PM PDT 24
Finished Aug 08 06:15:29 PM PDT 24
Peak memory 207744 kb
Host smart-884d9fde-fc35-42c4-bf0f-42353bcea646
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995840532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_
handshake.995840532
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.926750790
Short name T1265
Test name
Test status
Simulation time 552621720 ps
CPU time 1.57 seconds
Started Aug 08 06:15:00 PM PDT 24
Finished Aug 08 06:15:01 PM PDT 24
Peak memory 207604 kb
Host smart-e91dd97c-5d3f-4324-9bfd-e88c6d938435
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926750790 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.926750790
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.2699152016
Short name T944
Test name
Test status
Simulation time 148333779 ps
CPU time 0.87 seconds
Started Aug 08 06:21:19 PM PDT 24
Finished Aug 08 06:21:20 PM PDT 24
Peak memory 207544 kb
Host smart-d5df68e1-b107-42b2-a635-224dfeca33c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2699152016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.2699152016
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.2143023453
Short name T1710
Test name
Test status
Simulation time 647124590 ps
CPU time 1.82 seconds
Started Aug 08 06:21:27 PM PDT 24
Finished Aug 08 06:21:29 PM PDT 24
Peak memory 207572 kb
Host smart-cf264ebb-d06d-4270-a010-f3063ce1f355
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143023453 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.2143023453
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.3001212800
Short name T3345
Test name
Test status
Simulation time 786180374 ps
CPU time 1.77 seconds
Started Aug 08 06:21:32 PM PDT 24
Finished Aug 08 06:21:34 PM PDT 24
Peak memory 207540 kb
Host smart-86f72c40-36ac-43dd-98d7-35090c5b85a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3001212800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.3001212800
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.3063032126
Short name T868
Test name
Test status
Simulation time 496727916 ps
CPU time 1.59 seconds
Started Aug 08 06:21:11 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207612 kb
Host smart-e91c6471-5711-40d6-ac5a-d6987456fb6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063032126 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.3063032126
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.3089462262
Short name T3032
Test name
Test status
Simulation time 441824785 ps
CPU time 1.26 seconds
Started Aug 08 06:21:12 PM PDT 24
Finished Aug 08 06:21:13 PM PDT 24
Peak memory 207512 kb
Host smart-96ec4a4a-18aa-4b80-9818-1aa31c8d0195
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3089462262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.3089462262
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.1718876415
Short name T1831
Test name
Test status
Simulation time 593966614 ps
CPU time 1.54 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:25 PM PDT 24
Peak memory 207540 kb
Host smart-a9f91846-e8f2-4bb1-92fe-b087f69b0935
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718876415 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.1718876415
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.2476566920
Short name T3374
Test name
Test status
Simulation time 486986169 ps
CPU time 1.35 seconds
Started Aug 08 06:21:15 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207540 kb
Host smart-376f6949-20cc-4d73-8000-4cbaf185341e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2476566920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2476566920
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.329672517
Short name T1314
Test name
Test status
Simulation time 671393210 ps
CPU time 1.97 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207584 kb
Host smart-44788c04-0da8-4fe3-8442-9d9ba9ac3cbd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329672517 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.329672517
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.1557684125
Short name T3598
Test name
Test status
Simulation time 842003861 ps
CPU time 1.81 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 207572 kb
Host smart-42cdad32-2d07-47af-9598-5707aa6ed6da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1557684125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.1557684125
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.2540503157
Short name T2484
Test name
Test status
Simulation time 484424987 ps
CPU time 1.7 seconds
Started Aug 08 06:21:16 PM PDT 24
Finished Aug 08 06:21:18 PM PDT 24
Peak memory 207516 kb
Host smart-b01ade9c-0e81-41a3-9703-1581fd0092cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540503157 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.2540503157
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.980940528
Short name T2427
Test name
Test status
Simulation time 503842283 ps
CPU time 1.54 seconds
Started Aug 08 06:21:37 PM PDT 24
Finished Aug 08 06:21:39 PM PDT 24
Peak memory 207576 kb
Host smart-5217be57-5f39-4ca7-b8e3-e691943b8c42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980940528 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.980940528
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.4025924528
Short name T1070
Test name
Test status
Simulation time 223639076 ps
CPU time 0.94 seconds
Started Aug 08 06:21:23 PM PDT 24
Finished Aug 08 06:21:24 PM PDT 24
Peak memory 207540 kb
Host smart-6f285aa5-db1b-4955-b3d9-83e1f4031a4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4025924528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.4025924528
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.3195921994
Short name T92
Test name
Test status
Simulation time 509094584 ps
CPU time 1.56 seconds
Started Aug 08 06:21:10 PM PDT 24
Finished Aug 08 06:21:11 PM PDT 24
Peak memory 207588 kb
Host smart-fb647556-a796-497a-ae49-6077c9427327
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195921994 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.3195921994
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.242878599
Short name T479
Test name
Test status
Simulation time 160748624 ps
CPU time 0.91 seconds
Started Aug 08 06:21:17 PM PDT 24
Finished Aug 08 06:21:18 PM PDT 24
Peak memory 207500 kb
Host smart-60bd1855-c08d-4813-8fd1-39e84b06088f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=242878599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.242878599
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.3985033485
Short name T3248
Test name
Test status
Simulation time 503860441 ps
CPU time 1.53 seconds
Started Aug 08 06:21:25 PM PDT 24
Finished Aug 08 06:21:27 PM PDT 24
Peak memory 207532 kb
Host smart-2b9df2c4-920c-4f4f-8a60-9bb90712cd5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985033485 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.3985033485
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.2688978442
Short name T370
Test name
Test status
Simulation time 517202720 ps
CPU time 1.46 seconds
Started Aug 08 06:21:08 PM PDT 24
Finished Aug 08 06:21:09 PM PDT 24
Peak memory 207480 kb
Host smart-6c9ca0da-7541-4e6a-a1a2-b2e6faa58bf4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2688978442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.2688978442
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.1053181563
Short name T2676
Test name
Test status
Simulation time 490363791 ps
CPU time 1.53 seconds
Started Aug 08 06:21:16 PM PDT 24
Finished Aug 08 06:21:17 PM PDT 24
Peak memory 207624 kb
Host smart-ad3986f4-2c33-46f4-81c5-65807fddd069
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053181563 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.1053181563
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.3358505743
Short name T441
Test name
Test status
Simulation time 539276759 ps
CPU time 1.57 seconds
Started Aug 08 06:21:14 PM PDT 24
Finished Aug 08 06:21:15 PM PDT 24
Peak memory 207484 kb
Host smart-3d7f0bf7-d764-4c0a-ade7-b2885c28c9be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3358505743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.3358505743
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.331264504
Short name T1227
Test name
Test status
Simulation time 491295662 ps
CPU time 1.58 seconds
Started Aug 08 06:21:13 PM PDT 24
Finished Aug 08 06:21:14 PM PDT 24
Peak memory 207556 kb
Host smart-22944463-dc9a-4309-8bcd-37f5c3fca646
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331264504 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.331264504
Directory /workspace/99.usbdev_tx_rx_disruption/latest
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