Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	93134	1			T1	2		T2	2		T3	4
all_values[1]	93134	1			T1	2		T2	2		T3	4
all_values[2]	93134	1			T1	2		T2	2		T3	4
all_values[3]	93134	1			T1	2		T2	2		T3	4
all_values[4]	93134	1			T1	2		T2	2		T3	4
all_values[5]	93134	1			T1	2		T2	2		T3	4
all_values[6]	93134	1			T1	2		T2	2		T3	4
all_values[7]	93134	1			T1	2		T2	2		T3	4
all_values[8]	93134	1			T1	2		T2	2		T3	4
all_values[9]	93134	1			T1	2		T2	2		T3	4
all_values[10]	93134	1			T1	2		T2	2		T3	4
all_values[11]	93134	1			T1	2		T2	2		T3	4
all_values[12]	93134	1			T1	2		T2	2		T3	4
all_values[13]	93134	1			T1	2		T2	2		T3	4
all_values[14]	93134	1			T1	2		T2	2		T3	4
all_values[15]	93134	1			T1	2		T2	2		T3	4
all_values[16]	93134	1			T1	2		T2	2		T3	4
all_values[17]	93134	1			T1	2		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2970580

1

T1

64

T2

64

T3

124

auto[1]

9708

1

T3

4

T27

5

T29

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2489306

1

T1

60

T2

57

T3

110

auto[1]

490982

1

T1

4

T2

7

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	64093	1			T1	2		T2	2		T24	2
all_values[0]	auto[0]	auto[1]	25709	1			T28	1		T30	3		T31	1
all_values[0]	auto[1]	auto[0]	3228	1			T3	3		T27	5		T29	5
all_values[0]	auto[1]	auto[1]	104	1			T3	1		T84	1		T335	1
all_values[1]	auto[0]	auto[0]	88661	1			T1	2		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	3071	1			T27	3		T4	2		T29	3
all_values[1]	auto[1]	auto[0]	520	1			T6	1		T39	1		T40	1
all_values[1]	auto[1]	auto[1]	882	1			T6	1		T39	1		T40	1
all_values[2]	auto[0]	auto[0]	4232	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	88630	1			T1	1		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	148	1			T37	1		T18	1		T38	1
all_values[2]	auto[1]	auto[1]	124	1			T37	1		T18	1		T38	1
all_values[3]	auto[0]	auto[0]	91201	1			T1	2		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	290	1			T57	1		T58	1		T59	1
all_values[3]	auto[1]	auto[0]	1588	1			T60	1484		T209	4		T211	3
all_values[3]	auto[1]	auto[1]	55	1			T60	1		T207	1		T209	1
all_values[4]	auto[0]	auto[0]	4201	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	88772	1			T1	1		T2	1		T3	3
all_values[4]	auto[1]	auto[0]	109	1			T61	1		T209	1		T211	4
all_values[4]	auto[1]	auto[1]	52	1			T61	1		T207	2		T210	2
all_values[5]	auto[0]	auto[0]	92622	1			T1	2		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	352	1			T4	1		T6	1		T39	1
all_values[5]	auto[1]	auto[0]	90	1			T207	3		T210	5		T211	2
all_values[5]	auto[1]	auto[1]	70	1			T207	1		T210	1		T211	3
all_values[6]	auto[0]	auto[0]	92694	1			T1	2		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	208	1			T4	1		T62	1		T40	1
all_values[6]	auto[1]	auto[0]	110	1			T207	2		T209	1		T210	4
all_values[6]	auto[1]	auto[1]	122	1			T63	1		T64	1		T65	1
all_values[7]	auto[0]	auto[0]	35637	1			T1	2		T24	2		T4	2
all_values[7]	auto[0]	auto[1]	57336	1			T2	2		T3	4		T27	5
all_values[7]	auto[1]	auto[0]	95	1			T41	1		T42	1		T43	1
all_values[7]	auto[1]	auto[1]	66	1			T41	1		T42	1		T43	1
all_values[8]	auto[0]	auto[0]	92392	1			T1	2		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	55	1			T207	2		T209	1		T210	2
all_values[8]	auto[1]	auto[0]	611	1			T17	10		T44	10		T47	10
all_values[8]	auto[1]	auto[1]	76	1			T44	1		T45	1		T46	1
all_values[9]	auto[0]	auto[0]	92883	1			T1	2		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	62	1			T207	1		T209	1		T210	4
all_values[9]	auto[1]	auto[0]	119	1			T54	3		T55	3		T56	3
all_values[9]	auto[1]	auto[1]	70	1			T54	2		T55	2		T56	2
all_values[10]	auto[0]	auto[0]	92592	1			T1	2		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	387	1			T22	1		T52	1		T53	1
all_values[10]	auto[1]	auto[0]	99	1			T207	4		T209	1		T210	1
all_values[10]	auto[1]	auto[1]	56	1			T209	2		T210	1		T211	1
all_values[11]	auto[0]	auto[0]	92196	1			T1	2		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	694	1			T4	1		T16	1		T23	3
all_values[11]	auto[1]	auto[0]	134	1			T69	1		T70	1		T71	1
all_values[11]	auto[1]	auto[1]	110	1			T69	1		T70	1		T71	1
all_values[12]	auto[0]	auto[0]	92744	1			T1	2		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	201	1			T4	1		T72	3		T73	3
all_values[12]	auto[1]	auto[0]	103	1			T74	2		T75	2		T76	2
all_values[12]	auto[1]	auto[1]	86	1			T74	1		T75	1		T76	1
all_values[13]	auto[0]	auto[0]	92806	1			T1	2		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	51	1			T4	1		T79	1		T80	1
all_values[13]	auto[1]	auto[0]	143	1			T16	1		T77	1		T78	1
all_values[13]	auto[1]	auto[1]	134	1			T16	1		T77	1		T78	1
all_values[14]	auto[0]	auto[0]	18134	1			T1	1		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	74858	1			T1	1		T4	1		T32	1
all_values[14]	auto[1]	auto[0]	93	1			T207	2		T209	1		T210	1
all_values[14]	auto[1]	auto[1]	49	1			T207	2		T211	3		T212	1
all_values[15]	auto[0]	auto[0]	4267	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	88725	1			T1	1		T2	1		T3	3
all_values[15]	auto[1]	auto[0]	81	1			T207	4		T209	1		T210	2
all_values[15]	auto[1]	auto[1]	61	1			T207	1		T209	1		T210	1
all_values[16]	auto[0]	auto[0]	92155	1			T1	2		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	803	1			T4	1		T19	1		T58	1
all_values[16]	auto[1]	auto[0]	113	1			T66	4		T67	4		T68	4
all_values[16]	auto[1]	auto[1]	63	1			T66	4		T67	4		T68	4
all_values[17]	auto[0]	auto[0]	34450	1			T1	2		T24	2		T4	2
all_values[17]	auto[0]	auto[1]	58540	1			T2	2		T3	4		T27	5
all_values[17]	auto[1]	auto[0]	86	1			T51	1		T207	2		T209	3
all_values[17]	auto[1]	auto[1]	58	1			T51	1		T207	2		T209	1