Group : usbdev_env_pkg::usbdev_env_cov::address_cg
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Group : usbdev_env_pkg::usbdev_env_cov::address_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 14 0 14 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_address 7 0 7 100.00 100 1 1 0
cp_endp 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_address_X_endp 14 0 14 100.00 100 1 1 0


Summary for Variable cp_address

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_address

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
range_127 937 1 T1 1 T58 5 T234 1
range_16_to_126 152195 1 T1 104 T3 1 T27 10
fifteen 1886 1 T28 1 T58 3 T93 5
range_2_to_14 22654 1 T1 1 T82 3 T16 1
seven 2556 1 T1 1 T58 5 T93 4
one 3670 1 T58 4 T93 5 T106 702
zero 566 1 T58 4 T93 8 T106 9



Summary for Variable cp_endp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_endp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
seven 13191 1 T1 1 T27 7 T4 4
three 13622 1 T1 17 T4 16 T5 67



Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 0 14 100.00


Automatically Generated Cross Bins for cr_address_X_endp

Bins
cp_addresscp_endpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
range_127 seven 187 1 T345 7 T346 1 T347 1
range_127 three 26 1 T58 1 T93 1 T116 9
range_16_to_126 seven 11304 1 T1 1 T27 7 T4 4
range_16_to_126 three 10553 1 T1 17 T4 16 T5 67
fifteen seven 120 1 T348 7 T349 1 T350 1
fifteen three 149 1 T58 1 T171 6 T233 1
range_2_to_14 seven 1288 1 T58 1 T93 66 T106 3
range_2_to_14 three 2598 1 T58 5 T250 91 T93 57
seven seven 76 1 T351 1 T352 1 T183 1
seven three 84 1 T58 1 T349 1 T347 1
one seven 269 1 T106 51 T87 69 T233 1
one three 286 1 T106 42 T87 84 T352 1
zero seven 23 1 T58 1 T106 1 T353 1
zero three 10 1 T347 1 T354 1 T355 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%