Group : usbdev_env_pkg::usbdev_env_cov::crc16_cg
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Group : usbdev_env_pkg::usbdev_env_cov::crc16_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 1 3 75.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc16 2 0 2 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc16_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc16_X_dir 4 1 3 75.00 100 1 1 0


Summary for Variable cp_crc16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_crc16

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
six_ones 19 1 T292 1 T324 2 T325 2
all_ones 5 1 T4 1 T326 1 T327 1



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 112567 1 T1 53 T3 1 T27 6
auto[1] 46785 1 T1 42 T27 3 T4 49



Summary for Cross cr_crc16_X_dir

Samples crossed: cp_crc16 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cr_crc16_X_dir

Uncovered bins
cp_crc16cp_dirCOUNTAT LEASTNUMBERSTATUS
[all_ones] [auto[1]] 0 1 1


Covered bins
cp_crc16cp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
six_ones auto[0] 13 1 T292 1 T324 1 T325 1
six_ones auto[1] 6 1 T324 1 T325 1 T328 1
all_ones auto[0] 5 1 T4 1 T326 1 T327 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%