Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112567

1

T1

53

T3

1

T27

6

auto[1]

46785

1

T1

42

T27

3

T4

49

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30798	1			T1	6		T5	2		T23	1
max_len_m1	793	1			T4	3		T187	2		T62	2
max_len_m2	853	1			T1	2		T57	2		T89	1
max_len_m3	825	1			T27	1		T4	2		T5	2
five	1105	1			T1	2		T23	1		T187	2
four	1212	1			T4	2		T62	2		T57	2
three	784	1			T1	2		T59	3		T289	10
one	851	1			T109	1		T57	1		T163	1
zero	12072	1			T1	2		T4	1		T16	1

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24634	1			T1	3		T5	1		T85	1
max_len	auto[1]	6164	1			T1	3		T5	1		T23	1
max_len_m1	auto[0]	550	1			T4	2		T187	1		T62	1
max_len_m1	auto[1]	243	1			T4	1		T187	1		T62	1
max_len_m2	auto[0]	594	1			T1	1		T57	1		T89	1
max_len_m2	auto[1]	259	1			T1	1		T57	1		T356	2
max_len_m3	auto[0]	584	1			T4	1		T5	1		T187	1
max_len_m3	auto[1]	241	1			T27	1		T4	1		T5	1
five	auto[0]	584	1			T1	1		T187	1		T62	1
five	auto[1]	521	1			T1	1		T23	1		T187	1
four	auto[0]	642	1			T4	1		T62	1		T57	2
four	auto[1]	570	1			T4	1		T62	1		T90	1
three	auto[0]	380	1			T1	2		T59	3		T289	5
three	auto[1]	404	1			T289	5		T290	5		T263	7
one	auto[0]	400	1			T109	1		T57	1		T163	1
one	auto[1]	451	1			T192	1		T231	1		T289	9
zero	auto[0]	546	1			T1	2		T4	1		T16	1
zero	auto[1]	11526	1			T22	9		T52	9		T57	2