Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71181

1

T1

44

T3

1

T27

6

auto[1]

78609

1

T1

84

T27

6

T4

98

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10494	1			T1	21		T4	22		T31	1
endpoints[0x1]	9184	1			T1	21		T4	23		T62	18
endpoints[0x2]	10911	1			T3	1		T4	24		T149	3
endpoints[0x3]	13271	1			T1	22		T4	21		T5	99
endpoints[0x4]	15752	1			T19	1		T23	8		T44	8
endpoints[0x5]	17030	1			T1	21		T62	18		T152	3
endpoints[0x6]	11689	1			T27	4		T29	4		T6	3
endpoints[0x7]	12549	1			T27	8		T29	8		T17	7
endpoints[0x8]	12992	1			T4	23		T22	12		T62	18
endpoints[0x9]	13288	1			T1	22		T4	22		T310	1
endpoints[0xa]	11164	1			T1	21		T4	22		T30	1
endpoints[0xb]	11466	1			T28	1		T62	18		T40	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	182	1			T102	5		T103	7		T105	2
ack	38703	1			T1	42		T27	3		T4	49
data1	51668	1			T1	29		T27	6		T4	48
data0	59177	1			T1	57		T3	1		T27	3

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	12	1			T102	1		T311	1		T312	1
nak	auto[1]	endpoints[0x1]	16	1			T103	1		T313	1		T314	1
nak	auto[1]	endpoints[0x2]	13	1			T315	1		T316	3		T317	1
nak	auto[1]	endpoints[0x3]	16	1			T103	1		T312	1		T315	1
nak	auto[1]	endpoints[0x4]	12	1			T102	2		T105	1		T313	1
nak	auto[1]	endpoints[0x5]	18	1			T102	1		T318	3		T319	2
nak	auto[1]	endpoints[0x6]	20	1			T103	1		T320	1		T312	1
nak	auto[1]	endpoints[0x7]	17	1			T313	1		T311	1		T314	2
nak	auto[1]	endpoints[0x8]	16	1			T102	1		T103	1		T311	1
nak	auto[1]	endpoints[0x9]	12	1			T103	2		T318	1		T321	1
nak	auto[1]	endpoints[0xa]	16	1			T103	1		T314	1		T322	2
nak	auto[1]	endpoints[0xb]	14	1			T105	1		T311	1		T312	1
ack	auto[1]	endpoints[0x0]	3012	1			T1	7		T4	7		T39	1
ack	auto[1]	endpoints[0x1]	2793	1			T1	7		T4	7		T62	6
ack	auto[1]	endpoints[0x2]	3097	1			T4	7		T149	1		T150	2
ack	auto[1]	endpoints[0x3]	3776	1			T1	7		T4	7		T5	33
ack	auto[1]	endpoints[0x4]	3188	1			T23	2		T62	6		T90	2
ack	auto[1]	endpoints[0x5]	3657	1			T1	7		T62	6		T152	1
ack	auto[1]	endpoints[0x6]	3315	1			T27	1		T29	1		T6	1
ack	auto[1]	endpoints[0x7]	3269	1			T27	2		T29	2		T154	1
ack	auto[1]	endpoints[0x8]	3121	1			T4	7		T22	3		T62	6
ack	auto[1]	endpoints[0x9]	3142	1			T1	7		T4	7		T62	6
ack	auto[1]	endpoints[0xa]	3132	1			T1	7		T4	7		T187	34
ack	auto[1]	endpoints[0xb]	3201	1			T62	6		T40	1		T155	1
data1	auto[0]	endpoints[0x0]	1856	1			T1	2		T4	3		T155	2
data1	auto[0]	endpoints[0x1]	1365	1			T4	4		T62	2		T109	2
data1	auto[0]	endpoints[0x2]	1796	1			T4	3		T150	2		T151	2
data1	auto[0]	endpoints[0x3]	2298	1			T4	3		T5	16		T23	1
data1	auto[0]	endpoints[0x4]	4218	1			T23	2		T62	2		T90	2
data1	auto[0]	endpoints[0x5]	4341	1			T1	3		T62	2		T153	2
data1	auto[0]	endpoints[0x6]	2087	1			T27	1		T29	1		T62	2
data1	auto[0]	endpoints[0x7]	2536	1			T27	2		T29	2		T17	3
data1	auto[0]	endpoints[0x8]	2854	1			T4	4		T62	2		T57	4
data1	auto[0]	endpoints[0x9]	2970	1			T4	3		T62	1		T100	1
data1	auto[0]	endpoints[0xa]	1987	1			T1	1		T4	3		T187	17
data1	auto[0]	endpoints[0xb]	2056	1			T62	2		T155	1		T232	1
data1	auto[1]	endpoints[0x0]	1672	1			T1	5		T4	3		T155	2
data1	auto[1]	endpoints[0x1]	1524	1			T1	3		T4	3		T62	2
data1	auto[1]	endpoints[0x2]	1715	1			T4	3		T150	2		T151	2
data1	auto[1]	endpoints[0x3]	2095	1			T1	3		T4	3		T5	16
data1	auto[1]	endpoints[0x4]	1715	1			T23	2		T62	2		T90	2
data1	auto[1]	endpoints[0x5]	2022	1			T1	4		T62	2		T153	2
data1	auto[1]	endpoints[0x6]	1832	1			T27	1		T29	1		T62	2
data1	auto[1]	endpoints[0x7]	1779	1			T27	2		T29	2		T154	1
data1	auto[1]	endpoints[0x8]	1719	1			T4	4		T22	3		T62	2
data1	auto[1]	endpoints[0x9]	1756	1			T1	3		T4	5		T62	3
data1	auto[1]	endpoints[0xa]	1724	1			T1	5		T4	4		T187	17
data1	auto[1]	endpoints[0xb]	1751	1			T62	2		T155	1		T232	1
data0	auto[0]	endpoints[0x0]	2537	1			T1	5		T4	5		T31	1
data0	auto[0]	endpoints[0x1]	2105	1			T1	7		T4	4		T62	4
data0	auto[0]	endpoints[0x2]	2830	1			T3	1		T4	7		T149	1
data0	auto[0]	endpoints[0x3]	3286	1			T1	8		T4	4		T5	17
data0	auto[0]	endpoints[0x4]	5073	1			T19	1		T23	2		T44	8
data0	auto[0]	endpoints[0x5]	5269	1			T1	4		T62	4		T152	1
data0	auto[0]	endpoints[0x6]	2873	1			T27	1		T29	1		T6	1
data0	auto[0]	endpoints[0x7]	3381	1			T27	2		T29	2		T17	4
data0	auto[0]	endpoints[0x8]	3814	1			T4	5		T62	4		T57	7
data0	auto[0]	endpoints[0x9]	3926	1			T1	8		T4	5		T310	1
data0	auto[0]	endpoints[0xa]	2794	1			T1	6		T4	5		T30	1
data0	auto[0]	endpoints[0xb]	2919	1			T28	1		T62	4		T40	1
data0	auto[1]	endpoints[0x0]	1403	1			T1	2		T4	4		T39	1
data0	auto[1]	endpoints[0x1]	1371	1			T1	4		T4	4		T62	4
data0	auto[1]	endpoints[0x2]	1456	1			T4	4		T149	1		T289	22
data0	auto[1]	endpoints[0x3]	1796	1			T1	4		T4	4		T5	17
data0	auto[1]	endpoints[0x4]	1541	1			T62	4		T63	1		T59	5
data0	auto[1]	endpoints[0x5]	1721	1			T1	3		T62	4		T152	1
data0	auto[1]	endpoints[0x6]	1554	1			T6	1		T62	4		T58	3
data0	auto[1]	endpoints[0x7]	1565	1			T59	4		T53	6		T289	11
data0	auto[1]	endpoints[0x8]	1463	1			T4	3		T22	6		T62	4
data0	auto[1]	endpoints[0x9]	1478	1			T1	4		T4	2		T62	3
data0	auto[1]	endpoints[0xa]	1502	1			T1	2		T4	3		T187	17
data0	auto[1]	endpoints[0xb]	1520	1			T62	4		T40	1		T323	1