Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8680 1 T1 3 T20 1 T57 6
auto[1] 55025 1 T1 50 T27 3 T4 59


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55373 1 T1 43 T27 3 T4 59
auto[1] 8332 1 T1 10 T30 1 T57 30


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57538 1 T1 53 T27 3 T4 59
auto[1] 6167 1 T82 5 T20 1 T58 75


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4594 1 T1 5 T82 1 T20 1
pkt_types[PidTypeInToken] 59111 1 T1 48 T27 3 T4 59


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1529 1 T1 1 T57 2 T58 13
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 703 1 T20 1 T58 7 T93 15
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 93 1 T1 2 T57 4 T181 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 10 1 T357 1 T358 1 T359 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1334 1 T1 2 T82 1 T58 23
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 816 1 T58 10 T93 29 T106 8
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 88 1 T57 2 T229 3 T181 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 21 1 T360 1 T361 1 T362 2
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4204 1 T58 52 T234 1 T93 124
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2040 1 T58 31 T93 48 T235 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 49 1 T234 2 T358 1 T361 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 52 1 T234 1 T363 1 T353 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42276 1 T1 40 T27 3 T4 59
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2471 1 T82 5 T58 27 T234 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7965 1 T1 8 T30 1 T57 24
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 54 1 T360 1 T364 1 T365 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%