Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	93134	1			T1	2		T2	2		T3	4
all_pins[1]	93134	1			T1	2		T2	2		T3	4
all_pins[2]	93134	1			T1	2		T2	2		T3	4
all_pins[3]	93134	1			T1	2		T2	2		T3	4
all_pins[4]	93134	1			T1	2		T2	2		T3	4
all_pins[5]	93134	1			T1	2		T2	2		T3	4
all_pins[6]	93134	1			T1	2		T2	2		T3	4
all_pins[7]	93134	1			T1	2		T2	2		T3	4
all_pins[8]	93134	1			T1	2		T2	2		T3	4
all_pins[9]	93134	1			T1	2		T2	2		T3	4
all_pins[10]	93134	1			T1	2		T2	2		T3	4
all_pins[11]	93134	1			T1	2		T2	2		T3	4
all_pins[12]	93134	1			T1	2		T2	2		T3	4
all_pins[13]	93134	1			T1	2		T2	2		T3	4
all_pins[14]	93134	1			T1	2		T2	2		T3	4
all_pins[15]	93134	1			T1	2		T2	2		T3	4
all_pins[16]	93134	1			T1	2		T2	2		T3	4
all_pins[17]	93134	1			T1	2		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2978050	1			T1	64		T2	64		T3	127
values[0x1]	2238	1			T3	1		T37	1		T6	1
transitions[0x0=>0x1]	1935	1			T3	1		T37	1		T6	1
transitions[0x1=>0x0]	1935	1			T3	1		T37	1		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93030	1			T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	104	1			T3	1		T84	1		T335	1
all_pins[0]	transitions[0x0=>0x1]	85	1			T3	1		T84	1		T335	1
all_pins[0]	transitions[0x1=>0x0]	863	1			T6	1		T39	1		T40	1
all_pins[1]	values[0x0]	92252	1			T1	2		T2	2		T3	4
all_pins[1]	values[0x1]	882	1			T6	1		T39	1		T40	1
all_pins[1]	transitions[0x0=>0x1]	862	1			T6	1		T39	1		T40	1
all_pins[1]	transitions[0x1=>0x0]	104	1			T37	1		T18	1		T38	1
all_pins[2]	values[0x0]	93010	1			T1	2		T2	2		T3	4
all_pins[2]	values[0x1]	124	1			T37	1		T18	1		T38	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T37	1		T18	1		T38	1
all_pins[2]	transitions[0x1=>0x0]	39	1			T60	1		T209	1		T210	1
all_pins[3]	values[0x0]	93079	1			T1	2		T2	2		T3	4
all_pins[3]	values[0x1]	55	1			T60	1		T207	1		T209	1
all_pins[3]	transitions[0x0=>0x1]	39	1			T60	1		T209	1		T210	1
all_pins[3]	transitions[0x1=>0x0]	36	1			T61	1		T207	1		T332	3
all_pins[4]	values[0x0]	93082	1			T1	2		T2	2		T3	4
all_pins[4]	values[0x1]	52	1			T61	1		T207	2		T210	2
all_pins[4]	transitions[0x0=>0x1]	32	1			T61	1		T207	1		T210	1
all_pins[4]	transitions[0x1=>0x0]	50	1			T211	1		T330	2		T329	1
all_pins[5]	values[0x0]	93064	1			T1	2		T2	2		T3	4
all_pins[5]	values[0x1]	70	1			T207	1		T210	1		T211	3
all_pins[5]	transitions[0x0=>0x1]	44	1			T210	1		T211	3		T331	1
all_pins[5]	transitions[0x1=>0x0]	96	1			T63	1		T64	1		T65	1
all_pins[6]	values[0x0]	93012	1			T1	2		T2	2		T3	4
all_pins[6]	values[0x1]	122	1			T63	1		T64	1		T65	1
all_pins[6]	transitions[0x0=>0x1]	104	1			T63	1		T64	1		T65	1
all_pins[6]	transitions[0x1=>0x0]	48	1			T41	1		T42	1		T43	1
all_pins[7]	values[0x0]	93068	1			T1	2		T2	2		T3	4
all_pins[7]	values[0x1]	66	1			T41	1		T42	1		T43	1
all_pins[7]	transitions[0x0=>0x1]	52	1			T41	1		T42	1		T43	1
all_pins[7]	transitions[0x1=>0x0]	62	1			T44	1		T45	1		T46	1
all_pins[8]	values[0x0]	93058	1			T1	2		T2	2		T3	4
all_pins[8]	values[0x1]	76	1			T44	1		T45	1		T46	1
all_pins[8]	transitions[0x0=>0x1]	63	1			T44	1		T45	1		T46	1
all_pins[8]	transitions[0x1=>0x0]	57	1			T54	2		T55	2		T56	2
all_pins[9]	values[0x0]	93064	1			T1	2		T2	2		T3	4
all_pins[9]	values[0x1]	70	1			T54	2		T55	2		T56	2
all_pins[9]	transitions[0x0=>0x1]	55	1			T54	2		T55	2		T56	2
all_pins[9]	transitions[0x1=>0x0]	41	1			T211	1		T212	3		T297	1
all_pins[10]	values[0x0]	93078	1			T1	2		T2	2		T3	4
all_pins[10]	values[0x1]	56	1			T209	2		T210	1		T211	1
all_pins[10]	transitions[0x0=>0x1]	38	1			T209	2		T211	1		T212	3
all_pins[10]	transitions[0x1=>0x0]	92	1			T69	1		T70	1		T71	1
all_pins[11]	values[0x0]	93024	1			T1	2		T2	2		T3	4
all_pins[11]	values[0x1]	110	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	94	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	70	1			T74	1		T75	1		T76	1
all_pins[12]	values[0x0]	93048	1			T1	2		T2	2		T3	4
all_pins[12]	values[0x1]	86	1			T74	1		T75	1		T76	1
all_pins[12]	transitions[0x0=>0x1]	56	1			T74	1		T75	1		T76	1
all_pins[12]	transitions[0x1=>0x0]	104	1			T16	1		T77	1		T78	1
all_pins[13]	values[0x0]	93000	1			T1	2		T2	2		T3	4
all_pins[13]	values[0x1]	134	1			T16	1		T77	1		T78	1
all_pins[13]	transitions[0x0=>0x1]	110	1			T16	1		T77	1		T78	1
all_pins[13]	transitions[0x1=>0x0]	25	1			T211	2		T297	2		T334	1
all_pins[14]	values[0x0]	93085	1			T1	2		T2	2		T3	4
all_pins[14]	values[0x1]	49	1			T207	2		T211	3		T212	1
all_pins[14]	transitions[0x0=>0x1]	39	1			T207	2		T211	3		T212	1
all_pins[14]	transitions[0x1=>0x0]	51	1			T207	1		T209	1		T210	1
all_pins[15]	values[0x0]	93073	1			T1	2		T2	2		T3	4
all_pins[15]	values[0x1]	61	1			T207	1		T209	1		T210	1
all_pins[15]	transitions[0x0=>0x1]	43	1			T212	2		T298	2		T332	1
all_pins[15]	transitions[0x1=>0x0]	45	1			T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	93071	1			T1	2		T2	2		T3	4
all_pins[16]	values[0x1]	63	1			T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	53	1			T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	48	1			T51	1		T209	1		T210	2
all_pins[17]	values[0x0]	93076	1			T1	2		T2	2		T3	4
all_pins[17]	values[0x1]	58	1			T51	1		T207	2		T209	1
all_pins[17]	transitions[0x0=>0x1]	58	1			T51	1		T207	2		T209	1