Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4600	1			T4	1		T58	57		T234	1
invalid_ep[0xd]	4677	1			T4	1		T58	47		T59	14
invalid_ep[0xe]	4736	1			T4	2		T58	62		T234	1
invalid_ep[0xf]	4730	1			T58	57		T234	1		T59	12
endpoints[0x0]	12351	1			T1	16		T4	17		T31	1
endpoints[0x1]	10621	1			T1	16		T4	17		T62	13
endpoints[0x2]	12364	1			T3	1		T4	22		T82	7
endpoints[0x3]	13622	1			T1	17		T4	16		T5	67
endpoints[0x4]	16655	1			T1	3		T19	1		T23	7
endpoints[0x5]	17525	1			T1	19		T4	3		T62	13
endpoints[0x6]	12662	1			T27	3		T4	4		T29	3
endpoints[0x7]	13191	1			T1	1		T27	7		T4	4
endpoints[0x8]	14832	1			T1	1		T4	19		T22	9
endpoints[0x9]	14384	1			T1	16		T4	17		T310	1
endpoints[0xa]	12120	1			T1	16		T4	16		T30	2
endpoints[0xb]	12838	1			T1	1		T4	1		T28	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23267	1			T1	12		T27	4		T4	11
pkt_types[PidTypeOutToken]	77683	1			T1	32		T3	1		T27	3
pkt_types[PidTypeInToken]	63247	1			T1	48		T27	3		T4	59

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	960	1			T58	12		T93	20		T106	23
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1044	1			T58	14		T93	39		T106	23
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1061	1			T58	21		T93	26		T363	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1046	1			T58	13		T93	28		T363	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1683	1			T1	4		T31	1		T156	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1445	1			T4	1		T109	2		T58	16
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1695	1			T82	1		T58	11		T150	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1688	1			T23	1		T85	1		T62	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1495	1			T23	2		T44	8		T58	10
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1680	1			T1	3		T58	11		T153	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1571	1			T27	1		T29	1		T160	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1526	1			T27	3		T29	2		T82	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1536	1			T4	4		T57	6		T154	2
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1643	1			T4	3		T62	4		T100	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1586	1			T1	5		T4	3		T82	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1608	1			T28	1		T155	1		T161	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1571	1			T4	1		T58	12		T234	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1597	1			T4	1		T58	12		T59	14
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1559	1			T4	2		T58	14		T59	14
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1588	1			T58	14		T234	1		T59	12
pkt_types[PidTypeOutToken]	endpoints[0x0]	4583	1			T1	3		T4	8		T39	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	3664	1			T1	7		T4	8		T62	6
pkt_types[PidTypeOutToken]	endpoints[0x2]	4725	1			T3	1		T4	10		T82	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5374	1			T1	8		T4	8		T5	33
pkt_types[PidTypeOutToken]	endpoints[0x4]	9364	1			T19	1		T23	3		T62	6
pkt_types[PidTypeOutToken]	endpoints[0x5]	9603	1			T1	4		T4	2		T62	6
pkt_types[PidTypeOutToken]	endpoints[0x6]	5023	1			T27	1		T4	3		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5874	1			T27	2		T4	3		T29	2
pkt_types[PidTypeOutToken]	endpoints[0x8]	6625	1			T4	5		T62	6		T57	5
pkt_types[PidTypeOutToken]	endpoints[0x9]	6630	1			T1	8		T4	5		T310	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4907	1			T1	2		T4	5		T30	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	4996	1			T4	1		T82	1		T62	6
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1030	1			T58	11		T93	36		T106	12
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1024	1			T58	7		T93	36		T504	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1046	1			T58	13		T93	37		T106	24
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1036	1			T58	14		T93	26		T106	20
pkt_types[PidTypeInToken]	endpoints[0x0]	4978	1			T1	8		T4	8		T39	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4380	1			T1	8		T4	8		T62	7
pkt_types[PidTypeInToken]	endpoints[0x2]	4797	1			T4	10		T82	4		T149	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5426	1			T1	8		T4	8		T5	34
pkt_types[PidTypeInToken]	endpoints[0x4]	4650	1			T23	2		T62	7		T58	9
pkt_types[PidTypeInToken]	endpoints[0x5]	5100	1			T1	8		T62	7		T152	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4921	1			T27	1		T29	1		T82	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4646	1			T27	2		T29	2		T154	1
pkt_types[PidTypeInToken]	endpoints[0x8]	5564	1			T4	9		T22	9		T62	7
pkt_types[PidTypeInToken]	endpoints[0x9]	5035	1			T1	8		T4	8		T62	7
pkt_types[PidTypeInToken]	endpoints[0xa]	4504	1			T1	8		T4	8		T30	1
pkt_types[PidTypeInToken]	endpoints[0xb]	5110	1			T82	1		T62	7		T40	1