Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1			T207	4		T209	4		T210	7
all_values[1]	263	1			T207	4		T209	4		T210	7
all_values[2]	263	1			T207	4		T209	4		T210	7
all_values[3]	263	1			T207	4		T209	4		T210	7
all_values[4]	263	1			T207	4		T209	4		T210	7
all_values[5]	263	1			T207	4		T209	4		T210	7
all_values[6]	263	1			T207	4		T209	4		T210	7
all_values[7]	263	1			T207	4		T209	4		T210	7
all_values[8]	263	1			T207	4		T209	4		T210	7
all_values[9]	263	1			T207	4		T209	4		T210	7
all_values[10]	263	1			T207	4		T209	4		T210	7
all_values[11]	263	1			T207	4		T209	4		T210	7
all_values[12]	263	1			T207	4		T209	4		T210	7
all_values[13]	263	1			T207	4		T209	4		T210	7
all_values[14]	263	1			T207	4		T209	4		T210	7
all_values[15]	263	1			T207	4		T209	4		T210	7
all_values[16]	263	1			T207	4		T209	4		T210	7
all_values[17]	263	1			T207	4		T209	4		T210	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6215

1

T207

96

T209

102

T210

168

auto[1]

2201

1

T207

32

T209

26

T210

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5785

1

T207

85

T209

94

T210

162

auto[1]

2631

1

T207

43

T209

34

T210

62

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5014

1

T207

81

T209

71

T210

138

auto[1]

3402

1

T207

47

T209

57

T210

86

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	76	1			T207	1		T209	3		T210	2
all_values[0]	auto[0]	auto[1]	auto[0]	85	1			T207	1		T210	2		T211	2
all_values[0]	auto[1]	auto[0]	auto[1]	54	1			T207	1		T209	1		T210	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1			T207	1		T210	2		T212	1
all_values[1]	auto[0]	auto[0]	auto[0]	70	1			T207	2		T209	2		T210	2
all_values[1]	auto[0]	auto[1]	auto[0]	79	1			T210	4		T211	2		T212	4
all_values[1]	auto[1]	auto[0]	auto[1]	57	1			T207	2		T209	2		T211	3
all_values[1]	auto[1]	auto[1]	auto[1]	57	1			T210	1		T212	1		T329	1
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T207	1		T210	1		T211	1
all_values[2]	auto[0]	auto[0]	auto[1]	35	1			T209	1		T211	1		T212	2
all_values[2]	auto[0]	auto[1]	auto[0]	44	1			T207	1		T209	1		T210	2
all_values[2]	auto[0]	auto[1]	auto[1]	31	1			T207	1		T210	1		T330	1
all_values[2]	auto[1]	auto[0]	auto[1]	59	1			T207	1		T209	1		T211	2
all_values[2]	auto[1]	auto[1]	auto[1]	51	1			T209	1		T210	3		T211	2
all_values[3]	auto[0]	auto[0]	auto[0]	59	1			T207	1		T209	1		T211	1
all_values[3]	auto[0]	auto[0]	auto[1]	21	1			T207	1		T210	2		T211	1
all_values[3]	auto[0]	auto[1]	auto[0]	52	1			T209	1		T211	1		T212	1
all_values[3]	auto[0]	auto[1]	auto[1]	22	1			T211	1		T212	1		T330	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1			T207	2		T210	1		T211	2
all_values[3]	auto[1]	auto[1]	auto[1]	50	1			T209	2		T210	4		T211	1
all_values[4]	auto[0]	auto[0]	auto[0]	57	1			T209	3		T210	3		T211	2
all_values[4]	auto[0]	auto[0]	auto[1]	20	1			T207	1		T330	2		T297	1
all_values[4]	auto[0]	auto[1]	auto[0]	57	1			T211	3		T329	1		T331	2
all_values[4]	auto[0]	auto[1]	auto[1]	30	1			T207	2		T210	1		T211	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1			T207	1		T209	1		T210	2
all_values[4]	auto[1]	auto[1]	auto[1]	39	1			T210	1		T211	1		T330	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1			T207	1		T209	4		T210	3
all_values[5]	auto[0]	auto[0]	auto[1]	26	1			T212	5		T297	1		T329	1
all_values[5]	auto[0]	auto[1]	auto[0]	41	1			T207	2		T210	2		T211	1
all_values[5]	auto[0]	auto[1]	auto[1]	31	1			T211	1		T330	1		T299	2
all_values[5]	auto[1]	auto[0]	auto[1]	56	1			T210	1		T211	1		T212	1
all_values[5]	auto[1]	auto[1]	auto[1]	47	1			T207	1		T210	1		T211	2
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T207	1		T209	1		T210	3
all_values[6]	auto[0]	auto[0]	auto[1]	18	1			T330	1		T329	1		T332	1
all_values[6]	auto[0]	auto[1]	auto[0]	53	1			T210	2		T211	1		T298	1
all_values[6]	auto[0]	auto[1]	auto[1]	28	1			T207	1		T209	1		T210	1
all_values[6]	auto[1]	auto[0]	auto[1]	53	1			T210	1		T212	3		T330	1
all_values[6]	auto[1]	auto[1]	auto[1]	54	1			T207	2		T209	2		T211	1
all_values[7]	auto[0]	auto[0]	auto[0]	77	1			T207	4		T209	2		T210	3
all_values[7]	auto[0]	auto[1]	auto[0]	62	1			T209	1		T210	2		T211	1
all_values[7]	auto[1]	auto[0]	auto[1]	72	1			T210	2		T211	2		T212	2
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T209	1		T211	1		T212	3
all_values[8]	auto[0]	auto[0]	auto[0]	80	1			T207	1		T209	1		T210	2
all_values[8]	auto[0]	auto[1]	auto[0]	76	1			T210	2		T211	3		T212	3
all_values[8]	auto[1]	auto[0]	auto[1]	54	1			T207	1		T209	1		T210	2
all_values[8]	auto[1]	auto[1]	auto[1]	53	1			T207	2		T209	2		T210	1
all_values[9]	auto[0]	auto[0]	auto[0]	51	1			T207	2		T211	1		T330	2
all_values[9]	auto[0]	auto[0]	auto[1]	28	1			T210	2		T211	1		T212	1
all_values[9]	auto[0]	auto[1]	auto[0]	53	1			T211	2		T330	2		T298	1
all_values[9]	auto[0]	auto[1]	auto[1]	23	1			T209	2		T211	2		T212	1
all_values[9]	auto[1]	auto[0]	auto[1]	60	1			T207	2		T209	1		T210	3
all_values[9]	auto[1]	auto[1]	auto[1]	48	1			T209	1		T210	2		T211	1
all_values[10]	auto[0]	auto[0]	auto[0]	57	1			T207	2		T210	5		T211	2
all_values[10]	auto[0]	auto[0]	auto[1]	25	1			T211	3		T212	1		T299	1
all_values[10]	auto[0]	auto[1]	auto[0]	50	1			T207	1		T210	1		T297	1
all_values[10]	auto[0]	auto[1]	auto[1]	24	1			T209	1		T212	2		T297	1
all_values[10]	auto[1]	auto[0]	auto[1]	63	1			T207	1		T209	3		T211	2
all_values[10]	auto[1]	auto[1]	auto[1]	44	1			T210	1		T212	2		T297	2
all_values[11]	auto[0]	auto[0]	auto[0]	53	1			T209	2		T210	3		T211	1
all_values[11]	auto[0]	auto[0]	auto[1]	34	1			T207	1		T211	2		T298	1
all_values[11]	auto[0]	auto[1]	auto[0]	40	1			T209	2		T212	2		T330	2
all_values[11]	auto[0]	auto[1]	auto[1]	24	1			T329	1		T331	1		T333	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1			T207	1		T210	2		T211	2
all_values[11]	auto[1]	auto[1]	auto[1]	43	1			T207	2		T210	2		T211	2
all_values[12]	auto[0]	auto[0]	auto[0]	54	1			T207	1		T209	1		T210	1
all_values[12]	auto[0]	auto[0]	auto[1]	21	1			T207	1		T209	1		T211	1
all_values[12]	auto[0]	auto[1]	auto[0]	47	1			T210	1		T297	1		T298	1
all_values[12]	auto[0]	auto[1]	auto[1]	35	1			T210	1		T211	2		T212	1
all_values[12]	auto[1]	auto[0]	auto[1]	50	1			T209	2		T210	1		T211	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T207	2		T210	3		T211	1
all_values[13]	auto[0]	auto[0]	auto[0]	63	1			T207	1		T209	3		T210	2
all_values[13]	auto[0]	auto[0]	auto[1]	19	1			T211	1		T212	1		T299	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T210	1		T212	1		T298	1
all_values[13]	auto[0]	auto[1]	auto[1]	41	1			T207	1		T210	3		T330	1
all_values[13]	auto[1]	auto[0]	auto[1]	52	1			T209	1		T211	2		T329	1
all_values[13]	auto[1]	auto[1]	auto[1]	50	1			T207	2		T210	1		T211	2
all_values[14]	auto[0]	auto[0]	auto[0]	62	1			T207	2		T209	2		T210	3
all_values[14]	auto[0]	auto[0]	auto[1]	32	1			T210	2		T212	1		T329	1
all_values[14]	auto[0]	auto[1]	auto[0]	48	1			T209	2		T210	1		T211	1
all_values[14]	auto[0]	auto[1]	auto[1]	23	1			T207	1		T211	2		T297	2
all_values[14]	auto[1]	auto[0]	auto[1]	59	1			T207	1		T210	1		T212	2
all_values[14]	auto[1]	auto[1]	auto[1]	39	1			T211	2		T212	2		T330	1
all_values[15]	auto[0]	auto[0]	auto[0]	66	1			T209	2		T210	3		T211	1
all_values[15]	auto[0]	auto[0]	auto[1]	29	1			T211	1		T212	1		T332	2
all_values[15]	auto[0]	auto[1]	auto[0]	30	1			T207	3		T210	2		T330	3
all_values[15]	auto[0]	auto[1]	auto[1]	23	1			T209	1		T298	1		T334	1
all_values[15]	auto[1]	auto[0]	auto[1]	63	1			T207	1		T210	1		T211	5
all_values[15]	auto[1]	auto[1]	auto[1]	52	1			T209	1		T210	1		T212	2
all_values[16]	auto[0]	auto[0]	auto[0]	64	1			T209	1		T210	1		T211	5
all_values[16]	auto[0]	auto[0]	auto[1]	20	1			T210	1		T212	1		T297	2
all_values[16]	auto[0]	auto[1]	auto[0]	52	1			T209	1		T210	1		T211	1
all_values[16]	auto[0]	auto[1]	auto[1]	24	1			T207	2		T331	1		T334	1
all_values[16]	auto[1]	auto[0]	auto[1]	67	1			T207	1		T210	3		T212	3
all_values[16]	auto[1]	auto[1]	auto[1]	36	1			T207	1		T209	2		T210	1
all_values[17]	auto[0]	auto[0]	auto[0]	79	1			T209	1		T210	4		T212	3
all_values[17]	auto[0]	auto[1]	auto[0]	66	1			T207	1		T209	1		T211	1
all_values[17]	auto[1]	auto[0]	auto[1]	68	1			T207	1		T209	2		T210	1
all_values[17]	auto[1]	auto[1]	auto[1]	50	1			T207	2		T210	2		T211	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal