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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.56 98.11 95.94 97.44 94.92 98.30 98.17 93.03


Total test records in report: 3740
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T3569 /workspace/coverage/default/18.usbdev_disconnected.348564373 Aug 09 05:28:28 PM PDT 24 Aug 09 05:28:29 PM PDT 24 167238920 ps
T3570 /workspace/coverage/default/27.usbdev_device_address.2650533346 Aug 09 05:29:49 PM PDT 24 Aug 09 05:30:30 PM PDT 24 24740968533 ps
T3571 /workspace/coverage/default/160.usbdev_tx_rx_disruption.1548852320 Aug 09 05:33:08 PM PDT 24 Aug 09 05:33:15 PM PDT 24 525463858 ps
T3572 /workspace/coverage/default/42.usbdev_random_length_out_transaction.1095554110 Aug 09 05:32:03 PM PDT 24 Aug 09 05:32:04 PM PDT 24 161990725 ps
T3573 /workspace/coverage/default/45.usbdev_setup_stage.615694431 Aug 09 05:32:10 PM PDT 24 Aug 09 05:32:11 PM PDT 24 164043637 ps
T3574 /workspace/coverage/default/35.usbdev_stall_trans.3662918384 Aug 09 05:31:04 PM PDT 24 Aug 09 05:31:05 PM PDT 24 188040353 ps
T3575 /workspace/coverage/default/20.usbdev_fifo_rst.1391447229 Aug 09 05:28:52 PM PDT 24 Aug 09 05:28:54 PM PDT 24 171740362 ps
T3576 /workspace/coverage/default/3.usbdev_random_length_in_transaction.3511754193 Aug 09 05:26:12 PM PDT 24 Aug 09 05:26:13 PM PDT 24 271324069 ps
T3577 /workspace/coverage/default/7.usbdev_endpoint_access.1690334917 Aug 09 05:26:54 PM PDT 24 Aug 09 05:26:57 PM PDT 24 1043473326 ps
T3578 /workspace/coverage/default/177.usbdev_endpoint_types.4162254973 Aug 09 05:33:29 PM PDT 24 Aug 09 05:33:30 PM PDT 24 339793943 ps
T3579 /workspace/coverage/default/48.usbdev_in_stall.621072765 Aug 09 05:32:38 PM PDT 24 Aug 09 05:32:39 PM PDT 24 177790252 ps
T3580 /workspace/coverage/default/30.usbdev_streaming_out.3289852194 Aug 09 05:30:21 PM PDT 24 Aug 09 05:31:05 PM PDT 24 1619700520 ps
T3581 /workspace/coverage/default/12.usbdev_phy_config_pinflip.1721197131 Aug 09 05:27:48 PM PDT 24 Aug 09 05:27:49 PM PDT 24 236853581 ps
T3582 /workspace/coverage/default/5.usbdev_aon_wake_reset.795608003 Aug 09 05:26:25 PM PDT 24 Aug 09 05:26:48 PM PDT 24 19629544948 ps
T3583 /workspace/coverage/default/7.usbdev_max_length_out_transaction.307809344 Aug 09 05:26:53 PM PDT 24 Aug 09 05:26:54 PM PDT 24 254203112 ps
T3584 /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.333081073 Aug 09 05:28:54 PM PDT 24 Aug 09 05:29:38 PM PDT 24 4824171809 ps
T3585 /workspace/coverage/default/19.usbdev_random_length_in_transaction.868518653 Aug 09 05:28:43 PM PDT 24 Aug 09 05:28:44 PM PDT 24 184596639 ps
T3586 /workspace/coverage/default/22.usbdev_streaming_out.3626662331 Aug 09 05:29:05 PM PDT 24 Aug 09 05:29:28 PM PDT 24 2387447604 ps
T3587 /workspace/coverage/default/426.usbdev_tx_rx_disruption.3441916338 Aug 09 05:34:06 PM PDT 24 Aug 09 05:34:07 PM PDT 24 469304764 ps
T3588 /workspace/coverage/default/5.usbdev_data_toggle_clear.1805688379 Aug 09 05:26:38 PM PDT 24 Aug 09 05:26:40 PM PDT 24 605957778 ps
T3589 /workspace/coverage/default/231.usbdev_tx_rx_disruption.3481215547 Aug 09 05:33:38 PM PDT 24 Aug 09 05:33:39 PM PDT 24 540629445 ps
T3590 /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3659956164 Aug 09 05:31:33 PM PDT 24 Aug 09 05:31:44 PM PDT 24 650009938 ps
T3591 /workspace/coverage/default/10.usbdev_enable.1030945865 Aug 09 05:27:19 PM PDT 24 Aug 09 05:27:20 PM PDT 24 50349330 ps
T3592 /workspace/coverage/default/47.usbdev_rx_crc_err.301164592 Aug 09 05:32:27 PM PDT 24 Aug 09 05:32:28 PM PDT 24 142613920 ps
T3593 /workspace/coverage/default/133.usbdev_endpoint_types.2798246668 Aug 09 05:33:10 PM PDT 24 Aug 09 05:33:11 PM PDT 24 519795869 ps
T3594 /workspace/coverage/default/1.usbdev_av_overflow.105463661 Aug 09 05:25:51 PM PDT 24 Aug 09 05:25:52 PM PDT 24 181330163 ps
T3595 /workspace/coverage/default/14.usbdev_out_trans_nak.4038885388 Aug 09 05:27:55 PM PDT 24 Aug 09 05:27:56 PM PDT 24 155315842 ps
T3596 /workspace/coverage/default/265.usbdev_tx_rx_disruption.4286319682 Aug 09 05:33:59 PM PDT 24 Aug 09 05:34:00 PM PDT 24 492052257 ps
T3597 /workspace/coverage/default/22.usbdev_enable.1287127227 Aug 09 05:29:06 PM PDT 24 Aug 09 05:29:06 PM PDT 24 31549626 ps
T3598 /workspace/coverage/default/23.usbdev_aon_wake_reset.3063142812 Aug 09 05:29:14 PM PDT 24 Aug 09 05:29:33 PM PDT 24 16237741277 ps
T3599 /workspace/coverage/default/21.usbdev_av_buffer.2519094046 Aug 09 05:29:02 PM PDT 24 Aug 09 05:29:03 PM PDT 24 147876422 ps
T3600 /workspace/coverage/default/38.usbdev_enable.661712861 Aug 09 05:31:10 PM PDT 24 Aug 09 05:31:11 PM PDT 24 64090577 ps
T3601 /workspace/coverage/default/39.usbdev_enable.4066504968 Aug 09 05:31:16 PM PDT 24 Aug 09 05:31:17 PM PDT 24 67291204 ps
T3602 /workspace/coverage/default/456.usbdev_tx_rx_disruption.3706904269 Aug 09 05:33:49 PM PDT 24 Aug 09 05:33:50 PM PDT 24 504964270 ps
T3603 /workspace/coverage/default/29.usbdev_stream_len_max.1413258733 Aug 09 05:30:09 PM PDT 24 Aug 09 05:30:12 PM PDT 24 1164514309 ps
T3604 /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.1498756090 Aug 09 05:31:01 PM PDT 24 Aug 09 05:31:39 PM PDT 24 5617436772 ps
T3605 /workspace/coverage/default/29.usbdev_smoke.1951732360 Aug 09 05:30:08 PM PDT 24 Aug 09 05:30:09 PM PDT 24 257946926 ps
T3606 /workspace/coverage/default/340.usbdev_tx_rx_disruption.379768536 Aug 09 05:34:00 PM PDT 24 Aug 09 05:34:02 PM PDT 24 577728316 ps
T3607 /workspace/coverage/default/13.usbdev_rx_crc_err.2657508878 Aug 09 05:28:02 PM PDT 24 Aug 09 05:28:03 PM PDT 24 136593323 ps
T3608 /workspace/coverage/default/246.usbdev_tx_rx_disruption.3027260940 Aug 09 05:33:30 PM PDT 24 Aug 09 05:33:32 PM PDT 24 635436259 ps
T3609 /workspace/coverage/default/192.usbdev_tx_rx_disruption.3175067039 Aug 09 05:33:39 PM PDT 24 Aug 09 05:33:41 PM PDT 24 522482065 ps
T3610 /workspace/coverage/default/319.usbdev_tx_rx_disruption.1061144438 Aug 09 05:34:03 PM PDT 24 Aug 09 05:34:05 PM PDT 24 530010999 ps
T3611 /workspace/coverage/default/45.usbdev_in_stall.1627159005 Aug 09 05:32:04 PM PDT 24 Aug 09 05:32:05 PM PDT 24 141763648 ps
T3612 /workspace/coverage/default/16.usbdev_device_address.399412075 Aug 09 05:28:34 PM PDT 24 Aug 09 05:29:42 PM PDT 24 44504946676 ps
T3613 /workspace/coverage/default/47.usbdev_data_toggle_clear.1088350987 Aug 09 05:32:11 PM PDT 24 Aug 09 05:32:12 PM PDT 24 379908596 ps
T3614 /workspace/coverage/default/205.usbdev_tx_rx_disruption.337454982 Aug 09 05:33:36 PM PDT 24 Aug 09 05:33:37 PM PDT 24 514537662 ps
T3615 /workspace/coverage/default/32.usbdev_min_length_in_transaction.1666542529 Aug 09 05:30:40 PM PDT 24 Aug 09 05:30:41 PM PDT 24 164111706 ps
T3616 /workspace/coverage/default/25.usbdev_random_length_in_transaction.275329717 Aug 09 05:29:33 PM PDT 24 Aug 09 05:29:34 PM PDT 24 168908718 ps
T3617 /workspace/coverage/default/42.usbdev_setup_trans_ignored.173651946 Aug 09 05:31:45 PM PDT 24 Aug 09 05:31:46 PM PDT 24 150060177 ps
T3618 /workspace/coverage/default/11.usbdev_link_in_err.4040960837 Aug 09 05:27:36 PM PDT 24 Aug 09 05:27:37 PM PDT 24 163275537 ps
T3619 /workspace/coverage/default/197.usbdev_tx_rx_disruption.277596361 Aug 09 05:33:30 PM PDT 24 Aug 09 05:33:31 PM PDT 24 510650592 ps
T3620 /workspace/coverage/default/2.usbdev_av_buffer.3979364621 Aug 09 05:25:53 PM PDT 24 Aug 09 05:25:54 PM PDT 24 160580876 ps
T3621 /workspace/coverage/default/141.usbdev_endpoint_types.4278421199 Aug 09 05:33:26 PM PDT 24 Aug 09 05:33:27 PM PDT 24 361458204 ps
T3622 /workspace/coverage/default/3.usbdev_aon_wake_resume.1997214922 Aug 09 05:26:12 PM PDT 24 Aug 09 05:26:50 PM PDT 24 30312011212 ps
T3623 /workspace/coverage/default/13.usbdev_min_length_out_transaction.322159425 Aug 09 05:27:55 PM PDT 24 Aug 09 05:27:56 PM PDT 24 162438532 ps
T3624 /workspace/coverage/default/49.usbdev_stream_len_max.1571086612 Aug 09 05:32:55 PM PDT 24 Aug 09 05:32:58 PM PDT 24 1065051117 ps
T3625 /workspace/coverage/default/46.usbdev_iso_retraction.571080519 Aug 09 05:32:06 PM PDT 24 Aug 09 05:33:18 PM PDT 24 10003000761 ps
T130 /workspace/coverage/default/4.usbdev_nak_trans.3300962833 Aug 09 05:26:19 PM PDT 24 Aug 09 05:26:20 PM PDT 24 243285940 ps
T3626 /workspace/coverage/default/33.usbdev_streaming_out.131663852 Aug 09 05:30:44 PM PDT 24 Aug 09 05:31:20 PM PDT 24 3402863600 ps
T3627 /workspace/coverage/default/48.usbdev_in_trans.4119545611 Aug 09 05:32:30 PM PDT 24 Aug 09 05:32:31 PM PDT 24 178720839 ps
T3628 /workspace/coverage/default/6.usbdev_nak_trans.2993363748 Aug 09 05:26:43 PM PDT 24 Aug 09 05:26:44 PM PDT 24 223525811 ps
T3629 /workspace/coverage/default/16.usbdev_endpoint_access.857872797 Aug 09 05:28:10 PM PDT 24 Aug 09 05:28:13 PM PDT 24 926970994 ps
T3630 /workspace/coverage/default/18.usbdev_low_speed_traffic.3904692290 Aug 09 05:28:31 PM PDT 24 Aug 09 05:29:51 PM PDT 24 2886128781 ps
T3631 /workspace/coverage/default/37.usbdev_bitstuff_err.3728873186 Aug 09 05:31:05 PM PDT 24 Aug 09 05:31:06 PM PDT 24 162903110 ps
T3632 /workspace/coverage/default/1.usbdev_stall_trans.1757191742 Aug 09 05:25:47 PM PDT 24 Aug 09 05:25:48 PM PDT 24 172802681 ps
T204 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.497246924 Aug 09 07:11:31 PM PDT 24 Aug 09 07:11:34 PM PDT 24 356408781 ps
T270 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2753627154 Aug 09 07:11:21 PM PDT 24 Aug 09 07:11:24 PM PDT 24 76868877 ps
T239 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.409504735 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 120573301 ps
T240 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1200414837 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:05 PM PDT 24 219500679 ps
T207 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.86255643 Aug 09 07:11:38 PM PDT 24 Aug 09 07:11:39 PM PDT 24 65507361 ps
T205 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2637954285 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:05 PM PDT 24 314224584 ps
T3633 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1257583333 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:58 PM PDT 24 711127938 ps
T206 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2776808000 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:22 PM PDT 24 194467822 ps
T208 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3481263082 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 94844975 ps
T283 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.313493603 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:02 PM PDT 24 116337946 ps
T284 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2716326988 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:19 PM PDT 24 120180726 ps
T209 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.190474232 Aug 09 07:11:21 PM PDT 24 Aug 09 07:11:22 PM PDT 24 35204006 ps
T237 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2828428176 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:35 PM PDT 24 100094139 ps
T285 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2278346461 Aug 09 07:11:22 PM PDT 24 Aug 09 07:11:23 PM PDT 24 140532515 ps
T210 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3317367370 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:20 PM PDT 24 55442746 ps
T211 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2757498156 Aug 09 07:11:13 PM PDT 24 Aug 09 07:11:14 PM PDT 24 53022846 ps
T3634 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.152225317 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:18 PM PDT 24 120535196 ps
T238 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2828411814 Aug 09 07:11:17 PM PDT 24 Aug 09 07:11:19 PM PDT 24 67129147 ps
T247 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3605708260 Aug 09 07:11:22 PM PDT 24 Aug 09 07:11:25 PM PDT 24 542413984 ps
T212 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1668062920 Aug 09 07:11:34 PM PDT 24 Aug 09 07:11:35 PM PDT 24 39099046 ps
T286 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.311509538 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:34 PM PDT 24 334912521 ps
T330 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3956420769 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:19 PM PDT 24 38170588 ps
T294 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3214744149 Aug 09 07:10:59 PM PDT 24 Aug 09 07:11:00 PM PDT 24 108838751 ps
T297 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2262352889 Aug 09 07:11:38 PM PDT 24 Aug 09 07:11:39 PM PDT 24 67042832 ps
T271 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2459313696 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:03 PM PDT 24 188583419 ps
T272 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2071193770 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 115731540 ps
T329 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4821810 Aug 09 07:11:06 PM PDT 24 Aug 09 07:11:06 PM PDT 24 70841375 ps
T273 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.198408173 Aug 09 07:11:30 PM PDT 24 Aug 09 07:11:31 PM PDT 24 132469798 ps
T274 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3650104657 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:04 PM PDT 24 141774376 ps
T248 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3269161362 Aug 09 07:11:25 PM PDT 24 Aug 09 07:11:27 PM PDT 24 69527310 ps
T287 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3834140573 Aug 09 07:11:24 PM PDT 24 Aug 09 07:11:25 PM PDT 24 107053082 ps
T298 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2206143366 Aug 09 07:11:31 PM PDT 24 Aug 09 07:11:32 PM PDT 24 81022713 ps
T288 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3532433833 Aug 09 07:11:15 PM PDT 24 Aug 09 07:11:16 PM PDT 24 117601919 ps
T332 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1879484056 Aug 09 07:11:37 PM PDT 24 Aug 09 07:11:38 PM PDT 24 39071113 ps
T258 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3035298377 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:02 PM PDT 24 101015096 ps
T331 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.948588001 Aug 09 07:11:25 PM PDT 24 Aug 09 07:11:26 PM PDT 24 72894760 ps
T259 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2099174395 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:03 PM PDT 24 99796901 ps
T299 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1922612676 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:17 PM PDT 24 96038493 ps
T260 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2094300630 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:21 PM PDT 24 105497632 ps
T334 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4283081240 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:16 PM PDT 24 43535105 ps
T3635 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1208932469 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:02 PM PDT 24 66704631 ps
T333 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3129696337 Aug 09 07:11:31 PM PDT 24 Aug 09 07:11:37 PM PDT 24 36313996 ps
T300 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1303419611 Aug 09 07:11:39 PM PDT 24 Aug 09 07:11:40 PM PDT 24 99109894 ps
T254 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2984663950 Aug 09 07:11:05 PM PDT 24 Aug 09 07:11:09 PM PDT 24 282976027 ps
T261 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.555643173 Aug 09 07:11:34 PM PDT 24 Aug 09 07:11:37 PM PDT 24 95419129 ps
T3636 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3842905068 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:19 PM PDT 24 45613786 ps
T3637 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.537752604 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:15 PM PDT 24 48425758 ps
T3638 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2756032023 Aug 09 07:11:11 PM PDT 24 Aug 09 07:11:15 PM PDT 24 586617912 ps
T251 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1199666999 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:25 PM PDT 24 1748101031 ps
T275 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1480828577 Aug 09 07:11:15 PM PDT 24 Aug 09 07:11:16 PM PDT 24 101503469 ps
T295 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4107347890 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:58 PM PDT 24 758632260 ps
T276 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3541961339 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:04 PM PDT 24 214905582 ps
T262 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.512184537 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:16 PM PDT 24 170253399 ps
T277 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.578669259 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:05 PM PDT 24 611906111 ps
T3639 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4027502701 Aug 09 07:10:59 PM PDT 24 Aug 09 07:11:00 PM PDT 24 36554485 ps
T255 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.986229593 Aug 09 07:11:00 PM PDT 24 Aug 09 07:11:02 PM PDT 24 80864588 ps
T336 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1548497631 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:04 PM PDT 24 507477209 ps
T3640 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2801501209 Aug 09 07:11:05 PM PDT 24 Aug 09 07:11:06 PM PDT 24 36912059 ps
T3641 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2137904927 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:14 PM PDT 24 77288026 ps
T3642 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2188076210 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:04 PM PDT 24 123546190 ps
T296 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.919071007 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:02 PM PDT 24 121979754 ps
T252 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2107786386 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:16 PM PDT 24 188896380 ps
T278 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1512272064 Aug 09 07:10:53 PM PDT 24 Aug 09 07:11:02 PM PDT 24 1337487246 ps
T3643 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1252717410 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:21 PM PDT 24 125761204 ps
T256 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.408146741 Aug 09 07:11:26 PM PDT 24 Aug 09 07:11:29 PM PDT 24 241260306 ps
T3644 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1179072325 Aug 09 07:11:36 PM PDT 24 Aug 09 07:11:37 PM PDT 24 102192060 ps
T279 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4131042723 Aug 09 07:11:07 PM PDT 24 Aug 09 07:11:08 PM PDT 24 104521249 ps
T3645 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4048196278 Aug 09 07:11:36 PM PDT 24 Aug 09 07:11:37 PM PDT 24 59009814 ps
T3646 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2180006039 Aug 09 07:11:27 PM PDT 24 Aug 09 07:11:29 PM PDT 24 167693065 ps
T3647 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3328812437 Aug 09 07:11:09 PM PDT 24 Aug 09 07:11:10 PM PDT 24 41077093 ps
T3648 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2949407986 Aug 09 07:11:36 PM PDT 24 Aug 09 07:11:37 PM PDT 24 53887262 ps
T3649 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4170384517 Aug 09 07:11:26 PM PDT 24 Aug 09 07:11:27 PM PDT 24 45184929 ps
T253 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3991904592 Aug 09 07:11:17 PM PDT 24 Aug 09 07:11:20 PM PDT 24 83391785 ps
T3650 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.832464582 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:04 PM PDT 24 53650921 ps
T3651 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3467149418 Aug 09 07:11:30 PM PDT 24 Aug 09 07:11:30 PM PDT 24 42701596 ps
T3652 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.654304584 Aug 09 07:11:04 PM PDT 24 Aug 09 07:11:06 PM PDT 24 135106212 ps
T3653 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1373650482 Aug 09 07:11:23 PM PDT 24 Aug 09 07:11:25 PM PDT 24 117757809 ps
T343 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1093886935 Aug 09 07:11:17 PM PDT 24 Aug 09 07:11:20 PM PDT 24 379230653 ps
T3654 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3399653148 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:35 PM PDT 24 62448760 ps
T3655 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2013964707 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:06 PM PDT 24 107913520 ps
T3656 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3899419306 Aug 09 07:11:21 PM PDT 24 Aug 09 07:11:22 PM PDT 24 41192508 ps
T3657 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3800121025 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:19 PM PDT 24 49702314 ps
T3658 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.695504674 Aug 09 07:11:22 PM PDT 24 Aug 09 07:11:24 PM PDT 24 208756460 ps
T3659 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4044340678 Aug 09 07:11:26 PM PDT 24 Aug 09 07:11:27 PM PDT 24 37752344 ps
T3660 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.411477120 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:20 PM PDT 24 41012644 ps
T3661 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4086868876 Aug 09 07:11:25 PM PDT 24 Aug 09 07:11:27 PM PDT 24 65008439 ps
T340 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2565967551 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:20 PM PDT 24 639473173 ps
T3662 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.894167673 Aug 09 07:11:38 PM PDT 24 Aug 09 07:11:40 PM PDT 24 100660698 ps
T3663 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1462636409 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:04 PM PDT 24 171152830 ps
T339 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1676522755 Aug 09 07:11:32 PM PDT 24 Aug 09 07:11:36 PM PDT 24 630794219 ps
T3664 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2990535092 Aug 09 07:11:15 PM PDT 24 Aug 09 07:11:16 PM PDT 24 154289942 ps
T282 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.800800779 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:04 PM PDT 24 221244490 ps
T3665 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3162931139 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:15 PM PDT 24 97156280 ps
T280 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3327833482 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:35 PM PDT 24 143431555 ps
T3666 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2931046663 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:34 PM PDT 24 135059331 ps
T3667 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2233853503 Aug 09 07:11:09 PM PDT 24 Aug 09 07:11:11 PM PDT 24 193931149 ps
T3668 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2891316774 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:56 PM PDT 24 232498781 ps
T3669 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.351493042 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:55 PM PDT 24 56075649 ps
T3670 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3293519192 Aug 09 07:11:23 PM PDT 24 Aug 09 07:11:24 PM PDT 24 48590471 ps
T3671 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3331324535 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:15 PM PDT 24 38433878 ps
T3672 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2788107931 Aug 09 07:11:30 PM PDT 24 Aug 09 07:11:32 PM PDT 24 119319305 ps
T3673 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1326249277 Aug 09 07:11:22 PM PDT 24 Aug 09 07:11:23 PM PDT 24 188315460 ps
T3674 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2492100663 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:03 PM PDT 24 112983757 ps
T3675 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2359712929 Aug 09 07:11:38 PM PDT 24 Aug 09 07:11:39 PM PDT 24 35009257 ps
T3676 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1988008560 Aug 09 07:11:34 PM PDT 24 Aug 09 07:11:35 PM PDT 24 41851491 ps
T3677 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1994197827 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:21 PM PDT 24 329621292 ps
T341 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.177048440 Aug 09 07:11:11 PM PDT 24 Aug 09 07:11:14 PM PDT 24 257004136 ps
T3678 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4288496785 Aug 09 07:11:26 PM PDT 24 Aug 09 07:11:27 PM PDT 24 35517914 ps
T3679 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.621643330 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:57 PM PDT 24 384238774 ps
T3680 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4120414665 Aug 09 07:11:28 PM PDT 24 Aug 09 07:11:29 PM PDT 24 31345676 ps
T342 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4039571871 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:58 PM PDT 24 1567427233 ps
T3681 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.813122166 Aug 09 07:11:10 PM PDT 24 Aug 09 07:11:11 PM PDT 24 54267029 ps
T281 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1379808078 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 69504652 ps
T3682 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2556841928 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:04 PM PDT 24 212771742 ps
T3683 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2950641363 Aug 09 07:11:28 PM PDT 24 Aug 09 07:11:30 PM PDT 24 63552893 ps
T3684 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.363172906 Aug 09 07:11:02 PM PDT 24 Aug 09 07:11:04 PM PDT 24 96600529 ps
T3685 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2723945955 Aug 09 07:11:27 PM PDT 24 Aug 09 07:11:29 PM PDT 24 124992031 ps
T337 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1963191029 Aug 09 07:11:07 PM PDT 24 Aug 09 07:11:14 PM PDT 24 2137469522 ps
T3686 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1507363389 Aug 09 07:10:46 PM PDT 24 Aug 09 07:10:48 PM PDT 24 213403311 ps
T3687 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.198681932 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:05 PM PDT 24 171163513 ps
T3688 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1580640885 Aug 09 07:11:30 PM PDT 24 Aug 09 07:11:32 PM PDT 24 153860207 ps
T3689 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3886206339 Aug 09 07:11:07 PM PDT 24 Aug 09 07:11:08 PM PDT 24 74934390 ps
T3690 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1533039509 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:33 PM PDT 24 43806943 ps
T338 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2584623990 Aug 09 07:11:27 PM PDT 24 Aug 09 07:11:30 PM PDT 24 446705522 ps
T3691 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3637020553 Aug 09 07:11:08 PM PDT 24 Aug 09 07:11:11 PM PDT 24 256806591 ps
T3692 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2018576783 Aug 09 07:11:21 PM PDT 24 Aug 09 07:11:22 PM PDT 24 58214126 ps
T3693 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1886298612 Aug 09 07:11:12 PM PDT 24 Aug 09 07:11:15 PM PDT 24 119671675 ps
T3694 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.163297207 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:16 PM PDT 24 87280089 ps
T3695 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2417477196 Aug 09 07:11:12 PM PDT 24 Aug 09 07:11:14 PM PDT 24 282069749 ps
T3696 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.373939709 Aug 09 07:11:17 PM PDT 24 Aug 09 07:11:18 PM PDT 24 40860723 ps
T3697 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.654876947 Aug 09 07:10:58 PM PDT 24 Aug 09 07:10:59 PM PDT 24 51686769 ps
T3698 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1549791688 Aug 09 07:11:17 PM PDT 24 Aug 09 07:11:18 PM PDT 24 96745740 ps
T3699 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3990515849 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:06 PM PDT 24 345210249 ps
T3700 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2348735825 Aug 09 07:11:29 PM PDT 24 Aug 09 07:11:30 PM PDT 24 83713174 ps
T3701 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.109569355 Aug 09 07:11:11 PM PDT 24 Aug 09 07:11:12 PM PDT 24 144386636 ps
T3702 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1519403094 Aug 09 07:11:26 PM PDT 24 Aug 09 07:11:28 PM PDT 24 162953175 ps
T3703 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1663450672 Aug 09 07:11:20 PM PDT 24 Aug 09 07:11:22 PM PDT 24 80609690 ps
T3704 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2299736446 Aug 09 07:11:07 PM PDT 24 Aug 09 07:11:08 PM PDT 24 59570632 ps
T3705 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1712219681 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:19 PM PDT 24 52942500 ps
T3706 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4102325650 Aug 09 07:11:21 PM PDT 24 Aug 09 07:11:21 PM PDT 24 64286412 ps
T3707 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2223038767 Aug 09 07:11:14 PM PDT 24 Aug 09 07:11:18 PM PDT 24 480685413 ps
T3708 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2352094493 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:34 PM PDT 24 54428299 ps
T3709 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.846482648 Aug 09 07:11:03 PM PDT 24 Aug 09 07:11:04 PM PDT 24 48339296 ps
T3710 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4150439722 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:02 PM PDT 24 71928683 ps
T3711 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2111482532 Aug 09 07:11:06 PM PDT 24 Aug 09 07:11:08 PM PDT 24 296303146 ps
T3712 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.430293293 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 119835977 ps
T3713 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2132103724 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:23 PM PDT 24 496137700 ps
T3714 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2688592642 Aug 09 07:11:32 PM PDT 24 Aug 09 07:11:34 PM PDT 24 84145395 ps
T344 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1589644471 Aug 09 07:11:24 PM PDT 24 Aug 09 07:11:27 PM PDT 24 519651785 ps
T3715 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3541229612 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 57291914 ps
T3716 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3105912891 Aug 09 07:11:35 PM PDT 24 Aug 09 07:11:36 PM PDT 24 58482090 ps
T3717 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.268880304 Aug 09 07:11:29 PM PDT 24 Aug 09 07:11:34 PM PDT 24 741125884 ps
T3718 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2795276585 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:04 PM PDT 24 267910882 ps
T3719 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1723692388 Aug 09 07:11:28 PM PDT 24 Aug 09 07:11:29 PM PDT 24 95960946 ps
T3720 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3756914306 Aug 09 07:11:31 PM PDT 24 Aug 09 07:11:32 PM PDT 24 31835714 ps
T3721 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3108608939 Aug 09 07:11:33 PM PDT 24 Aug 09 07:11:34 PM PDT 24 67521555 ps
T3722 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2339114125 Aug 09 07:11:01 PM PDT 24 Aug 09 07:11:04 PM PDT 24 448865932 ps
T3723 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3112351645 Aug 09 07:11:04 PM PDT 24 Aug 09 07:11:04 PM PDT 24 61113985 ps
T3724 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3845171502 Aug 09 07:11:31 PM PDT 24 Aug 09 07:11:32 PM PDT 24 41307561 ps
T3725 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.987509681 Aug 09 07:11:04 PM PDT 24 Aug 09 07:11:13 PM PDT 24 1477020689 ps
T3726 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.777907782 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 38356122 ps
T3727 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2445239573 Aug 09 07:11:28 PM PDT 24 Aug 09 07:11:29 PM PDT 24 67057623 ps
T3728 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.128031845 Aug 09 07:11:10 PM PDT 24 Aug 09 07:11:11 PM PDT 24 97637314 ps
T3729 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2594043071 Aug 09 07:11:18 PM PDT 24 Aug 09 07:11:21 PM PDT 24 1167970841 ps
T3730 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2240673578 Aug 09 07:11:04 PM PDT 24 Aug 09 07:11:07 PM PDT 24 465809106 ps
T3731 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.521723050 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:20 PM PDT 24 50353478 ps
T3732 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.810423718 Aug 09 07:11:11 PM PDT 24 Aug 09 07:11:12 PM PDT 24 92729995 ps
T3733 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3220401947 Aug 09 07:11:27 PM PDT 24 Aug 09 07:11:29 PM PDT 24 203877953 ps
T3734 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2756287705 Aug 09 07:11:22 PM PDT 24 Aug 09 07:11:23 PM PDT 24 80788749 ps
T3735 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2606871098 Aug 09 07:11:25 PM PDT 24 Aug 09 07:11:26 PM PDT 24 99174963 ps
T3736 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1079776166 Aug 09 07:11:19 PM PDT 24 Aug 09 07:11:20 PM PDT 24 91953774 ps
T3737 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3577502917 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:55 PM PDT 24 211787941 ps
T3738 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1751382338 Aug 09 07:11:07 PM PDT 24 Aug 09 07:11:08 PM PDT 24 289259795 ps
T3739 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3543075949 Aug 09 07:11:11 PM PDT 24 Aug 09 07:11:12 PM PDT 24 59843734 ps
T3740 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3728174211 Aug 09 07:11:16 PM PDT 24 Aug 09 07:11:17 PM PDT 24 50209416 ps

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.197643983
Short name T4
Test name
Test status
Simulation time 7846981627 ps
CPU time 37.36 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 219332 kb
Host smart-7df329f7-d861-44e5-9c3e-78cf03073cf9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197643983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.197643983
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.851639338
Short name T23
Test name
Test status
Simulation time 594611311 ps
CPU time 1.61 seconds
Started Aug 09 05:32:59 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207428 kb
Host smart-f35cc27e-99cc-4f92-9c2a-682d4baeb2b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851639338 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.851639338
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1477904986
Short name T58
Test name
Test status
Simulation time 21918386675 ps
CPU time 36.68 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:28:28 PM PDT 24
Peak memory 207812 kb
Host smart-2d788c49-5f54-4ec7-b45e-bce67cfbb10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14779
04986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1477904986
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.4155729035
Short name T6
Test name
Test status
Simulation time 11436812627 ps
CPU time 14.25 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:19 PM PDT 24
Peak memory 207652 kb
Host smart-35b61f06-e730-4e8f-9646-26a551990a84
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155729035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.4155729035
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2757498156
Short name T211
Test name
Test status
Simulation time 53022846 ps
CPU time 0.73 seconds
Started Aug 09 07:11:13 PM PDT 24
Finished Aug 09 07:11:14 PM PDT 24
Peak memory 206640 kb
Host smart-546ada29-97ab-4077-b1a1-64e665bee749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2757498156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2757498156
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2828428176
Short name T237
Test name
Test status
Simulation time 100094139 ps
CPU time 1.2 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:35 PM PDT 24
Peak memory 214988 kb
Host smart-5859abb6-806c-4d25-914c-0702e934cf1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828428176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2828428176
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2187255658
Short name T1
Test name
Test status
Simulation time 3533759753 ps
CPU time 25.01 seconds
Started Aug 09 05:26:05 PM PDT 24
Finished Aug 09 05:26:30 PM PDT 24
Peak memory 216084 kb
Host smart-f4ea9806-bd0c-472a-aa8c-3a71c3fa532f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2187255658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2187255658
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2441179066
Short name T91
Test name
Test status
Simulation time 25437428851 ps
CPU time 37.35 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 215944 kb
Host smart-e1ab5e38-f44a-429a-af7a-863e40215485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
79066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2441179066
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.1979162521
Short name T109
Test name
Test status
Simulation time 469325750 ps
CPU time 1.47 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207480 kb
Host smart-c364195b-8229-4019-a18b-71ab5c1f174c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979162521 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.1979162521
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2673175809
Short name T103
Test name
Test status
Simulation time 1208286788 ps
CPU time 3 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207624 kb
Host smart-a6127036-7a9a-4c11-b63e-feddb084eebd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2673175809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2673175809
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.179072247
Short name T190
Test name
Test status
Simulation time 304773329 ps
CPU time 1.17 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:28 PM PDT 24
Peak memory 207492 kb
Host smart-607ede67-cdc7-4e0c-8b06-134dfe5237d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
2247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.179072247
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3997991732
Short name T63
Test name
Test status
Simulation time 31999740531 ps
CPU time 49.6 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 207888 kb
Host smart-710c6a99-9c8e-42dc-9de0-580fc13ae45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
91732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3997991732
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3502398653
Short name T33
Test name
Test status
Simulation time 48602268 ps
CPU time 0.71 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207472 kb
Host smart-f7d31958-2933-4887-89ed-2b31c3005d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
98653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3502398653
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3317367370
Short name T210
Test name
Test status
Simulation time 55442746 ps
CPU time 0.75 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206568 kb
Host smart-6181bdec-4d80-46bf-a36c-6a1765e56c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3317367370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3317367370
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4107347890
Short name T295
Test name
Test status
Simulation time 758632260 ps
CPU time 5.11 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 206964 kb
Host smart-41bc72af-91c5-4476-a217-80dfc70ca827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4107347890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4107347890
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2390702869
Short name T241
Test name
Test status
Simulation time 21356614376 ps
CPU time 25.92 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 207808 kb
Host smart-d9b4513e-8266-4334-9e7b-e2a229bbd19b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390702869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2390702869
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.155849142
Short name T110
Test name
Test status
Simulation time 613410768 ps
CPU time 1.65 seconds
Started Aug 09 05:31:19 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 207548 kb
Host smart-50a45cfa-c783-4b2b-bce7-910b9aecc0bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155849142 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.155849142
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3329795779
Short name T215
Test name
Test status
Simulation time 734448133 ps
CPU time 1.64 seconds
Started Aug 09 05:25:34 PM PDT 24
Finished Aug 09 05:25:36 PM PDT 24
Peak memory 224396 kb
Host smart-ddd188f3-5d2d-475c-a719-4fd006d7e2fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3329795779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3329795779
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1128260607
Short name T2823
Test name
Test status
Simulation time 13403715484 ps
CPU time 15.38 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:40 PM PDT 24
Peak memory 215948 kb
Host smart-e95b4094-e25a-4a4f-96ba-95c17bb3f818
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128260607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1128260607
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.304096227
Short name T195
Test name
Test status
Simulation time 461553979 ps
CPU time 1.48 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207504 kb
Host smart-f65750f3-b825-40aa-b8f5-f3821ab245d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304096227 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.304096227
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.2971793579
Short name T236
Test name
Test status
Simulation time 598358363 ps
CPU time 1.71 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207556 kb
Host smart-fd23c206-1cd3-4d2e-bcd5-8f596b4eddb5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971793579 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.2971793579
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1300836495
Short name T857
Test name
Test status
Simulation time 42149364 ps
CPU time 0.7 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207456 kb
Host smart-ad6ca2b2-e879-48b3-8352-e03aebdb9248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1300836495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1300836495
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2685385730
Short name T93
Test name
Test status
Simulation time 44434429128 ps
CPU time 71.33 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207764 kb
Host smart-8a5e0733-5e5a-4f70-9690-d50cc3c35cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26853
85730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2685385730
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.198408173
Short name T273
Test name
Test status
Simulation time 132469798 ps
CPU time 1.05 seconds
Started Aug 09 07:11:30 PM PDT 24
Finished Aug 09 07:11:31 PM PDT 24
Peak memory 206684 kb
Host smart-01dfed5f-599d-4940-bb55-da2ca14487e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=198408173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.198408173
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.1382428744
Short name T45
Test name
Test status
Simulation time 250944803 ps
CPU time 1.19 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207464 kb
Host smart-00eb4bcc-b8e8-4781-a6ec-e2867b9bb6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13824
28744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1382428744
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3375706690
Short name T59
Test name
Test status
Simulation time 4989026052 ps
CPU time 50.01 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:55 PM PDT 24
Peak memory 217528 kb
Host smart-7a4ffcbb-ed2d-4a1f-8857-de098f89ef33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3375706690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3375706690
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.2820801752
Short name T382
Test name
Test status
Simulation time 676837096 ps
CPU time 1.71 seconds
Started Aug 09 05:33:22 PM PDT 24
Finished Aug 09 05:33:23 PM PDT 24
Peak memory 207452 kb
Host smart-19d1b43c-d5c7-400f-b2f8-08ae79c88a39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2820801752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.2820801752
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.3445815118
Short name T361
Test name
Test status
Simulation time 507909959 ps
CPU time 1.49 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207472 kb
Host smart-9c1f036d-b310-4117-8590-1c32fe3f2c84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3445815118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.3445815118
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2828411814
Short name T238
Test name
Test status
Simulation time 67129147 ps
CPU time 1.82 seconds
Started Aug 09 07:11:17 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 222896 kb
Host smart-f81de093-2675-4551-acd1-e5e87a644c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2828411814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2828411814
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.2893462476
Short name T410
Test name
Test status
Simulation time 833733929 ps
CPU time 1.98 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207512 kb
Host smart-b92bc97c-dab5-4710-b253-478617af2259
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2893462476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.2893462476
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.672426396
Short name T395
Test name
Test status
Simulation time 530943109 ps
CPU time 1.5 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207516 kb
Host smart-d7441a7b-bf04-42b8-a050-99c635b759ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=672426396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.672426396
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4027502701
Short name T3639
Test name
Test status
Simulation time 36554485 ps
CPU time 0.72 seconds
Started Aug 09 07:10:59 PM PDT 24
Finished Aug 09 07:11:00 PM PDT 24
Peak memory 206596 kb
Host smart-8b2350e2-ced8-432c-91a8-cc6e66f8085e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4027502701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4027502701
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.496865797
Short name T37
Test name
Test status
Simulation time 135522629 ps
CPU time 0.79 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207472 kb
Host smart-6d5d32fa-7286-4963-ad64-c5b2398d01ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49686
5797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.496865797
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_device_address.563340439
Short name T352
Test name
Test status
Simulation time 40095917101 ps
CPU time 70.51 seconds
Started Aug 09 05:26:51 PM PDT 24
Finished Aug 09 05:28:02 PM PDT 24
Peak memory 207820 kb
Host smart-f7e98d30-05ba-4946-9362-9873408efee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56334
0439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.563340439
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.284047459
Short name T70
Test name
Test status
Simulation time 204916510 ps
CPU time 0.92 seconds
Started Aug 09 05:25:46 PM PDT 24
Finished Aug 09 05:25:47 PM PDT 24
Peak memory 207472 kb
Host smart-ee3e68ad-7479-40ab-958f-4be329531337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.284047459
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.37645826
Short name T827
Test name
Test status
Simulation time 161015831 ps
CPU time 0.82 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207348 kb
Host smart-468ad75a-fe7f-4093-bbe9-037790677a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.37645826
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.3577517396
Short name T357
Test name
Test status
Simulation time 417962583 ps
CPU time 1.34 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207520 kb
Host smart-70c34c16-eb21-4efc-ac2f-d5df4cf10815
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3577517396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.3577517396
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.127444962
Short name T377
Test name
Test status
Simulation time 592934354 ps
CPU time 1.61 seconds
Started Aug 09 05:33:07 PM PDT 24
Finished Aug 09 05:33:09 PM PDT 24
Peak memory 207500 kb
Host smart-3e844d25-0e41-4a42-9c68-11838cc14c9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=127444962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.127444962
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.2475628866
Short name T485
Test name
Test status
Simulation time 647442026 ps
CPU time 1.6 seconds
Started Aug 09 05:33:25 PM PDT 24
Finished Aug 09 05:33:27 PM PDT 24
Peak memory 207520 kb
Host smart-12d0181e-528f-4546-b8fd-4f60e56c270e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2475628866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.2475628866
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.2180108351
Short name T364
Test name
Test status
Simulation time 711842533 ps
CPU time 1.77 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207416 kb
Host smart-e67c0ac8-120d-4ab9-8bb8-67a543dcc2ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2180108351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.2180108351
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2121399154
Short name T324
Test name
Test status
Simulation time 5695504760 ps
CPU time 54.76 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 219720 kb
Host smart-ec1a5383-b005-4e5d-8286-c09291b7c61c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2121399154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2121399154
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.3614318767
Short name T416
Test name
Test status
Simulation time 519223609 ps
CPU time 1.38 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207436 kb
Host smart-de3b0622-bf34-4ba3-bc29-94c003659005
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3614318767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3614318767
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.320138473
Short name T413
Test name
Test status
Simulation time 512581497 ps
CPU time 1.42 seconds
Started Aug 09 05:33:06 PM PDT 24
Finished Aug 09 05:33:08 PM PDT 24
Peak memory 207464 kb
Host smart-8945cf16-bdb5-4d8c-8e9e-d9f53c7c74e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=320138473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.320138473
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.1803635118
Short name T375
Test name
Test status
Simulation time 431116929 ps
CPU time 1.29 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 207348 kb
Host smart-4ff59159-b9f6-41ee-9392-45e1462f2bdd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1803635118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.1803635118
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.3803922495
Short name T480
Test name
Test status
Simulation time 607871993 ps
CPU time 1.5 seconds
Started Aug 09 05:32:55 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207344 kb
Host smart-72f96c3a-f0a9-47b7-95e3-89811652e87b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3803922495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.3803922495
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3558399825
Short name T2475
Test name
Test status
Simulation time 477497450 ps
CPU time 1.53 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:25:34 PM PDT 24
Peak memory 207504 kb
Host smart-ca135cef-0e45-41d4-b82b-c38de3414120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
99825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3558399825
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2163926616
Short name T62
Test name
Test status
Simulation time 11459762588 ps
CPU time 77.12 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:28:31 PM PDT 24
Peak memory 224212 kb
Host smart-6b6f29ae-0014-4641-82ba-019cdab48990
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2163926616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2163926616
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1963191029
Short name T337
Test name
Test status
Simulation time 2137469522 ps
CPU time 6.17 seconds
Started Aug 09 07:11:07 PM PDT 24
Finished Aug 09 07:11:14 PM PDT 24
Peak memory 206932 kb
Host smart-f06c15d6-475a-498d-9b84-cf8ed0672091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1963191029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1963191029
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.213526674
Short name T431
Test name
Test status
Simulation time 707929936 ps
CPU time 1.7 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207464 kb
Host smart-a0d85adb-df5c-40d0-ad68-da49f233a4f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=213526674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.213526674
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.2798246668
Short name T3593
Test name
Test status
Simulation time 519795869 ps
CPU time 1.5 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207556 kb
Host smart-7d994e10-60d7-4693-8c2c-8ee7d7f511a2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2798246668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2798246668
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.1429156592
Short name T400
Test name
Test status
Simulation time 484765662 ps
CPU time 1.28 seconds
Started Aug 09 05:33:06 PM PDT 24
Finished Aug 09 05:33:08 PM PDT 24
Peak memory 207468 kb
Host smart-4ebd9a0b-d3c6-4453-b83c-55224f8e42af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1429156592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.1429156592
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2192679934
Short name T1764
Test name
Test status
Simulation time 1055761883 ps
CPU time 3 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207588 kb
Host smart-996a6c0a-c95a-4f23-9d34-d1a4dcaab199
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2192679934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2192679934
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.1379538672
Short name T478
Test name
Test status
Simulation time 481362185 ps
CPU time 1.34 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207456 kb
Host smart-a97368f6-9b4e-4f0c-83bc-099a32f88470
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1379538672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.1379538672
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.3026201112
Short name T231
Test name
Test status
Simulation time 491354335 ps
CPU time 1.52 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207564 kb
Host smart-665daadf-2896-4af9-813a-b2d10eb6b053
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026201112 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.3026201112
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.611003150
Short name T86
Test name
Test status
Simulation time 13842204000 ps
CPU time 94.05 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:30:53 PM PDT 24
Peak memory 207784 kb
Host smart-0ff1fb27-506c-4213-bdb3-1c41d8b76ee2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=611003150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.611003150
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.2762084574
Short name T389
Test name
Test status
Simulation time 587988724 ps
CPU time 1.52 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207520 kb
Host smart-6d887c2c-4d2c-4cb0-8506-7cdb94033a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2762084574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.2762084574
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.2094581527
Short name T391
Test name
Test status
Simulation time 573235531 ps
CPU time 1.56 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207468 kb
Host smart-f0d6bcda-9b81-41a7-885c-e15395f94893
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2094581527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.2094581527
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2002714026
Short name T515
Test name
Test status
Simulation time 256405602 ps
CPU time 1.07 seconds
Started Aug 09 05:27:53 PM PDT 24
Finished Aug 09 05:27:54 PM PDT 24
Peak memory 207360 kb
Host smart-a03998cf-2d22-4f3f-8e02-6f6953dd0b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
14026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2002714026
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.1939456025
Short name T396
Test name
Test status
Simulation time 619257406 ps
CPU time 1.49 seconds
Started Aug 09 05:33:35 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207560 kb
Host smart-384755b0-ed63-42b7-8747-24f5794ca94d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1939456025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.1939456025
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.3528379259
Short name T366
Test name
Test status
Simulation time 544731840 ps
CPU time 1.49 seconds
Started Aug 09 05:28:02 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207396 kb
Host smart-b39e756d-ab5c-4b69-b5cc-fba1b7a5f984
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3528379259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.3528379259
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3258617453
Short name T1787
Test name
Test status
Simulation time 47824972149 ps
CPU time 80.67 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:29:25 PM PDT 24
Peak memory 207776 kb
Host smart-e39ae286-9b2b-4b32-9740-13eecdecd29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586
17453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3258617453
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.2502256479
Short name T423
Test name
Test status
Simulation time 418706431 ps
CPU time 1.35 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207556 kb
Host smart-3552fb5b-e99e-480c-91c9-6d98a8ebe029
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2502256479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.2502256479
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1656478172
Short name T134
Test name
Test status
Simulation time 238124629 ps
CPU time 0.98 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207788 kb
Host smart-06657a7c-1042-4f15-be69-111feb5d6143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16564
78172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1656478172
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2339015656
Short name T56
Test name
Test status
Simulation time 144975984 ps
CPU time 0.81 seconds
Started Aug 09 05:25:23 PM PDT 24
Finished Aug 09 05:25:24 PM PDT 24
Peak memory 207492 kb
Host smart-b4db298c-3db5-4d92-92ac-11f8a250ac8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
15656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2339015656
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1548497631
Short name T336
Test name
Test status
Simulation time 507477209 ps
CPU time 2.58 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206912 kb
Host smart-4421d944-f481-4bae-99eb-f3848b0dbe4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1548497631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1548497631
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3129696337
Short name T333
Test name
Test status
Simulation time 36313996 ps
CPU time 0.69 seconds
Started Aug 09 07:11:31 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 206592 kb
Host smart-c0cb42f2-2d6a-4529-aeac-712e89c82c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3129696337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3129696337
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2659031476
Short name T508
Test name
Test status
Simulation time 5171988374 ps
CPU time 49.49 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:26:16 PM PDT 24
Peak memory 207708 kb
Host smart-7a716eea-dc15-456a-a23d-c71a8fe13365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
31476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2659031476
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.3190441223
Short name T387
Test name
Test status
Simulation time 380787759 ps
CPU time 1.2 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207472 kb
Host smart-4a89bc21-3a93-45f4-bad7-587693d74c96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3190441223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.3190441223
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.4202713871
Short name T3018
Test name
Test status
Simulation time 421092359 ps
CPU time 1.37 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207384 kb
Host smart-aa141040-63ab-4c4f-8328-0a95b76f6812
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4202713871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.4202713871
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.597064688
Short name T224
Test name
Test status
Simulation time 444351707 ps
CPU time 1.28 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207488 kb
Host smart-9882d330-4786-450b-9e31-e64bedb844bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=597064688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.597064688
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.2315587720
Short name T383
Test name
Test status
Simulation time 489392457 ps
CPU time 1.41 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207436 kb
Host smart-5381ecae-27e3-4125-939f-b9f4701f449a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2315587720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.2315587720
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.310125406
Short name T408
Test name
Test status
Simulation time 532040412 ps
CPU time 1.7 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:12 PM PDT 24
Peak memory 207468 kb
Host smart-7333d095-0d28-456d-a62e-d6bb6529cc9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=310125406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.310125406
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.3907224122
Short name T17
Test name
Test status
Simulation time 460754688 ps
CPU time 1.34 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207448 kb
Host smart-967008b4-3268-4f24-8556-41697d9ae9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072
24122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.3907224122
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1369098671
Short name T318
Test name
Test status
Simulation time 1012224821 ps
CPU time 2.57 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:29:54 PM PDT 24
Peak memory 207708 kb
Host smart-810b0e39-3496-494e-9835-d708231a92fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1369098671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1369098671
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1981963016
Short name T505
Test name
Test status
Simulation time 109198001642 ps
CPU time 180.99 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:29:14 PM PDT 24
Peak memory 207792 kb
Host smart-9277f0b3-d8d6-4f66-9253-76237906c406
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1981963016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1981963016
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.747362159
Short name T80
Test name
Test status
Simulation time 8689940573 ps
CPU time 56.51 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 224152 kb
Host smart-17a1f93b-01d6-47d3-bbdd-83541e0d8507
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747362159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.747362159
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.3285988962
Short name T151
Test name
Test status
Simulation time 523351669 ps
CPU time 1.71 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207560 kb
Host smart-4b179b99-9951-4e6e-9713-a1b37ed05fb5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285988962 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.3285988962
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3991904592
Short name T253
Test name
Test status
Simulation time 83391785 ps
CPU time 2.09 seconds
Started Aug 09 07:11:17 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206964 kb
Host smart-38d8bf2a-7dce-4713-9453-0990f80bcd8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3991904592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3991904592
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.177048440
Short name T341
Test name
Test status
Simulation time 257004136 ps
CPU time 2.48 seconds
Started Aug 09 07:11:11 PM PDT 24
Finished Aug 09 07:11:14 PM PDT 24
Peak memory 206952 kb
Host smart-722925c7-9c9e-4e8e-86af-d85ee847eff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=177048440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.177048440
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1120609380
Short name T985
Test name
Test status
Simulation time 191301704 ps
CPU time 0.89 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:25:52 PM PDT 24
Peak memory 207504 kb
Host smart-5255a3fd-e7b0-4c7f-a95e-8ce259c5f1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
09380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1120609380
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.874940300
Short name T374
Test name
Test status
Simulation time 388351644 ps
CPU time 1.26 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207468 kb
Host smart-abeacedf-9c45-4c3a-8692-35fa7045d2cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=874940300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.874940300
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.2001540262
Short name T441
Test name
Test status
Simulation time 469300228 ps
CPU time 1.32 seconds
Started Aug 09 05:33:09 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 207428 kb
Host smart-822435d3-07c8-405b-99eb-ce953a3af9fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2001540262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.2001540262
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.814364432
Short name T419
Test name
Test status
Simulation time 781934826 ps
CPU time 1.84 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207368 kb
Host smart-bba1ede2-6572-46ed-92d1-38139cd66afb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=814364432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.814364432
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.3657770488
Short name T399
Test name
Test status
Simulation time 644973681 ps
CPU time 1.56 seconds
Started Aug 09 05:33:07 PM PDT 24
Finished Aug 09 05:33:08 PM PDT 24
Peak memory 207344 kb
Host smart-92b1457a-842e-49bc-94e3-2235a7e37411
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3657770488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.3657770488
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.474562263
Short name T438
Test name
Test status
Simulation time 272214671 ps
CPU time 1.09 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207460 kb
Host smart-8b5d2d4b-c622-49cc-9e8f-59955268d4ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=474562263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.474562263
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3326840755
Short name T355
Test name
Test status
Simulation time 29315898626 ps
CPU time 51.67 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:28:25 PM PDT 24
Peak memory 207720 kb
Host smart-56371c06-7547-4b23-aaa8-441963f3c70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
40755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3326840755
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.1850651946
Short name T437
Test name
Test status
Simulation time 427592401 ps
CPU time 1.24 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207520 kb
Host smart-5a7b95eb-cee7-47b7-87ec-890b081fd1ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1850651946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.1850651946
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.3876750329
Short name T434
Test name
Test status
Simulation time 568332454 ps
CPU time 1.6 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207516 kb
Host smart-645cfe46-021b-4fab-9b72-8afb9ed0ee8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3876750329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.3876750329
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.2572359597
Short name T3057
Test name
Test status
Simulation time 413120037 ps
CPU time 1.41 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207472 kb
Host smart-703ef5e2-8cea-48ba-800a-bda400b9e40f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2572359597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.2572359597
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.2086107427
Short name T365
Test name
Test status
Simulation time 420456013 ps
CPU time 1.28 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207532 kb
Host smart-e98fff86-dd68-4913-90ad-7b22767dc3ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2086107427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.2086107427
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.930332409
Short name T290
Test name
Test status
Simulation time 8916455769 ps
CPU time 24.75 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 215972 kb
Host smart-8327e1a3-69d3-4298-a15b-7234413e35a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93033
2409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.930332409
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.430346193
Short name T2940
Test name
Test status
Simulation time 250439607 ps
CPU time 1.12 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207504 kb
Host smart-db6d0d78-6bf2-412d-90e4-293e6b6b44e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43034
6193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.430346193
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.2214538278
Short name T402
Test name
Test status
Simulation time 456179381 ps
CPU time 1.39 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207484 kb
Host smart-3bc490ce-cdab-42ff-9e01-27af8287bbc6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2214538278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.2214538278
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.755332751
Short name T451
Test name
Test status
Simulation time 313032509 ps
CPU time 1.04 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207344 kb
Host smart-30beb31c-4128-405a-bd1b-1e8cf1211833
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=755332751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.755332751
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.845206858
Short name T381
Test name
Test status
Simulation time 390249438 ps
CPU time 1.4 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 207392 kb
Host smart-a36a4c4b-d5ba-4bcb-b353-f4b4740f37c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=845206858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.845206858
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.1023110048
Short name T372
Test name
Test status
Simulation time 300412465 ps
CPU time 1.18 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207368 kb
Host smart-9ccedc6a-239b-48df-b1d5-526dbba374c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1023110048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1023110048
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3938712886
Short name T949
Test name
Test status
Simulation time 192969492 ps
CPU time 0.92 seconds
Started Aug 09 05:28:44 PM PDT 24
Finished Aug 09 05:28:45 PM PDT 24
Peak memory 207344 kb
Host smart-710aa7d2-4493-4bd6-beec-553ab5927e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
12886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3938712886
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2703048373
Short name T39
Test name
Test status
Simulation time 10307080166 ps
CPU time 16.06 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:58 PM PDT 24
Peak memory 207848 kb
Host smart-d3019ba7-ecc6-4f57-8d45-a12bbcd4816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
48373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2703048373
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3691155394
Short name T863
Test name
Test status
Simulation time 48701495 ps
CPU time 0.75 seconds
Started Aug 09 05:28:37 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207472 kb
Host smart-b75170be-ec29-4062-8ce2-c1fd2039cf4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
55394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3691155394
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.580679586
Short name T42
Test name
Test status
Simulation time 233233791 ps
CPU time 0.98 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:25:30 PM PDT 24
Peak memory 207528 kb
Host smart-23a2d66d-1d85-4cc5-b262-e4ca4798ce43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58067
9586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.580679586
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3703221137
Short name T60
Test name
Test status
Simulation time 4165613805 ps
CPU time 9.8 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:35 PM PDT 24
Peak memory 207872 kb
Host smart-321b164f-00ff-43b4-945c-6d97e95ad4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
21137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3703221137
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3167896950
Short name T68
Test name
Test status
Simulation time 475602089 ps
CPU time 1.52 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:25:29 PM PDT 24
Peak memory 207384 kb
Host smart-21d6d187-3fe6-4e15-bd3a-6a63b4849189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
96950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3167896950
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.747402819
Short name T61
Test name
Test status
Simulation time 207085834 ps
CPU time 0.89 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:27 PM PDT 24
Peak memory 207468 kb
Host smart-1eec905a-6a3a-41ca-83d8-75c123177256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74740
2819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.747402819
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2740477738
Short name T74
Test name
Test status
Simulation time 155750519 ps
CPU time 0.9 seconds
Started Aug 09 05:25:31 PM PDT 24
Finished Aug 09 05:25:32 PM PDT 24
Peak memory 207436 kb
Host smart-5225605e-4fd2-4992-aa8b-d873e3f4d53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27404
77738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2740477738
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.284894311
Short name T51
Test name
Test status
Simulation time 160060223 ps
CPU time 0.92 seconds
Started Aug 09 05:26:24 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 207556 kb
Host smart-3078efee-f6ab-45b9-8690-f95407f2db89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28489
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.284894311
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.351781576
Short name T197
Test name
Test status
Simulation time 197044176 ps
CPU time 2.29 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:27 PM PDT 24
Peak memory 207652 kb
Host smart-c2871a91-3b66-42a5-8ebc-edc610e93e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35178
1576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.351781576
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2030641448
Short name T1714
Test name
Test status
Simulation time 219056383 ps
CPU time 0.96 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207508 kb
Host smart-3bc8060c-fbb4-47f4-97ca-ed364730d918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
41448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2030641448
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2420680028
Short name T172
Test name
Test status
Simulation time 2527638283 ps
CPU time 24.94 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 216068 kb
Host smart-96e155dc-5731-4917-8e51-a4679ee359cb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2420680028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2420680028
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.4038596693
Short name T79
Test name
Test status
Simulation time 7053698934 ps
CPU time 105.89 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 216048 kb
Host smart-15449906-6405-4122-92ae-625f371f9162
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038596693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.4038596693
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3837769210
Short name T2293
Test name
Test status
Simulation time 225227482 ps
CPU time 1.01 seconds
Started Aug 09 05:27:23 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 207504 kb
Host smart-d65beac3-1c7c-4bd8-8023-ec71741ab97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377
69210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3837769210
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3295461318
Short name T129
Test name
Test status
Simulation time 206686788 ps
CPU time 0.95 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 207432 kb
Host smart-3a6ab129-75a3-49b6-8289-715d869d4796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954
61318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3295461318
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3144660976
Short name T124
Test name
Test status
Simulation time 177756026 ps
CPU time 0.9 seconds
Started Aug 09 05:27:51 PM PDT 24
Finished Aug 09 05:27:52 PM PDT 24
Peak memory 207548 kb
Host smart-62841739-6eef-4a49-8186-ef8bbbaf5344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31446
60976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3144660976
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3009744860
Short name T137
Test name
Test status
Simulation time 213012738 ps
CPU time 0.93 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207528 kb
Host smart-bf9638f5-c270-463d-85c1-2fd43c841750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30097
44860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3009744860
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3772496699
Short name T127
Test name
Test status
Simulation time 223596728 ps
CPU time 1 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207508 kb
Host smart-9e042345-5d7f-4a8d-9cfb-852147737355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
96699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3772496699
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1713951770
Short name T147
Test name
Test status
Simulation time 189360951 ps
CPU time 0.96 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:46 PM PDT 24
Peak memory 207540 kb
Host smart-cdc3c84b-f2f7-4689-9dfe-c476a9418e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
51770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1713951770
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2767711418
Short name T2460
Test name
Test status
Simulation time 254916363 ps
CPU time 1.09 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207500 kb
Host smart-22fce284-cc6a-46dc-aebb-afed72a2ffe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
11418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2767711418
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3771453020
Short name T10
Test name
Test status
Simulation time 10129844015 ps
CPU time 14.47 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207832 kb
Host smart-d93ae6a9-d6e9-4f64-8fc5-2ea2476f7c7f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771453020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.3771453020
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2591043440
Short name T143
Test name
Test status
Simulation time 186281249 ps
CPU time 0.92 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:29:18 PM PDT 24
Peak memory 207504 kb
Host smart-dfa14a00-27da-4fcf-bc42-9b07048bcda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25910
43440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2591043440
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.2757999388
Short name T107
Test name
Test status
Simulation time 701543446 ps
CPU time 2.04 seconds
Started Aug 09 05:33:32 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207428 kb
Host smart-8a7d53c0-2ec7-4a09-bddd-252dc953c5e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757999388 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.2757999388
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1436461919
Short name T145
Test name
Test status
Simulation time 195205837 ps
CPU time 0.94 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207528 kb
Host smart-487477e5-c3bc-44cb-a99e-4875d85b5e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14364
61919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1436461919
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4257526815
Short name T133
Test name
Test status
Simulation time 199827390 ps
CPU time 0.99 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207476 kb
Host smart-574735ec-c782-4a02-8db6-0f3c91c3fb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
26815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4257526815
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1507363389
Short name T3686
Test name
Test status
Simulation time 213403311 ps
CPU time 2.33 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 206920 kb
Host smart-653a2efa-345a-46bd-9f16-bd47f71fd767
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1507363389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1507363389
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1512272064
Short name T278
Test name
Test status
Simulation time 1337487246 ps
CPU time 8.21 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 206912 kb
Host smart-d56c405c-0ce0-4412-a0c7-770452d3b33e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1512272064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1512272064
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3481263082
Short name T208
Test name
Test status
Simulation time 94844975 ps
CPU time 0.94 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 206588 kb
Host smart-46e59ab8-cd3a-43d0-a18a-26b2ff5b9d85
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3481263082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3481263082
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.430293293
Short name T3712
Test name
Test status
Simulation time 119835977 ps
CPU time 1.36 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 215144 kb
Host smart-0793d934-d0c1-4ac7-a4ff-3b9d3303eca7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430293293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.430293293
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.409504735
Short name T239
Test name
Test status
Simulation time 120573301 ps
CPU time 1 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 206632 kb
Host smart-e98c14d6-897d-453a-842d-898b38eb90b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=409504735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.409504735
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.777907782
Short name T3726
Test name
Test status
Simulation time 38356122 ps
CPU time 0.75 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 206580 kb
Host smart-a2412019-a71c-4839-951a-557072bf7fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777907782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.777907782
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2071193770
Short name T272
Test name
Test status
Simulation time 115731540 ps
CPU time 1.47 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 215056 kb
Host smart-2c31c05b-2abc-4dfc-9304-22ad136d8809
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2071193770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2071193770
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1257583333
Short name T3633
Test name
Test status
Simulation time 711127938 ps
CPU time 5.06 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 206752 kb
Host smart-6d07be90-7ae6-42a4-8aad-1b09a09508c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1257583333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1257583333
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3541229612
Short name T3715
Test name
Test status
Simulation time 57291914 ps
CPU time 1.09 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 206856 kb
Host smart-049504ba-c591-4ed7-abea-c7f52e4b57a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3541229612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3541229612
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3577502917
Short name T3737
Test name
Test status
Simulation time 211787941 ps
CPU time 2.43 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 220280 kb
Host smart-4a2fa6e2-5c7b-483c-bd06-cca8be9c230b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3577502917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3577502917
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4039571871
Short name T342
Test name
Test status
Simulation time 1567427233 ps
CPU time 6.23 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 206868 kb
Host smart-24098c9d-1c5a-4bb9-9a82-f00c2a1bf0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4039571871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4039571871
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.800800779
Short name T282
Test name
Test status
Simulation time 221244490 ps
CPU time 2.22 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 207016 kb
Host smart-5d5dd81d-5b43-494d-97fe-3c99b5568793
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=800800779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.800800779
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.578669259
Short name T277
Test name
Test status
Simulation time 611906111 ps
CPU time 4.52 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:05 PM PDT 24
Peak memory 206932 kb
Host smart-d3bdc6fd-a7ef-4ba7-801f-08b046cfab1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=578669259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.578669259
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1480828577
Short name T275
Test name
Test status
Simulation time 101503469 ps
CPU time 0.85 seconds
Started Aug 09 07:11:15 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206724 kb
Host smart-f06f97b4-f5bc-4a05-ae3c-a20882c25926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1480828577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1480828577
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2492100663
Short name T3674
Test name
Test status
Simulation time 112983757 ps
CPU time 1.18 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:03 PM PDT 24
Peak memory 214960 kb
Host smart-997afce3-add1-4b20-befa-c9c610cc9a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492100663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2492100663
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.654876947
Short name T3697
Test name
Test status
Simulation time 51686769 ps
CPU time 0.83 seconds
Started Aug 09 07:10:58 PM PDT 24
Finished Aug 09 07:10:59 PM PDT 24
Peak memory 206628 kb
Host smart-efd15c98-1ce4-45c4-afca-f1606238d342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=654876947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.654876947
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.351493042
Short name T3669
Test name
Test status
Simulation time 56075649 ps
CPU time 0.72 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 206568 kb
Host smart-3e2a2311-9b1f-4d42-a421-de6467c43f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=351493042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.351493042
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1379808078
Short name T281
Test name
Test status
Simulation time 69504652 ps
CPU time 1.4 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 215048 kb
Host smart-3a235d89-0864-45ea-8937-2ce16f49b5d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1379808078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1379808078
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.621643330
Short name T3679
Test name
Test status
Simulation time 384238774 ps
CPU time 2.83 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 206772 kb
Host smart-014987b6-8176-43ca-86d4-cc5f1e256446
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=621643330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.621643330
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.810423718
Short name T3732
Test name
Test status
Simulation time 92729995 ps
CPU time 1.12 seconds
Started Aug 09 07:11:11 PM PDT 24
Finished Aug 09 07:11:12 PM PDT 24
Peak memory 206884 kb
Host smart-29ac89bc-9c7a-495b-945a-bbbf545e7f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=810423718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.810423718
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2891316774
Short name T3668
Test name
Test status
Simulation time 232498781 ps
CPU time 2.75 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 219800 kb
Host smart-dcc7b7c6-0302-4e79-b2d3-6f8ad5cf25a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2891316774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2891316774
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.813122166
Short name T3681
Test name
Test status
Simulation time 54267029 ps
CPU time 0.89 seconds
Started Aug 09 07:11:10 PM PDT 24
Finished Aug 09 07:11:11 PM PDT 24
Peak memory 206716 kb
Host smart-dc7f25ff-9f8d-4cf8-abe2-1aca5e190cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=813122166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.813122166
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.695504674
Short name T3658
Test name
Test status
Simulation time 208756460 ps
CPU time 1.7 seconds
Started Aug 09 07:11:22 PM PDT 24
Finished Aug 09 07:11:24 PM PDT 24
Peak memory 206988 kb
Host smart-f28adbad-8e68-4b76-86a1-45fd9a731969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695504674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.695504674
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2107786386
Short name T252
Test name
Test status
Simulation time 188896380 ps
CPU time 2.14 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206932 kb
Host smart-d7354e5b-6483-4c66-955d-1175c287ae3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2107786386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2107786386
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1199666999
Short name T251
Test name
Test status
Simulation time 1748101031 ps
CPU time 6.36 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:25 PM PDT 24
Peak memory 206960 kb
Host smart-b662b6c2-59a5-4b89-a68f-e3760678e9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1199666999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1199666999
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2180006039
Short name T3646
Test name
Test status
Simulation time 167693065 ps
CPU time 1.93 seconds
Started Aug 09 07:11:27 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 215232 kb
Host smart-ac340eb6-2cd6-4b52-81a4-516e78428c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180006039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2180006039
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3543075949
Short name T3739
Test name
Test status
Simulation time 59843734 ps
CPU time 0.78 seconds
Started Aug 09 07:11:11 PM PDT 24
Finished Aug 09 07:11:12 PM PDT 24
Peak memory 206648 kb
Host smart-91c32efb-1af8-4be6-be4a-cfeaeb84a66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3543075949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3543075949
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.163297207
Short name T3694
Test name
Test status
Simulation time 87280089 ps
CPU time 0.77 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206568 kb
Host smart-84531bf6-3c5f-48ec-9cde-9fcd343ffd8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=163297207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.163297207
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3220401947
Short name T3733
Test name
Test status
Simulation time 203877953 ps
CPU time 1.73 seconds
Started Aug 09 07:11:27 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 206856 kb
Host smart-6bed35bb-717b-4639-bc91-b2fa3004d105
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3220401947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3220401947
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.408146741
Short name T256
Test name
Test status
Simulation time 241260306 ps
CPU time 2.55 seconds
Started Aug 09 07:11:26 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 215120 kb
Host smart-16108134-5d74-43cb-abce-2cbebbb51117
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=408146741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.408146741
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2223038767
Short name T3707
Test name
Test status
Simulation time 480685413 ps
CPU time 4.11 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:18 PM PDT 24
Peak memory 206948 kb
Host smart-97f5fa61-8d9f-4f33-aedc-4603a3c11f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2223038767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2223038767
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1519403094
Short name T3702
Test name
Test status
Simulation time 162953175 ps
CPU time 1.88 seconds
Started Aug 09 07:11:26 PM PDT 24
Finished Aug 09 07:11:28 PM PDT 24
Peak memory 215244 kb
Host smart-d55a01a6-6020-49cb-87cd-60213aa641d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519403094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1519403094
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2716326988
Short name T284
Test name
Test status
Simulation time 120180726 ps
CPU time 1.04 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 206776 kb
Host smart-01c7a054-1544-45b8-aba4-88a86c0690ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2716326988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2716326988
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2137904927
Short name T3641
Test name
Test status
Simulation time 77288026 ps
CPU time 0.75 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:14 PM PDT 24
Peak memory 206568 kb
Host smart-a130a7de-7bb8-4301-9e45-e97a188ed303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2137904927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2137904927
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3532433833
Short name T288
Test name
Test status
Simulation time 117601919 ps
CPU time 1.22 seconds
Started Aug 09 07:11:15 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206896 kb
Host smart-8ffb9eb7-41a3-43ff-a29b-1c1cea2bee3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3532433833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3532433833
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3399653148
Short name T3654
Test name
Test status
Simulation time 62448760 ps
CPU time 1.5 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:35 PM PDT 24
Peak memory 206988 kb
Host smart-15c7eba6-50a7-411f-96d8-366aa89394e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399653148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3399653148
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1589644471
Short name T344
Test name
Test status
Simulation time 519651785 ps
CPU time 3.16 seconds
Started Aug 09 07:11:24 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206988 kb
Host smart-c444a4f4-4c74-45e8-84a8-3cbd28864bc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1589644471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1589644471
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.555643173
Short name T261
Test name
Test status
Simulation time 95419129 ps
CPU time 2.59 seconds
Started Aug 09 07:11:34 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 215172 kb
Host smart-8780b860-90c4-420b-badf-afc5aafdffba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555643173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.555643173
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4120414665
Short name T3680
Test name
Test status
Simulation time 31345676 ps
CPU time 0.71 seconds
Started Aug 09 07:11:28 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 206572 kb
Host smart-999259f5-7fd4-440b-a0ce-59e9e5f713ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4120414665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.4120414665
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1326249277
Short name T3673
Test name
Test status
Simulation time 188315460 ps
CPU time 1.51 seconds
Started Aug 09 07:11:22 PM PDT 24
Finished Aug 09 07:11:23 PM PDT 24
Peak memory 206900 kb
Host smart-28f69b1a-3872-4855-aeb1-fa6431953833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1326249277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1326249277
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3269161362
Short name T248
Test name
Test status
Simulation time 69527310 ps
CPU time 1.47 seconds
Started Aug 09 07:11:25 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206932 kb
Host smart-3e58e635-d31a-4e54-b20c-a074d15499fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3269161362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3269161362
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.512184537
Short name T262
Test name
Test status
Simulation time 170253399 ps
CPU time 1.77 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 215200 kb
Host smart-586ebe8b-e068-4d5a-aa0e-22aa857533d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512184537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.512184537
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1723692388
Short name T3719
Test name
Test status
Simulation time 95960946 ps
CPU time 0.91 seconds
Started Aug 09 07:11:28 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 206624 kb
Host smart-50508150-fbda-4eea-8a8a-87bf9004ca5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1723692388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1723692388
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1922612676
Short name T299
Test name
Test status
Simulation time 96038493 ps
CPU time 0.79 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:17 PM PDT 24
Peak memory 206628 kb
Host smart-66b13813-a4fc-477e-aecb-3b873e1abc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1922612676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1922612676
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1549791688
Short name T3698
Test name
Test status
Simulation time 96745740 ps
CPU time 1.08 seconds
Started Aug 09 07:11:17 PM PDT 24
Finished Aug 09 07:11:18 PM PDT 24
Peak memory 206944 kb
Host smart-06f4306e-af41-4ef0-a9fb-27841dc0a049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1549791688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1549791688
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2565967551
Short name T340
Test name
Test status
Simulation time 639473173 ps
CPU time 4.09 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 207020 kb
Host smart-57f70e1e-d371-4ff5-a216-48297dbae85d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2565967551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2565967551
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2788107931
Short name T3672
Test name
Test status
Simulation time 119319305 ps
CPU time 1.49 seconds
Started Aug 09 07:11:30 PM PDT 24
Finished Aug 09 07:11:32 PM PDT 24
Peak memory 215100 kb
Host smart-3a4fac29-0893-4d71-9d80-1e716b9b7f9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788107931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2788107931
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2018576783
Short name T3692
Test name
Test status
Simulation time 58214126 ps
CPU time 0.94 seconds
Started Aug 09 07:11:21 PM PDT 24
Finished Aug 09 07:11:22 PM PDT 24
Peak memory 206736 kb
Host smart-9ff84161-c679-4504-9c52-5d0dd4802aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2018576783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2018576783
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4044340678
Short name T3659
Test name
Test status
Simulation time 37752344 ps
CPU time 0.73 seconds
Started Aug 09 07:11:26 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206624 kb
Host smart-50e7a387-d8c7-459b-8a88-75c7b07cd62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4044340678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4044340678
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1373650482
Short name T3653
Test name
Test status
Simulation time 117757809 ps
CPU time 1.16 seconds
Started Aug 09 07:11:23 PM PDT 24
Finished Aug 09 07:11:25 PM PDT 24
Peak memory 206944 kb
Host smart-b62f76b1-60bf-4820-9ee9-247c89eff27e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1373650482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1373650482
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2950641363
Short name T3683
Test name
Test status
Simulation time 63552893 ps
CPU time 1.41 seconds
Started Aug 09 07:11:28 PM PDT 24
Finished Aug 09 07:11:30 PM PDT 24
Peak memory 206880 kb
Host smart-26414e0a-4d5b-4439-a613-b4b558dcd216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2950641363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2950641363
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.268880304
Short name T3717
Test name
Test status
Simulation time 741125884 ps
CPU time 4.95 seconds
Started Aug 09 07:11:29 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206984 kb
Host smart-a9b05ac1-5d74-4d12-9250-82753f9dc262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=268880304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.268880304
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2094300630
Short name T260
Test name
Test status
Simulation time 105497632 ps
CPU time 2.43 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:21 PM PDT 24
Peak memory 215152 kb
Host smart-5e6ed91a-5958-479f-9503-16d02a6aaeda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094300630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2094300630
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3293519192
Short name T3670
Test name
Test status
Simulation time 48590471 ps
CPU time 0.8 seconds
Started Aug 09 07:11:23 PM PDT 24
Finished Aug 09 07:11:24 PM PDT 24
Peak memory 206624 kb
Host smart-5cc7f5a5-59c3-4f06-90fe-ad86057785d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3293519192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3293519192
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.311509538
Short name T286
Test name
Test status
Simulation time 334912521 ps
CPU time 1.62 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206920 kb
Host smart-71e99741-2fa2-4362-bc6e-ede71b3628ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=311509538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.311509538
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2233853503
Short name T3667
Test name
Test status
Simulation time 193931149 ps
CPU time 2.3 seconds
Started Aug 09 07:11:09 PM PDT 24
Finished Aug 09 07:11:11 PM PDT 24
Peak memory 207008 kb
Host smart-cec45933-4cff-4d73-b5f1-b82099f54f69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233853503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2233853503
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1093886935
Short name T343
Test name
Test status
Simulation time 379230653 ps
CPU time 2.5 seconds
Started Aug 09 07:11:17 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206992 kb
Host smart-d93b1ce7-4662-4d1d-bf82-223af40d972c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1093886935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1093886935
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1663450672
Short name T3703
Test name
Test status
Simulation time 80609690 ps
CPU time 2.1 seconds
Started Aug 09 07:11:20 PM PDT 24
Finished Aug 09 07:11:22 PM PDT 24
Peak memory 215152 kb
Host smart-aae8aa10-860a-4512-8377-8e013ec32cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663450672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1663450672
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3327833482
Short name T280
Test name
Test status
Simulation time 143431555 ps
CPU time 1.19 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:35 PM PDT 24
Peak memory 206772 kb
Host smart-fa49ec30-fdc6-45a7-beda-93cd63ed30c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3327833482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3327833482
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.948588001
Short name T331
Test name
Test status
Simulation time 72894760 ps
CPU time 0.75 seconds
Started Aug 09 07:11:25 PM PDT 24
Finished Aug 09 07:11:26 PM PDT 24
Peak memory 206588 kb
Host smart-9f6529e2-3a21-4d26-b5d2-410748892324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=948588001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.948588001
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3834140573
Short name T287
Test name
Test status
Simulation time 107053082 ps
CPU time 1.01 seconds
Started Aug 09 07:11:24 PM PDT 24
Finished Aug 09 07:11:25 PM PDT 24
Peak memory 206700 kb
Host smart-e5868fa4-5d24-44df-92fa-111b28ac7703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3834140573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3834140573
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.894167673
Short name T3662
Test name
Test status
Simulation time 100660698 ps
CPU time 1.73 seconds
Started Aug 09 07:11:38 PM PDT 24
Finished Aug 09 07:11:40 PM PDT 24
Peak memory 207028 kb
Host smart-dfdc1e2f-b2db-440d-bb9b-f867a5df5ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=894167673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.894167673
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.497246924
Short name T204
Test name
Test status
Simulation time 356408781 ps
CPU time 2.4 seconds
Started Aug 09 07:11:31 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206948 kb
Host smart-f9091049-b9e7-4c87-b1f6-bc8cd93a4dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=497246924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.497246924
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2688592642
Short name T3714
Test name
Test status
Simulation time 84145395 ps
CPU time 1.33 seconds
Started Aug 09 07:11:32 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 214976 kb
Host smart-21ee3593-ef30-41b3-82ca-37803815b3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688592642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2688592642
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2756287705
Short name T3734
Test name
Test status
Simulation time 80788749 ps
CPU time 0.9 seconds
Started Aug 09 07:11:22 PM PDT 24
Finished Aug 09 07:11:23 PM PDT 24
Peak memory 206740 kb
Host smart-fe90db59-5cad-412c-9a54-fe5e1a293705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2756287705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2756287705
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3728174211
Short name T3740
Test name
Test status
Simulation time 50209416 ps
CPU time 0.75 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:17 PM PDT 24
Peak memory 206580 kb
Host smart-c674b911-081a-4d3c-a000-772d8dbd2689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3728174211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3728174211
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2931046663
Short name T3666
Test name
Test status
Simulation time 135059331 ps
CPU time 1.54 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206888 kb
Host smart-c2a59b63-9aec-4c44-b608-00e9bb68c0f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2931046663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2931046663
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4086868876
Short name T3661
Test name
Test status
Simulation time 65008439 ps
CPU time 1.68 seconds
Started Aug 09 07:11:25 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206872 kb
Host smart-5d89ef9d-1530-4a4a-a5fd-e94755abc438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4086868876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4086868876
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1676522755
Short name T339
Test name
Test status
Simulation time 630794219 ps
CPU time 4.6 seconds
Started Aug 09 07:11:32 PM PDT 24
Finished Aug 09 07:11:36 PM PDT 24
Peak memory 206944 kb
Host smart-dbc96783-d56b-4be3-9419-72b66c3b6ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1676522755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1676522755
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2606871098
Short name T3735
Test name
Test status
Simulation time 99174963 ps
CPU time 1.24 seconds
Started Aug 09 07:11:25 PM PDT 24
Finished Aug 09 07:11:26 PM PDT 24
Peak memory 214924 kb
Host smart-42b6fd2b-e2c4-486c-b32d-bf0437b8a6fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606871098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2606871098
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4102325650
Short name T3706
Test name
Test status
Simulation time 64286412 ps
CPU time 0.8 seconds
Started Aug 09 07:11:21 PM PDT 24
Finished Aug 09 07:11:21 PM PDT 24
Peak memory 206676 kb
Host smart-c37a83b2-aebf-4020-ac35-b65a00ff07bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4102325650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4102325650
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.373939709
Short name T3696
Test name
Test status
Simulation time 40860723 ps
CPU time 0.71 seconds
Started Aug 09 07:11:17 PM PDT 24
Finished Aug 09 07:11:18 PM PDT 24
Peak memory 206628 kb
Host smart-2972a32c-bf26-46b6-9874-84eec7634fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373939709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.373939709
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2723945955
Short name T3685
Test name
Test status
Simulation time 124992031 ps
CPU time 1.1 seconds
Started Aug 09 07:11:27 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 206900 kb
Host smart-94e1c10c-7aa9-47c1-8db0-ae01d8e0acc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2723945955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2723945955
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1580640885
Short name T3688
Test name
Test status
Simulation time 153860207 ps
CPU time 1.76 seconds
Started Aug 09 07:11:30 PM PDT 24
Finished Aug 09 07:11:32 PM PDT 24
Peak memory 206940 kb
Host smart-5805c9b2-cea9-4068-8133-3af600934968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580640885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1580640885
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2584623990
Short name T338
Test name
Test status
Simulation time 446705522 ps
CPU time 2.97 seconds
Started Aug 09 07:11:27 PM PDT 24
Finished Aug 09 07:11:30 PM PDT 24
Peak memory 206904 kb
Host smart-d2a4ce9c-c8d6-4429-8c90-eac8a6e99895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2584623990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2584623990
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1462636409
Short name T3663
Test name
Test status
Simulation time 171152830 ps
CPU time 2.07 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206876 kb
Host smart-d1fa7a5b-34e2-4fd1-a6d7-dca19dde6460
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1462636409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1462636409
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.987509681
Short name T3725
Test name
Test status
Simulation time 1477020689 ps
CPU time 8.98 seconds
Started Aug 09 07:11:04 PM PDT 24
Finished Aug 09 07:11:13 PM PDT 24
Peak memory 206956 kb
Host smart-2862631b-4e52-4e1c-bff8-0312d46d870a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=987509681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.987509681
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.919071007
Short name T296
Test name
Test status
Simulation time 121979754 ps
CPU time 0.91 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 206748 kb
Host smart-5d0c33f3-238c-4252-9c91-edc91fdd7005
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=919071007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.919071007
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.363172906
Short name T3684
Test name
Test status
Simulation time 96600529 ps
CPU time 1.5 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 215152 kb
Host smart-0e9a9617-8dde-4c3b-aba0-aaa480602499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363172906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.363172906
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3331324535
Short name T3671
Test name
Test status
Simulation time 38433878 ps
CPU time 0.82 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:15 PM PDT 24
Peak memory 206600 kb
Host smart-de88a683-6cb1-49a0-913c-996768ddf712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3331324535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3331324535
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1712219681
Short name T3705
Test name
Test status
Simulation time 52942500 ps
CPU time 0.78 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 206600 kb
Host smart-dd93a4b5-148d-4275-be34-95852e5bb149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1712219681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1712219681
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2459313696
Short name T271
Test name
Test status
Simulation time 188583419 ps
CPU time 2.31 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:03 PM PDT 24
Peak memory 206860 kb
Host smart-e8290e7d-66f3-42cd-a0ba-2cc93041f60d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2459313696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2459313696
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.152225317
Short name T3634
Test name
Test status
Simulation time 120535196 ps
CPU time 2.36 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:18 PM PDT 24
Peak memory 206784 kb
Host smart-678e09d7-d394-4460-b69e-46a12241ec09
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=152225317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.152225317
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.109569355
Short name T3701
Test name
Test status
Simulation time 144386636 ps
CPU time 1.16 seconds
Started Aug 09 07:11:11 PM PDT 24
Finished Aug 09 07:11:12 PM PDT 24
Peak memory 206716 kb
Host smart-b7401ee8-8e49-48a5-b919-2ea277db6aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=109569355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.109569355
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2795276585
Short name T3718
Test name
Test status
Simulation time 267910882 ps
CPU time 2.95 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 223280 kb
Host smart-08cc6785-6054-44c6-b9d4-f6d713a3fe6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795276585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2795276585
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4283081240
Short name T334
Test name
Test status
Simulation time 43535105 ps
CPU time 0.71 seconds
Started Aug 09 07:11:16 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206520 kb
Host smart-5137d1c8-f71a-49a9-9ca5-be424883fe55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283081240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.4283081240
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3467149418
Short name T3651
Test name
Test status
Simulation time 42701596 ps
CPU time 0.78 seconds
Started Aug 09 07:11:30 PM PDT 24
Finished Aug 09 07:11:30 PM PDT 24
Peak memory 206624 kb
Host smart-510e0835-4652-4d2c-a4c5-de3d23ea4ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3467149418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3467149418
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4170384517
Short name T3649
Test name
Test status
Simulation time 45184929 ps
CPU time 0.69 seconds
Started Aug 09 07:11:26 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206536 kb
Host smart-a989d0a9-2836-47bf-899f-c271a8da5c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170384517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4170384517
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.190474232
Short name T209
Test name
Test status
Simulation time 35204006 ps
CPU time 0.67 seconds
Started Aug 09 07:11:21 PM PDT 24
Finished Aug 09 07:11:22 PM PDT 24
Peak memory 206592 kb
Host smart-b3e3bc61-a30a-4d63-904b-15dc8b7b4efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190474232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.190474232
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1988008560
Short name T3676
Test name
Test status
Simulation time 41851491 ps
CPU time 0.78 seconds
Started Aug 09 07:11:34 PM PDT 24
Finished Aug 09 07:11:35 PM PDT 24
Peak memory 206624 kb
Host smart-78464035-41b5-47b1-ad3e-3f6e062231f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1988008560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1988008560
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2445239573
Short name T3727
Test name
Test status
Simulation time 67057623 ps
CPU time 0.74 seconds
Started Aug 09 07:11:28 PM PDT 24
Finished Aug 09 07:11:29 PM PDT 24
Peak memory 206592 kb
Host smart-71ea021b-3ebe-4409-b0ce-2eadb008d4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2445239573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2445239573
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1533039509
Short name T3690
Test name
Test status
Simulation time 43806943 ps
CPU time 0.7 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:33 PM PDT 24
Peak memory 206576 kb
Host smart-0da5e10d-024d-440d-89ac-8fe0b86bab8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1533039509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1533039509
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2262352889
Short name T297
Test name
Test status
Simulation time 67042832 ps
CPU time 0.74 seconds
Started Aug 09 07:11:38 PM PDT 24
Finished Aug 09 07:11:39 PM PDT 24
Peak memory 206572 kb
Host smart-ecacf5ca-873a-461c-80b3-c48e2238bb6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2262352889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2262352889
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3899419306
Short name T3656
Test name
Test status
Simulation time 41192508 ps
CPU time 0.74 seconds
Started Aug 09 07:11:21 PM PDT 24
Finished Aug 09 07:11:22 PM PDT 24
Peak memory 206612 kb
Host smart-233ea127-d277-444d-a674-5dc22b65830a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899419306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3899419306
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3108608939
Short name T3721
Test name
Test status
Simulation time 67521555 ps
CPU time 0.73 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206516 kb
Host smart-0b0b68c5-a838-42fa-a8ff-326f01c01a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108608939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3108608939
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.198681932
Short name T3687
Test name
Test status
Simulation time 171163513 ps
CPU time 2.15 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:05 PM PDT 24
Peak memory 206860 kb
Host smart-9c638f51-ef09-4aae-99a1-229eb0742091
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=198681932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.198681932
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2756032023
Short name T3638
Test name
Test status
Simulation time 586617912 ps
CPU time 4.12 seconds
Started Aug 09 07:11:11 PM PDT 24
Finished Aug 09 07:11:15 PM PDT 24
Peak memory 206868 kb
Host smart-8eb45a0b-fefb-4433-857f-4ab64a6b38b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2756032023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2756032023
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3214744149
Short name T294
Test name
Test status
Simulation time 108838751 ps
CPU time 0.84 seconds
Started Aug 09 07:10:59 PM PDT 24
Finished Aug 09 07:11:00 PM PDT 24
Peak memory 206740 kb
Host smart-b03d02a1-8b07-4cc5-894b-338b98eb52bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3214744149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3214744149
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3035298377
Short name T258
Test name
Test status
Simulation time 101015096 ps
CPU time 2.18 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 215128 kb
Host smart-5552b670-9b53-46a8-ac26-68d5f8c55eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035298377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3035298377
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2990535092
Short name T3664
Test name
Test status
Simulation time 154289942 ps
CPU time 0.95 seconds
Started Aug 09 07:11:15 PM PDT 24
Finished Aug 09 07:11:16 PM PDT 24
Peak memory 206696 kb
Host smart-8c0f3b4d-00ec-4c99-9338-04b4a2bcbb85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2990535092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2990535092
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2556841928
Short name T3682
Test name
Test status
Simulation time 212771742 ps
CPU time 2.44 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 215056 kb
Host smart-6d267e4b-6a8d-412c-b7cc-8ce1c49d47e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2556841928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2556841928
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2132103724
Short name T3713
Test name
Test status
Simulation time 496137700 ps
CPU time 4.64 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:23 PM PDT 24
Peak memory 206816 kb
Host smart-bdfcb621-1fcf-4d77-90d3-ca9d24b264be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2132103724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2132103724
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4150439722
Short name T3710
Test name
Test status
Simulation time 71928683 ps
CPU time 1.09 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 206848 kb
Host smart-9c5462b3-3cc8-4083-a9a7-c29a5a23618f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4150439722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4150439722
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2013964707
Short name T3655
Test name
Test status
Simulation time 107913520 ps
CPU time 2.64 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:06 PM PDT 24
Peak memory 223240 kb
Host smart-2dd7aa12-143c-4898-8afe-e957c5590f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2013964707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2013964707
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2339114125
Short name T3722
Test name
Test status
Simulation time 448865932 ps
CPU time 3.41 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206992 kb
Host smart-01223990-84f5-42e1-b8c3-33c8ee10d9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2339114125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2339114125
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2206143366
Short name T298
Test name
Test status
Simulation time 81022713 ps
CPU time 0.78 seconds
Started Aug 09 07:11:31 PM PDT 24
Finished Aug 09 07:11:32 PM PDT 24
Peak memory 206540 kb
Host smart-b104d266-1683-4a6a-b73d-807a8878a7bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2206143366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2206143366
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1668062920
Short name T212
Test name
Test status
Simulation time 39099046 ps
CPU time 0.71 seconds
Started Aug 09 07:11:34 PM PDT 24
Finished Aug 09 07:11:35 PM PDT 24
Peak memory 206576 kb
Host smart-e8680c4f-d557-48b7-ba6b-5563a6ebf9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1668062920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1668062920
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4288496785
Short name T3678
Test name
Test status
Simulation time 35517914 ps
CPU time 0.71 seconds
Started Aug 09 07:11:26 PM PDT 24
Finished Aug 09 07:11:27 PM PDT 24
Peak memory 206604 kb
Host smart-86ee5833-cc80-45df-b08f-21a06a333a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288496785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.4288496785
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2949407986
Short name T3648
Test name
Test status
Simulation time 53887262 ps
CPU time 0.76 seconds
Started Aug 09 07:11:36 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 206532 kb
Host smart-5eaf0ce8-6068-4857-abcd-a161600fad33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2949407986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2949407986
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2348735825
Short name T3700
Test name
Test status
Simulation time 83713174 ps
CPU time 0.74 seconds
Started Aug 09 07:11:29 PM PDT 24
Finished Aug 09 07:11:30 PM PDT 24
Peak memory 206540 kb
Host smart-59579c43-4297-4a8b-b32e-010aa7403b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2348735825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2348735825
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1303419611
Short name T300
Test name
Test status
Simulation time 99109894 ps
CPU time 0.8 seconds
Started Aug 09 07:11:39 PM PDT 24
Finished Aug 09 07:11:40 PM PDT 24
Peak memory 206624 kb
Host smart-541a7580-a6ff-4f49-a258-704a5273a760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1303419611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1303419611
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3845171502
Short name T3724
Test name
Test status
Simulation time 41307561 ps
CPU time 0.68 seconds
Started Aug 09 07:11:31 PM PDT 24
Finished Aug 09 07:11:32 PM PDT 24
Peak memory 206592 kb
Host smart-3173512f-1010-4d91-82b7-5c8a4399add2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845171502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3845171502
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1179072325
Short name T3644
Test name
Test status
Simulation time 102192060 ps
CPU time 0.76 seconds
Started Aug 09 07:11:36 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 206528 kb
Host smart-946c464a-5e89-47c1-b7ee-302316ba6121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1179072325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1179072325
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1879484056
Short name T332
Test name
Test status
Simulation time 39071113 ps
CPU time 0.71 seconds
Started Aug 09 07:11:37 PM PDT 24
Finished Aug 09 07:11:38 PM PDT 24
Peak memory 206552 kb
Host smart-664638cd-86f1-4b4e-a176-6f1ad181c1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879484056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1879484056
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1886298612
Short name T3693
Test name
Test status
Simulation time 119671675 ps
CPU time 3.14 seconds
Started Aug 09 07:11:12 PM PDT 24
Finished Aug 09 07:11:15 PM PDT 24
Peak memory 207116 kb
Host smart-7d8d5c5b-5874-45fb-b230-6e25bc6f87e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1886298612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1886298612
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3541961339
Short name T276
Test name
Test status
Simulation time 214905582 ps
CPU time 3.76 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206952 kb
Host smart-6c47f8cc-97db-4940-87b9-037da607aad5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3541961339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3541961339
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3650104657
Short name T274
Test name
Test status
Simulation time 141774376 ps
CPU time 1.02 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206752 kb
Host smart-a36eebd7-4768-4a94-9773-7d52a73de162
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3650104657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3650104657
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1252717410
Short name T3643
Test name
Test status
Simulation time 125761204 ps
CPU time 1.4 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:21 PM PDT 24
Peak memory 215456 kb
Host smart-9dd2dfe7-110f-495b-a62a-b1b037519554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252717410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1252717410
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3112351645
Short name T3723
Test name
Test status
Simulation time 61113985 ps
CPU time 0.82 seconds
Started Aug 09 07:11:04 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206720 kb
Host smart-63662f69-a3e6-46bb-a8b5-d7cea95ee5d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3112351645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3112351645
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3328812437
Short name T3647
Test name
Test status
Simulation time 41077093 ps
CPU time 0.75 seconds
Started Aug 09 07:11:09 PM PDT 24
Finished Aug 09 07:11:10 PM PDT 24
Peak memory 206600 kb
Host smart-1b545201-c1d9-4f4c-8f43-b27d6de2555c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3328812437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3328812437
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2753627154
Short name T270
Test name
Test status
Simulation time 76868877 ps
CPU time 2.31 seconds
Started Aug 09 07:11:21 PM PDT 24
Finished Aug 09 07:11:24 PM PDT 24
Peak memory 215040 kb
Host smart-ce34f54b-5d18-43aa-b7c8-a3c5d66e6f8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2753627154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2753627154
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1994197827
Short name T3677
Test name
Test status
Simulation time 329621292 ps
CPU time 2.59 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:21 PM PDT 24
Peak memory 206816 kb
Host smart-8f66e776-fab4-4850-b9f4-05f096032fca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1994197827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1994197827
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.313493603
Short name T283
Test name
Test status
Simulation time 116337946 ps
CPU time 1.67 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 206864 kb
Host smart-4647f82d-0f5a-442d-ab9c-edb3a1c68c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=313493603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.313493603
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.986229593
Short name T255
Test name
Test status
Simulation time 80864588 ps
CPU time 1.89 seconds
Started Aug 09 07:11:00 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 207040 kb
Host smart-50cf4c75-6b0c-4af8-9324-24aae2b4ca83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=986229593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.986229593
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2594043071
Short name T3729
Test name
Test status
Simulation time 1167970841 ps
CPU time 3.42 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:21 PM PDT 24
Peak memory 206920 kb
Host smart-ab768970-ac3a-4955-a277-e5583a6540bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2594043071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2594043071
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3956420769
Short name T330
Test name
Test status
Simulation time 38170588 ps
CPU time 0.66 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 206604 kb
Host smart-8c013c51-87e3-4708-b895-71e2fe71ef84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3956420769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3956420769
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4048196278
Short name T3645
Test name
Test status
Simulation time 59009814 ps
CPU time 0.77 seconds
Started Aug 09 07:11:36 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 206604 kb
Host smart-d47fd86a-3f05-4cb7-bc73-3860d61e18d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048196278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4048196278
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.86255643
Short name T207
Test name
Test status
Simulation time 65507361 ps
CPU time 0.74 seconds
Started Aug 09 07:11:38 PM PDT 24
Finished Aug 09 07:11:39 PM PDT 24
Peak memory 206620 kb
Host smart-27015932-616f-43b3-9a44-393dff3ce8ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=86255643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.86255643
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3105912891
Short name T3716
Test name
Test status
Simulation time 58482090 ps
CPU time 0.75 seconds
Started Aug 09 07:11:35 PM PDT 24
Finished Aug 09 07:11:36 PM PDT 24
Peak memory 206592 kb
Host smart-4f2878e6-951b-49d2-b245-c7f7c84b0c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3105912891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3105912891
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.411477120
Short name T3660
Test name
Test status
Simulation time 41012644 ps
CPU time 0.68 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206540 kb
Host smart-81d2cf44-b07f-4d28-bf69-5d173a6556ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=411477120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.411477120
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2352094493
Short name T3708
Test name
Test status
Simulation time 54428299 ps
CPU time 0.73 seconds
Started Aug 09 07:11:33 PM PDT 24
Finished Aug 09 07:11:34 PM PDT 24
Peak memory 206552 kb
Host smart-a849302c-f492-4fae-a11c-7dddd49217e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352094493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2352094493
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3800121025
Short name T3657
Test name
Test status
Simulation time 49702314 ps
CPU time 0.68 seconds
Started Aug 09 07:11:18 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 206592 kb
Host smart-139a306d-0891-4abf-9009-7d880484907c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3800121025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3800121025
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3756914306
Short name T3720
Test name
Test status
Simulation time 31835714 ps
CPU time 0.73 seconds
Started Aug 09 07:11:31 PM PDT 24
Finished Aug 09 07:11:32 PM PDT 24
Peak memory 206532 kb
Host smart-2cee1bf8-a02e-4848-b392-e32031c5b576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3756914306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3756914306
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2359712929
Short name T3675
Test name
Test status
Simulation time 35009257 ps
CPU time 0.73 seconds
Started Aug 09 07:11:38 PM PDT 24
Finished Aug 09 07:11:39 PM PDT 24
Peak memory 206548 kb
Host smart-2adb0c6b-9025-4a8c-bc63-b8f586baa50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2359712929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2359712929
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3842905068
Short name T3636
Test name
Test status
Simulation time 45613786 ps
CPU time 0.72 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:19 PM PDT 24
Peak memory 206620 kb
Host smart-9eba4f6a-ffa2-467b-8052-39db8fb96398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3842905068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3842905068
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2188076210
Short name T3642
Test name
Test status
Simulation time 123546190 ps
CPU time 1.52 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 215096 kb
Host smart-ab53c5a7-b1cf-4b1f-b2be-508bf85d5314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188076210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2188076210
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1208932469
Short name T3635
Test name
Test status
Simulation time 66704631 ps
CPU time 1 seconds
Started Aug 09 07:11:01 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 206748 kb
Host smart-6d402995-1b34-48e1-80af-2dd49007903e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1208932469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1208932469
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.521723050
Short name T3731
Test name
Test status
Simulation time 50353478 ps
CPU time 0.73 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206820 kb
Host smart-21233809-71b3-4b72-8116-3951114f4109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=521723050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.521723050
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2278346461
Short name T285
Test name
Test status
Simulation time 140532515 ps
CPU time 1.28 seconds
Started Aug 09 07:11:22 PM PDT 24
Finished Aug 09 07:11:23 PM PDT 24
Peak memory 207144 kb
Host smart-53e4f190-7ef8-4498-9c79-e20e8eda23d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2278346461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2278346461
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2776808000
Short name T206
Test name
Test status
Simulation time 194467822 ps
CPU time 2.27 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:22 PM PDT 24
Peak memory 207152 kb
Host smart-9cb55f1a-3b29-4c4e-bcc8-bc1f8983545f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2776808000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2776808000
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2240673578
Short name T3730
Test name
Test status
Simulation time 465809106 ps
CPU time 2.58 seconds
Started Aug 09 07:11:04 PM PDT 24
Finished Aug 09 07:11:07 PM PDT 24
Peak memory 206908 kb
Host smart-7284d7a9-41a7-4b58-bfa3-19db554fc515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2240673578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2240673578
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2099174395
Short name T259
Test name
Test status
Simulation time 99796901 ps
CPU time 1.25 seconds
Started Aug 09 07:11:02 PM PDT 24
Finished Aug 09 07:11:03 PM PDT 24
Peak memory 215204 kb
Host smart-46598c8f-746c-4e2b-a337-cdb1264123dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099174395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2099174395
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1079776166
Short name T3736
Test name
Test status
Simulation time 91953774 ps
CPU time 0.94 seconds
Started Aug 09 07:11:19 PM PDT 24
Finished Aug 09 07:11:20 PM PDT 24
Peak memory 206608 kb
Host smart-dd142048-d3bd-4d56-bc9c-6790f8c8c4b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1079776166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1079776166
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.846482648
Short name T3709
Test name
Test status
Simulation time 48339296 ps
CPU time 0.81 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 206588 kb
Host smart-f9eeb9e2-da3b-4c79-8034-253928d7b3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=846482648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.846482648
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1200414837
Short name T240
Test name
Test status
Simulation time 219500679 ps
CPU time 1.6 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:05 PM PDT 24
Peak memory 207012 kb
Host smart-88258680-b6c8-41e8-95e5-37deea07c07e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1200414837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1200414837
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.654304584
Short name T3652
Test name
Test status
Simulation time 135106212 ps
CPU time 1.74 seconds
Started Aug 09 07:11:04 PM PDT 24
Finished Aug 09 07:11:06 PM PDT 24
Peak memory 206860 kb
Host smart-9ba56cd0-dee8-4d47-8312-84346e8f77d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=654304584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.654304584
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2637954285
Short name T205
Test name
Test status
Simulation time 314224584 ps
CPU time 2.23 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:05 PM PDT 24
Peak memory 206936 kb
Host smart-28142838-c828-4d4d-a6f4-760bca9f8be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2637954285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2637954285
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.832464582
Short name T3650
Test name
Test status
Simulation time 53650921 ps
CPU time 1.26 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:04 PM PDT 24
Peak memory 214948 kb
Host smart-d9319a1f-74de-4efa-93db-8d0c02688daa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832464582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.832464582
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4131042723
Short name T279
Test name
Test status
Simulation time 104521249 ps
CPU time 0.94 seconds
Started Aug 09 07:11:07 PM PDT 24
Finished Aug 09 07:11:08 PM PDT 24
Peak memory 206728 kb
Host smart-9e57f1b3-4699-4d93-a829-d7377412b7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4131042723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4131042723
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2801501209
Short name T3640
Test name
Test status
Simulation time 36912059 ps
CPU time 0.68 seconds
Started Aug 09 07:11:05 PM PDT 24
Finished Aug 09 07:11:06 PM PDT 24
Peak memory 206624 kb
Host smart-e73c6155-820d-4d26-9eb8-60de9ea7624d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2801501209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2801501209
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3990515849
Short name T3699
Test name
Test status
Simulation time 345210249 ps
CPU time 2.33 seconds
Started Aug 09 07:11:03 PM PDT 24
Finished Aug 09 07:11:06 PM PDT 24
Peak memory 206972 kb
Host smart-ec5804f3-cde9-40d4-9ae7-ab25de748ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3990515849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3990515849
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2984663950
Short name T254
Test name
Test status
Simulation time 282976027 ps
CPU time 3.26 seconds
Started Aug 09 07:11:05 PM PDT 24
Finished Aug 09 07:11:09 PM PDT 24
Peak memory 220380 kb
Host smart-fd8c6eb7-619e-4d83-af04-9aabd430b56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984663950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2984663950
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3605708260
Short name T247
Test name
Test status
Simulation time 542413984 ps
CPU time 3.15 seconds
Started Aug 09 07:11:22 PM PDT 24
Finished Aug 09 07:11:25 PM PDT 24
Peak memory 207180 kb
Host smart-ec8b4c41-b624-4916-b664-ca77b3c2ddfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3605708260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3605708260
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3162931139
Short name T3665
Test name
Test status
Simulation time 97156280 ps
CPU time 1.22 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:15 PM PDT 24
Peak memory 215200 kb
Host smart-5a815196-92c9-4cce-ab1f-4c6263b3c0df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162931139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3162931139
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2299736446
Short name T3704
Test name
Test status
Simulation time 59570632 ps
CPU time 0.98 seconds
Started Aug 09 07:11:07 PM PDT 24
Finished Aug 09 07:11:08 PM PDT 24
Peak memory 206724 kb
Host smart-27f3dc29-20a1-4d14-94f5-ba037204e067
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2299736446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2299736446
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4821810
Short name T329
Test name
Test status
Simulation time 70841375 ps
CPU time 0.74 seconds
Started Aug 09 07:11:06 PM PDT 24
Finished Aug 09 07:11:06 PM PDT 24
Peak memory 206620 kb
Host smart-bd8fa3e0-0224-4e2d-848e-26a53b85ed67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4821810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4821810
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2417477196
Short name T3695
Test name
Test status
Simulation time 282069749 ps
CPU time 1.7 seconds
Started Aug 09 07:11:12 PM PDT 24
Finished Aug 09 07:11:14 PM PDT 24
Peak memory 207164 kb
Host smart-6d81dc23-49e8-4757-b2c6-ae7e8abd5372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2417477196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2417477196
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2111482532
Short name T3711
Test name
Test status
Simulation time 296303146 ps
CPU time 2.5 seconds
Started Aug 09 07:11:06 PM PDT 24
Finished Aug 09 07:11:08 PM PDT 24
Peak memory 206968 kb
Host smart-c00fb177-e4f8-4932-9e6b-227d622d04e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2111482532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2111482532
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.128031845
Short name T3728
Test name
Test status
Simulation time 97637314 ps
CPU time 1.23 seconds
Started Aug 09 07:11:10 PM PDT 24
Finished Aug 09 07:11:11 PM PDT 24
Peak memory 215196 kb
Host smart-e92d733b-30dc-4867-9514-ae3154a0c512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128031845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.128031845
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3886206339
Short name T3689
Test name
Test status
Simulation time 74934390 ps
CPU time 0.83 seconds
Started Aug 09 07:11:07 PM PDT 24
Finished Aug 09 07:11:08 PM PDT 24
Peak memory 206568 kb
Host smart-c7f1389c-1793-4a12-bf74-baca354003db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3886206339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3886206339
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.537752604
Short name T3637
Test name
Test status
Simulation time 48425758 ps
CPU time 0.72 seconds
Started Aug 09 07:11:14 PM PDT 24
Finished Aug 09 07:11:15 PM PDT 24
Peak memory 206592 kb
Host smart-369211ea-4b1e-47bc-b3bf-25575c198d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=537752604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.537752604
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1751382338
Short name T3738
Test name
Test status
Simulation time 289259795 ps
CPU time 1.63 seconds
Started Aug 09 07:11:07 PM PDT 24
Finished Aug 09 07:11:08 PM PDT 24
Peak memory 206932 kb
Host smart-7c162c96-4d9f-46f8-b761-449422954149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1751382338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1751382338
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3637020553
Short name T3691
Test name
Test status
Simulation time 256806591 ps
CPU time 3.41 seconds
Started Aug 09 07:11:08 PM PDT 24
Finished Aug 09 07:11:11 PM PDT 24
Peak memory 206916 kb
Host smart-94811b86-f814-46fc-9b41-a4ff6f4528c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3637020553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3637020553
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1231747791
Short name T2214
Test name
Test status
Simulation time 39081504 ps
CPU time 0.68 seconds
Started Aug 09 05:25:30 PM PDT 24
Finished Aug 09 05:25:31 PM PDT 24
Peak memory 207484 kb
Host smart-e45c29a5-ad99-4f05-82b2-54b78d32c645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1231747791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1231747791
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2765726579
Short name T3332
Test name
Test status
Simulation time 11728437335 ps
CPU time 14.2 seconds
Started Aug 09 05:25:19 PM PDT 24
Finished Aug 09 05:25:34 PM PDT 24
Peak memory 207704 kb
Host smart-07954df6-f96f-4e32-b042-314d0c6f7e23
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765726579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.2765726579
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.482622498
Short name T1857
Test name
Test status
Simulation time 29839507438 ps
CPU time 33.18 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207756 kb
Host smart-2015612f-f131-4ad6-91b1-f63ded6c0a48
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482622498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon
_wake_resume.482622498
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2426160364
Short name T1935
Test name
Test status
Simulation time 217782082 ps
CPU time 0.91 seconds
Started Aug 09 05:25:23 PM PDT 24
Finished Aug 09 05:25:24 PM PDT 24
Peak memory 207528 kb
Host smart-87c3bd91-40ea-456e-9e5f-91baab050a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261
60364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2426160364
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3282501190
Short name T2228
Test name
Test status
Simulation time 146640166 ps
CPU time 0.84 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:26 PM PDT 24
Peak memory 207468 kb
Host smart-58d597c4-805d-493f-843b-4a5ce53d0d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
01190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3282501190
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3418598557
Short name T3123
Test name
Test status
Simulation time 205137872 ps
CPU time 0.98 seconds
Started Aug 09 05:25:20 PM PDT 24
Finished Aug 09 05:25:21 PM PDT 24
Peak memory 207556 kb
Host smart-41539811-5d3d-46a3-9143-2263eb6517a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
98557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3418598557
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2476939637
Short name T3013
Test name
Test status
Simulation time 1114627192 ps
CPU time 2.61 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:29 PM PDT 24
Peak memory 207680 kb
Host smart-2034a3dd-2b94-484e-8a53-e5793d50abbd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2476939637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2476939637
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3500369516
Short name T183
Test name
Test status
Simulation time 41007059097 ps
CPU time 68.37 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:26:33 PM PDT 24
Peak memory 207800 kb
Host smart-e78bc335-3d0f-49f2-bcec-9a68f91088ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35003
69516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3500369516
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.1568902514
Short name T2368
Test name
Test status
Simulation time 1137464769 ps
CPU time 24.87 seconds
Started Aug 09 05:25:21 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207680 kb
Host smart-bc96f413-ea82-4067-af7a-e8c846b2b684
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568902514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.1568902514
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.92838779
Short name T3560
Test name
Test status
Simulation time 841385873 ps
CPU time 1.97 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:25:31 PM PDT 24
Peak memory 207500 kb
Host smart-1be2cf2a-f218-4ed6-a624-4993a8ca2bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92838
779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.92838779
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3577974242
Short name T732
Test name
Test status
Simulation time 153366339 ps
CPU time 0.85 seconds
Started Aug 09 05:25:20 PM PDT 24
Finished Aug 09 05:25:21 PM PDT 24
Peak memory 207472 kb
Host smart-c097e8e8-48f4-4a24-85a4-5db574e0acdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
74242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3577974242
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.3860594336
Short name T3182
Test name
Test status
Simulation time 43402216 ps
CPU time 0.74 seconds
Started Aug 09 05:25:24 PM PDT 24
Finished Aug 09 05:25:25 PM PDT 24
Peak memory 207356 kb
Host smart-c326346a-fd1d-4cca-8f63-4baf175e7075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38605
94336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3860594336
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1164241896
Short name T3272
Test name
Test status
Simulation time 820797931 ps
CPU time 2.16 seconds
Started Aug 09 05:25:19 PM PDT 24
Finished Aug 09 05:25:21 PM PDT 24
Peak memory 207616 kb
Host smart-c80b1e12-f233-4e8b-abcd-22cca3312899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
41896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1164241896
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.3763039223
Short name T359
Test name
Test status
Simulation time 225233134 ps
CPU time 0.97 seconds
Started Aug 09 05:25:28 PM PDT 24
Finished Aug 09 05:25:29 PM PDT 24
Peak memory 207772 kb
Host smart-20197b0b-3495-46df-8c66-ac7b4165729b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3763039223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.3763039223
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2171692411
Short name T1319
Test name
Test status
Simulation time 101186424295 ps
CPU time 164.81 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207768 kb
Host smart-c2d1e570-4f1c-42fe-8951-953b0a9f218b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2171692411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2171692411
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.4133005719
Short name T2833
Test name
Test status
Simulation time 121047918862 ps
CPU time 204.2 seconds
Started Aug 09 05:25:30 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207796 kb
Host smart-ed26061b-bdb5-4369-a92a-4f0e15e5a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133005719 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.4133005719
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3582094629
Short name T512
Test name
Test status
Simulation time 115095140374 ps
CPU time 168.12 seconds
Started Aug 09 05:25:31 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207788 kb
Host smart-a66ec33f-6e29-4248-afbd-6957b68df09b
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3582094629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3582094629
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3305922650
Short name T2332
Test name
Test status
Simulation time 87276083776 ps
CPU time 136.59 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:27:44 PM PDT 24
Peak memory 207668 kb
Host smart-b14bafd9-9e19-4de2-ab4f-4efed91d7fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305922650 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3305922650
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.688556461
Short name T511
Test name
Test status
Simulation time 104187480145 ps
CPU time 163.46 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 207800 kb
Host smart-ba5f0205-86e7-4f87-80ae-95fc6ab9c463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68855
6461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.688556461
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3825853654
Short name T2369
Test name
Test status
Simulation time 177369761 ps
CPU time 1 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:27 PM PDT 24
Peak memory 207516 kb
Host smart-75181281-d3d5-42b4-985b-e76aba184891
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3825853654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3825853654
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1008787902
Short name T1749
Test name
Test status
Simulation time 136637023 ps
CPU time 0.84 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:25:30 PM PDT 24
Peak memory 207360 kb
Host smart-e4b4ddb3-28da-4f93-801e-dd0019ec5889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
87902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1008787902
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3460807433
Short name T1137
Test name
Test status
Simulation time 229911255 ps
CPU time 0.98 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:26 PM PDT 24
Peak memory 207552 kb
Host smart-8de18a69-222c-4b2f-b330-8bba3d14de79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
07433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3460807433
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1560053572
Short name T3212
Test name
Test status
Simulation time 5064447759 ps
CPU time 50.41 seconds
Started Aug 09 05:25:36 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 216052 kb
Host smart-fec4043b-35ca-4cc4-b483-b294d1ab2468
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1560053572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1560053572
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.3087274397
Short name T2889
Test name
Test status
Simulation time 12848819323 ps
CPU time 169.31 seconds
Started Aug 09 05:25:35 PM PDT 24
Finished Aug 09 05:28:25 PM PDT 24
Peak memory 207652 kb
Host smart-f4f77c4c-0b71-4cf6-b2a7-87824a0412fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3087274397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.3087274397
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.967895092
Short name T115
Test name
Test status
Simulation time 219168490 ps
CPU time 1.01 seconds
Started Aug 09 05:25:24 PM PDT 24
Finished Aug 09 05:25:25 PM PDT 24
Peak memory 207436 kb
Host smart-18bbefd4-278e-4edc-b56c-ff5250624a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96789
5092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.967895092
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.4154202602
Short name T67
Test name
Test status
Simulation time 553696734 ps
CPU time 1.64 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:25:28 PM PDT 24
Peak memory 207456 kb
Host smart-0fc6111d-753b-425d-9886-e3fa40e8fccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41542
02602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.4154202602
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2482385744
Short name T1849
Test name
Test status
Simulation time 14500861753 ps
CPU time 19.24 seconds
Started Aug 09 05:25:23 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207848 kb
Host smart-017f6c99-bfd4-48cf-9249-6701b71be0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24823
85744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2482385744
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.985171415
Short name T1793
Test name
Test status
Simulation time 4177712481 ps
CPU time 5.91 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:31 PM PDT 24
Peak memory 207764 kb
Host smart-909c6d54-15e1-4aac-9640-a7b5b16fc6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98517
1415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.985171415
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.691835516
Short name T792
Test name
Test status
Simulation time 3845966347 ps
CPU time 28.81 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 219216 kb
Host smart-7c94d535-fdba-423d-9815-86978d5a814c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=691835516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.691835516
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1759433496
Short name T2454
Test name
Test status
Simulation time 2484415001 ps
CPU time 26.69 seconds
Started Aug 09 05:25:24 PM PDT 24
Finished Aug 09 05:25:51 PM PDT 24
Peak memory 216000 kb
Host smart-248a18ee-8ad3-4c25-b02e-6c3643aef9e3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1759433496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1759433496
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1548248827
Short name T3185
Test name
Test status
Simulation time 275326997 ps
CPU time 1.03 seconds
Started Aug 09 05:25:30 PM PDT 24
Finished Aug 09 05:25:32 PM PDT 24
Peak memory 207492 kb
Host smart-1b7cf7a6-fd90-4439-a75e-cbddcc0c90b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1548248827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1548248827
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.642881296
Short name T2703
Test name
Test status
Simulation time 259017918 ps
CPU time 0.97 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:27 PM PDT 24
Peak memory 207480 kb
Host smart-8781aef5-47a0-485f-836f-a21bf42a6b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64288
1296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.642881296
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.3369741500
Short name T1323
Test name
Test status
Simulation time 2094659327 ps
CPU time 20.44 seconds
Started Aug 09 05:25:36 PM PDT 24
Finished Aug 09 05:25:57 PM PDT 24
Peak memory 224104 kb
Host smart-4e87ced9-1e3a-4083-a75c-dff2b1499e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
41500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.3369741500
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.221712502
Short name T2869
Test name
Test status
Simulation time 2702838150 ps
CPU time 29.06 seconds
Started Aug 09 05:25:25 PM PDT 24
Finished Aug 09 05:25:54 PM PDT 24
Peak memory 218668 kb
Host smart-4d3c84b9-76c4-4f24-ba33-81a08b6ef329
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=221712502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.221712502
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.500684163
Short name T1396
Test name
Test status
Simulation time 4167096555 ps
CPU time 33.17 seconds
Started Aug 09 05:25:36 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 217752 kb
Host smart-758da42c-7440-48c4-9c0c-bc8bfc443479
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=500684163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.500684163
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.2212765103
Short name T2745
Test name
Test status
Simulation time 217721860 ps
CPU time 0.95 seconds
Started Aug 09 05:25:35 PM PDT 24
Finished Aug 09 05:25:36 PM PDT 24
Peak memory 207532 kb
Host smart-070511c6-0cb3-41df-a05b-884fe28347b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2212765103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.2212765103
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.479796212
Short name T696
Test name
Test status
Simulation time 146798990 ps
CPU time 0.9 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:25:40 PM PDT 24
Peak memory 207480 kb
Host smart-5dfd311f-08ca-44ab-915c-0001bd7a4bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47979
6212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.479796212
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1101693271
Short name T66
Test name
Test status
Simulation time 554843672 ps
CPU time 1.65 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:25:31 PM PDT 24
Peak memory 207316 kb
Host smart-498b5f06-1e4d-4d7e-91e5-8371e7d91d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11016
93271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1101693271
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.525621929
Short name T2904
Test name
Test status
Simulation time 249211359 ps
CPU time 1.05 seconds
Started Aug 09 05:25:29 PM PDT 24
Finished Aug 09 05:25:30 PM PDT 24
Peak memory 207504 kb
Host smart-ee45c0a1-dd17-487f-8d05-cee929c533b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52562
1929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.525621929
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.929671373
Short name T2965
Test name
Test status
Simulation time 198723011 ps
CPU time 0.95 seconds
Started Aug 09 05:25:35 PM PDT 24
Finished Aug 09 05:25:36 PM PDT 24
Peak memory 207500 kb
Host smart-cea18761-d567-4695-9485-c09422c78a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92967
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.929671373
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2901484498
Short name T1555
Test name
Test status
Simulation time 188261712 ps
CPU time 1 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:28 PM PDT 24
Peak memory 207524 kb
Host smart-a6780767-3095-48f7-a004-3c6df6581ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
84498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2901484498
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.898060138
Short name T491
Test name
Test status
Simulation time 148766542 ps
CPU time 0.82 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:25:48 PM PDT 24
Peak memory 207452 kb
Host smart-d2a209c8-2756-4c07-a491-58735295372d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89806
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.898060138
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1458482968
Short name T3009
Test name
Test status
Simulation time 162249702 ps
CPU time 0.83 seconds
Started Aug 09 05:25:30 PM PDT 24
Finished Aug 09 05:25:31 PM PDT 24
Peak memory 207524 kb
Host smart-426f4a38-8d83-4f78-869e-4286c22314e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
82968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1458482968
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3045494352
Short name T2002
Test name
Test status
Simulation time 176258470 ps
CPU time 0.91 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207408 kb
Host smart-f9e4a8e0-4c5b-490f-8d62-1cf9b541e125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30454
94352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.3045494352
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2219768311
Short name T2671
Test name
Test status
Simulation time 285712259 ps
CPU time 1.1 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:25:41 PM PDT 24
Peak memory 207808 kb
Host smart-7304d36a-73b4-49d7-9d4a-2ea202f9e5ca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2219768311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2219768311
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2236574270
Short name T889
Test name
Test status
Simulation time 227996611 ps
CPU time 0.96 seconds
Started Aug 09 05:25:23 PM PDT 24
Finished Aug 09 05:25:24 PM PDT 24
Peak memory 207408 kb
Host smart-af3371f2-3723-49be-b3a1-e13ef465ef00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
74270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2236574270
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.2212823403
Short name T1359
Test name
Test status
Simulation time 251231089 ps
CPU time 1.05 seconds
Started Aug 09 05:25:26 PM PDT 24
Finished Aug 09 05:25:27 PM PDT 24
Peak memory 207396 kb
Host smart-38f59e17-2bbb-42e1-9e1d-66d04861b54d
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2212823403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2212823403
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3564793237
Short name T3282
Test name
Test status
Simulation time 218973051 ps
CPU time 1.05 seconds
Started Aug 09 05:25:27 PM PDT 24
Finished Aug 09 05:25:28 PM PDT 24
Peak memory 207476 kb
Host smart-9845cc00-c284-4873-a4e4-c0415417b509
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3564793237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3564793237
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.443297909
Short name T3292
Test name
Test status
Simulation time 160666074 ps
CPU time 0.83 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:25:33 PM PDT 24
Peak memory 207528 kb
Host smart-76e636d8-2442-49fd-baae-2e30ff7fc169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44329
7909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.443297909
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.606956995
Short name T2198
Test name
Test status
Simulation time 36457443 ps
CPU time 0.7 seconds
Started Aug 09 05:25:33 PM PDT 24
Finished Aug 09 05:25:34 PM PDT 24
Peak memory 207348 kb
Host smart-38df7649-72bc-4532-8af6-0ae9b7af3b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60695
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.606956995
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3945432582
Short name T2636
Test name
Test status
Simulation time 10598847725 ps
CPU time 25.05 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:25:57 PM PDT 24
Peak memory 215924 kb
Host smart-dfd942ba-72db-465b-bd50-a524e854f619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
32582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3945432582
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1608366007
Short name T3131
Test name
Test status
Simulation time 181721148 ps
CPU time 0.93 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:25:40 PM PDT 24
Peak memory 207792 kb
Host smart-2a450791-1d09-4f67-9771-3583b7b58586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
66007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1608366007
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.211675800
Short name T519
Test name
Test status
Simulation time 194176397 ps
CPU time 0.91 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:25:33 PM PDT 24
Peak memory 207404 kb
Host smart-e5859afa-e59e-451b-bf5a-9eeeb53da338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21167
5800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.211675800
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3449187199
Short name T2032
Test name
Test status
Simulation time 6012948520 ps
CPU time 72.77 seconds
Started Aug 09 05:25:44 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 216084 kb
Host smart-2ee465b1-9712-4a69-a425-f999c87dea44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449187199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3449187199
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2899540178
Short name T2221
Test name
Test status
Simulation time 13917106848 ps
CPU time 98.49 seconds
Started Aug 09 05:25:34 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 224164 kb
Host smart-71662c31-ca5d-43b3-aaf4-206d3eb36b5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2899540178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2899540178
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1870225243
Short name T1092
Test name
Test status
Simulation time 5926441311 ps
CPU time 27.39 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:26:00 PM PDT 24
Peak memory 219076 kb
Host smart-2e97e371-0bb2-42b1-a32b-9bed984676b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870225243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1870225243
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.2140670838
Short name T649
Test name
Test status
Simulation time 281866604 ps
CPU time 1.02 seconds
Started Aug 09 05:25:46 PM PDT 24
Finished Aug 09 05:25:47 PM PDT 24
Peak memory 207376 kb
Host smart-e1282e03-cb51-4271-97cd-4e9bccf1d947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21406
70838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.2140670838
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1542514780
Short name T2672
Test name
Test status
Simulation time 175684563 ps
CPU time 0.97 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207420 kb
Host smart-8a3c7b1f-b038-402c-b79f-a0502634749d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15425
14780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1542514780
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.3601720497
Short name T1088
Test name
Test status
Simulation time 20186674644 ps
CPU time 23.2 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207480 kb
Host smart-1dd32368-4b7e-4ebc-95fe-ab3982b6558b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
20497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.3601720497
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1520467343
Short name T3379
Test name
Test status
Simulation time 291997035 ps
CPU time 1.27 seconds
Started Aug 09 05:25:35 PM PDT 24
Finished Aug 09 05:25:36 PM PDT 24
Peak memory 207512 kb
Host smart-cfc53d29-7b0c-4e8d-a2af-291ab178bec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
67343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1520467343
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3584290090
Short name T1461
Test name
Test status
Simulation time 208817327 ps
CPU time 0.99 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:25:40 PM PDT 24
Peak memory 207496 kb
Host smart-5cda680f-3b53-4d2e-a678-3173a18b74c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
90090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3584290090
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3105967881
Short name T1736
Test name
Test status
Simulation time 198185437 ps
CPU time 0.97 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207448 kb
Host smart-bae48099-8209-4aa7-9277-0aa672f68829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
67881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3105967881
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1266856023
Short name T466
Test name
Test status
Simulation time 147353365 ps
CPU time 0.85 seconds
Started Aug 09 05:25:36 PM PDT 24
Finished Aug 09 05:25:37 PM PDT 24
Peak memory 207412 kb
Host smart-1163fe85-1926-4b3a-848a-37712b29d143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12668
56023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1266856023
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2202691319
Short name T1132
Test name
Test status
Simulation time 240885320 ps
CPU time 0.99 seconds
Started Aug 09 05:25:33 PM PDT 24
Finished Aug 09 05:25:34 PM PDT 24
Peak memory 207504 kb
Host smart-8d62bec0-cab6-4c55-9d2d-62228e915093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22026
91319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2202691319
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1905353140
Short name T2349
Test name
Test status
Simulation time 2327447320 ps
CPU time 66.27 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 218076 kb
Host smart-0c24f3ef-9b9b-4306-99ef-819f8d2dedde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1905353140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1905353140
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.773961975
Short name T1966
Test name
Test status
Simulation time 152131255 ps
CPU time 0.89 seconds
Started Aug 09 05:25:31 PM PDT 24
Finished Aug 09 05:25:32 PM PDT 24
Peak memory 207504 kb
Host smart-f9eacf1a-200c-46bb-be92-9d136ce3b394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77396
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.773961975
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3700666881
Short name T574
Test name
Test status
Simulation time 210436035 ps
CPU time 0.91 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207424 kb
Host smart-f629fcf7-cc5a-4c69-8e42-63dba9d4b1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
66881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3700666881
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.262468481
Short name T3065
Test name
Test status
Simulation time 1078577574 ps
CPU time 2.7 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:25:41 PM PDT 24
Peak memory 207668 kb
Host smart-4c91e064-5c67-4c25-acd3-df985a807376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
8481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.262468481
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.941349339
Short name T2709
Test name
Test status
Simulation time 2055557844 ps
CPU time 57.76 seconds
Started Aug 09 05:25:32 PM PDT 24
Finished Aug 09 05:26:30 PM PDT 24
Peak memory 224152 kb
Host smart-59a077c0-8488-4388-8ae2-44204dd1b80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94134
9339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.941349339
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.649264850
Short name T101
Test name
Test status
Simulation time 13341179790 ps
CPU time 83.44 seconds
Started Aug 09 05:25:34 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 216372 kb
Host smart-519c6525-2ebb-4320-9ac4-b862eb6d02bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649264850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.649264850
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.3179250917
Short name T1147
Test name
Test status
Simulation time 4792141736 ps
CPU time 43.18 seconds
Started Aug 09 05:25:24 PM PDT 24
Finished Aug 09 05:26:08 PM PDT 24
Peak memory 207736 kb
Host smart-c7b432f9-218f-44db-8b21-153e29e367e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179250917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.3179250917
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.399716253
Short name T1462
Test name
Test status
Simulation time 633161862 ps
CPU time 1.8 seconds
Started Aug 09 05:25:43 PM PDT 24
Finished Aug 09 05:25:45 PM PDT 24
Peak memory 207392 kb
Host smart-df7c8ad7-7522-49d8-9dc0-35e0970d4bbb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399716253 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.399716253
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3566153489
Short name T1943
Test name
Test status
Simulation time 37711489 ps
CPU time 0.7 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 207520 kb
Host smart-43786b11-d1d0-4753-8743-b9e1db10c6a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3566153489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3566153489
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3184573076
Short name T3171
Test name
Test status
Simulation time 10439186442 ps
CPU time 13.21 seconds
Started Aug 09 05:25:36 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207808 kb
Host smart-52c02e4f-91e6-4fd7-9649-9bda8813b324
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184573076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.3184573076
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2179391875
Short name T1151
Test name
Test status
Simulation time 15167985580 ps
CPU time 20.44 seconds
Started Aug 09 05:25:33 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 216048 kb
Host smart-2bfd3946-8afc-44c7-9168-775f0e92eaab
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179391875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2179391875
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3391483250
Short name T1807
Test name
Test status
Simulation time 23301055596 ps
CPU time 27.57 seconds
Started Aug 09 05:25:33 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 215844 kb
Host smart-d63d5f33-5480-40f4-8cb3-dd612e02d45e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391483250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.3391483250
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1852884860
Short name T1974
Test name
Test status
Simulation time 231605952 ps
CPU time 0.96 seconds
Started Aug 09 05:25:46 PM PDT 24
Finished Aug 09 05:25:47 PM PDT 24
Peak memory 207408 kb
Host smart-f22c47ea-bc91-4f11-8f6e-d912f834c118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18528
84860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1852884860
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.519392551
Short name T3513
Test name
Test status
Simulation time 177024563 ps
CPU time 0.91 seconds
Started Aug 09 05:25:35 PM PDT 24
Finished Aug 09 05:25:36 PM PDT 24
Peak memory 207508 kb
Host smart-125d1f3a-969f-4994-8304-819ddf45f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51939
2551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.519392551
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.105463661
Short name T3594
Test name
Test status
Simulation time 181330163 ps
CPU time 0.9 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:25:52 PM PDT 24
Peak memory 207356 kb
Host smart-f1774d98-e39f-423e-9e82-1aece979a73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10546
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.105463661
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2093658882
Short name T3309
Test name
Test status
Simulation time 209709471 ps
CPU time 0.93 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207424 kb
Host smart-c9cf18a1-4feb-4839-9634-315994bec0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20936
58882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2093658882
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1122632486
Short name T778
Test name
Test status
Simulation time 481585283 ps
CPU time 1.62 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207472 kb
Host smart-848c48a2-5eb2-463b-a25e-e6786c71298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
32486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1122632486
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2317258924
Short name T317
Test name
Test status
Simulation time 549506606 ps
CPU time 1.69 seconds
Started Aug 09 05:25:40 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207492 kb
Host smart-d0a781e4-4ba6-4822-b412-f8952ba10e62
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2317258924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2317258924
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2080469584
Short name T1632
Test name
Test status
Simulation time 40619470712 ps
CPU time 70.59 seconds
Started Aug 09 05:25:40 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207796 kb
Host smart-a41a1542-e06a-4779-b847-c1df3f8ed1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20804
69584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2080469584
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.3327620643
Short name T806
Test name
Test status
Simulation time 989608612 ps
CPU time 21.93 seconds
Started Aug 09 05:25:44 PM PDT 24
Finished Aug 09 05:26:06 PM PDT 24
Peak memory 207584 kb
Host smart-7d01428d-4fcb-471f-9d66-45211de85a02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327620643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.3327620643
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2549602146
Short name T1541
Test name
Test status
Simulation time 676161362 ps
CPU time 1.62 seconds
Started Aug 09 05:25:43 PM PDT 24
Finished Aug 09 05:25:45 PM PDT 24
Peak memory 207380 kb
Host smart-31faa3e8-fa20-4a11-aa5c-fe60da5b5b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
02146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2549602146
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.685294875
Short name T1540
Test name
Test status
Simulation time 165553850 ps
CPU time 0.85 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207400 kb
Host smart-f3109ad4-729d-4ef6-941a-3a75bef7d4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68529
4875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.685294875
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.158256561
Short name T1274
Test name
Test status
Simulation time 46755647 ps
CPU time 0.85 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207464 kb
Host smart-beb2101c-a5a4-4986-94bd-38a7e8f72579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.158256561
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4217753563
Short name T1077
Test name
Test status
Simulation time 895239937 ps
CPU time 2.46 seconds
Started Aug 09 05:25:43 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207740 kb
Host smart-c76177b4-f9a7-4299-944a-c07d7f943277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
53563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4217753563
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.4048250468
Short name T3484
Test name
Test status
Simulation time 475963819 ps
CPU time 1.5 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207436 kb
Host smart-4564bf6c-a781-4b46-8272-928ef936291d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4048250468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.4048250468
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2860782205
Short name T2294
Test name
Test status
Simulation time 351492338 ps
CPU time 2.56 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:44 PM PDT 24
Peak memory 207648 kb
Host smart-8c3d8509-3c93-4e61-a6e5-75095638c0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607
82205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2860782205
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1248588623
Short name T2946
Test name
Test status
Simulation time 94184273644 ps
CPU time 149.95 seconds
Started Aug 09 05:25:46 PM PDT 24
Finished Aug 09 05:28:16 PM PDT 24
Peak memory 207732 kb
Host smart-9f40c2e6-6db6-4a8a-b3a5-d37093127499
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1248588623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1248588623
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2215762449
Short name T2109
Test name
Test status
Simulation time 121472749037 ps
CPU time 181.17 seconds
Started Aug 09 05:25:40 PM PDT 24
Finished Aug 09 05:28:41 PM PDT 24
Peak memory 207864 kb
Host smart-d092b510-a865-4b0b-a6f9-c5646a8344bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215762449 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2215762449
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.398553463
Short name T1812
Test name
Test status
Simulation time 84132711757 ps
CPU time 146.54 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207852 kb
Host smart-7edd00fd-e67e-4586-8a5b-fa5fcc4dcde5
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=398553463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.398553463
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.361147350
Short name T1918
Test name
Test status
Simulation time 113226687922 ps
CPU time 196.69 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207860 kb
Host smart-55eca652-42c2-488c-acb5-5b425789ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361147350 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.361147350
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.2244733642
Short name T1500
Test name
Test status
Simulation time 90126152098 ps
CPU time 128.3 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207812 kb
Host smart-6c0f25d6-1a1f-45b2-90e8-c54f156967bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22447
33642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2244733642
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1826705955
Short name T1415
Test name
Test status
Simulation time 231428263 ps
CPU time 1.17 seconds
Started Aug 09 05:25:46 PM PDT 24
Finished Aug 09 05:25:47 PM PDT 24
Peak memory 215916 kb
Host smart-1760ba8d-ce96-4943-a6a5-ed349c4b3a96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1826705955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1826705955
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1419835174
Short name T2306
Test name
Test status
Simulation time 139847889 ps
CPU time 0.8 seconds
Started Aug 09 05:25:40 PM PDT 24
Finished Aug 09 05:25:41 PM PDT 24
Peak memory 207440 kb
Host smart-7bc90559-c417-4554-bd71-4862442c8ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14198
35174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1419835174
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.956979222
Short name T948
Test name
Test status
Simulation time 180316645 ps
CPU time 0.94 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207436 kb
Host smart-e1257c5f-6fe7-4a99-b76a-84f6c48a72fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95697
9222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.956979222
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.100788363
Short name T1662
Test name
Test status
Simulation time 2595807775 ps
CPU time 27.14 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 218348 kb
Host smart-3c499bb8-2b35-49ed-a64f-2cb552909298
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=100788363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.100788363
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1762018288
Short name T2962
Test name
Test status
Simulation time 12258430658 ps
CPU time 144.31 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207752 kb
Host smart-c8d1d0be-f969-4eee-b90a-84bcaf13f162
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1762018288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1762018288
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3085627261
Short name T3354
Test name
Test status
Simulation time 228489506 ps
CPU time 1.01 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207508 kb
Host smart-7e133b70-b2c5-47b7-8e15-6990910aed41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30856
27261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3085627261
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.459357739
Short name T3568
Test name
Test status
Simulation time 23596339669 ps
CPU time 32.64 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 216012 kb
Host smart-37892f87-e1b3-4dd0-93f6-d12d7a3245a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45935
7739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.459357739
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3262196516
Short name T1625
Test name
Test status
Simulation time 3801908512 ps
CPU time 39.8 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 218640 kb
Host smart-f95e6a3d-0007-44b8-b2ed-5bce08f01494
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3262196516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3262196516
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.4217891684
Short name T1291
Test name
Test status
Simulation time 2528445068 ps
CPU time 24.88 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 224220 kb
Host smart-2ef9b116-eea3-40b6-8efe-e80da8581387
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4217891684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.4217891684
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1717169662
Short name T3286
Test name
Test status
Simulation time 249408618 ps
CPU time 1 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207492 kb
Host smart-26ce4618-c77f-44e7-a64a-ed49aac62045
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1717169662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1717169662
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2512448072
Short name T3405
Test name
Test status
Simulation time 201341080 ps
CPU time 1.02 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207548 kb
Host smart-ce468b6a-8724-460c-999c-1348a9916e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25124
48072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2512448072
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.377815468
Short name T1099
Test name
Test status
Simulation time 2155393818 ps
CPU time 16.85 seconds
Started Aug 09 05:25:50 PM PDT 24
Finished Aug 09 05:26:07 PM PDT 24
Peak memory 224220 kb
Host smart-0f8d0ba9-ff8f-44f8-942f-537ea4a4babd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
5468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.377815468
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.131635309
Short name T2309
Test name
Test status
Simulation time 2659569895 ps
CPU time 74.36 seconds
Started Aug 09 05:25:50 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 224272 kb
Host smart-86c9f22f-1cdc-4584-a5df-8bcd8348a4ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=131635309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.131635309
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4004513478
Short name T2450
Test name
Test status
Simulation time 2170106397 ps
CPU time 18 seconds
Started Aug 09 05:25:40 PM PDT 24
Finished Aug 09 05:25:58 PM PDT 24
Peak memory 217488 kb
Host smart-62354026-95cc-4834-abb4-9d8770abb7be
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4004513478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4004513478
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.522469580
Short name T879
Test name
Test status
Simulation time 244975782 ps
CPU time 0.96 seconds
Started Aug 09 05:25:43 PM PDT 24
Finished Aug 09 05:25:44 PM PDT 24
Peak memory 207492 kb
Host smart-8ef6522c-59c1-4c83-b5ac-0b67311b78d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=522469580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.522469580
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3199639752
Short name T692
Test name
Test status
Simulation time 153260880 ps
CPU time 0.87 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207436 kb
Host smart-fa49e73c-f05c-4c3b-968f-6bbeec120cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
39752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3199639752
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1699012923
Short name T2384
Test name
Test status
Simulation time 189162488 ps
CPU time 0.93 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207432 kb
Host smart-afd1a195-1377-4a58-90e9-507436091f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16990
12923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1699012923
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3483152685
Short name T1232
Test name
Test status
Simulation time 175186472 ps
CPU time 0.9 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207484 kb
Host smart-7e366522-bd49-43c0-b2f7-b1319ec98a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34831
52685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3483152685
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1638178866
Short name T684
Test name
Test status
Simulation time 172614692 ps
CPU time 0.86 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207508 kb
Host smart-0f02cfda-32ac-438b-a1a4-9696287e689e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16381
78866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1638178866
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.319989940
Short name T1663
Test name
Test status
Simulation time 150991369 ps
CPU time 0.87 seconds
Started Aug 09 05:25:41 PM PDT 24
Finished Aug 09 05:25:42 PM PDT 24
Peak memory 207424 kb
Host smart-1d679adb-3543-4e44-824e-751acc55917b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
9940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.319989940
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3608834150
Short name T2792
Test name
Test status
Simulation time 212438630 ps
CPU time 1 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:25:48 PM PDT 24
Peak memory 207428 kb
Host smart-a4a773d9-5eb5-4119-a2f7-99dc9be1681b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3608834150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3608834150
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.379820992
Short name T2122
Test name
Test status
Simulation time 201897693 ps
CPU time 0.97 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207504 kb
Host smart-dcd16682-00eb-4e03-a1c1-73010a02a25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37982
0992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.379820992
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3612434381
Short name T1613
Test name
Test status
Simulation time 143695114 ps
CPU time 0.81 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207328 kb
Host smart-19f98988-fd1a-4c83-b69e-c5c679b8c904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
34381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3612434381
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2019818618
Short name T1011
Test name
Test status
Simulation time 65936346 ps
CPU time 0.83 seconds
Started Aug 09 05:25:44 PM PDT 24
Finished Aug 09 05:25:45 PM PDT 24
Peak memory 207448 kb
Host smart-5deedca4-8340-472e-ab4e-c4d652568cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20198
18618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2019818618
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2688196056
Short name T2111
Test name
Test status
Simulation time 19023820623 ps
CPU time 50.19 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:26:38 PM PDT 24
Peak memory 215924 kb
Host smart-73527584-60c3-432b-99aa-edbc59a441ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26881
96056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2688196056
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3481613084
Short name T2425
Test name
Test status
Simulation time 200526012 ps
CPU time 0.97 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207512 kb
Host smart-8e5efa9f-3aeb-452f-8cf5-c960e32f2bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34816
13084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3481613084
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3418711295
Short name T2917
Test name
Test status
Simulation time 234936945 ps
CPU time 1.01 seconds
Started Aug 09 05:25:45 PM PDT 24
Finished Aug 09 05:25:46 PM PDT 24
Peak memory 207452 kb
Host smart-f4dc1988-e608-4e65-a839-ce19f116fa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
11295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3418711295
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.283266531
Short name T168
Test name
Test status
Simulation time 3875779478 ps
CPU time 25.13 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:26:17 PM PDT 24
Peak memory 218656 kb
Host smart-db5a788f-2721-4b84-9fde-3085364c4684
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=283266531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.283266531
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1621303184
Short name T2549
Test name
Test status
Simulation time 5854801784 ps
CPU time 27.12 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:26:16 PM PDT 24
Peak memory 224204 kb
Host smart-0393a5ff-a9bf-4e43-b0e4-d134e2590bf5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1621303184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1621303184
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3607818786
Short name T2918
Test name
Test status
Simulation time 5971864029 ps
CPU time 28.69 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 218676 kb
Host smart-c4925710-b20c-4fb3-a40f-53f43e58e63c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607818786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3607818786
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1091206959
Short name T2346
Test name
Test status
Simulation time 200084740 ps
CPU time 0.94 seconds
Started Aug 09 05:25:42 PM PDT 24
Finished Aug 09 05:25:43 PM PDT 24
Peak memory 207500 kb
Host smart-a18524e2-208a-43c2-a17f-33860db61784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
06959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1091206959
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3899327197
Short name T558
Test name
Test status
Simulation time 188405203 ps
CPU time 1 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207384 kb
Host smart-e075d0c4-95c7-48fd-bd0d-91ee2b34d7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
27197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3899327197
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.35950921
Short name T2102
Test name
Test status
Simulation time 20194759912 ps
CPU time 23.17 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:24 PM PDT 24
Peak memory 207300 kb
Host smart-6dda8d0c-4d4b-4ddb-a1b0-d7cad662e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.35950921
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1241644458
Short name T2354
Test name
Test status
Simulation time 161489258 ps
CPU time 0.88 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207440 kb
Host smart-79ddf7cc-01e8-4734-9a81-13915cf9c03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12416
44458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1241644458
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.3596224686
Short name T3448
Test name
Test status
Simulation time 402482593 ps
CPU time 1.32 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207512 kb
Host smart-101ae179-1451-4203-8a6d-c29eb096010e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35962
24686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.3596224686
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2013609237
Short name T76
Test name
Test status
Simulation time 170520152 ps
CPU time 0.88 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207504 kb
Host smart-fe34c4b5-b62e-4b7e-91c8-edd94ccbbce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
09237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2013609237
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2423103482
Short name T216
Test name
Test status
Simulation time 439896919 ps
CPU time 1.41 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 223556 kb
Host smart-8d3cb376-d781-4d9b-86e0-c479f926edc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2423103482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2423103482
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.4140961459
Short name T2900
Test name
Test status
Simulation time 429722865 ps
CPU time 1.41 seconds
Started Aug 09 05:25:50 PM PDT 24
Finished Aug 09 05:25:52 PM PDT 24
Peak memory 207548 kb
Host smart-0eecbe21-3ff8-4586-8f0c-1d5aade742a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
61459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.4140961459
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2309480239
Short name T178
Test name
Test status
Simulation time 218619875 ps
CPU time 1 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207552 kb
Host smart-1c4563e2-6da8-46fb-a164-76a01b5468c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23094
80239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2309480239
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.163439596
Short name T1026
Test name
Test status
Simulation time 210638709 ps
CPU time 0.88 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207472 kb
Host smart-a60932d7-f061-4bee-9221-f73b623377b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.163439596
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3223176644
Short name T1790
Test name
Test status
Simulation time 153184200 ps
CPU time 0.85 seconds
Started Aug 09 05:25:50 PM PDT 24
Finished Aug 09 05:25:51 PM PDT 24
Peak memory 207552 kb
Host smart-c1384100-58f0-4426-9b49-4022583f49b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32231
76644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3223176644
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1398280263
Short name T3225
Test name
Test status
Simulation time 250438510 ps
CPU time 1.1 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:25:54 PM PDT 24
Peak memory 207444 kb
Host smart-d6b334d9-b2f7-45e0-9748-4fb484bb2a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13982
80263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1398280263
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1757191742
Short name T3632
Test name
Test status
Simulation time 172802681 ps
CPU time 0.96 seconds
Started Aug 09 05:25:47 PM PDT 24
Finished Aug 09 05:25:48 PM PDT 24
Peak memory 207508 kb
Host smart-94e550dd-80ce-459d-bc02-3f1faca73d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17571
91742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1757191742
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1005941574
Short name T811
Test name
Test status
Simulation time 1234792314 ps
CPU time 3.21 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:52 PM PDT 24
Peak memory 207616 kb
Host smart-33b7e17d-8e24-4092-a4a1-e77718cbec3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10059
41574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1005941574
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3292286002
Short name T518
Test name
Test status
Simulation time 2135118097 ps
CPU time 21.53 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:26:16 PM PDT 24
Peak memory 216508 kb
Host smart-12600723-513c-465a-b346-a99830219082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
86002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3292286002
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.170928169
Short name T2686
Test name
Test status
Simulation time 1522281841 ps
CPU time 37.63 seconds
Started Aug 09 05:25:39 PM PDT 24
Finished Aug 09 05:26:17 PM PDT 24
Peak memory 207640 kb
Host smart-fc8c522c-f794-40d7-8eb1-566825f25e05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170928169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host_
handshake.170928169
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.847976757
Short name T1372
Test name
Test status
Simulation time 587204049 ps
CPU time 1.64 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 207480 kb
Host smart-d2999e39-dfa4-4722-8af9-dd10965f4530
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847976757 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.847976757
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3546944496
Short name T2237
Test name
Test status
Simulation time 58150669 ps
CPU time 0.69 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207392 kb
Host smart-05d51a44-becf-489f-928c-280aac1e9bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3546944496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3546944496
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1605022399
Short name T1752
Test name
Test status
Simulation time 4819398965 ps
CPU time 7.31 seconds
Started Aug 09 05:27:25 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 215996 kb
Host smart-20448539-c10a-4b5a-b8a3-67db64507285
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605022399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.1605022399
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1688660890
Short name T2593
Test name
Test status
Simulation time 14433633821 ps
CPU time 16.9 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:37 PM PDT 24
Peak memory 215984 kb
Host smart-4117bd21-3b51-4558-9833-26440809831e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688660890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1688660890
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3392342373
Short name T1823
Test name
Test status
Simulation time 25696173755 ps
CPU time 33.57 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 215896 kb
Host smart-1dcf692a-f203-4872-b195-404b7aea10ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392342373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.3392342373
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2026989342
Short name T157
Test name
Test status
Simulation time 156411477 ps
CPU time 0.86 seconds
Started Aug 09 05:27:23 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207504 kb
Host smart-c701450a-80f3-48f0-b547-297252886a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20269
89342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2026989342
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3862022989
Short name T1438
Test name
Test status
Simulation time 177427336 ps
CPU time 0.89 seconds
Started Aug 09 05:27:23 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207476 kb
Host smart-5e05c9e1-edb3-47f1-85f6-0d1517912918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
22989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3862022989
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2668567222
Short name T3423
Test name
Test status
Simulation time 161114341 ps
CPU time 0.89 seconds
Started Aug 09 05:27:19 PM PDT 24
Finished Aug 09 05:27:20 PM PDT 24
Peak memory 207452 kb
Host smart-9e2bdfde-e7ef-49df-b06f-167e06e91f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685
67222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2668567222
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.446669469
Short name T2021
Test name
Test status
Simulation time 526892840 ps
CPU time 1.66 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207504 kb
Host smart-25f3748e-b88c-4c49-b627-c44728cbd3ec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=446669469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.446669469
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3172416386
Short name T1965
Test name
Test status
Simulation time 20454560937 ps
CPU time 34.88 seconds
Started Aug 09 05:27:19 PM PDT 24
Finished Aug 09 05:27:54 PM PDT 24
Peak memory 207820 kb
Host smart-631a9ecd-d4f4-49a5-b8a7-282c01bf74bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
16386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3172416386
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.2036552720
Short name T2468
Test name
Test status
Simulation time 571602162 ps
CPU time 11.95 seconds
Started Aug 09 05:27:25 PM PDT 24
Finished Aug 09 05:27:37 PM PDT 24
Peak memory 207628 kb
Host smart-896ee273-edb6-478c-ada0-f4045182caea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036552720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.2036552720
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3979110556
Short name T2798
Test name
Test status
Simulation time 603812229 ps
CPU time 1.82 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:23 PM PDT 24
Peak memory 207400 kb
Host smart-ac308f99-ed8a-4876-88d4-d11dc578138c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
10556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3979110556
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3636237865
Short name T1850
Test name
Test status
Simulation time 136166678 ps
CPU time 0.8 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207396 kb
Host smart-4328791e-2a48-4d98-8b00-a087f34b599b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
37865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3636237865
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1030945865
Short name T3591
Test name
Test status
Simulation time 50349330 ps
CPU time 0.69 seconds
Started Aug 09 05:27:19 PM PDT 24
Finished Aug 09 05:27:20 PM PDT 24
Peak memory 207400 kb
Host smart-ef6a2e9d-6b29-44ed-ab3e-a032f878ffac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309
45865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1030945865
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3271870234
Short name T838
Test name
Test status
Simulation time 827573203 ps
CPU time 2.13 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:23 PM PDT 24
Peak memory 207772 kb
Host smart-e5a05261-d7e6-4d25-80f0-fc14602716c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
70234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3271870234
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.3857840367
Short name T2948
Test name
Test status
Simulation time 284092172 ps
CPU time 1.03 seconds
Started Aug 09 05:27:28 PM PDT 24
Finished Aug 09 05:27:29 PM PDT 24
Peak memory 207480 kb
Host smart-0e4679d8-7624-4486-9e0b-29f6c67155d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3857840367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.3857840367
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.280061688
Short name T2696
Test name
Test status
Simulation time 375404866 ps
CPU time 2.57 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:23 PM PDT 24
Peak memory 207640 kb
Host smart-04c24628-47d3-466b-876f-9288e687abf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006
1688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.280061688
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2592024551
Short name T1978
Test name
Test status
Simulation time 184800366 ps
CPU time 0.97 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207500 kb
Host smart-470d2520-c9f8-4b33-b02b-53079fab4999
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2592024551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2592024551
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1055115599
Short name T1762
Test name
Test status
Simulation time 145094789 ps
CPU time 0.85 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207444 kb
Host smart-d2cb4edc-c12e-4356-8eb9-dc64da6ec79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10551
15599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1055115599
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3086743006
Short name T2668
Test name
Test status
Simulation time 269921902 ps
CPU time 1.05 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207480 kb
Host smart-7bd10498-2632-44f9-8b12-5237ab724b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30867
43006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3086743006
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2212312810
Short name T2599
Test name
Test status
Simulation time 3586051250 ps
CPU time 99.96 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:29:07 PM PDT 24
Peak memory 218500 kb
Host smart-508c4818-8e4f-47df-800f-af29bd2251ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2212312810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2212312810
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.255459962
Short name T2025
Test name
Test status
Simulation time 12415573372 ps
CPU time 138.44 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207748 kb
Host smart-13c8caeb-85c3-4da5-ad33-927be5475a1e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=255459962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.255459962
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3692835779
Short name T1748
Test name
Test status
Simulation time 199144072 ps
CPU time 0.93 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207500 kb
Host smart-ef2b5f55-3b23-40c7-9058-3aa11dd895c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36928
35779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3692835779
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2896005344
Short name T1447
Test name
Test status
Simulation time 13951076906 ps
CPU time 20.7 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 207680 kb
Host smart-7fecddba-0a4d-42c3-9f16-202f23394b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28960
05344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2896005344
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.203091339
Short name T3538
Test name
Test status
Simulation time 4353260667 ps
CPU time 5.6 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 216100 kb
Host smart-a4e87651-7e49-45ab-bc25-afded5cfdfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20309
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.203091339
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2400109116
Short name T1671
Test name
Test status
Simulation time 3843669170 ps
CPU time 117.99 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:29:18 PM PDT 24
Peak memory 218960 kb
Host smart-487db834-9425-4d13-ac3c-27f98241e376
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2400109116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2400109116
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2165856377
Short name T3421
Test name
Test status
Simulation time 2444627036 ps
CPU time 69.09 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:28:31 PM PDT 24
Peak memory 216060 kb
Host smart-adad49ab-2b1f-47d2-9555-02355f7498a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2165856377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2165856377
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1694994889
Short name T1058
Test name
Test status
Simulation time 238650473 ps
CPU time 1.02 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207500 kb
Host smart-c2c9e405-e3c4-4886-996c-b03b7ee19aa6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1694994889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1694994889
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2776659507
Short name T2981
Test name
Test status
Simulation time 186129734 ps
CPU time 1.02 seconds
Started Aug 09 05:27:23 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207504 kb
Host smart-e39a7cdc-a6e5-4327-98a7-8d1a88536b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
59507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2776659507
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.2146566758
Short name T3088
Test name
Test status
Simulation time 3092570123 ps
CPU time 31.74 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 217980 kb
Host smart-ca084892-e281-40ce-957b-655218093f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
66758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.2146566758
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3751987524
Short name T2997
Test name
Test status
Simulation time 3294879099 ps
CPU time 28.64 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 224176 kb
Host smart-4220ff22-b406-43d7-897d-6b8abc6cfc37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3751987524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3751987524
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3071973496
Short name T1439
Test name
Test status
Simulation time 2423835688 ps
CPU time 19.29 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:42 PM PDT 24
Peak memory 215940 kb
Host smart-78fd05c6-e663-4cdf-8ed5-38fca7ab68ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3071973496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3071973496
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2933998726
Short name T1750
Test name
Test status
Simulation time 154373577 ps
CPU time 0.82 seconds
Started Aug 09 05:27:24 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207520 kb
Host smart-05bfcbfe-dcfd-497c-9b2c-e065e2c7090c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2933998726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2933998726
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2764558996
Short name T1315
Test name
Test status
Simulation time 193700341 ps
CPU time 0.94 seconds
Started Aug 09 05:27:24 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 207528 kb
Host smart-fdc6e4a9-2f45-4031-8b80-c7b5bdeb3a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
58996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2764558996
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.384175716
Short name T1775
Test name
Test status
Simulation time 187795413 ps
CPU time 0.98 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 207476 kb
Host smart-7ad7532d-ee16-4671-a877-af075079807a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417
5716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.384175716
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.699898593
Short name T1719
Test name
Test status
Simulation time 193592650 ps
CPU time 0.95 seconds
Started Aug 09 05:27:25 PM PDT 24
Finished Aug 09 05:27:26 PM PDT 24
Peak memory 207556 kb
Host smart-9a16424d-8024-4318-be31-bdfd80d3683b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69989
8593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.699898593
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1229287715
Short name T730
Test name
Test status
Simulation time 186949965 ps
CPU time 0.95 seconds
Started Aug 09 05:27:31 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207400 kb
Host smart-bed20ae5-10c5-46f6-a750-f8332bd6017e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
87715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1229287715
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2664928098
Short name T825
Test name
Test status
Simulation time 152024055 ps
CPU time 0.92 seconds
Started Aug 09 05:27:26 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 207560 kb
Host smart-0ac582e4-57c5-4305-9995-ea8d594b06d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26649
28098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2664928098
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3859367994
Short name T2436
Test name
Test status
Simulation time 187943749 ps
CPU time 0.92 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:23 PM PDT 24
Peak memory 207524 kb
Host smart-39d38286-a745-45a1-8fd0-c7f88f6eeb41
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3859367994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3859367994
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.4198434973
Short name T3516
Test name
Test status
Simulation time 146570080 ps
CPU time 0.89 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207484 kb
Host smart-30aa51f7-8b85-4132-a03b-98953ff12bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
34973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.4198434973
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2541613998
Short name T3022
Test name
Test status
Simulation time 42759584 ps
CPU time 0.69 seconds
Started Aug 09 05:27:24 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207240 kb
Host smart-8903643b-5a00-4fe9-8650-c6d8906da4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25416
13998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2541613998
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1742324575
Short name T2808
Test name
Test status
Simulation time 12521606065 ps
CPU time 32.9 seconds
Started Aug 09 05:27:24 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 215996 kb
Host smart-2f816047-b71f-4c33-8e7c-f74ac3dd7242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17423
24575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1742324575
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1601296555
Short name T1568
Test name
Test status
Simulation time 162502541 ps
CPU time 0.85 seconds
Started Aug 09 05:27:22 PM PDT 24
Finished Aug 09 05:27:23 PM PDT 24
Peak memory 207556 kb
Host smart-fbae1d50-8e10-4f4a-bb70-ecf795407f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16012
96555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1601296555
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3968350358
Short name T2933
Test name
Test status
Simulation time 182958125 ps
CPU time 0.94 seconds
Started Aug 09 05:27:26 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 207528 kb
Host smart-fe455eb4-1c04-4221-bb39-7ff2cc434b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
50358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3968350358
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3628077850
Short name T1853
Test name
Test status
Simulation time 198661936 ps
CPU time 0.89 seconds
Started Aug 09 05:27:24 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 207432 kb
Host smart-94492df0-1018-4ea7-a1a9-32d753288b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
77850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3628077850
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3667856957
Short name T1936
Test name
Test status
Simulation time 163468624 ps
CPU time 0.87 seconds
Started Aug 09 05:27:26 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 207488 kb
Host smart-51ff0478-d9e6-47f1-ba96-e8553b2feb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
56957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3667856957
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.1079549329
Short name T2064
Test name
Test status
Simulation time 20179780625 ps
CPU time 24.36 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:51 PM PDT 24
Peak memory 207612 kb
Host smart-5b591caf-be6c-45bb-b094-8b6b0acd33ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
49329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.1079549329
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3028391271
Short name T1283
Test name
Test status
Simulation time 153060703 ps
CPU time 0.85 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207484 kb
Host smart-936e07a6-e83d-42b7-b4de-c421585069ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30283
91271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3028391271
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.3387261155
Short name T46
Test name
Test status
Simulation time 297404906 ps
CPU time 1.16 seconds
Started Aug 09 05:27:28 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207552 kb
Host smart-9396dc08-a51a-4d82-bfd0-ca6a8d25e383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33872
61155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.3387261155
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.991733802
Short name T2355
Test name
Test status
Simulation time 150278159 ps
CPU time 0.87 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207372 kb
Host smart-f2da4b17-968a-4fbc-9031-b9148a609947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99173
3802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.991733802
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1673610585
Short name T1008
Test name
Test status
Simulation time 151347714 ps
CPU time 0.81 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207504 kb
Host smart-3fc39a6c-e99d-41fc-b0ae-62fe8ee78a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
10585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1673610585
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4185660046
Short name T1431
Test name
Test status
Simulation time 187468927 ps
CPU time 0.91 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207792 kb
Host smart-57ac9d56-4fa1-4382-97ec-da48687e084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856
60046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4185660046
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2046286303
Short name T1642
Test name
Test status
Simulation time 2575595523 ps
CPU time 75.65 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:28:43 PM PDT 24
Peak memory 217872 kb
Host smart-74a7a39f-e9f9-4467-8f8b-69ba07a5321f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2046286303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2046286303
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2466061534
Short name T2971
Test name
Test status
Simulation time 157428211 ps
CPU time 0.85 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207548 kb
Host smart-b04ad029-d704-44e9-87df-7d485fb69927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
61534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2466061534
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1535023282
Short name T3545
Test name
Test status
Simulation time 173966460 ps
CPU time 0.88 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207788 kb
Host smart-8b594dd8-5831-4b13-978f-53d8533bac57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
23282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1535023282
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.1858140356
Short name T751
Test name
Test status
Simulation time 535429268 ps
CPU time 1.51 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 207528 kb
Host smart-6db67156-7ca1-4f7b-852c-805127382072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18581
40356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1858140356
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2639557682
Short name T1080
Test name
Test status
Simulation time 1550062401 ps
CPU time 43.43 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 215864 kb
Host smart-52e25de4-433e-4690-8c2e-5ded86ceb0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
57682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2639557682
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1406894920
Short name T2186
Test name
Test status
Simulation time 1034556348 ps
CPU time 21.1 seconds
Started Aug 09 05:27:19 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207596 kb
Host smart-750f044f-f173-477d-b8a4-687200b050d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406894920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1406894920
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.2253349057
Short name T2517
Test name
Test status
Simulation time 454319796 ps
CPU time 1.5 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207412 kb
Host smart-b945fe23-2478-4d74-b72b-b09238167289
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253349057 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.2253349057
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.3213417999
Short name T2449
Test name
Test status
Simulation time 507758401 ps
CPU time 1.59 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207536 kb
Host smart-cf1ce7bf-191b-464a-9b40-3e40ef44be03
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213417999 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.3213417999
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.2471987811
Short name T2341
Test name
Test status
Simulation time 541007503 ps
CPU time 1.68 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207440 kb
Host smart-25d11892-ac4d-4f00-86fc-226c6f5d5268
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471987811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.2471987811
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.3588272319
Short name T362
Test name
Test status
Simulation time 418689932 ps
CPU time 1.35 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207476 kb
Host smart-3a94e8e7-9fcc-4058-90ac-6686f4808c87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3588272319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.3588272319
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.2052495302
Short name T3409
Test name
Test status
Simulation time 650139042 ps
CPU time 1.7 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207564 kb
Host smart-b6368af3-3d35-40c0-8ae0-ab6685458bbf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052495302 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.2052495302
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.514817055
Short name T2380
Test name
Test status
Simulation time 467250341 ps
CPU time 1.6 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207464 kb
Host smart-7063ade1-1cc6-424f-9fad-b9e99390a014
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514817055 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.514817055
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.2702952124
Short name T3151
Test name
Test status
Simulation time 505795558 ps
CPU time 1.53 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207512 kb
Host smart-ac387d20-145b-4422-8466-30efacdeae89
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702952124 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.2702952124
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.2563673283
Short name T445
Test name
Test status
Simulation time 240434837 ps
CPU time 0.98 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207464 kb
Host smart-c2b595fc-0141-4ed4-b5fe-51d8657263b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2563673283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.2563673283
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.2176601770
Short name T1240
Test name
Test status
Simulation time 453032917 ps
CPU time 1.43 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207364 kb
Host smart-ead2ab3c-a3ba-4137-bbfe-353ad6c5ec9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176601770 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.2176601770
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.853708441
Short name T427
Test name
Test status
Simulation time 304346781 ps
CPU time 1.05 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207460 kb
Host smart-15fb7162-b49b-4ae5-b8eb-3c63481ff2ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=853708441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.853708441
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.3724075725
Short name T1834
Test name
Test status
Simulation time 602776355 ps
CPU time 1.76 seconds
Started Aug 09 05:33:09 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207484 kb
Host smart-d92eeb91-72fc-4e9a-8cce-36fc4a9b8dd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724075725 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.3724075725
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.1757401344
Short name T449
Test name
Test status
Simulation time 486141975 ps
CPU time 1.4 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207400 kb
Host smart-6ebb8af0-a059-4ae3-954b-545b6d01ede9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1757401344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1757401344
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.2751565214
Short name T1968
Test name
Test status
Simulation time 467699987 ps
CPU time 1.49 seconds
Started Aug 09 05:33:14 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207448 kb
Host smart-16bd3c67-849c-417d-a8df-d6c645e0be09
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751565214 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.2751565214
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.2916196177
Short name T1769
Test name
Test status
Simulation time 482333540 ps
CPU time 1.59 seconds
Started Aug 09 05:32:59 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207440 kb
Host smart-69acde19-8836-4ba5-91ac-a42836244501
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916196177 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.2916196177
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.2108699305
Short name T1838
Test name
Test status
Simulation time 164746954 ps
CPU time 0.91 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207468 kb
Host smart-21561c0a-bb99-402a-bc35-588bca45b0f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2108699305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.2108699305
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.1233801847
Short name T2625
Test name
Test status
Simulation time 551533210 ps
CPU time 1.57 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207512 kb
Host smart-dc411d7f-09db-4a8f-8735-44fca6cd192e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233801847 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.1233801847
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1292153051
Short name T3246
Test name
Test status
Simulation time 66369356 ps
CPU time 0.7 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 207432 kb
Host smart-df8b42b1-b8a3-4f74-af24-af7b1c5c04b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1292153051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1292153051
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.91857023
Short name T2315
Test name
Test status
Simulation time 10516965482 ps
CPU time 12.97 seconds
Started Aug 09 05:27:36 PM PDT 24
Finished Aug 09 05:27:49 PM PDT 24
Peak memory 207624 kb
Host smart-eaac89e6-e8b7-48e7-8b8c-9e3be83f5038
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91857023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon
_wake_disconnect.91857023
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3621834979
Short name T2281
Test name
Test status
Simulation time 14545984348 ps
CPU time 16.8 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:49 PM PDT 24
Peak memory 216008 kb
Host smart-cb4ae9b6-106a-4d76-b9c6-2aa605a99bb5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621834979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3621834979
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.622137755
Short name T2017
Test name
Test status
Simulation time 25876086923 ps
CPU time 36.37 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 216012 kb
Host smart-3be44a79-30d9-44df-b476-48909a470712
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622137755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_resume.622137755
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2733523240
Short name T2113
Test name
Test status
Simulation time 170736963 ps
CPU time 0.93 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207512 kb
Host smart-5066dc3d-7527-4375-8333-75820f436acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27335
23240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2733523240
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3297105946
Short name T1360
Test name
Test status
Simulation time 162409760 ps
CPU time 0.85 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 207424 kb
Host smart-7b07e7fa-daf1-48bc-aa25-ac9d8d9f7ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32971
05946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3297105946
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.2396014966
Short name T2897
Test name
Test status
Simulation time 372415548 ps
CPU time 1.36 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207396 kb
Host smart-5873dd2f-8706-49b4-bc27-ce5a74932ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23960
14966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2396014966
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4104973024
Short name T1702
Test name
Test status
Simulation time 314859278 ps
CPU time 1.19 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:29 PM PDT 24
Peak memory 207548 kb
Host smart-6a3f39a2-0e23-48d6-8d41-c339e708d730
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4104973024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4104973024
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.872028829
Short name T1544
Test name
Test status
Simulation time 19403618534 ps
CPU time 37.2 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207656 kb
Host smart-2922d155-9dfa-4be8-a93f-c0a87bef81bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87202
8829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.872028829
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.103264622
Short name T1600
Test name
Test status
Simulation time 2483926419 ps
CPU time 22.24 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 207680 kb
Host smart-b356ec2f-14f1-4ec5-a85e-384e867059b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103264622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.103264622
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2525579728
Short name T3388
Test name
Test status
Simulation time 782630306 ps
CPU time 1.84 seconds
Started Aug 09 05:27:39 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 207752 kb
Host smart-1ac2f8bf-dd60-44da-bd83-6336f32a4833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
79728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2525579728
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3243441556
Short name T3411
Test name
Test status
Simulation time 136049871 ps
CPU time 0.84 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207472 kb
Host smart-72292f5c-f5dd-4b02-8867-66fa0cd35d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32434
41556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3243441556
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3359088948
Short name T534
Test name
Test status
Simulation time 53980310 ps
CPU time 0.69 seconds
Started Aug 09 05:27:26 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 207492 kb
Host smart-2a878581-c9e6-4beb-bc53-c4cd76262e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
88948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3359088948
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3318102018
Short name T2026
Test name
Test status
Simulation time 836975795 ps
CPU time 2.47 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:32 PM PDT 24
Peak memory 207744 kb
Host smart-1d3739e1-ff9e-4caf-af4a-bd8210841712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33181
02018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3318102018
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.356318656
Short name T499
Test name
Test status
Simulation time 201266017 ps
CPU time 0.93 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207344 kb
Host smart-df36b405-c5d4-4c06-86f6-402cc0b52e36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=356318656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.356318656
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.4068348509
Short name T2080
Test name
Test status
Simulation time 256210734 ps
CPU time 1.64 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207620 kb
Host smart-08642ef6-0779-4048-9ff0-2c593115f041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
48509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.4068348509
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.617411409
Short name T1726
Test name
Test status
Simulation time 217135588 ps
CPU time 1.15 seconds
Started Aug 09 05:27:31 PM PDT 24
Finished Aug 09 05:27:32 PM PDT 24
Peak memory 215932 kb
Host smart-421ac610-92ab-478f-9613-6c5902b19f23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=617411409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.617411409
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2558979067
Short name T1517
Test name
Test status
Simulation time 144786638 ps
CPU time 0.85 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207468 kb
Host smart-66f62470-f706-430b-be08-b97970ffd6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25589
79067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2558979067
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3391550030
Short name T1910
Test name
Test status
Simulation time 214795185 ps
CPU time 1 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207360 kb
Host smart-3e24eccc-c6b3-4b8b-b67c-792deda62dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
50030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3391550030
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1905605037
Short name T2165
Test name
Test status
Simulation time 3642060761 ps
CPU time 36.2 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 224104 kb
Host smart-7e63f2a3-5a92-4c1b-9a0e-dbcfe9d9b671
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1905605037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1905605037
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2912325829
Short name T2907
Test name
Test status
Simulation time 11615774000 ps
CPU time 84.72 seconds
Started Aug 09 05:27:28 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207760 kb
Host smart-6ab3b7ab-209f-4002-b4a2-ba8446284cb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2912325829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2912325829
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4040960837
Short name T3618
Test name
Test status
Simulation time 163275537 ps
CPU time 0.88 seconds
Started Aug 09 05:27:36 PM PDT 24
Finished Aug 09 05:27:37 PM PDT 24
Peak memory 207376 kb
Host smart-f0d511d0-e345-4fa8-ba17-7e3d65feea1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
60837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4040960837
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.495189370
Short name T2370
Test name
Test status
Simulation time 25012149956 ps
CPU time 38.84 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 207692 kb
Host smart-816faa62-3643-41b6-bf22-a3485bdddd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49518
9370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.495189370
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1939913312
Short name T1493
Test name
Test status
Simulation time 9065718699 ps
CPU time 11.18 seconds
Started Aug 09 05:27:31 PM PDT 24
Finished Aug 09 05:27:42 PM PDT 24
Peak memory 207692 kb
Host smart-9589d578-ad31-4a60-b85a-cd1f9a05d0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19399
13312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1939913312
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1300837416
Short name T1942
Test name
Test status
Simulation time 3466367672 ps
CPU time 105.95 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 218896 kb
Host smart-5ea80d44-dd30-46b4-9d00-fbb518cd8b23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1300837416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1300837416
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2103448883
Short name T1797
Test name
Test status
Simulation time 3277903448 ps
CPU time 94.49 seconds
Started Aug 09 05:27:36 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 217424 kb
Host smart-58dc18b5-30b8-410b-a890-0b3c53e9b3fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2103448883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2103448883
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2213745766
Short name T1006
Test name
Test status
Simulation time 301304340 ps
CPU time 1.08 seconds
Started Aug 09 05:27:27 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 207376 kb
Host smart-e4c0927f-5892-467e-ad0a-ecb1fba89279
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2213745766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2213745766
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2971763857
Short name T2056
Test name
Test status
Simulation time 198278648 ps
CPU time 0.95 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207476 kb
Host smart-9931f5ce-f910-4689-8048-202be0069fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29717
63857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2971763857
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.2678290042
Short name T2350
Test name
Test status
Simulation time 2049270190 ps
CPU time 58.02 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:28:30 PM PDT 24
Peak memory 217764 kb
Host smart-c0a7f77a-b779-41e8-80d2-331183858ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26782
90042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.2678290042
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3433588833
Short name T3075
Test name
Test status
Simulation time 2499814957 ps
CPU time 73.64 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:28:43 PM PDT 24
Peak memory 217808 kb
Host smart-cb173372-3c54-4ba6-adfe-c4d55f949d50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3433588833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3433588833
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3996486957
Short name T1659
Test name
Test status
Simulation time 1836099977 ps
CPU time 52.5 seconds
Started Aug 09 05:27:25 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 217316 kb
Host smart-33b43434-20e6-4c11-8319-8fe0030e96f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3996486957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3996486957
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3744476366
Short name T2834
Test name
Test status
Simulation time 201150895 ps
CPU time 0.95 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207788 kb
Host smart-c43a76ee-4f19-4c6e-9241-7a6456602d0d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3744476366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3744476366
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.606549503
Short name T870
Test name
Test status
Simulation time 189452920 ps
CPU time 0.85 seconds
Started Aug 09 05:27:28 PM PDT 24
Finished Aug 09 05:27:29 PM PDT 24
Peak memory 207532 kb
Host smart-c9c583ef-c928-4e7a-811b-8d3588c29010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60654
9503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.606549503
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.512841571
Short name T3322
Test name
Test status
Simulation time 215468100 ps
CPU time 1.04 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207500 kb
Host smart-c003fc47-8d85-4fe9-9187-be603436057f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51284
1571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.512841571
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.96960272
Short name T1615
Test name
Test status
Simulation time 152138360 ps
CPU time 0.84 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207356 kb
Host smart-651f5077-7363-4b2b-94b3-f9d09ea010d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96960
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.96960272
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3283474783
Short name T2164
Test name
Test status
Simulation time 164484130 ps
CPU time 0.86 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207784 kb
Host smart-f65c82c7-21d6-4eef-a7ae-89d00d45e1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
74783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3283474783
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1688098606
Short name T490
Test name
Test status
Simulation time 190298846 ps
CPU time 0.93 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207508 kb
Host smart-86ed0b1e-becf-46c0-8d0d-759d4db6d5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16880
98606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1688098606
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3594438366
Short name T3333
Test name
Test status
Simulation time 161222138 ps
CPU time 0.82 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207432 kb
Host smart-82b572c0-a60a-430b-8936-3108b32d67f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35944
38366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3594438366
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1218365850
Short name T3035
Test name
Test status
Simulation time 219896797 ps
CPU time 1.03 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207500 kb
Host smart-250d529d-e3f0-4326-b50a-d716ac98b1ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1218365850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1218365850
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2882367289
Short name T2246
Test name
Test status
Simulation time 196729306 ps
CPU time 0.89 seconds
Started Aug 09 05:27:30 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 207456 kb
Host smart-3e72c067-cb45-41ab-8842-b8960f02f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
67289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2882367289
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.454216171
Short name T2687
Test name
Test status
Simulation time 95731508 ps
CPU time 0.74 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207360 kb
Host smart-35882933-27f0-4ed3-9d2d-f336ce7a162d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45421
6171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.454216171
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3420051299
Short name T2135
Test name
Test status
Simulation time 14252004592 ps
CPU time 39.88 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 215888 kb
Host smart-be924afa-3e91-428d-befc-9f2c0abbd925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
51299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3420051299
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.199906106
Short name T1922
Test name
Test status
Simulation time 190132361 ps
CPU time 0.91 seconds
Started Aug 09 05:27:39 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207792 kb
Host smart-2ec02d7b-1336-425f-9496-1abecb11ed46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
6106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.199906106
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1495032687
Short name T737
Test name
Test status
Simulation time 227176205 ps
CPU time 0.98 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207392 kb
Host smart-9c7af4d9-67f1-4089-8624-9f376b275bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14950
32687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1495032687
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.614874951
Short name T2512
Test name
Test status
Simulation time 267796331 ps
CPU time 1 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 207544 kb
Host smart-e38fffbc-451a-4f0f-9456-7f450f331221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61487
4951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.614874951
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2970334894
Short name T555
Test name
Test status
Simulation time 169789479 ps
CPU time 0.96 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207440 kb
Host smart-9148fa0c-4018-4d7b-83af-f42ab0584a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
34894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2970334894
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.2033422294
Short name T2241
Test name
Test status
Simulation time 20167657786 ps
CPU time 23.81 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207588 kb
Host smart-9e7ec028-4ec1-4dcd-9705-0e3670342ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
22294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.2033422294
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1284959181
Short name T1730
Test name
Test status
Simulation time 148258642 ps
CPU time 0.85 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207428 kb
Host smart-b3b4c558-006d-4415-bafe-6d322ba9a7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
59181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1284959181
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.2871457790
Short name T302
Test name
Test status
Simulation time 252947342 ps
CPU time 1.12 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207504 kb
Host smart-411e7563-a273-4ea9-8dab-36425dd769d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28714
57790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.2871457790
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2000586930
Short name T2158
Test name
Test status
Simulation time 164578903 ps
CPU time 0.89 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207400 kb
Host smart-095a894d-7c71-4fdd-8a37-af40e82f5121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
86930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2000586930
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2657926248
Short name T2296
Test name
Test status
Simulation time 229048936 ps
CPU time 0.88 seconds
Started Aug 09 05:27:32 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207560 kb
Host smart-5523be85-d8cc-44bd-bdc0-6def3f720fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
26248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2657926248
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2905881651
Short name T2485
Test name
Test status
Simulation time 227710274 ps
CPU time 1.1 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 207552 kb
Host smart-ad157eda-2193-47ca-9dfb-d6095f4c6d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
81651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2905881651
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.448881446
Short name T1995
Test name
Test status
Simulation time 2278421133 ps
CPU time 62.89 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:28:36 PM PDT 24
Peak memory 224196 kb
Host smart-ebb267a5-bbfb-4cb7-ba3e-94c9ec21a7db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=448881446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.448881446
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2419438967
Short name T3385
Test name
Test status
Simulation time 154043021 ps
CPU time 0.87 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207500 kb
Host smart-f3d0a32b-3a8e-4d73-b304-96ff3dbf290e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
38967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2419438967
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1537703131
Short name T2921
Test name
Test status
Simulation time 145385054 ps
CPU time 0.8 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207508 kb
Host smart-e42da7a1-f8f3-4118-b019-ddd097f12e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15377
03131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1537703131
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.4110975407
Short name T1219
Test name
Test status
Simulation time 822296662 ps
CPU time 2.11 seconds
Started Aug 09 05:27:37 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207596 kb
Host smart-2e56424e-4ec6-4fb1-8538-96288ae78f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
75407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.4110975407
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1589694830
Short name T250
Test name
Test status
Simulation time 2876473727 ps
CPU time 81.47 seconds
Started Aug 09 05:27:41 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 217572 kb
Host smart-56d52bba-73e3-4964-837a-cb14af2854ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
94830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1589694830
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2383992948
Short name T688
Test name
Test status
Simulation time 615874843 ps
CPU time 4.75 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:38 PM PDT 24
Peak memory 207552 kb
Host smart-3dc4a880-ca6b-419f-b6d4-cd7c1af44aa9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383992948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2383992948
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.3662114165
Short name T2565
Test name
Test status
Simulation time 458941443 ps
CPU time 1.52 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:37 PM PDT 24
Peak memory 207508 kb
Host smart-a01507f4-f456-4ed5-83ab-59a0e4c2aaae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662114165 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.3662114165
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.954743328
Short name T386
Test name
Test status
Simulation time 526359839 ps
CPU time 1.35 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207520 kb
Host smart-d9c26337-a878-452f-b8ec-11fd66cc2dd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=954743328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.954743328
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.2884506141
Short name T1986
Test name
Test status
Simulation time 562064032 ps
CPU time 1.55 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:12 PM PDT 24
Peak memory 207484 kb
Host smart-4b6b2976-64e9-48a8-9f5d-1382a6e4894b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884506141 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.2884506141
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.3821819994
Short name T1029
Test name
Test status
Simulation time 468145129 ps
CPU time 1.41 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207504 kb
Host smart-96d8bfb3-150d-43b1-9036-22001f5d5816
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821819994 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.3821819994
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.178312199
Short name T455
Test name
Test status
Simulation time 290562150 ps
CPU time 1.07 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207356 kb
Host smart-9e9437f9-e861-423e-8226-c502d3968634
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=178312199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.178312199
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.2625723248
Short name T1929
Test name
Test status
Simulation time 563377759 ps
CPU time 1.64 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207412 kb
Host smart-605001ad-a06c-4811-9371-d130a61b187d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625723248 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.2625723248
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.1619493707
Short name T3445
Test name
Test status
Simulation time 256927127 ps
CPU time 1.03 seconds
Started Aug 09 05:33:25 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207348 kb
Host smart-0a3cdfda-03f9-48d4-b2db-d74d29a1f62d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1619493707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.1619493707
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.3276524020
Short name T867
Test name
Test status
Simulation time 505614043 ps
CPU time 1.54 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207564 kb
Host smart-1304de61-c0db-4e56-92b7-a7c45e024337
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276524020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.3276524020
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.2882456678
Short name T503
Test name
Test status
Simulation time 174004052 ps
CPU time 0.92 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207440 kb
Host smart-e3e00ef2-93dc-41cb-bcb4-bec738167c23
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2882456678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.2882456678
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.2183907830
Short name T2038
Test name
Test status
Simulation time 472988858 ps
CPU time 1.51 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207444 kb
Host smart-e1d7ddc9-6a55-4412-8a94-6f9865e63ee5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183907830 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.2183907830
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.2587025067
Short name T3426
Test name
Test status
Simulation time 477236957 ps
CPU time 1.56 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207516 kb
Host smart-b3e5127e-1574-4ecf-9029-a5060dcb93cd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587025067 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.2587025067
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.734017546
Short name T446
Test name
Test status
Simulation time 317704906 ps
CPU time 1.09 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207492 kb
Host smart-2780e97a-50b7-4ed1-90ad-11095b80c5e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=734017546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.734017546
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.2854275048
Short name T1393
Test name
Test status
Simulation time 685222720 ps
CPU time 1.86 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207504 kb
Host smart-40e434d0-f5e6-4b16-9c9e-c6d07632a680
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854275048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.2854275048
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.523751102
Short name T3090
Test name
Test status
Simulation time 499849566 ps
CPU time 1.46 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207820 kb
Host smart-0b8ba0a8-c24f-4c4c-a9f1-4932af51eaea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523751102 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.523751102
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.3209445728
Short name T898
Test name
Test status
Simulation time 476435122 ps
CPU time 1.44 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207364 kb
Host smart-acd93ebd-3298-4dde-ba6b-71f7810f33c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209445728 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.3209445728
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.2994454526
Short name T360
Test name
Test status
Simulation time 281843417 ps
CPU time 1.1 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207520 kb
Host smart-43702212-183d-4173-a8aa-1526a0529631
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2994454526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.2994454526
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.1097222490
Short name T2609
Test name
Test status
Simulation time 528372208 ps
CPU time 1.7 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207508 kb
Host smart-98e5f5cd-a710-4152-8f0f-cbf76ab0f624
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097222490 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.1097222490
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.4060403771
Short name T2154
Test name
Test status
Simulation time 42148857 ps
CPU time 0.69 seconds
Started Aug 09 05:27:42 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 207496 kb
Host smart-cdf56cf4-df07-4571-aaa8-7b142b695642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4060403771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.4060403771
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1999379184
Short name T8
Test name
Test status
Simulation time 5057945556 ps
CPU time 7.44 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 216248 kb
Host smart-f51b5dd2-995b-423c-93b9-ab87e733334c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999379184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.1999379184
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1461930046
Short name T1024
Test name
Test status
Simulation time 15463394147 ps
CPU time 17.97 seconds
Started Aug 09 05:27:35 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 215960 kb
Host smart-0b9c78f1-d3bd-4a76-8d36-b2c72e9832fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461930046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1461930046
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2638653332
Short name T1189
Test name
Test status
Simulation time 30186701063 ps
CPU time 38.05 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207836 kb
Host smart-cecc74a6-cc9a-4df0-aee6-103c64ab3d88
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638653332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.2638653332
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.856583789
Short name T1903
Test name
Test status
Simulation time 154646371 ps
CPU time 0.83 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207496 kb
Host smart-9a744910-42ce-45c3-ba2c-5cfeaab957e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85658
3789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.856583789
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1960429056
Short name T2960
Test name
Test status
Simulation time 146633284 ps
CPU time 0.89 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207452 kb
Host smart-0564aeee-c65a-4790-86b6-3dc1f2704c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19604
29056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1960429056
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1983804207
Short name T2564
Test name
Test status
Simulation time 397367306 ps
CPU time 1.41 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 207524 kb
Host smart-b0228c7d-2a50-431e-b2e3-58518a152ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19838
04207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1983804207
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.363603734
Short name T313
Test name
Test status
Simulation time 1241680870 ps
CPU time 3.26 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 207720 kb
Host smart-8cd744c0-013e-4aba-a9f1-529bc08d223e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=363603734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.363603734
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.2322092667
Short name T3152
Test name
Test status
Simulation time 659406164 ps
CPU time 5.12 seconds
Started Aug 09 05:27:37 PM PDT 24
Finished Aug 09 05:27:42 PM PDT 24
Peak memory 207652 kb
Host smart-06c6709b-547c-449a-95e7-0f3f3d2119ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322092667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.2322092667
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3067036900
Short name T1571
Test name
Test status
Simulation time 774366833 ps
CPU time 1.86 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207432 kb
Host smart-fbe9f330-04b0-4935-bb36-d0133314db29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
36900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3067036900
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.424920901
Short name T38
Test name
Test status
Simulation time 190530680 ps
CPU time 0.87 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207468 kb
Host smart-0da06b92-2923-475f-8d9f-70de755b2152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42492
0901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.424920901
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.882981901
Short name T3224
Test name
Test status
Simulation time 79327880 ps
CPU time 0.74 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:38 PM PDT 24
Peak memory 207464 kb
Host smart-1c53cd86-1004-4ed8-aef8-8c9d32ba181c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88298
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.882981901
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3250645912
Short name T1158
Test name
Test status
Simulation time 969195471 ps
CPU time 2.48 seconds
Started Aug 09 05:27:38 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207760 kb
Host smart-b70077b7-1d69-4968-86f8-4edc07e6de0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32506
45912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3250645912
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.1639849659
Short name T458
Test name
Test status
Simulation time 159986036 ps
CPU time 0.89 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:27:35 PM PDT 24
Peak memory 207460 kb
Host smart-54900c09-48f8-45fc-a4a2-3dc9ba217c15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1639849659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.1639849659
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2166398992
Short name T1133
Test name
Test status
Simulation time 216181962 ps
CPU time 1.68 seconds
Started Aug 09 05:27:31 PM PDT 24
Finished Aug 09 05:27:33 PM PDT 24
Peak memory 207700 kb
Host smart-5ef3ecd4-4e8d-4b6d-81a6-79f257dc415d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
98992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2166398992
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.738238099
Short name T1188
Test name
Test status
Simulation time 221405745 ps
CPU time 1.24 seconds
Started Aug 09 05:27:33 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 215928 kb
Host smart-b00dd65c-bf3b-4e13-a82a-d80e2e7cc3fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=738238099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.738238099
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.91701795
Short name T2928
Test name
Test status
Simulation time 152285523 ps
CPU time 0.84 seconds
Started Aug 09 05:27:39 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207752 kb
Host smart-e1674141-20bc-4568-a456-e7216b1bc7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91701
795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.91701795
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.367455014
Short name T3114
Test name
Test status
Simulation time 244776502 ps
CPU time 1.08 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 207416 kb
Host smart-72303625-8405-4fe3-9540-52e2623f82d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
5014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.367455014
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2976924038
Short name T1904
Test name
Test status
Simulation time 4264236033 ps
CPU time 117.57 seconds
Started Aug 09 05:27:34 PM PDT 24
Finished Aug 09 05:29:31 PM PDT 24
Peak memory 216064 kb
Host smart-769648a3-37b9-4faf-8fec-62ecd75965ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2976924038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2976924038
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1473877126
Short name T2419
Test name
Test status
Simulation time 12008440109 ps
CPU time 139.82 seconds
Started Aug 09 05:27:43 PM PDT 24
Finished Aug 09 05:30:03 PM PDT 24
Peak memory 207704 kb
Host smart-273150ab-2ddf-4fa4-a1f9-72899e3f05bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1473877126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1473877126
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2247962374
Short name T2538
Test name
Test status
Simulation time 260151812 ps
CPU time 1.07 seconds
Started Aug 09 05:28:01 PM PDT 24
Finished Aug 09 05:28:02 PM PDT 24
Peak memory 207500 kb
Host smart-d8d4f93c-3386-449c-95ca-d66cb594b332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22479
62374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2247962374
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.369559679
Short name T914
Test name
Test status
Simulation time 30135091429 ps
CPU time 41.4 seconds
Started Aug 09 05:27:44 PM PDT 24
Finished Aug 09 05:28:26 PM PDT 24
Peak memory 216008 kb
Host smart-f8e908cc-8b0b-4f03-b827-77ef538b197f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
9679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.369559679
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3403285699
Short name T2704
Test name
Test status
Simulation time 4662723902 ps
CPU time 6.68 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 215868 kb
Host smart-e5aa00b2-ca2c-4b11-bcf2-b78a65dbd3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34032
85699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3403285699
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1433139591
Short name T2722
Test name
Test status
Simulation time 4353388360 ps
CPU time 123.4 seconds
Started Aug 09 05:27:48 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 224084 kb
Host smart-54470b02-e6bb-4b31-a814-701562be4f80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1433139591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1433139591
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.51566785
Short name T1495
Test name
Test status
Simulation time 1888084845 ps
CPU time 52.29 seconds
Started Aug 09 05:27:41 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 216000 kb
Host smart-14a86330-fd5b-4ec0-b7b7-1f3380ba2f7a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=51566785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.51566785
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.4196404253
Short name T3287
Test name
Test status
Simulation time 266438770 ps
CPU time 1.04 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207444 kb
Host smart-fffc5281-b7e5-4b6b-922f-22daf85dd13e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4196404253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.4196404253
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.715643258
Short name T2172
Test name
Test status
Simulation time 238319170 ps
CPU time 1.09 seconds
Started Aug 09 05:27:50 PM PDT 24
Finished Aug 09 05:27:51 PM PDT 24
Peak memory 207428 kb
Host smart-9bf0df6d-3c9e-429e-a33c-cd3cad689726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71564
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.715643258
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.105661431
Short name T1089
Test name
Test status
Simulation time 2439210350 ps
CPU time 18.94 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 217068 kb
Host smart-3fe04cb5-f8bf-45d5-94f4-d3cf322b1582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
1431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.105661431
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.3005285627
Short name T3511
Test name
Test status
Simulation time 1680836137 ps
CPU time 14.78 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 224020 kb
Host smart-81139dc8-65d1-4c41-8965-0f3ac673255d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3005285627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.3005285627
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3223499988
Short name T2717
Test name
Test status
Simulation time 2415877356 ps
CPU time 72.01 seconds
Started Aug 09 05:27:53 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 215948 kb
Host smart-b51a9de4-f124-433b-900d-5b6a8639f458
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3223499988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3223499988
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2700928352
Short name T2561
Test name
Test status
Simulation time 186185180 ps
CPU time 0.93 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 207496 kb
Host smart-b049acab-fa19-48c1-bfab-308c8023d6d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2700928352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2700928352
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.4087162278
Short name T1715
Test name
Test status
Simulation time 151889436 ps
CPU time 0.85 seconds
Started Aug 09 05:27:44 PM PDT 24
Finished Aug 09 05:27:45 PM PDT 24
Peak memory 207484 kb
Host smart-2699d349-c10b-47ee-8c35-3464a5548407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40871
62278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.4087162278
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.522513987
Short name T2478
Test name
Test status
Simulation time 196498148 ps
CPU time 0.91 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 207508 kb
Host smart-009c3d44-8437-491a-a757-5f9d11534913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52251
3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.522513987
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1288684351
Short name T2886
Test name
Test status
Simulation time 201610337 ps
CPU time 0.94 seconds
Started Aug 09 05:27:44 PM PDT 24
Finished Aug 09 05:27:45 PM PDT 24
Peak memory 207508 kb
Host smart-c32a427e-0cbb-4895-b671-b1d451c8b71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
84351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1288684351
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.4106289248
Short name T3014
Test name
Test status
Simulation time 178528619 ps
CPU time 0.92 seconds
Started Aug 09 05:27:42 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 207552 kb
Host smart-ce09ea00-93ef-437f-aedd-b8a40d823109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41062
89248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.4106289248
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3484105975
Short name T164
Test name
Test status
Simulation time 168239725 ps
CPU time 0.87 seconds
Started Aug 09 05:27:48 PM PDT 24
Finished Aug 09 05:27:49 PM PDT 24
Peak memory 207496 kb
Host smart-b75c6dd8-c2cd-4ced-8f74-ecafd65bb9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841
05975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3484105975
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1721197131
Short name T3581
Test name
Test status
Simulation time 236853581 ps
CPU time 1.12 seconds
Started Aug 09 05:27:48 PM PDT 24
Finished Aug 09 05:27:49 PM PDT 24
Peak memory 207496 kb
Host smart-e3216e59-1f40-4003-9248-ab9af3bfc13e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1721197131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1721197131
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2969249356
Short name T2085
Test name
Test status
Simulation time 146242717 ps
CPU time 0.83 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 207516 kb
Host smart-6a419016-9aa6-4315-b4cd-a953ebc9eea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
49356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2969249356
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2922935762
Short name T1651
Test name
Test status
Simulation time 40788738 ps
CPU time 0.76 seconds
Started Aug 09 05:27:47 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 207468 kb
Host smart-240f0f17-4369-45ad-8431-61c376614655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
35762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2922935762
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.652021396
Short name T950
Test name
Test status
Simulation time 18038283618 ps
CPU time 47.69 seconds
Started Aug 09 05:27:53 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 215972 kb
Host smart-a58c370c-4466-4940-a142-74f8e4aec22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65202
1396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.652021396
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.675135165
Short name T1297
Test name
Test status
Simulation time 202970867 ps
CPU time 1.09 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 207408 kb
Host smart-ccf830fc-31da-43ee-a272-3990cff842b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67513
5165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.675135165
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.144963018
Short name T619
Test name
Test status
Simulation time 206630595 ps
CPU time 0.94 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207384 kb
Host smart-1f6e96ff-01b5-40de-a87e-66086bba23bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
3018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.144963018
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.655834558
Short name T2733
Test name
Test status
Simulation time 222364129 ps
CPU time 0.95 seconds
Started Aug 09 05:27:44 PM PDT 24
Finished Aug 09 05:27:45 PM PDT 24
Peak memory 207544 kb
Host smart-64f15cf8-1a6d-416d-9fd9-5861ba435b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65583
4558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.655834558
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4163261402
Short name T758
Test name
Test status
Simulation time 153240078 ps
CPU time 0.88 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 207416 kb
Host smart-74855e70-ae24-4433-9267-d0f7d1c572dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41632
61402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4163261402
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.1964374926
Short name T1971
Test name
Test status
Simulation time 20161584558 ps
CPU time 24.53 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207632 kb
Host smart-ad7b58c6-7200-4dac-b66b-65a8dde4fada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
74926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.1964374926
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1598549104
Short name T912
Test name
Test status
Simulation time 143131523 ps
CPU time 0.85 seconds
Started Aug 09 05:27:51 PM PDT 24
Finished Aug 09 05:27:52 PM PDT 24
Peak memory 207328 kb
Host smart-b7c00057-8a5b-41c3-85dd-ea4e76ff76d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15985
49104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1598549104
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.735429409
Short name T2201
Test name
Test status
Simulation time 296585626 ps
CPU time 1.07 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207472 kb
Host smart-88eb5c90-afd8-4165-b54c-13bc8d8d0011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73542
9409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.735429409
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.467027734
Short name T2216
Test name
Test status
Simulation time 158860418 ps
CPU time 0.81 seconds
Started Aug 09 05:27:40 PM PDT 24
Finished Aug 09 05:27:41 PM PDT 24
Peak memory 206456 kb
Host smart-a30ede61-adc7-4037-94f2-c397b7ad3e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46702
7734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.467027734
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2748283515
Short name T552
Test name
Test status
Simulation time 159167980 ps
CPU time 0.85 seconds
Started Aug 09 05:27:43 PM PDT 24
Finished Aug 09 05:27:44 PM PDT 24
Peak memory 207396 kb
Host smart-918be63c-18c9-4bca-8e69-b6072c37fbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27482
83515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2748283515
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2795873047
Short name T3559
Test name
Test status
Simulation time 226348691 ps
CPU time 1.03 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 207504 kb
Host smart-a6f4e4ec-5719-4ec2-8e49-98a1ae91b8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
73047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2795873047
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.848984382
Short name T733
Test name
Test status
Simulation time 1965254315 ps
CPU time 13.97 seconds
Started Aug 09 05:27:41 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 223992 kb
Host smart-a837aed3-491f-475b-bd0d-e4f2c03e4239
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=848984382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.848984382
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3207780350
Short name T2312
Test name
Test status
Simulation time 188870593 ps
CPU time 0.9 seconds
Started Aug 09 05:27:47 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 207504 kb
Host smart-99641a9b-de26-425b-a0a9-92a883d91e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32077
80350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3207780350
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1144306310
Short name T1882
Test name
Test status
Simulation time 185663605 ps
CPU time 0.9 seconds
Started Aug 09 05:27:42 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 207472 kb
Host smart-4b5da7fc-b43e-4cd9-9a3e-06ca7be9f7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11443
06310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1144306310
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3435655367
Short name T3475
Test name
Test status
Simulation time 607183478 ps
CPU time 1.72 seconds
Started Aug 09 05:27:41 PM PDT 24
Finished Aug 09 05:27:43 PM PDT 24
Peak memory 207520 kb
Host smart-06845415-0dcf-4aee-83c4-a942a8caf6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34356
55367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3435655367
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1141046177
Short name T1756
Test name
Test status
Simulation time 3921301380 ps
CPU time 31.02 seconds
Started Aug 09 05:27:45 PM PDT 24
Finished Aug 09 05:28:16 PM PDT 24
Peak memory 217812 kb
Host smart-8b41d7dd-8ef4-4a4a-b549-98a5f7f3cfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11410
46177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1141046177
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.4159230682
Short name T2942
Test name
Test status
Simulation time 6772985798 ps
CPU time 45.98 seconds
Started Aug 09 05:27:37 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207772 kb
Host smart-ae029bd1-9e93-4118-b3a8-6c1953f9dbc2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159230682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.4159230682
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.3467997385
Short name T3042
Test name
Test status
Simulation time 493289025 ps
CPU time 1.57 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207500 kb
Host smart-a90d6079-5941-4843-87c7-60b6b82d9894
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467997385 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.3467997385
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.1558146156
Short name T483
Test name
Test status
Simulation time 194587400 ps
CPU time 0.97 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:16 PM PDT 24
Peak memory 207432 kb
Host smart-13683203-398e-47a4-b280-7e4a7a64d9a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1558146156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.1558146156
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.450126741
Short name T2835
Test name
Test status
Simulation time 583811242 ps
CPU time 1.55 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207404 kb
Host smart-2fef9989-cfc3-487b-a052-9271f0a6e9f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450126741 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.450126741
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.1262592059
Short name T3487
Test name
Test status
Simulation time 687490355 ps
CPU time 1.71 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207556 kb
Host smart-8ccdd641-e4f9-44dc-807d-9dbd6bec215a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1262592059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.1262592059
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.4197938383
Short name T2399
Test name
Test status
Simulation time 547769763 ps
CPU time 1.71 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207512 kb
Host smart-51bbb855-54e4-4746-a880-57402a9ad204
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197938383 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.4197938383
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.3874506523
Short name T715
Test name
Test status
Simulation time 481981493 ps
CPU time 1.56 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207444 kb
Host smart-81b5b1b9-8acd-4337-acab-3ea8228bf9b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874506523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.3874506523
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.16532854
Short name T1534
Test name
Test status
Simulation time 148688468 ps
CPU time 0.87 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207452 kb
Host smart-8aa5c2d7-08ef-444d-91c0-bbdd3fb74dcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=16532854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.16532854
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.2633525688
Short name T832
Test name
Test status
Simulation time 448434612 ps
CPU time 1.5 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207476 kb
Host smart-fbf83500-fc18-410d-9c4b-21a328230ffa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633525688 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.2633525688
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.2025969901
Short name T3461
Test name
Test status
Simulation time 257896889 ps
CPU time 1.03 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207512 kb
Host smart-b8ea555d-438f-48f8-a936-1c6476fe3f4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2025969901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.2025969901
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.1051946571
Short name T548
Test name
Test status
Simulation time 506722995 ps
CPU time 1.46 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207412 kb
Host smart-3ff82e08-ab91-4cd0-9eed-9bf4981a83d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051946571 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.1051946571
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.4219410570
Short name T405
Test name
Test status
Simulation time 334641620 ps
CPU time 1.17 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207396 kb
Host smart-172ad9bb-e2a8-4df5-b970-cbe05ee6773b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4219410570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.4219410570
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.2096266542
Short name T2457
Test name
Test status
Simulation time 449970047 ps
CPU time 1.42 seconds
Started Aug 09 05:33:07 PM PDT 24
Finished Aug 09 05:33:08 PM PDT 24
Peak memory 207380 kb
Host smart-b1e55686-9f29-4769-831a-b957e61afe8d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096266542 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.2096266542
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.1936219784
Short name T1576
Test name
Test status
Simulation time 654897380 ps
CPU time 1.73 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207480 kb
Host smart-3b16f190-9c88-44b3-8d21-b6a81d4d3155
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936219784 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.1936219784
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.794610400
Short name T3037
Test name
Test status
Simulation time 272029323 ps
CPU time 1.03 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207412 kb
Host smart-7fbb44fb-d1ff-49bd-9afd-595ac6f46870
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=794610400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.794610400
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.3459749323
Short name T72
Test name
Test status
Simulation time 555839540 ps
CPU time 1.61 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207436 kb
Host smart-dd947868-7964-4f77-ad2b-0e8162029240
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459749323 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.3459749323
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.2885138590
Short name T3317
Test name
Test status
Simulation time 615326720 ps
CPU time 1.72 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207492 kb
Host smart-db1a6bf6-5790-49bb-b00b-ef5021c808e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2885138590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.2885138590
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.262415353
Short name T112
Test name
Test status
Simulation time 638398300 ps
CPU time 1.74 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207448 kb
Host smart-75ec4113-201b-4073-aba3-15c649b8e7d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262415353 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.262415353
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.4128793548
Short name T1792
Test name
Test status
Simulation time 596255936 ps
CPU time 1.65 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207560 kb
Host smart-d0fb888d-3a4f-4bb7-98ff-0db5ae1a0542
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128793548 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.4128793548
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3561323287
Short name T3145
Test name
Test status
Simulation time 36277355 ps
CPU time 0.67 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207544 kb
Host smart-8ef2fd3a-64bc-4ee4-96c6-5cb6a6487596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3561323287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3561323287
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2302292319
Short name T3404
Test name
Test status
Simulation time 11738073292 ps
CPU time 14.7 seconds
Started Aug 09 05:27:44 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207696 kb
Host smart-036c8f59-db4f-441c-bed2-715cf6818b89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302292319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.2302292319
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1305142583
Short name T242
Test name
Test status
Simulation time 14575735888 ps
CPU time 17.46 seconds
Started Aug 09 05:27:42 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 215976 kb
Host smart-fd190a97-4e7c-4441-af68-c875cbe6fc71
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305142583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1305142583
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1309574183
Short name T1057
Test name
Test status
Simulation time 25823973284 ps
CPU time 31.72 seconds
Started Aug 09 05:27:42 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 216028 kb
Host smart-8e04fac0-c4f4-47fc-a705-bd3a1782a412
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309574183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.1309574183
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1598042328
Short name T1369
Test name
Test status
Simulation time 144961199 ps
CPU time 0.89 seconds
Started Aug 09 05:27:41 PM PDT 24
Finished Aug 09 05:27:42 PM PDT 24
Peak memory 207504 kb
Host smart-210f313c-9b79-457c-be19-f201ba3daaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15980
42328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1598042328
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3342546135
Short name T1338
Test name
Test status
Simulation time 147939202 ps
CPU time 0.83 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:00 PM PDT 24
Peak memory 207416 kb
Host smart-e1ca66b0-2653-46c2-82ec-354fcc84b3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
46135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3342546135
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1683188164
Short name T218
Test name
Test status
Simulation time 225351976 ps
CPU time 1.06 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207396 kb
Host smart-a2eb7e34-40af-4fc9-9817-383032a739bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831
88164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1683188164
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2774636821
Short name T1897
Test name
Test status
Simulation time 673507787 ps
CPU time 1.93 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207408 kb
Host smart-d1dafaf2-cc05-4302-bd8d-5770ee52cd76
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2774636821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2774636821
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.2953431333
Short name T2357
Test name
Test status
Simulation time 3779982920 ps
CPU time 26.57 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 208008 kb
Host smart-bbdfa2cb-2d57-4bf0-8a3a-7e293fcea853
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953431333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.2953431333
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1753071740
Short name T2523
Test name
Test status
Simulation time 548560290 ps
CPU time 1.5 seconds
Started Aug 09 05:27:51 PM PDT 24
Finished Aug 09 05:27:52 PM PDT 24
Peak memory 207516 kb
Host smart-c0586466-a5b7-4e42-853e-8cca24e6347d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
71740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1753071740
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.14604878
Short name T586
Test name
Test status
Simulation time 139309575 ps
CPU time 0.87 seconds
Started Aug 09 05:27:50 PM PDT 24
Finished Aug 09 05:27:51 PM PDT 24
Peak memory 207472 kb
Host smart-d944ec4a-0574-49d0-a47e-5578e736ace5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14604
878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.14604878
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1695106250
Short name T2571
Test name
Test status
Simulation time 36240012 ps
CPU time 0.74 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 207520 kb
Host smart-fdb3f51d-e3c8-4a0b-ba7d-df3605996573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951
06250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1695106250
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4238913187
Short name T946
Test name
Test status
Simulation time 1015962768 ps
CPU time 2.63 seconds
Started Aug 09 05:27:47 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207696 kb
Host smart-9333508d-2919-4995-923d-2dc3f877b2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
13187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4238913187
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.2176259984
Short name T404
Test name
Test status
Simulation time 487363034 ps
CPU time 1.46 seconds
Started Aug 09 05:27:50 PM PDT 24
Finished Aug 09 05:27:52 PM PDT 24
Peak memory 207468 kb
Host smart-53a0caf6-2fae-4e98-b997-6fec7361ec04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2176259984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.2176259984
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3054643817
Short name T1259
Test name
Test status
Simulation time 171163463 ps
CPU time 1.66 seconds
Started Aug 09 05:27:48 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207600 kb
Host smart-15e0a147-4151-4f12-9b56-af9165e08753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30546
43817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3054643817
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2962043087
Short name T3372
Test name
Test status
Simulation time 251128849 ps
CPU time 1.25 seconds
Started Aug 09 05:27:47 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 215928 kb
Host smart-cca81cb1-dd3c-4d8c-aa5c-4b9e1af6f343
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2962043087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2962043087
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3971222456
Short name T3117
Test name
Test status
Simulation time 137128378 ps
CPU time 0.84 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207512 kb
Host smart-e80bcba9-b92d-4c9c-9a33-a445719c809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
22456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3971222456
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2937611267
Short name T1872
Test name
Test status
Simulation time 223881453 ps
CPU time 1.01 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207476 kb
Host smart-fb23c920-1f4e-4abd-addc-4b39b40fd8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29376
11267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2937611267
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1514199887
Short name T3323
Test name
Test status
Simulation time 3732289375 ps
CPU time 40.69 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 218432 kb
Host smart-4093d910-1ee0-4072-afe0-57c29459aa33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1514199887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1514199887
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.222005092
Short name T1228
Test name
Test status
Simulation time 11724050984 ps
CPU time 139.19 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207664 kb
Host smart-0e9c4c41-e9c1-4dfb-afcf-b7dc85e6a0fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=222005092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.222005092
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2017094263
Short name T3532
Test name
Test status
Simulation time 202448747 ps
CPU time 1 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207428 kb
Host smart-f89341ba-7117-4414-803b-e679c7b9a973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
94263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2017094263
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.29482780
Short name T65
Test name
Test status
Simulation time 5682460565 ps
CPU time 8.12 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:28:00 PM PDT 24
Peak memory 216120 kb
Host smart-bbb07a30-f363-4445-a42b-e83694e93ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29482
780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.29482780
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.43489066
Short name T1157
Test name
Test status
Simulation time 4773375809 ps
CPU time 6.95 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 216084 kb
Host smart-a7bbf34e-1c7b-44c1-b2a8-8af25497ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43489
066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.43489066
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.1811204659
Short name T3248
Test name
Test status
Simulation time 2972815922 ps
CPU time 84 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 224060 kb
Host smart-fd6a27ce-d917-479f-9947-cd82ec56ed4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1811204659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.1811204659
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3517047666
Short name T2200
Test name
Test status
Simulation time 2864411574 ps
CPU time 81.88 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 217616 kb
Host smart-990e46ac-5e8e-4613-b74c-93f7445191ad
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3517047666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3517047666
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3763120533
Short name T837
Test name
Test status
Simulation time 248057628 ps
CPU time 1.05 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:00 PM PDT 24
Peak memory 207528 kb
Host smart-52272569-371e-4cfb-9330-c2829af92056
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3763120533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3763120533
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1824046055
Short name T2474
Test name
Test status
Simulation time 221866194 ps
CPU time 0.95 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 207428 kb
Host smart-ef9afddc-71bc-4b41-9d17-f6c8b7b396c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
46055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1824046055
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.902758087
Short name T2178
Test name
Test status
Simulation time 2712154798 ps
CPU time 79.53 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 224112 kb
Host smart-3d54e315-0739-475c-893c-29d97d1c57f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90275
8087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.902758087
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2555996151
Short name T668
Test name
Test status
Simulation time 3263272336 ps
CPU time 31.68 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:28:27 PM PDT 24
Peak memory 217972 kb
Host smart-1f1b6e22-2d79-45b3-acdd-f0dd69c77fd8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2555996151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2555996151
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1274481820
Short name T677
Test name
Test status
Simulation time 2858516536 ps
CPU time 21.21 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:28:16 PM PDT 24
Peak memory 224136 kb
Host smart-96c4f252-8c73-4bed-b86d-4b180ae203b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1274481820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1274481820
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1845634709
Short name T932
Test name
Test status
Simulation time 166266402 ps
CPU time 0.89 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 207392 kb
Host smart-b5f78f1c-9d90-4fc7-bcd3-d5ca4cd2f947
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1845634709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1845634709
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.322159425
Short name T3623
Test name
Test status
Simulation time 162438532 ps
CPU time 0.86 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207396 kb
Host smart-0635d4fd-bfdf-4f1c-9157-e8fc044ff84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.322159425
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1276573591
Short name T2130
Test name
Test status
Simulation time 172837197 ps
CPU time 0.89 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207432 kb
Host smart-bed615b4-18bf-4246-9947-dbebe604242c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12765
73591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1276573591
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3221015314
Short name T2456
Test name
Test status
Simulation time 174969400 ps
CPU time 0.92 seconds
Started Aug 09 05:28:02 PM PDT 24
Finished Aug 09 05:28:03 PM PDT 24
Peak memory 207436 kb
Host smart-e0992745-13d4-493c-b735-097ea7d38fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
15314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3221015314
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1356861263
Short name T674
Test name
Test status
Simulation time 147469351 ps
CPU time 0.85 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 207496 kb
Host smart-8e289307-4bb5-49eb-995f-c3125cd1ac60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568
61263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1356861263
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.611906714
Short name T984
Test name
Test status
Simulation time 172556964 ps
CPU time 0.89 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207420 kb
Host smart-b9deb3b8-6602-4697-a55b-d2b05229199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61190
6714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.611906714
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3500249820
Short name T1294
Test name
Test status
Simulation time 251634972 ps
CPU time 1.11 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207556 kb
Host smart-15d9f833-3ebc-41de-b5c9-9af7b1f9398f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3500249820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3500249820
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3110299486
Short name T1526
Test name
Test status
Simulation time 158541349 ps
CPU time 0.94 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207468 kb
Host smart-bcf6ad18-84af-438b-88c7-ec09fe39d808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31102
99486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3110299486
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2054049269
Short name T1039
Test name
Test status
Simulation time 95039450 ps
CPU time 0.75 seconds
Started Aug 09 05:27:46 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 207392 kb
Host smart-53bb033b-edd1-463e-8b9c-685da585d480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540
49269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2054049269
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2134313894
Short name T2117
Test name
Test status
Simulation time 9814438180 ps
CPU time 27.57 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:31 PM PDT 24
Peak memory 215976 kb
Host smart-a9f23ffa-071e-4c12-8e7b-1a02adfccb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343
13894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2134313894
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1742826235
Short name T1356
Test name
Test status
Simulation time 235675824 ps
CPU time 0.92 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:00 PM PDT 24
Peak memory 207504 kb
Host smart-4de7ff33-408d-4943-aac2-776ae400b7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17428
26235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1742826235
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4230625534
Short name T2700
Test name
Test status
Simulation time 221623639 ps
CPU time 0.96 seconds
Started Aug 09 05:27:47 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 207480 kb
Host smart-6ddd00e8-c877-43d8-9d0d-5ee5c2524f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
25534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4230625534
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3351612300
Short name T994
Test name
Test status
Simulation time 213711005 ps
CPU time 0.99 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207476 kb
Host smart-700178cc-8c70-49c0-aa7c-91324b74cefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
12300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3351612300
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.2343587201
Short name T2251
Test name
Test status
Simulation time 20154792522 ps
CPU time 28.08 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 207552 kb
Host smart-75b31a02-7e60-4657-8393-ba82e4123b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
87201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.2343587201
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2657508878
Short name T3607
Test name
Test status
Simulation time 136593323 ps
CPU time 0.84 seconds
Started Aug 09 05:28:02 PM PDT 24
Finished Aug 09 05:28:03 PM PDT 24
Peak memory 207428 kb
Host smart-6c097106-ebfc-47a5-adf8-29459a9d547a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26575
08878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2657508878
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.2509299307
Short name T2389
Test name
Test status
Simulation time 374048034 ps
CPU time 1.28 seconds
Started Aug 09 05:27:49 PM PDT 24
Finished Aug 09 05:27:50 PM PDT 24
Peak memory 207428 kb
Host smart-25467470-c138-4eee-9b31-5f9dc1f45adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
99307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2509299307
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.573515650
Short name T846
Test name
Test status
Simulation time 210626539 ps
CPU time 0.89 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207440 kb
Host smart-5352a666-d630-43be-a4aa-f7a8ea02f6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57351
5650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.573515650
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.233065209
Short name T1127
Test name
Test status
Simulation time 151038958 ps
CPU time 0.99 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 207496 kb
Host smart-d832b816-51ea-4a7d-b454-0015c64ee4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23306
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.233065209
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2407100988
Short name T2681
Test name
Test status
Simulation time 196481364 ps
CPU time 1 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 207412 kb
Host smart-5e38c911-cfe8-4e26-bf44-33e97633e05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
00988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2407100988
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2496649063
Short name T1628
Test name
Test status
Simulation time 2013447527 ps
CPU time 20.51 seconds
Started Aug 09 05:27:48 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 217720 kb
Host smart-26289336-6c72-427e-9771-7a8ab74ffc3b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2496649063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2496649063
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3921311218
Short name T3266
Test name
Test status
Simulation time 175120243 ps
CPU time 0.84 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207556 kb
Host smart-a2abe075-5350-4ca4-8ce3-a41ac914d7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39213
11218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3921311218
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1916163176
Short name T3017
Test name
Test status
Simulation time 185447095 ps
CPU time 0.97 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207532 kb
Host smart-a09ee98b-ba90-4c70-9337-6ed4c1ebee60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
63176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1916163176
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1223249812
Short name T2725
Test name
Test status
Simulation time 244235964 ps
CPU time 1 seconds
Started Aug 09 05:28:01 PM PDT 24
Finished Aug 09 05:28:02 PM PDT 24
Peak memory 207364 kb
Host smart-584ca901-6481-4ab2-bd8f-c44148686242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
49812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1223249812
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3758028908
Short name T3298
Test name
Test status
Simulation time 2957625424 ps
CPU time 21.54 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 215968 kb
Host smart-37538657-8680-4d3e-9c5b-4770d77bfe5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37580
28908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3758028908
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1824366951
Short name T2598
Test name
Test status
Simulation time 2575792382 ps
CPU time 22.93 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:28:18 PM PDT 24
Peak memory 207784 kb
Host smart-42773686-aea5-4225-81c9-6ef41fe8c487
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824366951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1824366951
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.2689444927
Short name T29
Test name
Test status
Simulation time 488474329 ps
CPU time 1.51 seconds
Started Aug 09 05:27:54 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 207504 kb
Host smart-e0f76752-48d8-43a3-8612-ea613a8cdd47
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689444927 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.2689444927
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.3627624422
Short name T557
Test name
Test status
Simulation time 621835430 ps
CPU time 1.74 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207444 kb
Host smart-09258be5-aa72-4e25-824c-f93834c53fce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627624422 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.3627624422
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.1682071614
Short name T226
Test name
Test status
Simulation time 453665028 ps
CPU time 1.53 seconds
Started Aug 09 05:33:09 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 207536 kb
Host smart-cc0142e4-e6cd-4cbd-ae6e-2dc60fd603b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682071614 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.1682071614
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.2654653327
Short name T2551
Test name
Test status
Simulation time 661271814 ps
CPU time 1.74 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207364 kb
Host smart-ab86d552-1d93-4655-b9fb-71c04b9ed45a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654653327 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.2654653327
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.4167765810
Short name T1598
Test name
Test status
Simulation time 488254159 ps
CPU time 1.53 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207432 kb
Host smart-8338b59b-f9ca-4f68-bfd1-54c0e2c97222
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167765810 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.4167765810
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.1769612291
Short name T481
Test name
Test status
Simulation time 155305418 ps
CPU time 0.83 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207372 kb
Host smart-fad95986-82a1-468b-a312-d42d7c1c53b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1769612291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.1769612291
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.2696259237
Short name T658
Test name
Test status
Simulation time 512592718 ps
CPU time 1.53 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207516 kb
Host smart-06c3fb0f-4b5c-44e3-995b-212b89e500f4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696259237 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.2696259237
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.2495443230
Short name T2403
Test name
Test status
Simulation time 183227922 ps
CPU time 0.98 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207520 kb
Host smart-9d8b1662-181a-4063-a724-728d2786bfd7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2495443230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.2495443230
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/135.usbdev_tx_rx_disruption.2342388389
Short name T2476
Test name
Test status
Simulation time 586046071 ps
CPU time 1.66 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207720 kb
Host smart-753230eb-1776-48c5-bb01-513799f2b5d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342388389 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.usbdev_tx_rx_disruption.2342388389
Directory /workspace/135.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.3663775948
Short name T90
Test name
Test status
Simulation time 516563754 ps
CPU time 1.57 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207448 kb
Host smart-da2dae65-6840-4a99-9bc9-d6c9dccc6388
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663775948 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.3663775948
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.1332149463
Short name T3476
Test name
Test status
Simulation time 490749161 ps
CPU time 1.58 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207484 kb
Host smart-e79daeb6-2097-46c8-ad22-67d802b7c770
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332149463 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.1332149463
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.3764973985
Short name T430
Test name
Test status
Simulation time 606088905 ps
CPU time 1.73 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207344 kb
Host smart-952a3d1f-36e3-4f22-abcc-6cd7fceccda9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3764973985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.3764973985
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.2200189695
Short name T1643
Test name
Test status
Simulation time 616806949 ps
CPU time 1.76 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207364 kb
Host smart-49bc870d-781b-4c7d-8a18-2e880e022419
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200189695 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2200189695
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.1293547426
Short name T407
Test name
Test status
Simulation time 281888139 ps
CPU time 1.06 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207428 kb
Host smart-3811e8b4-0c33-473f-8d28-32de09a16cf4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1293547426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1293547426
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.3670675804
Short name T1822
Test name
Test status
Simulation time 628425730 ps
CPU time 1.64 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207464 kb
Host smart-05ba9877-7775-4801-ac01-e087a2dce95b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670675804 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.3670675804
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1650537452
Short name T1740
Test name
Test status
Simulation time 84502380 ps
CPU time 0.73 seconds
Started Aug 09 05:28:16 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 207492 kb
Host smart-70bfa6d1-ba30-486f-9b0b-ee10b3282b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1650537452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1650537452
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2658382232
Short name T3522
Test name
Test status
Simulation time 11132970329 ps
CPU time 13.74 seconds
Started Aug 09 05:28:01 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207748 kb
Host smart-a4d0498c-cdd6-47ff-b006-1b77f060fa3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658382232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.2658382232
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2589161776
Short name T2665
Test name
Test status
Simulation time 15491693572 ps
CPU time 17.98 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 215944 kb
Host smart-b7077e98-7549-4ebe-823d-1ed31b40b93c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589161776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2589161776
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2394047538
Short name T99
Test name
Test status
Simulation time 25559057608 ps
CPU time 29.75 seconds
Started Aug 09 05:27:52 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 215976 kb
Host smart-e4498636-a63c-45dc-b7d4-eb126aa59f23
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394047538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.2394047538
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3993659849
Short name T2022
Test name
Test status
Simulation time 163696779 ps
CPU time 0.94 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207440 kb
Host smart-f4b2e42f-3b3b-44fe-9382-2eaea0c1f1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
59849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3993659849
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.604540379
Short name T1033
Test name
Test status
Simulation time 164848336 ps
CPU time 0.89 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207496 kb
Host smart-562598a1-7051-4ca2-b852-e92937734a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60454
0379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.604540379
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.940885928
Short name T813
Test name
Test status
Simulation time 485818769 ps
CPU time 1.74 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207444 kb
Host smart-9916d8ca-c7c5-447e-9a3f-07f64e88e763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94088
5928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.940885928
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.560564187
Short name T2493
Test name
Test status
Simulation time 1139168309 ps
CPU time 3.02 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:07 PM PDT 24
Peak memory 207688 kb
Host smart-a4c547bd-19c3-4005-8561-c5d6c247c1ee
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=560564187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.560564187
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1317716153
Short name T1224
Test name
Test status
Simulation time 43714762882 ps
CPU time 70.62 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207828 kb
Host smart-60cf9e8a-09ae-45ba-ba2f-afad995c2745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13177
16153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1317716153
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.658403907
Short name T2784
Test name
Test status
Simulation time 779219129 ps
CPU time 15.44 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207684 kb
Host smart-21baf644-0bca-4200-8581-d952f5ca0597
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658403907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.658403907
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.23533338
Short name T3254
Test name
Test status
Simulation time 1041668641 ps
CPU time 2.1 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:07 PM PDT 24
Peak memory 207396 kb
Host smart-4968761f-cd65-4274-89b3-261c649bb999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23533
338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.23533338
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3272659687
Short name T2795
Test name
Test status
Simulation time 153794125 ps
CPU time 0.87 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207404 kb
Host smart-9346d689-650a-4142-b3fe-46ff4fcadd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
59687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3272659687
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3522267682
Short name T249
Test name
Test status
Simulation time 81907499 ps
CPU time 0.76 seconds
Started Aug 09 05:28:02 PM PDT 24
Finished Aug 09 05:28:03 PM PDT 24
Peak memory 207440 kb
Host smart-b69fc789-504f-4136-9bab-46ec1e82d540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
67682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3522267682
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.871177610
Short name T1140
Test name
Test status
Simulation time 824639574 ps
CPU time 2.46 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207684 kb
Host smart-3598242e-bb19-4826-ae35-a5392a8ac45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87117
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.871177610
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4253679186
Short name T2
Test name
Test status
Simulation time 220525327 ps
CPU time 1.53 seconds
Started Aug 09 05:28:12 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 207676 kb
Host smart-e48756ad-b7df-4070-8911-0c672792b423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42536
79186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4253679186
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3576271516
Short name T3116
Test name
Test status
Simulation time 220692968 ps
CPU time 1.2 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 215928 kb
Host smart-267deefc-3600-4cc8-82c5-b2f8b3974253
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3576271516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3576271516
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.4011201042
Short name T1425
Test name
Test status
Simulation time 168627851 ps
CPU time 0.87 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207352 kb
Host smart-3bd64feb-22a9-40ca-afc2-45760a8f68b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112
01042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.4011201042
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2986916636
Short name T704
Test name
Test status
Simulation time 179143371 ps
CPU time 0.96 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207456 kb
Host smart-c8fe2b89-56b1-4401-936f-0c4055d6cfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
16636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2986916636
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1593868720
Short name T1465
Test name
Test status
Simulation time 3735627009 ps
CPU time 28.6 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:28:26 PM PDT 24
Peak memory 224144 kb
Host smart-d02fb1de-0250-4581-b31a-a575dd8be030
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1593868720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1593868720
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.2819543499
Short name T3440
Test name
Test status
Simulation time 9412324221 ps
CPU time 66.15 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207788 kb
Host smart-04426376-93eb-4991-9fb1-158713c1c0cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2819543499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.2819543499
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3981874639
Short name T2083
Test name
Test status
Simulation time 220242688 ps
CPU time 0.99 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207520 kb
Host smart-bb364a6c-c06c-4184-bce3-9730b9aa78a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
74639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3981874639
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2907974731
Short name T2658
Test name
Test status
Simulation time 6328343959 ps
CPU time 8.99 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 216116 kb
Host smart-c1d1bbbc-aeba-4768-987c-7131181af42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
74731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2907974731
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.885829282
Short name T2098
Test name
Test status
Simulation time 3452010833 ps
CPU time 99.67 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 218488 kb
Host smart-5e43c2f9-2cd1-42fe-a180-a9c959f7fdca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=885829282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.885829282
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3671437989
Short name T3155
Test name
Test status
Simulation time 2159639618 ps
CPU time 21.09 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 216072 kb
Host smart-fcd1b15e-d865-4038-ace1-a210503dd668
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3671437989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3671437989
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1747908222
Short name T2908
Test name
Test status
Simulation time 263816969 ps
CPU time 1.02 seconds
Started Aug 09 05:28:02 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207460 kb
Host smart-baf728f5-6b3f-4bcd-b77d-bdd6b523e151
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1747908222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1747908222
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4089951972
Short name T3043
Test name
Test status
Simulation time 227868310 ps
CPU time 1.02 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207484 kb
Host smart-1ed68f2d-38e1-41f7-acb3-62aa3c80df23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40899
51972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4089951972
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.2395114590
Short name T1429
Test name
Test status
Simulation time 2172628943 ps
CPU time 16.6 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 217804 kb
Host smart-aa40c5a4-8d41-4844-889f-60389ec65941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23951
14590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.2395114590
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2165342224
Short name T2340
Test name
Test status
Simulation time 2445416972 ps
CPU time 28.18 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:36 PM PDT 24
Peak memory 218604 kb
Host smart-30fac464-1d71-4773-a8d1-215e38abbc50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2165342224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2165342224
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2272024208
Short name T2573
Test name
Test status
Simulation time 1406160021 ps
CPU time 12.99 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 216628 kb
Host smart-aaa4660e-8e68-434a-a180-4abbe6d0fbd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2272024208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2272024208
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2461628869
Short name T1169
Test name
Test status
Simulation time 158303570 ps
CPU time 0.87 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207500 kb
Host smart-713db651-fbb0-4edc-bf6c-4f380fa7e666
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2461628869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2461628869
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.274425889
Short name T3135
Test name
Test status
Simulation time 161498832 ps
CPU time 0.87 seconds
Started Aug 09 05:27:56 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207508 kb
Host smart-b4bfbb5d-af90-4ff1-8805-e336ee2b7d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.274425889
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3670502449
Short name T123
Test name
Test status
Simulation time 218409848 ps
CPU time 0.96 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207504 kb
Host smart-bcba9860-56bf-496b-85cd-1b3fa20451bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36705
02449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3670502449
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.476506252
Short name T3092
Test name
Test status
Simulation time 184919461 ps
CPU time 0.97 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207368 kb
Host smart-98f5d415-64a6-475e-9045-c0a34ef763b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47650
6252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.476506252
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1286289414
Short name T2091
Test name
Test status
Simulation time 155108602 ps
CPU time 0.88 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207492 kb
Host smart-468b598e-3113-4a16-8839-af75e483ec35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12862
89414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1286289414
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.4038885388
Short name T3595
Test name
Test status
Simulation time 155315842 ps
CPU time 0.82 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207528 kb
Host smart-e31d250c-f15c-4b45-abcb-6406a477963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40388
85388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.4038885388
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1306596693
Short name T1507
Test name
Test status
Simulation time 186895609 ps
CPU time 0.89 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:07 PM PDT 24
Peak memory 207412 kb
Host smart-ca511708-e2f6-49ad-b8c8-76ef6ce78a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
96693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1306596693
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1642174433
Short name T3056
Test name
Test status
Simulation time 260116446 ps
CPU time 1.08 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207524 kb
Host smart-4c361f8b-0e8d-42d4-8730-91cf68e93d64
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1642174433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1642174433
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1912761086
Short name T2028
Test name
Test status
Simulation time 214153296 ps
CPU time 0.94 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207472 kb
Host smart-17d83b0b-3edc-41a6-99f5-5189451b9b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19127
61086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1912761086
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2500630585
Short name T818
Test name
Test status
Simulation time 40437810 ps
CPU time 0.71 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 207344 kb
Host smart-0b12a651-d901-4bf1-a22f-17b387694e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25006
30585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2500630585
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3678708764
Short name T3064
Test name
Test status
Simulation time 18073253628 ps
CPU time 42.27 seconds
Started Aug 09 05:27:59 PM PDT 24
Finished Aug 09 05:28:41 PM PDT 24
Peak memory 216028 kb
Host smart-5e86dcad-93d4-4c1e-be03-230b40f30861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
08764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3678708764
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.452593271
Short name T697
Test name
Test status
Simulation time 181887230 ps
CPU time 0.92 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 207420 kb
Host smart-8d971680-950f-4ad6-ac5a-35bb9e2cdcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45259
3271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.452593271
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2406386883
Short name T591
Test name
Test status
Simulation time 273405335 ps
CPU time 1.05 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 207356 kb
Host smart-b0447a44-1300-4432-bbb1-6d870bddce45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
86883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2406386883
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2823512702
Short name T2855
Test name
Test status
Simulation time 190866803 ps
CPU time 0.93 seconds
Started Aug 09 05:28:00 PM PDT 24
Finished Aug 09 05:28:01 PM PDT 24
Peak memory 207412 kb
Host smart-afcf2a06-8baa-4ce2-808b-0e98cffbe70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28235
12702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2823512702
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3837913814
Short name T1472
Test name
Test status
Simulation time 184343014 ps
CPU time 0.85 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 207452 kb
Host smart-ccde9e8b-13b1-4385-8014-9071d18f9139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
13814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3837913814
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.939526432
Short name T2509
Test name
Test status
Simulation time 20157659778 ps
CPU time 23.73 seconds
Started Aug 09 05:27:58 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207660 kb
Host smart-acfeb3c0-2184-4ba3-8c53-240bc5767108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93952
6432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.939526432
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2607570398
Short name T1120
Test name
Test status
Simulation time 142247674 ps
CPU time 0.81 seconds
Started Aug 09 05:27:57 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207476 kb
Host smart-13b8d9e3-a547-435b-bd4c-5711cb2421ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26075
70398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2607570398
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.2186568309
Short name T2171
Test name
Test status
Simulation time 255391012 ps
CPU time 1.02 seconds
Started Aug 09 05:27:55 PM PDT 24
Finished Aug 09 05:27:56 PM PDT 24
Peak memory 207524 kb
Host smart-f9fc3f2e-5897-4463-a92b-d59740720e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21865
68309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.2186568309
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1327955814
Short name T2566
Test name
Test status
Simulation time 177396395 ps
CPU time 0.91 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 207468 kb
Host smart-67f8faf2-b078-44a0-8084-e0a3a1eeef7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
55814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1327955814
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3353588579
Short name T2653
Test name
Test status
Simulation time 199631896 ps
CPU time 0.9 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207556 kb
Host smart-23f2fd2a-a87d-4444-90a3-02ad8c3dbb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
88579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3353588579
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1601469851
Short name T1669
Test name
Test status
Simulation time 175505066 ps
CPU time 0.9 seconds
Started Aug 09 05:28:13 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 207364 kb
Host smart-47f3fb3a-f482-4a80-a021-7a9720b05476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
69851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1601469851
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2420930256
Short name T615
Test name
Test status
Simulation time 2952301276 ps
CPU time 29.83 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:36 PM PDT 24
Peak memory 218128 kb
Host smart-02d715e8-6fb8-4cd4-8043-d3e3abef4b9f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2420930256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2420930256
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2252749562
Short name T1854
Test name
Test status
Simulation time 179021962 ps
CPU time 0.87 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207556 kb
Host smart-a771d26d-3e7a-4c18-9651-d6f47ee9f9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
49562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2252749562
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2328223976
Short name T3351
Test name
Test status
Simulation time 178458989 ps
CPU time 0.89 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207412 kb
Host smart-2f27440e-7b9f-4243-8e5a-a6f23572b8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2328223976
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2108218843
Short name T2825
Test name
Test status
Simulation time 815205181 ps
CPU time 2.28 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207652 kb
Host smart-f53ed8e7-bc2a-4538-ae9b-ac0a06e71f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082
18843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2108218843
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1874400432
Short name T2743
Test name
Test status
Simulation time 2570305183 ps
CPU time 18.54 seconds
Started Aug 09 05:28:14 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 217788 kb
Host smart-bff814af-c3fe-43f9-9208-82f99c2aebae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744
00432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1874400432
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2539927024
Short name T2535
Test name
Test status
Simulation time 1025091742 ps
CPU time 22.58 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:31 PM PDT 24
Peak memory 207660 kb
Host smart-9a2f6bfb-3345-4453-9d9b-f9ea5cb27a93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539927024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.2539927024
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.1061023615
Short name T2465
Test name
Test status
Simulation time 506394628 ps
CPU time 1.66 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207508 kb
Host smart-982cf0a7-3cc4-4c47-8702-5c941f3a5c53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061023615 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.1061023615
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.3789408520
Short name T1478
Test name
Test status
Simulation time 509482671 ps
CPU time 1.57 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:19 PM PDT 24
Peak memory 207464 kb
Host smart-5c38706d-fc4b-4c90-8609-f666a4613abf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789408520 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.3789408520
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.4278421199
Short name T3621
Test name
Test status
Simulation time 361458204 ps
CPU time 1.19 seconds
Started Aug 09 05:33:26 PM PDT 24
Finished Aug 09 05:33:27 PM PDT 24
Peak memory 207460 kb
Host smart-2a64a2a9-d8b8-4f90-bdb9-41c95dd7491a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4278421199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.4278421199
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.4194034925
Short name T3034
Test name
Test status
Simulation time 499231869 ps
CPU time 1.47 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207444 kb
Host smart-d17a1aaf-201d-4769-b4fe-9d4165b6b11c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194034925 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.4194034925
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.128830716
Short name T353
Test name
Test status
Simulation time 253610672 ps
CPU time 1.02 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207412 kb
Host smart-e36999fc-cf15-4c20-87b4-7f9037220421
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=128830716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.128830716
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.3279364730
Short name T2477
Test name
Test status
Simulation time 581899603 ps
CPU time 1.56 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207412 kb
Host smart-9d787c24-0959-49e9-a19b-9017336b0a43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279364730 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.3279364730
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.1328810718
Short name T3458
Test name
Test status
Simulation time 558631465 ps
CPU time 1.74 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207480 kb
Host smart-6d77ac3e-403c-4a04-8369-b972cb322ca5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328810718 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.1328810718
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.3922809040
Short name T488
Test name
Test status
Simulation time 366924425 ps
CPU time 1.22 seconds
Started Aug 09 05:33:08 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 207520 kb
Host smart-30bfb778-4186-4269-9489-0eacc4d31e35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3922809040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.3922809040
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.4293685030
Short name T647
Test name
Test status
Simulation time 482203217 ps
CPU time 1.48 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:12 PM PDT 24
Peak memory 207564 kb
Host smart-0e4f1fe7-7c31-41a6-887e-d21bc4d1ca6a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293685030 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.4293685030
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.2879513524
Short name T3118
Test name
Test status
Simulation time 323021442 ps
CPU time 1.05 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207484 kb
Host smart-a8890fd5-a577-47cb-8e76-8cd14988c53b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2879513524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.2879513524
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.125895720
Short name T2096
Test name
Test status
Simulation time 485605503 ps
CPU time 1.56 seconds
Started Aug 09 05:33:06 PM PDT 24
Finished Aug 09 05:33:12 PM PDT 24
Peak memory 207432 kb
Host smart-36834b1d-c9eb-43fb-aad5-3aa9ad546554
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125895720 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.125895720
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.985345011
Short name T1455
Test name
Test status
Simulation time 644829141 ps
CPU time 1.84 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207504 kb
Host smart-f605b844-c7ec-4f62-b54d-a69caf9382d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985345011 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.985345011
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.2588886021
Short name T373
Test name
Test status
Simulation time 361624258 ps
CPU time 1.09 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:06 PM PDT 24
Peak memory 207512 kb
Host smart-4b303f35-f06d-46bb-afec-6521a7977d46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2588886021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.2588886021
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.2113648829
Short name T3262
Test name
Test status
Simulation time 450513064 ps
CPU time 1.33 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207460 kb
Host smart-977b0e3c-7c2c-44f4-9e9d-4829b0701732
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113648829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.2113648829
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.442996407
Short name T358
Test name
Test status
Simulation time 564939390 ps
CPU time 1.54 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207432 kb
Host smart-c07745c3-d064-421d-aa0b-d2d0d2ab7ecf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=442996407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.442996407
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.2330975084
Short name T173
Test name
Test status
Simulation time 460174671 ps
CPU time 1.39 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207556 kb
Host smart-c733777f-b2f0-45fd-880c-40fccdd110ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330975084 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.2330975084
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.1830819027
Short name T1884
Test name
Test status
Simulation time 139973054 ps
CPU time 0.81 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207448 kb
Host smart-af7a062c-7106-43e9-866f-c5ee1dcdcfe5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1830819027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.1830819027
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.3882142660
Short name T2666
Test name
Test status
Simulation time 485528862 ps
CPU time 1.47 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207472 kb
Host smart-dfc78ba9-fde6-4f11-8058-f01935e03a12
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882142660 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.3882142660
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2470585918
Short name T1445
Test name
Test status
Simulation time 104616826 ps
CPU time 0.71 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207572 kb
Host smart-e0ed68b2-af6c-4931-939e-85e20744e2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2470585918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2470585918
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3885946802
Short name T98
Test name
Test status
Simulation time 5461007654 ps
CPU time 7.62 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 215860 kb
Host smart-52e3f382-7409-4f1c-b145-6fa13a27c006
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885946802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3885946802
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2614527885
Short name T1912
Test name
Test status
Simulation time 26414562918 ps
CPU time 34.1 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 216024 kb
Host smart-19d3c656-fcf0-4625-8faf-f9af3bf0290b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614527885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2614527885
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1857499759
Short name T1698
Test name
Test status
Simulation time 202958938 ps
CPU time 0.94 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207592 kb
Host smart-b9d9cff9-8bf3-4d5f-9cb6-07991ed1e1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18574
99759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1857499759
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.311689423
Short name T3389
Test name
Test status
Simulation time 431943081 ps
CPU time 1.59 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207444 kb
Host smart-fca8fc81-e05b-409c-adb1-2ebf125ee78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.311689423
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1690967438
Short name T3537
Test name
Test status
Simulation time 954420147 ps
CPU time 2.23 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 207628 kb
Host smart-8546c4dd-e920-44b9-971b-7719e3fd4703
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1690967438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1690967438
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2166413420
Short name T1195
Test name
Test status
Simulation time 657952878 ps
CPU time 5.34 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:15 PM PDT 24
Peak memory 207628 kb
Host smart-4a73a633-18a1-4d09-a899-abc113083fe0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166413420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2166413420
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.225305674
Short name T3036
Test name
Test status
Simulation time 593877013 ps
CPU time 1.68 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207468 kb
Host smart-a040581d-aef7-4187-81d4-a23397a088df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22530
5674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.225305674
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1017280430
Short name T3529
Test name
Test status
Simulation time 152733568 ps
CPU time 0.83 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207328 kb
Host smart-e1a0895f-801e-4a46-9f58-53ff25e0014f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
80430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1017280430
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.4025702514
Short name T853
Test name
Test status
Simulation time 30555464 ps
CPU time 0.7 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207320 kb
Host smart-f4fea558-7f3e-4264-b419-4e5b839e6b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
02514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.4025702514
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1895735690
Short name T648
Test name
Test status
Simulation time 911740580 ps
CPU time 2.61 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:07 PM PDT 24
Peak memory 207632 kb
Host smart-2d9a8e38-426a-409b-aa7d-d353d8a0b77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957
35690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1895735690
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1004764059
Short name T1831
Test name
Test status
Simulation time 168187326 ps
CPU time 1.48 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207680 kb
Host smart-586baf6b-b82c-4f35-9d2a-f7c8be1a6207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10047
64059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1004764059
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.672268244
Short name T2590
Test name
Test status
Simulation time 229083871 ps
CPU time 1.14 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 215820 kb
Host smart-dc572f22-c9fe-4678-87a1-2636349b2f25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=672268244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.672268244
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2114793609
Short name T1519
Test name
Test status
Simulation time 171973261 ps
CPU time 0.82 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207448 kb
Host smart-c3d85503-a9f3-48ca-b25f-985709370a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21147
93609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2114793609
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.986611491
Short name T761
Test name
Test status
Simulation time 242895741 ps
CPU time 0.99 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207416 kb
Host smart-8919c48d-8ac8-4635-8140-94222e2d4151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98661
1491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.986611491
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1924928550
Short name T3003
Test name
Test status
Simulation time 4052863621 ps
CPU time 117.78 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 224120 kb
Host smart-ec6b05e2-fb95-4f83-a80e-b223be9e4148
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1924928550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1924928550
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2491644282
Short name T878
Test name
Test status
Simulation time 12255558930 ps
CPU time 76.82 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207780 kb
Host smart-b68bfe5f-0cae-4f18-86e6-d416e85e4ec1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2491644282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2491644282
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.196454184
Short name T2642
Test name
Test status
Simulation time 220758340 ps
CPU time 1.07 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207740 kb
Host smart-87eb40f3-2629-4503-9138-d6084da7e659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19645
4184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.196454184
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2001563308
Short name T2422
Test name
Test status
Simulation time 22800322268 ps
CPU time 35.32 seconds
Started Aug 09 05:28:13 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 215984 kb
Host smart-a8e9c139-1e2a-44d4-8370-29db7ccbe275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20015
63308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2001563308
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2487006061
Short name T1141
Test name
Test status
Simulation time 11105346442 ps
CPU time 14.55 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207792 kb
Host smart-7cc1fd3f-196d-4ad0-947f-ee9e412ba352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24870
06061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2487006061
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1899483775
Short name T2782
Test name
Test status
Simulation time 3797545789 ps
CPU time 112.01 seconds
Started Aug 09 05:28:14 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 224156 kb
Host smart-7d3c7728-548a-4e86-ac53-55b59e87af10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1899483775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1899483775
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2113925152
Short name T722
Test name
Test status
Simulation time 2991732663 ps
CPU time 31.46 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 216872 kb
Host smart-d078e8d4-834e-4ee4-b246-99a5e575d44b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2113925152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2113925152
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2181673237
Short name T2141
Test name
Test status
Simulation time 250968369 ps
CPU time 1.01 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207484 kb
Host smart-09a74569-483a-4b6e-a059-61e6b19c6b5b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2181673237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2181673237
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.308915141
Short name T2364
Test name
Test status
Simulation time 212767165 ps
CPU time 1 seconds
Started Aug 09 05:28:13 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 207456 kb
Host smart-54fe8564-4278-4884-88ec-9ed9ad7b2bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30891
5141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.308915141
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.2380735081
Short name T2233
Test name
Test status
Simulation time 2296082885 ps
CPU time 61.73 seconds
Started Aug 09 05:28:06 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 224216 kb
Host smart-863e977d-60a5-45e1-aabd-24d05e903df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23807
35081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.2380735081
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2637735938
Short name T1241
Test name
Test status
Simulation time 2249962887 ps
CPU time 61.21 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 215980 kb
Host smart-9ac82522-78d4-4bf7-b963-747edf357223
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2637735938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2637735938
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1588512327
Short name T2601
Test name
Test status
Simulation time 152275091 ps
CPU time 0.89 seconds
Started Aug 09 05:28:03 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 207396 kb
Host smart-573e5b36-87fa-4059-8ea4-bcac87068071
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1588512327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1588512327
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3200111078
Short name T2461
Test name
Test status
Simulation time 160318160 ps
CPU time 0.94 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207432 kb
Host smart-dddeed7c-2c35-4b47-9d22-9d3cdaa3d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32001
11078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3200111078
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3946642989
Short name T118
Test name
Test status
Simulation time 202971588 ps
CPU time 0.89 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207356 kb
Host smart-304a6987-2912-4f6e-978f-86433a02a3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
42989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3946642989
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2074118333
Short name T3499
Test name
Test status
Simulation time 172674232 ps
CPU time 0.87 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207352 kb
Host smart-8dd4fc36-48f2-4e5b-a911-b1ab513eb025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
18333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2074118333
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3847468207
Short name T815
Test name
Test status
Simulation time 273374656 ps
CPU time 1.03 seconds
Started Aug 09 05:28:28 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 207352 kb
Host smart-3b9f28b3-29a9-4abb-aa39-1e9bb2d69855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38474
68207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3847468207
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.121090755
Short name T749
Test name
Test status
Simulation time 175957736 ps
CPU time 0.87 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207476 kb
Host smart-75b26ac9-fba2-48c0-a3d2-66d8ffe717a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12109
0755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.121090755
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.869254799
Short name T903
Test name
Test status
Simulation time 157415181 ps
CPU time 0.84 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 207480 kb
Host smart-9d0dfb47-140a-40cd-bace-c4a47d0e733c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86925
4799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.869254799
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2151035768
Short name T3053
Test name
Test status
Simulation time 214384922 ps
CPU time 1 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207464 kb
Host smart-dffadd2f-12c5-42a3-bb43-d52d3a673e0b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2151035768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2151035768
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3025859672
Short name T1490
Test name
Test status
Simulation time 146509061 ps
CPU time 0.85 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207524 kb
Host smart-3df5c30f-4ace-4123-a0bf-a924e994f3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
59672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3025859672
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1683759947
Short name T2011
Test name
Test status
Simulation time 57001657 ps
CPU time 0.72 seconds
Started Aug 09 05:28:40 PM PDT 24
Finished Aug 09 05:28:41 PM PDT 24
Peak memory 207444 kb
Host smart-6e61e406-a5da-486f-9c68-b95280a1879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
59947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1683759947
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1903316147
Short name T872
Test name
Test status
Simulation time 10622067423 ps
CPU time 27.12 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 219748 kb
Host smart-310a07d2-add7-4431-9552-717d8bd74d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
16147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1903316147
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.236681777
Short name T908
Test name
Test status
Simulation time 156497355 ps
CPU time 0.91 seconds
Started Aug 09 05:28:35 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207460 kb
Host smart-60bcf08a-b644-4bc9-9ffb-b05e3088a82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23668
1777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.236681777
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1643831467
Short name T1085
Test name
Test status
Simulation time 203285138 ps
CPU time 1 seconds
Started Aug 09 05:28:04 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 207380 kb
Host smart-02b061a4-f44e-4106-94e9-f48ff4e89ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
31467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1643831467
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.217192706
Short name T2142
Test name
Test status
Simulation time 241731465 ps
CPU time 1 seconds
Started Aug 09 05:28:05 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 207484 kb
Host smart-3b10bdee-b0d7-4043-9a54-d4419d7ef962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21719
2706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.217192706
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1014541399
Short name T3386
Test name
Test status
Simulation time 169112102 ps
CPU time 0.88 seconds
Started Aug 09 05:28:26 PM PDT 24
Finished Aug 09 05:28:27 PM PDT 24
Peak memory 207516 kb
Host smart-5d146951-9987-42cf-adf6-0cf7a71f5396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
41399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1014541399
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.2264426916
Short name T1387
Test name
Test status
Simulation time 20151374178 ps
CPU time 25.63 seconds
Started Aug 09 05:28:29 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207532 kb
Host smart-3bb6d74b-df28-4969-83aa-e093b9c91f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
26916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.2264426916
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1063907062
Short name T1566
Test name
Test status
Simulation time 181014503 ps
CPU time 0.89 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207456 kb
Host smart-25632573-073b-4a5d-b571-347759e14fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
07062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1063907062
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.1804559921
Short name T3193
Test name
Test status
Simulation time 237648070 ps
CPU time 1.09 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:28:27 PM PDT 24
Peak memory 207792 kb
Host smart-0d3e30a6-fb60-4277-a15f-56636b84dd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18045
59921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.1804559921
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4124228082
Short name T2004
Test name
Test status
Simulation time 181234892 ps
CPU time 0.87 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207404 kb
Host smart-6396d431-b948-48e8-b7ac-de06c40cb80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
28082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4124228082
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.44553396
Short name T657
Test name
Test status
Simulation time 205868668 ps
CPU time 0.88 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207536 kb
Host smart-e23dc301-56b6-4e4a-aa0f-67f7a53a44c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44553
396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.44553396
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3294448170
Short name T2254
Test name
Test status
Simulation time 224839250 ps
CPU time 1.02 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207496 kb
Host smart-0c1713c0-ae65-42a8-b912-e89c61008056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32944
48170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3294448170
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1657971293
Short name T2572
Test name
Test status
Simulation time 3003685036 ps
CPU time 83.34 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:29:31 PM PDT 24
Peak memory 224256 kb
Host smart-b64a1b82-ad44-4f08-9ff2-e2fccb353fa2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1657971293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1657971293
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2047555864
Short name T796
Test name
Test status
Simulation time 201336638 ps
CPU time 0.91 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207552 kb
Host smart-7d567d8d-d6c2-4e93-b8be-13861b29ec78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
55864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2047555864
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3426895277
Short name T1075
Test name
Test status
Simulation time 177372924 ps
CPU time 0.86 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207500 kb
Host smart-4ce857e2-c31c-4d07-9f38-fb54c016113d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268
95277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3426895277
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1983092411
Short name T1518
Test name
Test status
Simulation time 1208030033 ps
CPU time 2.76 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207604 kb
Host smart-2a2c0c4c-0657-4867-9fe1-c6b9efb887bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19830
92411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1983092411
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3938881554
Short name T821
Test name
Test status
Simulation time 2535568793 ps
CPU time 26.46 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:35 PM PDT 24
Peak memory 217680 kb
Host smart-1583334a-8ae8-4053-b1e3-6d7351aa75dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39388
81554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3938881554
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.1275134817
Short name T820
Test name
Test status
Simulation time 1132342802 ps
CPU time 25.53 seconds
Started Aug 09 05:28:07 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207688 kb
Host smart-502d581c-8e57-44cf-910d-be92ecb31a8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275134817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.1275134817
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.4238005916
Short name T2752
Test name
Test status
Simulation time 554424274 ps
CPU time 1.62 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 207560 kb
Host smart-4edcb18c-d162-4074-bab0-817511f01be7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238005916 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.4238005916
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.354487872
Short name T20
Test name
Test status
Simulation time 177417758 ps
CPU time 0.87 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207392 kb
Host smart-47c1c792-be86-4b88-bf53-175489ab619c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=354487872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.354487872
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.1086203102
Short name T1554
Test name
Test status
Simulation time 600147349 ps
CPU time 1.73 seconds
Started Aug 09 05:33:08 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 207528 kb
Host smart-5d52805a-d556-49d4-8819-ece13f483a86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086203102 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.1086203102
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.641534472
Short name T385
Test name
Test status
Simulation time 251965964 ps
CPU time 1.05 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207760 kb
Host smart-01a3b4b2-16f1-4995-a854-adccb8790b1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=641534472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.641534472
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.600752230
Short name T1557
Test name
Test status
Simulation time 233993966 ps
CPU time 0.99 seconds
Started Aug 09 05:33:31 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207448 kb
Host smart-0bdab40c-c52f-4d7c-b062-5a350eb6b427
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=600752230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.600752230
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.510099744
Short name T1261
Test name
Test status
Simulation time 481789064 ps
CPU time 1.64 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207496 kb
Host smart-191a3d60-dbec-4e50-9a9d-055ad49ef43b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510099744 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.510099744
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.1156848589
Short name T504
Test name
Test status
Simulation time 218032442 ps
CPU time 0.99 seconds
Started Aug 09 05:33:22 PM PDT 24
Finished Aug 09 05:33:23 PM PDT 24
Peak memory 207776 kb
Host smart-71412136-6832-45db-8ba3-5e1bc420bc0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1156848589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.1156848589
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.2407729112
Short name T73
Test name
Test status
Simulation time 491614241 ps
CPU time 1.63 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207556 kb
Host smart-8d957a54-d893-472e-b37a-8e1fdf46732a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407729112 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.2407729112
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.2651421170
Short name T473
Test name
Test status
Simulation time 197350402 ps
CPU time 1.04 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207496 kb
Host smart-e3fc3b33-ba1a-4c44-8991-435639545215
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2651421170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2651421170
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.2526215517
Short name T992
Test name
Test status
Simulation time 646409844 ps
CPU time 1.83 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207516 kb
Host smart-65f082d7-b75c-493f-81a9-8f6bbcf20e9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526215517 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.2526215517
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2664862613
Short name T474
Test name
Test status
Simulation time 510425437 ps
CPU time 1.42 seconds
Started Aug 09 05:33:12 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207516 kb
Host smart-500d810a-206d-49aa-b7ae-4e947dcda5be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2664862613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2664862613
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.2404907637
Short name T2862
Test name
Test status
Simulation time 487813094 ps
CPU time 1.55 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207396 kb
Host smart-22a92673-12b2-4cbb-9cb6-26a65ec9e88e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404907637 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.2404907637
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.880472985
Short name T1034
Test name
Test status
Simulation time 649036995 ps
CPU time 1.7 seconds
Started Aug 09 05:33:22 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207396 kb
Host smart-f187691a-2516-4cf9-87fb-525e1d1df8c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880472985 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.880472985
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.1318212469
Short name T476
Test name
Test status
Simulation time 194890472 ps
CPU time 0.89 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207448 kb
Host smart-8e6002a8-7b8d-48b1-876d-53791df8435a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1318212469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.1318212469
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.2922948464
Short name T2240
Test name
Test status
Simulation time 498154615 ps
CPU time 1.54 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207508 kb
Host smart-60592136-7a1d-4bfa-a805-1a226a06d650
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922948464 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.2922948464
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.1487981203
Short name T384
Test name
Test status
Simulation time 437333427 ps
CPU time 1.33 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207496 kb
Host smart-27bf9573-f69b-466b-9d37-9f62ec5757d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1487981203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.1487981203
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.1733764812
Short name T936
Test name
Test status
Simulation time 531589121 ps
CPU time 1.59 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207520 kb
Host smart-45cec2b3-0658-4ac7-bf8c-445a4b5c7d73
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733764812 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.1733764812
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2190079955
Short name T2068
Test name
Test status
Simulation time 68835694 ps
CPU time 0.71 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207456 kb
Host smart-052e4326-8776-4de3-90b7-1b393adf775b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2190079955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2190079955
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1735129066
Short name T1782
Test name
Test status
Simulation time 9855849124 ps
CPU time 12.58 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207804 kb
Host smart-e479d610-d3f7-4ef4-bf89-e09c7b544eb9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735129066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.1735129066
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1292151611
Short name T509
Test name
Test status
Simulation time 20986986327 ps
CPU time 24.07 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207752 kb
Host smart-206b465e-9657-47ed-a740-7693baf68ba7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292151611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1292151611
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.4037120395
Short name T1939
Test name
Test status
Simulation time 29850218541 ps
CPU time 36.72 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 207816 kb
Host smart-88be4b23-7dd1-4dd9-9b8e-76bc9aa922c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037120395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.4037120395
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3778753190
Short name T3270
Test name
Test status
Simulation time 161416067 ps
CPU time 0.9 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207508 kb
Host smart-839113e0-1396-48d9-bb09-9ce4f8ced20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787
53190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3778753190
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1426240193
Short name T1424
Test name
Test status
Simulation time 155320687 ps
CPU time 0.86 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207480 kb
Host smart-b07c363e-8820-4dfe-a423-f1f8067ecbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
40193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1426240193
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1280454594
Short name T2123
Test name
Test status
Simulation time 255811320 ps
CPU time 1.11 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207504 kb
Host smart-5eb38e45-cf4a-43db-ad79-ca96e4ff1966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12804
54594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1280454594
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1946281878
Short name T2323
Test name
Test status
Simulation time 1011945036 ps
CPU time 2.79 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 207764 kb
Host smart-ee4b1038-3c7a-413e-b4d5-2076bfccb317
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1946281878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1946281878
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.399412075
Short name T3612
Test name
Test status
Simulation time 44504946676 ps
CPU time 67.17 seconds
Started Aug 09 05:28:34 PM PDT 24
Finished Aug 09 05:29:42 PM PDT 24
Peak memory 207788 kb
Host smart-d268326c-4fe6-427a-821f-d8ab15bc3e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39941
2075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.399412075
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.1859696914
Short name T1832
Test name
Test status
Simulation time 4374048523 ps
CPU time 38.66 seconds
Started Aug 09 05:28:25 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207728 kb
Host smart-4018398e-6b3a-4c7e-8ba1-f65c3e3e0a90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859696914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1859696914
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1252744400
Short name T379
Test name
Test status
Simulation time 1109185761 ps
CPU time 2.54 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207360 kb
Host smart-e5102cfb-fd46-428c-890f-052f2e121f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
44400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1252744400
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.716817468
Short name T2276
Test name
Test status
Simulation time 185082338 ps
CPU time 0.85 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207376 kb
Host smart-3af97426-be0c-4f6e-9345-7e26f6e5ab8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71681
7468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.716817468
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3286866263
Short name T2860
Test name
Test status
Simulation time 45988459 ps
CPU time 0.69 seconds
Started Aug 09 05:28:14 PM PDT 24
Finished Aug 09 05:28:15 PM PDT 24
Peak memory 207404 kb
Host smart-9a2f67e1-57e3-4b11-b422-8bcd366e125e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32868
66263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3286866263
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.857872797
Short name T3629
Test name
Test status
Simulation time 926970994 ps
CPU time 2.53 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:13 PM PDT 24
Peak memory 207752 kb
Host smart-62f22b09-af51-48dc-9d0e-1c1a6f80a1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85787
2797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.857872797
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.3875830413
Short name T411
Test name
Test status
Simulation time 259960823 ps
CPU time 1.08 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207468 kb
Host smart-8cd42997-2f81-4eb8-a6c0-3f6e83a8e64f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3875830413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3875830413
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3079787278
Short name T3420
Test name
Test status
Simulation time 215372910 ps
CPU time 1.64 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 207620 kb
Host smart-c28566b8-9ca3-4be0-a04a-2c89bc437450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30797
87278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3079787278
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3593295137
Short name T2367
Test name
Test status
Simulation time 186897789 ps
CPU time 0.92 seconds
Started Aug 09 05:28:16 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207484 kb
Host smart-ece4df36-84fb-419c-8384-7ba07151c590
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3593295137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3593295137
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4029561620
Short name T2271
Test name
Test status
Simulation time 151930506 ps
CPU time 0.88 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207360 kb
Host smart-dfa86969-ef92-470f-b10c-ccc9b215e6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
61620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4029561620
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3633882529
Short name T3157
Test name
Test status
Simulation time 215070953 ps
CPU time 0.94 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207528 kb
Host smart-8f9d22d9-cea8-4690-8cdd-9af76aa9d676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
82529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3633882529
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.3456722679
Short name T1191
Test name
Test status
Simulation time 4879913285 ps
CPU time 152.14 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 218388 kb
Host smart-5176bd47-63bc-4f78-a23a-1e37bf7d57f5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3456722679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.3456722679
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.3865354484
Short name T1435
Test name
Test status
Simulation time 7916883413 ps
CPU time 97.06 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207788 kb
Host smart-2bfa1790-b2b1-4d80-9a96-e1eae52904be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3865354484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3865354484
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3275826801
Short name T1531
Test name
Test status
Simulation time 231566516 ps
CPU time 0.99 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:10 PM PDT 24
Peak memory 207496 kb
Host smart-1e62f0df-3878-4c82-a2e3-48f39b1769f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32758
26801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3275826801
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.832533971
Short name T643
Test name
Test status
Simulation time 6355743943 ps
CPU time 9.15 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 216080 kb
Host smart-b06187d9-474c-4283-9723-6b03f8b90d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83253
3971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.832533971
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2079588544
Short name T961
Test name
Test status
Simulation time 5110713970 ps
CPU time 7.53 seconds
Started Aug 09 05:28:17 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 216764 kb
Host smart-dcbebf91-3df6-4fc1-b929-69ffb3db7a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20795
88544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2079588544
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2929748759
Short name T158
Test name
Test status
Simulation time 4220399288 ps
CPU time 33.56 seconds
Started Aug 09 05:28:10 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 219740 kb
Host smart-7c76c883-6d52-4c0e-9a02-d57a5e90cb93
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2929748759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2929748759
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.395796698
Short name T1200
Test name
Test status
Simulation time 2668564661 ps
CPU time 26.07 seconds
Started Aug 09 05:28:13 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 216344 kb
Host smart-1324c747-b929-4af9-b2f8-4ecf86244af8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=395796698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.395796698
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3992337512
Short name T975
Test name
Test status
Simulation time 243159500 ps
CPU time 1.02 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:12 PM PDT 24
Peak memory 207432 kb
Host smart-7a2c0306-045f-470a-9149-7805451e59f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3992337512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3992337512
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.74529297
Short name T1874
Test name
Test status
Simulation time 255190477 ps
CPU time 1 seconds
Started Aug 09 05:28:08 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 207512 kb
Host smart-442c068b-1d86-4ea5-a122-10a68198eaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74529
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.74529297
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.1089491045
Short name T3108
Test name
Test status
Simulation time 2735813635 ps
CPU time 28.52 seconds
Started Aug 09 05:28:11 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 217952 kb
Host smart-fb951995-493a-4b11-8a42-a12a1f98fe6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
91045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.1089491045
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.4226892438
Short name T2697
Test name
Test status
Simulation time 2330341924 ps
CPU time 22.56 seconds
Started Aug 09 05:28:09 PM PDT 24
Finished Aug 09 05:28:32 PM PDT 24
Peak memory 217232 kb
Host smart-ea87bd77-aef9-469e-aad2-22da45e151ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4226892438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.4226892438
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2778694183
Short name T3406
Test name
Test status
Simulation time 154418438 ps
CPU time 0.85 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207500 kb
Host smart-775fe3ed-f45b-4c8d-b612-f6f3818ebe13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2778694183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2778694183
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3453854917
Short name T1536
Test name
Test status
Simulation time 150726569 ps
CPU time 0.87 seconds
Started Aug 09 05:28:35 PM PDT 24
Finished Aug 09 05:28:36 PM PDT 24
Peak memory 207360 kb
Host smart-e97ae21b-519f-48d9-b265-83a4d6656835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
54917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3453854917
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1564642397
Short name T230
Test name
Test status
Simulation time 216202226 ps
CPU time 0.99 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207428 kb
Host smart-272700f6-8827-44af-8396-99e2e5533aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15646
42397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1564642397
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1135569163
Short name T3045
Test name
Test status
Simulation time 155111774 ps
CPU time 0.85 seconds
Started Aug 09 05:28:29 PM PDT 24
Finished Aug 09 05:28:30 PM PDT 24
Peak memory 207472 kb
Host smart-fcffde1d-7458-434e-a18d-fcdf3b9707b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11355
69163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1135569163
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1938208895
Short name T3507
Test name
Test status
Simulation time 176566929 ps
CPU time 0.92 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 207428 kb
Host smart-981929bf-08ff-40b4-a650-ae40caf1efe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
08895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1938208895
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.671144409
Short name T588
Test name
Test status
Simulation time 177600516 ps
CPU time 0.91 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:32 PM PDT 24
Peak memory 207364 kb
Host smart-ac27971c-d6e0-41bb-a106-07c803c616b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67114
4409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.671144409
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.254745871
Short name T1987
Test name
Test status
Simulation time 283748982 ps
CPU time 1.09 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 207424 kb
Host smart-7753f84e-72d9-48ec-94f4-215106610e93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=254745871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.254745871
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.4221216488
Short name T1103
Test name
Test status
Simulation time 149014375 ps
CPU time 0.83 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207404 kb
Host smart-a97d4d1b-d8cc-4036-9d96-4cb0fd2ecef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42212
16488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.4221216488
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2505134013
Short name T2119
Test name
Test status
Simulation time 33600252 ps
CPU time 0.72 seconds
Started Aug 09 05:28:39 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207328 kb
Host smart-4e5cac93-803a-49b6-b694-ade95b0f6070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
34013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2505134013
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.193296647
Short name T1051
Test name
Test status
Simulation time 182820816 ps
CPU time 0.91 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207488 kb
Host smart-682da6c5-8eea-462a-a71b-285a3c50677b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19329
6647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.193296647
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.140507028
Short name T2391
Test name
Test status
Simulation time 193914818 ps
CPU time 0.94 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207544 kb
Host smart-5fbe1429-19d8-41b9-869e-2e2d87b43183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050
7028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.140507028
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1115709397
Short name T513
Test name
Test status
Simulation time 215929030 ps
CPU time 0.95 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207792 kb
Host smart-f2b31a3b-fdbd-4bff-ab24-6a855eb488f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
09397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1115709397
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1036344265
Short name T1716
Test name
Test status
Simulation time 174092717 ps
CPU time 0.89 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207556 kb
Host smart-ab2e1b3d-93da-4f3d-8949-13e4a34a75fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10363
44265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1036344265
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.1132368459
Short name T1390
Test name
Test status
Simulation time 20161768525 ps
CPU time 27.46 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207584 kb
Host smart-442b33c5-581d-49f8-b013-99db4a8c9f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
68459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.1132368459
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2036684705
Short name T69
Test name
Test status
Simulation time 183636001 ps
CPU time 0.88 seconds
Started Aug 09 05:28:18 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 207436 kb
Host smart-deeb7a20-0131-41e3-ab54-2d9eecb2ec94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
84705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2036684705
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3906078811
Short name T1364
Test name
Test status
Simulation time 162996804 ps
CPU time 0.85 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207460 kb
Host smart-bcfce190-3e31-428b-baad-f3350987123a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
78811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3906078811
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2459543453
Short name T1994
Test name
Test status
Simulation time 147928561 ps
CPU time 0.86 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207436 kb
Host smart-acefda62-f3de-4797-a747-f089872006d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24595
43453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2459543453
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3632211533
Short name T3101
Test name
Test status
Simulation time 278800386 ps
CPU time 1.05 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207496 kb
Host smart-423173a4-5afa-40a6-b62a-8420f351b731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36322
11533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3632211533
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1274959772
Short name T700
Test name
Test status
Simulation time 3617690276 ps
CPU time 34.04 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 217540 kb
Host smart-5615344a-4c98-41b6-a1ed-7c619db353bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1274959772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1274959772
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2025316940
Short name T1262
Test name
Test status
Simulation time 184378487 ps
CPU time 0.9 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207516 kb
Host smart-e674e138-6f61-4b7f-b366-82bdef3520c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
16940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2025316940
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1933899455
Short name T1661
Test name
Test status
Simulation time 181955913 ps
CPU time 0.95 seconds
Started Aug 09 05:28:17 PM PDT 24
Finished Aug 09 05:28:18 PM PDT 24
Peak memory 207456 kb
Host smart-d3a7af18-4717-42eb-a855-ca9f78bcf2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
99455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1933899455
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.2064178228
Short name T2939
Test name
Test status
Simulation time 1325113793 ps
CPU time 3.29 seconds
Started Aug 09 05:28:20 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207704 kb
Host smart-a62a6b76-b0ad-43eb-8a65-42e9449e83fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20641
78228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2064178228
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3083058224
Short name T596
Test name
Test status
Simulation time 2356203203 ps
CPU time 69.08 seconds
Started Aug 09 05:28:25 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 216020 kb
Host smart-77032afc-f155-4faa-a22a-b4a625cfed6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30830
58224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3083058224
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.744567648
Short name T3124
Test name
Test status
Simulation time 4298640466 ps
CPU time 29.96 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207684 kb
Host smart-f14cd21f-103d-427e-84df-1772845d6eeb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744567648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.744567648
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.2263316905
Short name T2805
Test name
Test status
Simulation time 318996297 ps
CPU time 1.26 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207516 kb
Host smart-9ea7b5e8-d042-49b4-b8cc-a96c2dbf3271
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2263316905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.2263316905
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.1548852320
Short name T3571
Test name
Test status
Simulation time 525463858 ps
CPU time 1.65 seconds
Started Aug 09 05:33:08 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207444 kb
Host smart-03cbf7f2-0d28-47f3-8cfe-17c17d390811
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548852320 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.1548852320
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.2093366898
Short name T3380
Test name
Test status
Simulation time 501468237 ps
CPU time 1.36 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207452 kb
Host smart-38de9f27-40b4-4a4a-8d0b-cb542ae8a501
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2093366898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.2093366898
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.929941202
Short name T1932
Test name
Test status
Simulation time 456664143 ps
CPU time 1.47 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207532 kb
Host smart-8d2a431d-70ba-4d02-898e-a683e00f393d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929941202 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.929941202
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.1635938455
Short name T432
Test name
Test status
Simulation time 245524342 ps
CPU time 0.97 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207456 kb
Host smart-3dbb40e4-274a-4bf6-a5e1-21ad5978d9ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1635938455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.1635938455
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.2574983220
Short name T1635
Test name
Test status
Simulation time 623231689 ps
CPU time 1.68 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207480 kb
Host smart-0671bca7-1bfa-486b-8994-a16341d59ce7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574983220 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.2574983220
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.3263189652
Short name T394
Test name
Test status
Simulation time 481024663 ps
CPU time 1.29 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207432 kb
Host smart-1deab7a3-54f7-4d9f-97ec-07440ec18ad6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3263189652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3263189652
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.2534379628
Short name T1499
Test name
Test status
Simulation time 527885035 ps
CPU time 1.75 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207512 kb
Host smart-e1022572-7ad8-4649-be66-7211d8ba3a5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534379628 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.2534379628
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.349996699
Short name T1737
Test name
Test status
Simulation time 184431908 ps
CPU time 1 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207464 kb
Host smart-591c26b5-9ee1-4b83-92d3-21adb4f18dd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=349996699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.349996699
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.2605869933
Short name T1771
Test name
Test status
Simulation time 546918946 ps
CPU time 1.62 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207508 kb
Host smart-7f55c475-f38b-4422-985e-8ef0ebcb9c91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605869933 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.2605869933
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.501169277
Short name T1275
Test name
Test status
Simulation time 448761053 ps
CPU time 1.46 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207476 kb
Host smart-0747173e-4334-4577-8e41-335c9f520315
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501169277 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.501169277
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.4027065033
Short name T2994
Test name
Test status
Simulation time 597821584 ps
CPU time 1.58 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207600 kb
Host smart-82a8e2ff-973e-4a32-9e2d-7b611f64fea5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027065033 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.4027065033
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.449941055
Short name T2033
Test name
Test status
Simulation time 212418089 ps
CPU time 0.97 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207468 kb
Host smart-fd620f56-fcd7-4564-a72c-b0176260a72f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=449941055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.449941055
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.3457997483
Short name T154
Test name
Test status
Simulation time 590990423 ps
CPU time 1.52 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207400 kb
Host smart-8604addc-6558-4311-9f70-303d78ec9b26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457997483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.3457997483
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.597377144
Short name T484
Test name
Test status
Simulation time 176327862 ps
CPU time 0.93 seconds
Started Aug 09 05:33:14 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207532 kb
Host smart-7f3a7f9a-3cf0-4862-b71e-d5fe41f14ec1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=597377144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.597377144
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.3483112655
Short name T196
Test name
Test status
Simulation time 542663827 ps
CPU time 1.87 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207560 kb
Host smart-b45c6f41-7ce1-4739-88aa-d86dc2bae5ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483112655 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.3483112655
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.1964113802
Short name T3029
Test name
Test status
Simulation time 384832471 ps
CPU time 1.2 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207456 kb
Host smart-e5b4a517-44e8-4434-831b-6c130d529b7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1964113802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.1964113802
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.2678635523
Short name T3230
Test name
Test status
Simulation time 488029414 ps
CPU time 1.48 seconds
Started Aug 09 05:33:12 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207536 kb
Host smart-b1393470-1ba7-4215-945d-38b5ea195e28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678635523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.2678635523
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3209386667
Short name T2128
Test name
Test status
Simulation time 35142477 ps
CPU time 0.67 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 207808 kb
Host smart-e341c8d1-d985-4826-94ba-0897ae326f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3209386667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3209386667
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3943121169
Short name T1656
Test name
Test status
Simulation time 6864746740 ps
CPU time 9.12 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 215960 kb
Host smart-71467907-bc0b-4521-895b-323b20d6fa33
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943121169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.3943121169
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3079079596
Short name T1839
Test name
Test status
Simulation time 13424246148 ps
CPU time 15.94 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 215956 kb
Host smart-4f463284-6c3a-4823-a6a1-b6d7bb2d2ad9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079079596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3079079596
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2011573963
Short name T2423
Test name
Test status
Simulation time 28567828678 ps
CPU time 34.17 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207724 kb
Host smart-5cd0f8ca-edad-4ef9-bc89-a5380ed47935
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011573963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2011573963
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3909879737
Short name T738
Test name
Test status
Simulation time 160499217 ps
CPU time 0.89 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:21 PM PDT 24
Peak memory 207492 kb
Host smart-ff9e7c1e-72c7-43a5-8a8b-ce32c5d0beb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
79737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3909879737
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2552419627
Short name T1015
Test name
Test status
Simulation time 196695864 ps
CPU time 0.89 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207536 kb
Host smart-c1b0fdc2-a9ab-454f-b840-255fff8e53d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
19627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2552419627
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.3771489101
Short name T2735
Test name
Test status
Simulation time 414348845 ps
CPU time 1.48 seconds
Started Aug 09 05:28:39 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 207412 kb
Host smart-b5ea125f-f89a-4baa-b63e-b0602e1d2421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
89101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.3771489101
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4247389119
Short name T2613
Test name
Test status
Simulation time 659348785 ps
CPU time 2.02 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 207692 kb
Host smart-716f5050-88f3-42c1-a422-2b47bbc25ec8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4247389119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4247389119
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.163492233
Short name T2742
Test name
Test status
Simulation time 49968607328 ps
CPU time 83.19 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207684 kb
Host smart-4af03c75-d316-44a4-9f90-c94535807486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
2233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.163492233
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3882054965
Short name T550
Test name
Test status
Simulation time 1309543916 ps
CPU time 30.02 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207604 kb
Host smart-da163cf4-a4df-4036-814a-92f28c91327a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882054965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3882054965
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1169350557
Short name T1860
Test name
Test status
Simulation time 647785767 ps
CPU time 1.65 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207516 kb
Host smart-8f2606b3-32f9-4811-bf82-6a4e5a9f7e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
50557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1169350557
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3434278965
Short name T3005
Test name
Test status
Simulation time 139654320 ps
CPU time 0.82 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207452 kb
Host smart-c52ead82-062f-40a2-af11-0b9c9bbd1303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34342
78965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3434278965
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1138518440
Short name T3274
Test name
Test status
Simulation time 53526336 ps
CPU time 0.74 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207516 kb
Host smart-3170f6a4-18e6-48f6-a678-0bbc03d329b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
18440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1138518440
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2133652863
Short name T3112
Test name
Test status
Simulation time 947768395 ps
CPU time 2.46 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:25 PM PDT 24
Peak memory 207608 kb
Host smart-7510ea46-2e2c-494d-8d26-10169578afdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21336
52863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2133652863
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.627480636
Short name T3505
Test name
Test status
Simulation time 357066688 ps
CPU time 1.21 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:25 PM PDT 24
Peak memory 207356 kb
Host smart-75aeb1c3-ac6a-471d-85b9-ec6703f905ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=627480636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.627480636
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1051979788
Short name T83
Test name
Test status
Simulation time 190617201 ps
CPU time 2.17 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:25 PM PDT 24
Peak memory 207572 kb
Host smart-7cc2d274-84c4-48ef-847f-81fc4e77d18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
79788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1051979788
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2143954856
Short name T2502
Test name
Test status
Simulation time 208095128 ps
CPU time 1.12 seconds
Started Aug 09 05:28:27 PM PDT 24
Finished Aug 09 05:28:28 PM PDT 24
Peak memory 215856 kb
Host smart-eacc46c9-81bc-467b-8f2d-abfe115b5899
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2143954856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2143954856
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1445347934
Short name T1233
Test name
Test status
Simulation time 147530262 ps
CPU time 0.82 seconds
Started Aug 09 05:28:19 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207476 kb
Host smart-95486edc-7bec-4581-9b39-00508193aff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14453
47934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1445347934
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.753396244
Short name T916
Test name
Test status
Simulation time 195641213 ps
CPU time 0.95 seconds
Started Aug 09 05:28:30 PM PDT 24
Finished Aug 09 05:28:31 PM PDT 24
Peak memory 207400 kb
Host smart-88bd9d2a-1349-4480-bce9-205b588fc12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75339
6244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.753396244
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1520737706
Short name T3134
Test name
Test status
Simulation time 3448167000 ps
CPU time 101.64 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 215944 kb
Host smart-8fab4ed6-41a4-473a-958d-ca906785fff8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1520737706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1520737706
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1857552945
Short name T3341
Test name
Test status
Simulation time 8973320680 ps
CPU time 107.97 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207652 kb
Host smart-1b5b4b6b-d17f-4496-9552-f1ceff4ddc3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1857552945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1857552945
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.4054903921
Short name T1991
Test name
Test status
Simulation time 194191447 ps
CPU time 0.92 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207432 kb
Host smart-47a49409-e5f5-48f7-af4d-4e3f1d30d82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
03921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.4054903921
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2632392869
Short name T2358
Test name
Test status
Simulation time 14629838666 ps
CPU time 21.26 seconds
Started Aug 09 05:28:26 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207672 kb
Host smart-3f4f6348-5589-409d-8880-f0e7a2da0472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
92869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2632392869
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2671213790
Short name T3490
Test name
Test status
Simulation time 5359692758 ps
CPU time 7.8 seconds
Started Aug 09 05:28:27 PM PDT 24
Finished Aug 09 05:28:35 PM PDT 24
Peak memory 216060 kb
Host smart-d9ab1f45-d5cc-4a86-89b0-8cd53ea02525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26712
13790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2671213790
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2073899056
Short name T57
Test name
Test status
Simulation time 5053345376 ps
CPU time 53.85 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 219260 kb
Host smart-1d6b9292-912e-4bfe-bf43-0d98fd002f12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2073899056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2073899056
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3550417228
Short name T1367
Test name
Test status
Simulation time 2093240564 ps
CPU time 15.92 seconds
Started Aug 09 05:28:29 PM PDT 24
Finished Aug 09 05:28:45 PM PDT 24
Peak memory 224060 kb
Host smart-30fbf857-acd9-409c-b499-e5f237349dc3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3550417228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3550417228
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2355868191
Short name T2134
Test name
Test status
Simulation time 287312470 ps
CPU time 1.02 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 207528 kb
Host smart-2ce1ce01-5a3f-4bc8-8fe6-da7a30756434
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2355868191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2355868191
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2067609085
Short name T2075
Test name
Test status
Simulation time 194696274 ps
CPU time 1.01 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207548 kb
Host smart-c76737f1-b0a3-43bb-81a3-ba8a87bd53aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20676
09085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2067609085
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.2133397451
Short name T2926
Test name
Test status
Simulation time 3478314279 ps
CPU time 28.31 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 217988 kb
Host smart-fce5dea4-f54e-4c34-81ef-2579ef80768b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21333
97451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.2133397451
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.254874058
Short name T1304
Test name
Test status
Simulation time 2360201196 ps
CPU time 65.97 seconds
Started Aug 09 05:28:40 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 215984 kb
Host smart-4e75798e-a19f-47f1-bcdc-0f0cf7bf1aa6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=254874058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.254874058
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.4133867067
Short name T1288
Test name
Test status
Simulation time 250506353 ps
CPU time 1 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207376 kb
Host smart-d5a25636-cc42-4655-a4b9-c0af2c45b340
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4133867067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.4133867067
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3919457737
Short name T1783
Test name
Test status
Simulation time 148018325 ps
CPU time 0.87 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207548 kb
Host smart-5c026648-ab72-450d-8435-16b12b134ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
57737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3919457737
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4281528195
Short name T3021
Test name
Test status
Simulation time 184327014 ps
CPU time 0.89 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207404 kb
Host smart-c08a8606-92c3-4779-aa1b-4a1d74c45032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
28195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4281528195
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.550717592
Short name T3419
Test name
Test status
Simulation time 152520929 ps
CPU time 0.85 seconds
Started Aug 09 05:28:27 PM PDT 24
Finished Aug 09 05:28:28 PM PDT 24
Peak memory 207400 kb
Host smart-55627a23-d985-4021-b846-430b26a71c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55071
7592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.550717592
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1388717488
Short name T3523
Test name
Test status
Simulation time 161504983 ps
CPU time 0.85 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207476 kb
Host smart-4c2ec727-9176-4eb1-93fe-ed186aa9b011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13887
17488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1388717488
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1107092945
Short name T2506
Test name
Test status
Simulation time 186039068 ps
CPU time 0.93 seconds
Started Aug 09 05:28:28 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 207752 kb
Host smart-ebe74197-2b1d-463d-a654-26022a1e8dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11070
92945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1107092945
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2628064061
Short name T1732
Test name
Test status
Simulation time 161190857 ps
CPU time 0.84 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207512 kb
Host smart-c39d1c74-e9c0-473b-8a07-d62b30fdd669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26280
64061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2628064061
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.820029768
Short name T1695
Test name
Test status
Simulation time 222088775 ps
CPU time 0.99 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207544 kb
Host smart-6dbabef8-e51a-4a80-9383-59b7e434c9a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=820029768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.820029768
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3034550036
Short name T3472
Test name
Test status
Simulation time 157337698 ps
CPU time 0.86 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207452 kb
Host smart-2ba5e942-fd56-49e9-9157-2436c413a67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
50036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3034550036
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3345310685
Short name T2132
Test name
Test status
Simulation time 43985265 ps
CPU time 0.74 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 207436 kb
Host smart-90bb5e5b-8ee8-4aa2-8101-9da2088013f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33453
10685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3345310685
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.335675099
Short name T3436
Test name
Test status
Simulation time 13704567931 ps
CPU time 36.61 seconds
Started Aug 09 05:28:40 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 224464 kb
Host smart-991a890b-da38-4180-8c75-85f2dda34acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
5099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.335675099
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1642899980
Short name T560
Test name
Test status
Simulation time 190747665 ps
CPU time 0.94 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207788 kb
Host smart-a1bbeaa4-e503-4abb-85dd-e3271b48ef7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
99980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1642899980
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3094273661
Short name T2144
Test name
Test status
Simulation time 184749919 ps
CPU time 0.91 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207432 kb
Host smart-c11461a2-8345-43a0-8eba-8eea9a78a235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
73661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3094273661
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2642161767
Short name T589
Test name
Test status
Simulation time 194262645 ps
CPU time 0.94 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207472 kb
Host smart-65c8f48a-e0ed-4064-bf81-6bf68dcef5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26421
61767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2642161767
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2067895343
Short name T2072
Test name
Test status
Simulation time 158852690 ps
CPU time 0.88 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207508 kb
Host smart-185e86c2-3f50-40e5-b3d1-b64dc75e3450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20678
95343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2067895343
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.2333259127
Short name T3047
Test name
Test status
Simulation time 20155231744 ps
CPU time 25.03 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207628 kb
Host smart-32194e9d-2464-476f-baf9-7b1a6d9dd7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23332
59127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.2333259127
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1160224263
Short name T1135
Test name
Test status
Simulation time 223889775 ps
CPU time 0.96 seconds
Started Aug 09 05:28:27 PM PDT 24
Finished Aug 09 05:28:28 PM PDT 24
Peak memory 207396 kb
Host smart-cc34cb39-ace4-4186-a6d2-0012998a4aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11602
24263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1160224263
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2808793004
Short name T1515
Test name
Test status
Simulation time 151896879 ps
CPU time 0.85 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207756 kb
Host smart-9a53e124-c9d6-4baf-9619-3b6503395b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28087
93004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2808793004
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2320706185
Short name T2836
Test name
Test status
Simulation time 217730422 ps
CPU time 0.91 seconds
Started Aug 09 05:28:21 PM PDT 24
Finished Aug 09 05:28:22 PM PDT 24
Peak memory 207500 kb
Host smart-45522ffc-1518-4f97-9541-53f076e93235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
06185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2320706185
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1082459817
Short name T1123
Test name
Test status
Simulation time 243630075 ps
CPU time 1.06 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207508 kb
Host smart-322b8a93-a398-45fd-a577-e60ea22dd458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
59817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1082459817
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2746363972
Short name T2773
Test name
Test status
Simulation time 2034867957 ps
CPU time 15.68 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 223936 kb
Host smart-d9d9d03e-166a-436c-ac14-0ef103f13111
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2746363972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2746363972
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2086926279
Short name T2140
Test name
Test status
Simulation time 208120200 ps
CPU time 0.91 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207464 kb
Host smart-4e1b2ecb-f971-4dc7-bd46-8c4be285377b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20869
26279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2086926279
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2393971264
Short name T2177
Test name
Test status
Simulation time 158840884 ps
CPU time 0.85 seconds
Started Aug 09 05:28:28 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 207528 kb
Host smart-45657f05-07b3-458e-a6c0-5b4dd598e2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23939
71264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2393971264
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.923341011
Short name T2348
Test name
Test status
Simulation time 410960208 ps
CPU time 1.37 seconds
Started Aug 09 05:28:23 PM PDT 24
Finished Aug 09 05:28:24 PM PDT 24
Peak memory 207352 kb
Host smart-42bbcb2a-16f2-4413-a2b4-32ea08b81d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92334
1011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.923341011
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3606740873
Short name T2325
Test name
Test status
Simulation time 2457233855 ps
CPU time 24.95 seconds
Started Aug 09 05:28:22 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 215960 kb
Host smart-d6da743d-0257-46bf-98bf-a5e9a3e1908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36067
40873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3606740873
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4213546823
Short name T1630
Test name
Test status
Simulation time 4278303190 ps
CPU time 27.68 seconds
Started Aug 09 05:28:26 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207652 kb
Host smart-c0024db1-a53d-4c13-a598-a21a839aaefc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213546823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.4213546823
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.649877950
Short name T2247
Test name
Test status
Simulation time 559689984 ps
CPU time 1.56 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 207424 kb
Host smart-f2ef079f-02c9-424e-9212-7abba89fe303
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649877950 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.649877950
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.1871609503
Short name T3289
Test name
Test status
Simulation time 271811258 ps
CPU time 0.94 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207348 kb
Host smart-36dbd981-c52a-4fa5-b650-f2336dae578f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1871609503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.1871609503
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.4110795887
Short name T1179
Test name
Test status
Simulation time 453640360 ps
CPU time 1.39 seconds
Started Aug 09 05:33:12 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207496 kb
Host smart-e00456ae-601b-4bc1-82b4-75619a0ea884
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110795887 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.4110795887
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.558105271
Short name T367
Test name
Test status
Simulation time 439262339 ps
CPU time 1.19 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207488 kb
Host smart-8719f789-2fd3-4073-9c37-111f07fda715
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=558105271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.558105271
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.2141029349
Short name T3070
Test name
Test status
Simulation time 488320213 ps
CPU time 1.51 seconds
Started Aug 09 05:33:14 PM PDT 24
Finished Aug 09 05:33:16 PM PDT 24
Peak memory 207484 kb
Host smart-ebf490fe-d5b5-42fa-8905-b9fcf50316b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141029349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.2141029349
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.3513646170
Short name T2427
Test name
Test status
Simulation time 452029633 ps
CPU time 1.38 seconds
Started Aug 09 05:33:25 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207376 kb
Host smart-7f6464b6-6403-4a4e-97fa-6690a4ba8912
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3513646170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.3513646170
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.4120332451
Short name T1178
Test name
Test status
Simulation time 510806846 ps
CPU time 1.55 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207516 kb
Host smart-ec8a150a-a1a8-495a-9c64-93f3adf832d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120332451 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.4120332451
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.2621172765
Short name T3533
Test name
Test status
Simulation time 399801929 ps
CPU time 1.34 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207456 kb
Host smart-c759124b-0017-4de3-ab10-8153369508c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2621172765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.2621172765
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.792952935
Short name T2095
Test name
Test status
Simulation time 440396012 ps
CPU time 1.35 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207392 kb
Host smart-5771fbb4-b9fb-4666-a762-43901cb90e32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792952935 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.792952935
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.902640155
Short name T502
Test name
Test status
Simulation time 351042674 ps
CPU time 1.13 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207344 kb
Host smart-80ec611b-07a5-42f6-b8be-444317f45d9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=902640155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.902640155
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.1593575020
Short name T1023
Test name
Test status
Simulation time 509746744 ps
CPU time 1.38 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207496 kb
Host smart-8bde2425-8dba-4b05-9af6-59fb5e6365cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593575020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.1593575020
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.406433546
Short name T1346
Test name
Test status
Simulation time 498172252 ps
CPU time 1.49 seconds
Started Aug 09 05:33:05 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207416 kb
Host smart-951a685c-907f-4416-9d9b-860267707038
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406433546 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.406433546
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.4269111666
Short name T2786
Test name
Test status
Simulation time 756949833 ps
CPU time 1.85 seconds
Started Aug 09 05:33:39 PM PDT 24
Finished Aug 09 05:33:41 PM PDT 24
Peak memory 207392 kb
Host smart-a903a4b6-a982-4c05-a7f7-520ed6a637bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269111666 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.4269111666
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.4162254973
Short name T3578
Test name
Test status
Simulation time 339793943 ps
CPU time 1.25 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 207472 kb
Host smart-7977e914-3ce5-41e8-a63b-0c8a089c472e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4162254973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.4162254973
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.1473674761
Short name T100
Test name
Test status
Simulation time 478003923 ps
CPU time 1.42 seconds
Started Aug 09 05:33:44 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207444 kb
Host smart-65d959d3-5386-42fd-922a-220d2bc2d544
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473674761 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.1473674761
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.2403808828
Short name T3424
Test name
Test status
Simulation time 450718536 ps
CPU time 1.27 seconds
Started Aug 09 05:33:35 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207520 kb
Host smart-c0076975-5fe5-43ec-8484-ca0fd9e54138
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2403808828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.2403808828
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.362726370
Short name T1867
Test name
Test status
Simulation time 603035943 ps
CPU time 1.72 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207484 kb
Host smart-52ad5e5b-e43c-4627-9b13-44e060452675
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362726370 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.362726370
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.1305100197
Short name T609
Test name
Test status
Simulation time 518865606 ps
CPU time 1.65 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207392 kb
Host smart-8a9172c5-2ff2-4bff-8777-625fb6ca6ef5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305100197 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.1305100197
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1799438185
Short name T1426
Test name
Test status
Simulation time 46293029 ps
CPU time 0.73 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207496 kb
Host smart-21ec70fe-f382-425b-a387-7d84fa49b6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1799438185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1799438185
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3020964890
Short name T2680
Test name
Test status
Simulation time 8995035837 ps
CPU time 11.65 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207736 kb
Host smart-a3e7c75b-f9dd-4ad3-8b67-b2465cb40597
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020964890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.3020964890
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2936409500
Short name T2386
Test name
Test status
Simulation time 18914103905 ps
CPU time 26.87 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 207800 kb
Host smart-a82f1268-f11d-48dc-a053-d020e4f55902
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936409500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2936409500
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1659435253
Short name T1895
Test name
Test status
Simulation time 30441481604 ps
CPU time 36.11 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207860 kb
Host smart-da1fce8a-763d-45f4-8bf2-521535fb3f85
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659435253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.1659435253
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1924596745
Short name T3542
Test name
Test status
Simulation time 207694196 ps
CPU time 0.93 seconds
Started Aug 09 05:28:42 PM PDT 24
Finished Aug 09 05:28:43 PM PDT 24
Peak memory 207472 kb
Host smart-c8dad6ca-ffde-48c1-82c9-9f2e4e2a146f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
96745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1924596745
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3245817443
Short name T3177
Test name
Test status
Simulation time 153077498 ps
CPU time 0.86 seconds
Started Aug 09 05:28:37 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 207480 kb
Host smart-737aadc3-15a2-44d5-b4e3-7f4d06cce81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32458
17443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3245817443
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2128863929
Short name T612
Test name
Test status
Simulation time 201689472 ps
CPU time 1.04 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207480 kb
Host smart-205f2049-100a-47c7-849f-3dbe5218dda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
63929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2128863929
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1970352944
Short name T902
Test name
Test status
Simulation time 354620614 ps
CPU time 1.37 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207492 kb
Host smart-849a48db-a200-4700-8294-221d36a8d08c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1970352944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1970352944
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.631558403
Short name T2714
Test name
Test status
Simulation time 49337599473 ps
CPU time 75.36 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207728 kb
Host smart-5209d49a-1fe3-43a5-9451-51d7bfb95d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63155
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.631558403
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.857642723
Short name T2788
Test name
Test status
Simulation time 1659516222 ps
CPU time 37.83 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207612 kb
Host smart-caf9041f-1e30-4b58-b945-8f3122101bfa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857642723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.857642723
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3691576696
Short name T2303
Test name
Test status
Simulation time 721003893 ps
CPU time 1.7 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207356 kb
Host smart-8682d2ea-6ca6-464c-8442-7cec6f9e835b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36915
76696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3691576696
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.348564373
Short name T3569
Test name
Test status
Simulation time 167238920 ps
CPU time 0.85 seconds
Started Aug 09 05:28:28 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 207476 kb
Host smart-e3650850-3a90-44e2-8cbe-4f06ab635c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
4373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.348564373
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.981595514
Short name T2037
Test name
Test status
Simulation time 99412140 ps
CPU time 0.79 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207444 kb
Host smart-d0a14e3b-3bb4-45c5-960f-73a2b688a695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98159
5514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.981595514
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1647891750
Short name T1027
Test name
Test status
Simulation time 968371766 ps
CPU time 2.45 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207552 kb
Host smart-3dfff212-3024-4e85-a376-26f4744d9fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16478
91750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1647891750
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.136990457
Short name T472
Test name
Test status
Simulation time 276307892 ps
CPU time 1.17 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 207356 kb
Host smart-d133eb5a-8111-4af3-97ca-7cec6870f752
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=136990457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.136990457
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2286966001
Short name T3336
Test name
Test status
Simulation time 193957540 ps
CPU time 1.88 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207680 kb
Host smart-88636a06-5981-4b5c-a869-1ce68471dd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
66001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2286966001
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3429558913
Short name T590
Test name
Test status
Simulation time 242748616 ps
CPU time 1.11 seconds
Started Aug 09 05:28:33 PM PDT 24
Finished Aug 09 05:28:35 PM PDT 24
Peak memory 215924 kb
Host smart-0fd6f5c5-278d-46a4-9c62-9703cae06f5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3429558913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3429558913
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3005137973
Short name T1214
Test name
Test status
Simulation time 156256386 ps
CPU time 0.87 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207348 kb
Host smart-9d23da57-39e4-4f28-838f-663110b5b511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
37973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3005137973
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3322930387
Short name T2414
Test name
Test status
Simulation time 265299140 ps
CPU time 1.04 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:32 PM PDT 24
Peak memory 207552 kb
Host smart-7209a2eb-c730-46b5-ac7d-b1b60241bfc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33229
30387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3322930387
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2810425050
Short name T3110
Test name
Test status
Simulation time 4894699413 ps
CPU time 136.17 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 224156 kb
Host smart-7dad2b5a-d352-422d-b7ae-ce230283f489
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2810425050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2810425050
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.4175326145
Short name T2929
Test name
Test status
Simulation time 13246844411 ps
CPU time 96.28 seconds
Started Aug 09 05:28:35 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207796 kb
Host smart-f5c7587a-8ef3-4a92-b7c6-69a354838985
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4175326145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4175326145
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2673030440
Short name T2872
Test name
Test status
Simulation time 198578775 ps
CPU time 0.96 seconds
Started Aug 09 05:28:28 PM PDT 24
Finished Aug 09 05:28:29 PM PDT 24
Peak memory 207552 kb
Host smart-c2119e75-66e8-4239-a344-7a34f253fd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
30440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2673030440
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.4242066541
Short name T1944
Test name
Test status
Simulation time 11180407456 ps
CPU time 14.95 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207720 kb
Host smart-e40e86f8-8a05-4b05-ae43-7e4a92033a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42420
66541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.4242066541
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1951303371
Short name T3427
Test name
Test status
Simulation time 10851615238 ps
CPU time 13.67 seconds
Started Aug 09 05:28:30 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207792 kb
Host smart-42e8db46-8b1d-44d1-b422-de762c4fc108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
03371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1951303371
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3904692290
Short name T3630
Test name
Test status
Simulation time 2886128781 ps
CPU time 79.17 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 216024 kb
Host smart-07270e27-cb03-41dd-9b83-37bc737b389d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3904692290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3904692290
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2006032061
Short name T2957
Test name
Test status
Simulation time 2468661058 ps
CPU time 69.19 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 217328 kb
Host smart-40dac28f-ef08-43bb-8e9f-1f464ad0248a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2006032061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2006032061
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3139582453
Short name T1381
Test name
Test status
Simulation time 257674323 ps
CPU time 1.09 seconds
Started Aug 09 05:28:33 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 207544 kb
Host smart-50c5b178-5662-429f-80d5-cf171b55f984
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3139582453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3139582453
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3033323797
Short name T1731
Test name
Test status
Simulation time 187363379 ps
CPU time 0.94 seconds
Started Aug 09 05:28:29 PM PDT 24
Finished Aug 09 05:28:30 PM PDT 24
Peak memory 207452 kb
Host smart-40f70552-4c2a-45b5-8afd-98328aeecb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30333
23797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3033323797
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.1892831700
Short name T3358
Test name
Test status
Simulation time 2375526345 ps
CPU time 65.89 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:29:53 PM PDT 24
Peak memory 217952 kb
Host smart-eeac1abc-defa-4b4f-9ee7-5816d71f1d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
31700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.1892831700
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1328513171
Short name T3244
Test name
Test status
Simulation time 2843033761 ps
CPU time 81.99 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 216028 kb
Host smart-c0501dc0-4f97-4a89-ad89-bb738fc2fc50
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1328513171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1328513171
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3424865745
Short name T2562
Test name
Test status
Simulation time 157399573 ps
CPU time 0.84 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:46 PM PDT 24
Peak memory 207424 kb
Host smart-50b31451-6ed0-4977-9f9a-94fbd5db8b6c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3424865745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3424865745
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3887981981
Short name T549
Test name
Test status
Simulation time 140455540 ps
CPU time 0.89 seconds
Started Aug 09 05:28:32 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207392 kb
Host smart-55518973-d233-4c50-897d-b8ca43a79f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879
81981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3887981981
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2547810347
Short name T1773
Test name
Test status
Simulation time 168880578 ps
CPU time 0.87 seconds
Started Aug 09 05:28:33 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 207432 kb
Host smart-c701ca3b-bbaa-4c79-b45f-256706e16b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25478
10347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2547810347
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.536909612
Short name T532
Test name
Test status
Simulation time 155989873 ps
CPU time 0.84 seconds
Started Aug 09 05:28:31 PM PDT 24
Finished Aug 09 05:28:32 PM PDT 24
Peak memory 207432 kb
Host smart-76b1d792-9b4c-4ed0-8a7c-1bd1f17426b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53690
9612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.536909612
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3813899517
Short name T1682
Test name
Test status
Simulation time 167288799 ps
CPU time 0.86 seconds
Started Aug 09 05:28:34 PM PDT 24
Finished Aug 09 05:28:35 PM PDT 24
Peak memory 207428 kb
Host smart-3bc28b56-d0f3-4fb2-adc3-cbd4e7d640f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
99517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3813899517
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.227948367
Short name T1361
Test name
Test status
Simulation time 160895653 ps
CPU time 0.88 seconds
Started Aug 09 05:28:33 PM PDT 24
Finished Aug 09 05:28:34 PM PDT 24
Peak memory 207428 kb
Host smart-318ee994-286c-4944-9d8d-59b710d42c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794
8367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.227948367
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1396011346
Short name T2277
Test name
Test status
Simulation time 255978330 ps
CPU time 1.09 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207504 kb
Host smart-0ef40a67-5254-4e3a-a3d2-3a4f02d1a414
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1396011346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1396011346
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2961755248
Short name T289
Test name
Test status
Simulation time 16934227655 ps
CPU time 43.93 seconds
Started Aug 09 05:28:37 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 220856 kb
Host smart-78c7ca4c-60db-42ae-a65a-5ca5e881d775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29617
55248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2961755248
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.34069826
Short name T947
Test name
Test status
Simulation time 162866332 ps
CPU time 0.93 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207548 kb
Host smart-5a2f5cfe-ebe8-4b4c-8aaf-536498a6028c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.34069826
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1546535257
Short name T1539
Test name
Test status
Simulation time 209124337 ps
CPU time 0.99 seconds
Started Aug 09 05:28:54 PM PDT 24
Finished Aug 09 05:28:55 PM PDT 24
Peak memory 207404 kb
Host smart-4f72cce6-fbb9-4f2f-a841-4b052beda6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
35257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1546535257
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3945671144
Short name T3439
Test name
Test status
Simulation time 199526083 ps
CPU time 0.9 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207476 kb
Host smart-7010d4f6-e655-46ff-afbd-8528202d9d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456
71144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3945671144
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1145464531
Short name T652
Test name
Test status
Simulation time 187673632 ps
CPU time 0.85 seconds
Started Aug 09 05:28:35 PM PDT 24
Finished Aug 09 05:28:36 PM PDT 24
Peak memory 207504 kb
Host smart-2e170469-5882-4c0c-abbe-7814ce5ec5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11454
64531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1145464531
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.1568806953
Short name T1690
Test name
Test status
Simulation time 20182051810 ps
CPU time 25.94 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207584 kb
Host smart-9cd8f75e-03f6-494d-86fb-a15da6410ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
06953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.1568806953
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.961485003
Short name T860
Test name
Test status
Simulation time 205787660 ps
CPU time 0.96 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207528 kb
Host smart-bff6b67b-c96c-466b-b003-6c5941b6303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96148
5003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.961485003
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.3575945764
Short name T718
Test name
Test status
Simulation time 309225333 ps
CPU time 1.11 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207496 kb
Host smart-63e65d86-f81b-46ac-913b-7960ff3010a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
45764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3575945764
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3796080099
Short name T678
Test name
Test status
Simulation time 187583411 ps
CPU time 0.88 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207480 kb
Host smart-aeea7c25-28ac-4c60-939f-2cf2fab10439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37960
80099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3796080099
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3962465178
Short name T2193
Test name
Test status
Simulation time 149758223 ps
CPU time 0.87 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207508 kb
Host smart-5af76f58-0ee8-4c1c-a198-a567067c2801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39624
65178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3962465178
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.502214017
Short name T1814
Test name
Test status
Simulation time 232838633 ps
CPU time 1 seconds
Started Aug 09 05:28:44 PM PDT 24
Finished Aug 09 05:28:45 PM PDT 24
Peak memory 207508 kb
Host smart-9a5d7a98-4718-4368-9519-9fc4fafe8b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50221
4017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.502214017
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.232240675
Short name T998
Test name
Test status
Simulation time 2833739916 ps
CPU time 75.38 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 217980 kb
Host smart-e5580e16-345b-4206-a59a-48b651b219d2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=232240675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.232240675
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.4019503652
Short name T1255
Test name
Test status
Simulation time 194611098 ps
CPU time 0.9 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:46 PM PDT 24
Peak memory 207548 kb
Host smart-4bbe2118-d284-4445-81fd-3bbb33ec20e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
03652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.4019503652
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.565246980
Short name T644
Test name
Test status
Simulation time 181416595 ps
CPU time 0.87 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207396 kb
Host smart-a04b3041-dd49-4c3e-bfee-8dcb29b9d7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56524
6980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.565246980
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.918963062
Short name T2729
Test name
Test status
Simulation time 962921022 ps
CPU time 2.47 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207652 kb
Host smart-fd30f68c-315d-4f8a-904f-2db555ed2eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91896
3062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.918963062
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3417344308
Short name T2388
Test name
Test status
Simulation time 1604821219 ps
CPU time 12.16 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 217536 kb
Host smart-d05488fc-9d9d-457d-b4f8-b826ed35f86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
44308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3417344308
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2104610688
Short name T3447
Test name
Test status
Simulation time 5665221322 ps
CPU time 37.91 seconds
Started Aug 09 05:28:30 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207820 kb
Host smart-a3cf31eb-2b3b-412a-88d9-46aebc6c7cf3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104610688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.2104610688
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.2541904843
Short name T2595
Test name
Test status
Simulation time 660266743 ps
CPU time 1.92 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 207480 kb
Host smart-cd3ceacb-11ab-44ea-b810-1d2c22d0736a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541904843 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.2541904843
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.3870790889
Short name T1467
Test name
Test status
Simulation time 192160502 ps
CPU time 0.95 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:19 PM PDT 24
Peak memory 207472 kb
Host smart-9ef31e29-0442-4be1-aca8-a83bd1b67508
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3870790889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.3870790889
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.3450043365
Short name T3306
Test name
Test status
Simulation time 632537091 ps
CPU time 1.72 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:19 PM PDT 24
Peak memory 207500 kb
Host smart-fc5ad737-4511-42e3-967b-f4bac8164496
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450043365 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.3450043365
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.527265568
Short name T465
Test name
Test status
Simulation time 623241867 ps
CPU time 1.53 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207404 kb
Host smart-5ce8168f-5fc0-4e89-b69c-48cfa80ac738
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=527265568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.527265568
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.1290537711
Short name T1031
Test name
Test status
Simulation time 623224322 ps
CPU time 1.79 seconds
Started Aug 09 05:33:42 PM PDT 24
Finished Aug 09 05:33:44 PM PDT 24
Peak memory 207520 kb
Host smart-0f15ee98-6a72-4206-8b72-38d4edf322fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290537711 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.1290537711
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.3054465510
Short name T1700
Test name
Test status
Simulation time 159662721 ps
CPU time 0.9 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207472 kb
Host smart-40ac4f9e-5546-4da4-a602-c93e2e46c9c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3054465510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.3054465510
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.3332560928
Short name T2058
Test name
Test status
Simulation time 478526398 ps
CPU time 1.49 seconds
Started Aug 09 05:33:25 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207508 kb
Host smart-16499b9c-0eb4-4295-a1fd-0b1cb5442cc1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332560928 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.3332560928
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.2121568524
Short name T417
Test name
Test status
Simulation time 581077940 ps
CPU time 1.51 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207420 kb
Host smart-02a28357-d288-4626-b031-0053a1f1ac3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2121568524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.2121568524
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.1274480138
Short name T243
Test name
Test status
Simulation time 570016193 ps
CPU time 1.69 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 207560 kb
Host smart-6466f56d-55b3-419d-aa4a-385a47acb449
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274480138 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.1274480138
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.2641182950
Short name T433
Test name
Test status
Simulation time 683376321 ps
CPU time 1.78 seconds
Started Aug 09 05:33:25 PM PDT 24
Finished Aug 09 05:33:27 PM PDT 24
Peak memory 207760 kb
Host smart-2050ffa7-837e-4cdf-bacb-67fd5d466302
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2641182950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.2641182950
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.972843417
Short name T167
Test name
Test status
Simulation time 520248243 ps
CPU time 1.67 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:44 PM PDT 24
Peak memory 207392 kb
Host smart-9c1e0382-d444-41e8-9200-6c9319971d5e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972843417 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.972843417
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.3068008088
Short name T463
Test name
Test status
Simulation time 280289496 ps
CPU time 1.23 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207520 kb
Host smart-918606a4-9814-4c62-bd56-fa88b959bbfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3068008088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.3068008088
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.1467067070
Short name T2945
Test name
Test status
Simulation time 448669246 ps
CPU time 1.47 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207416 kb
Host smart-07501133-df8f-4abc-984d-475e616dc109
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467067070 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.1467067070
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.3416024241
Short name T2675
Test name
Test status
Simulation time 563949555 ps
CPU time 1.52 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:12 PM PDT 24
Peak memory 207480 kb
Host smart-4cc6f064-c643-4850-b1eb-1b744433f8af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416024241 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.3416024241
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.2650329307
Short name T1887
Test name
Test status
Simulation time 530085260 ps
CPU time 1.6 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 207404 kb
Host smart-95cd6005-17fa-4653-8d5a-80f53d64346a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2650329307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2650329307
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.2077814952
Short name T2529
Test name
Test status
Simulation time 652219975 ps
CPU time 1.66 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207508 kb
Host smart-19ca26c4-a1a2-4e8a-82b0-e8d9716dfe22
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077814952 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.2077814952
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.1065853946
Short name T477
Test name
Test status
Simulation time 299118046 ps
CPU time 1.08 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207516 kb
Host smart-044b990f-f7d2-404e-819e-a0539e3437a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1065853946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.1065853946
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.6660694
Short name T3106
Test name
Test status
Simulation time 488603728 ps
CPU time 1.47 seconds
Started Aug 09 05:33:26 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207484 kb
Host smart-e951a233-7d60-423f-aaf9-3cfbb19d167b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6660694 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.6660694
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3635478337
Short name T1784
Test name
Test status
Simulation time 381272781 ps
CPU time 1.26 seconds
Started Aug 09 05:33:12 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207520 kb
Host smart-e63c0f49-eba8-4186-81af-cd96f0972e80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3635478337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3635478337
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.514282943
Short name T2973
Test name
Test status
Simulation time 477332854 ps
CPU time 1.53 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207516 kb
Host smart-e98f8ab2-acf9-47dd-885b-92320bd972a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514282943 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.514282943
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1218570948
Short name T2656
Test name
Test status
Simulation time 6216883551 ps
CPU time 7.94 seconds
Started Aug 09 05:28:40 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 215876 kb
Host smart-ca1f98b6-9a9f-4518-b7fe-28898879725b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218570948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.1218570948
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3208268371
Short name T2739
Test name
Test status
Simulation time 18819080740 ps
CPU time 21.23 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207812 kb
Host smart-268f1d71-1978-4079-abf6-8882cf706574
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208268371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3208268371
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.525117683
Short name T2510
Test name
Test status
Simulation time 24721835737 ps
CPU time 31.08 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:29:19 PM PDT 24
Peak memory 215904 kb
Host smart-8952c285-c8dc-4068-a9a7-c6dbe8d43943
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525117683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.525117683
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.689836378
Short name T2272
Test name
Test status
Simulation time 174092386 ps
CPU time 0.89 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207408 kb
Host smart-6061cdbf-ead7-48c9-bc93-8790ed567b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68983
6378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.689836378
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1491221465
Short name T1025
Test name
Test status
Simulation time 142325809 ps
CPU time 0.86 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207412 kb
Host smart-3036b1e4-eed1-4802-af00-4a39e1f95965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14912
21465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1491221465
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3254579647
Short name T2592
Test name
Test status
Simulation time 271406104 ps
CPU time 1.15 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207504 kb
Host smart-6e00ce0d-748d-450b-a746-3984cdfecd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32545
79647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3254579647
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.588073358
Short name T1577
Test name
Test status
Simulation time 1209589954 ps
CPU time 3.34 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 207760 kb
Host smart-99e0d880-128e-44c9-9dd1-684a280775d9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=588073358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.588073358
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2208371786
Short name T2978
Test name
Test status
Simulation time 20078368690 ps
CPU time 34.69 seconds
Started Aug 09 05:28:42 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207796 kb
Host smart-6c163b79-a7fb-4c30-8265-2ee02844c404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22083
71786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2208371786
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1862749154
Short name T2569
Test name
Test status
Simulation time 593110163 ps
CPU time 4.83 seconds
Started Aug 09 05:28:37 PM PDT 24
Finished Aug 09 05:28:42 PM PDT 24
Peak memory 207604 kb
Host smart-d03a475d-70ec-4c12-bd98-9082c11f40c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862749154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1862749154
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.830573846
Short name T1562
Test name
Test status
Simulation time 602193572 ps
CPU time 1.64 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:40 PM PDT 24
Peak memory 207444 kb
Host smart-a029a6c2-e45b-474a-8b19-28a2f2fbec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83057
3846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.830573846
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.4151764821
Short name T691
Test name
Test status
Simulation time 171592777 ps
CPU time 0.86 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207524 kb
Host smart-b1ae1fcb-165b-4463-afe6-05315f11ba29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
64821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.4151764821
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.973970525
Short name T3234
Test name
Test status
Simulation time 35385064 ps
CPU time 0.76 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:45 PM PDT 24
Peak memory 207464 kb
Host smart-b84ff308-3772-4ed4-a3a5-df0026fe7d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97397
0525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.973970525
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1669174026
Short name T3469
Test name
Test status
Simulation time 947132007 ps
CPU time 2.37 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207536 kb
Host smart-31f4c853-b0f1-4689-83bb-2e6f4965e3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691
74026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1669174026
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.884605709
Short name T453
Test name
Test status
Simulation time 699504879 ps
CPU time 1.76 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 207472 kb
Host smart-5f4a8345-0cd1-43cd-b258-76491e9431a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=884605709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.884605709
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2707582513
Short name T2031
Test name
Test status
Simulation time 385479903 ps
CPU time 2.54 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207692 kb
Host smart-973958ff-1bd6-4d37-98a5-7404aaa74db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27075
82513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2707582513
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3527562692
Short name T2333
Test name
Test status
Simulation time 213707726 ps
CPU time 1.18 seconds
Started Aug 09 05:28:40 PM PDT 24
Finished Aug 09 05:28:41 PM PDT 24
Peak memory 215808 kb
Host smart-7a257cbc-1405-4423-843d-e7521febc10e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3527562692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3527562692
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2120344294
Short name T752
Test name
Test status
Simulation time 161111744 ps
CPU time 0.83 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207400 kb
Host smart-6ebff511-57d9-4362-a19b-b8c1ca123415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21203
44294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2120344294
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3258998215
Short name T910
Test name
Test status
Simulation time 224935963 ps
CPU time 0.98 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 207396 kb
Host smart-92fd0c3a-0ed4-4613-8a6a-ddfc26836b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
98215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3258998215
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1359248207
Short name T227
Test name
Test status
Simulation time 3774060600 ps
CPU time 105.16 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:30:32 PM PDT 24
Peak memory 216036 kb
Host smart-58e0ff54-5703-43e4-8d32-731d70a5b2d2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1359248207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1359248207
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.4108260501
Short name T2818
Test name
Test status
Simulation time 5780203877 ps
CPU time 37.19 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207668 kb
Host smart-a30b8e43-f6dc-4138-80ee-eba5d5ce7465
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4108260501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.4108260501
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3850842091
Short name T1848
Test name
Test status
Simulation time 209077009 ps
CPU time 0.95 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207428 kb
Host smart-fbf89d32-4683-44d8-9e44-a6724e9a4147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
42091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3850842091
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3396259276
Short name T1174
Test name
Test status
Simulation time 31692054644 ps
CPU time 49.05 seconds
Started Aug 09 05:28:35 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207736 kb
Host smart-91f848ba-18d2-4ca2-9ccf-8b1a47620431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33962
59276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3396259276
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.634442381
Short name T734
Test name
Test status
Simulation time 3768625830 ps
CPU time 5.58 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 216700 kb
Host smart-d320b1df-6be5-49cf-b171-ae93123d177d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63444
2381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.634442381
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1209159165
Short name T1320
Test name
Test status
Simulation time 4167952246 ps
CPU time 124.6 seconds
Started Aug 09 05:28:37 PM PDT 24
Finished Aug 09 05:30:42 PM PDT 24
Peak memory 218484 kb
Host smart-5e192449-4990-46ff-afb8-290bf638430a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1209159165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1209159165
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.986500730
Short name T1879
Test name
Test status
Simulation time 2565608015 ps
CPU time 25.61 seconds
Started Aug 09 05:28:42 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 217792 kb
Host smart-fbf31d40-2413-4824-9a6c-31c718a9bd9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=986500730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.986500730
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3580047448
Short name T1777
Test name
Test status
Simulation time 274284252 ps
CPU time 1.08 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 207796 kb
Host smart-4bac3e96-12e8-4695-9df9-83b6b87c4214
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3580047448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3580047448
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1149144745
Short name T3360
Test name
Test status
Simulation time 197800759 ps
CPU time 1.02 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207532 kb
Host smart-5a10fd24-6a50-477f-af27-d5355aa1c1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
44745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1149144745
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.2126005142
Short name T2055
Test name
Test status
Simulation time 2844473056 ps
CPU time 83.2 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 217716 kb
Host smart-ec583d24-306b-42f2-a64a-53ed3f2be0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21260
05142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.2126005142
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1815848905
Short name T2199
Test name
Test status
Simulation time 2404100508 ps
CPU time 63.01 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 217496 kb
Host smart-e28880c5-ece3-4367-927c-8ed73a569ad6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1815848905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1815848905
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2382268707
Short name T2234
Test name
Test status
Simulation time 159492946 ps
CPU time 0.86 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:48 PM PDT 24
Peak memory 207524 kb
Host smart-5826ed6a-24a5-49f4-9954-1764cc6dbe69
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2382268707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2382268707
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3723384176
Short name T1837
Test name
Test status
Simulation time 153923297 ps
CPU time 0.88 seconds
Started Aug 09 05:28:41 PM PDT 24
Finished Aug 09 05:28:42 PM PDT 24
Peak memory 207436 kb
Host smart-30075e92-d23f-46e0-ac06-c66884d11e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
84176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3723384176
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2835141869
Short name T539
Test name
Test status
Simulation time 185930703 ps
CPU time 0.92 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207472 kb
Host smart-bd43d1c1-60eb-42f6-9bf8-ffb2820aede9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
41869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2835141869
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3797897484
Short name T1639
Test name
Test status
Simulation time 147533026 ps
CPU time 0.84 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:38 PM PDT 24
Peak memory 207556 kb
Host smart-5516f126-44ec-4bc7-8295-bdacf446a316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
97484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3797897484
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.864020268
Short name T1835
Test name
Test status
Simulation time 188064509 ps
CPU time 1.04 seconds
Started Aug 09 05:28:38 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 207476 kb
Host smart-4a5a1388-700d-4c60-a92f-f16b312fccd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86402
0268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.864020268
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2355020552
Short name T1885
Test name
Test status
Simulation time 164176275 ps
CPU time 0.86 seconds
Started Aug 09 05:28:36 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207596 kb
Host smart-7e5a3139-5421-473e-829d-14bc796f7ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
20552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2355020552
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.893144445
Short name T1423
Test name
Test status
Simulation time 227420682 ps
CPU time 0.98 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207504 kb
Host smart-83c011d8-c355-4aad-957d-b5df724881d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=893144445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.893144445
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.185918820
Short name T1347
Test name
Test status
Simulation time 155123095 ps
CPU time 0.86 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207468 kb
Host smart-37838eea-64d3-45d8-b5ca-b12ee943d5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
8820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.185918820
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1272472879
Short name T1670
Test name
Test status
Simulation time 39158784 ps
CPU time 0.67 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207492 kb
Host smart-32ab48d9-d2ef-40df-aa14-5b7f1ec310f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
72879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1272472879
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2148989713
Short name T263
Test name
Test status
Simulation time 15009000306 ps
CPU time 39.19 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 215920 kb
Host smart-265b1b3c-cf07-479c-8b8f-b6f34b2181a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21489
89713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2148989713
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1914874292
Short name T587
Test name
Test status
Simulation time 172545856 ps
CPU time 0.88 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207524 kb
Host smart-7d299852-4913-4f9e-95cd-46ea8a9afa08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
74292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1914874292
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.899907550
Short name T816
Test name
Test status
Simulation time 243413328 ps
CPU time 0.99 seconds
Started Aug 09 05:28:45 PM PDT 24
Finished Aug 09 05:28:46 PM PDT 24
Peak memory 207532 kb
Host smart-f5c95521-b964-4d5f-834b-78003ec6c222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89990
7550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.899907550
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.868518653
Short name T3585
Test name
Test status
Simulation time 184596639 ps
CPU time 0.87 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207504 kb
Host smart-3a44fe02-6de6-4523-9f6d-798745036cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86851
8653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.868518653
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2179061014
Short name T1014
Test name
Test status
Simulation time 173582989 ps
CPU time 0.9 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207360 kb
Host smart-250de57b-9470-4206-af38-7b180054f60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
61014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2179061014
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.2384893816
Short name T1335
Test name
Test status
Simulation time 20168541353 ps
CPU time 30.08 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207544 kb
Host smart-679e31a9-9e9c-4517-8800-010ccddb27d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
93816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.2384893816
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3804501614
Short name T3198
Test name
Test status
Simulation time 191910398 ps
CPU time 0.9 seconds
Started Aug 09 05:28:41 PM PDT 24
Finished Aug 09 05:28:42 PM PDT 24
Peak memory 207548 kb
Host smart-afc19665-9c16-4107-8aa9-b658bca33380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38045
01614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3804501614
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.299887246
Short name T47
Test name
Test status
Simulation time 306616265 ps
CPU time 1.23 seconds
Started Aug 09 05:28:44 PM PDT 24
Finished Aug 09 05:28:45 PM PDT 24
Peak memory 207584 kb
Host smart-25b56b79-997b-4426-8fb6-e0804fef16bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
7246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.299887246
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.4202150509
Short name T2661
Test name
Test status
Simulation time 220687007 ps
CPU time 0.95 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207484 kb
Host smart-876ef8f5-af71-45ae-ac82-e9330d9e51fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42021
50509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.4202150509
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3125210421
Short name T228
Test name
Test status
Simulation time 170449769 ps
CPU time 0.86 seconds
Started Aug 09 05:28:41 PM PDT 24
Finished Aug 09 05:28:42 PM PDT 24
Peak memory 207456 kb
Host smart-c1ac3a3b-4563-4f2e-8770-060e7fb07e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31252
10421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3125210421
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2901659618
Short name T2035
Test name
Test status
Simulation time 201508636 ps
CPU time 0.97 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:28:51 PM PDT 24
Peak memory 207444 kb
Host smart-a93e3f46-c8c9-4bdd-8d62-e7c2e6fa8716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29016
59618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2901659618
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2474293904
Short name T166
Test name
Test status
Simulation time 1455813256 ps
CPU time 11.28 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 224000 kb
Host smart-aa9cb0f8-75c1-4f11-abac-e168f58f7bd6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2474293904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2474293904
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3245106521
Short name T1589
Test name
Test status
Simulation time 200019523 ps
CPU time 0.97 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207408 kb
Host smart-ef095986-a919-4fc7-ab2e-d0e4aee93f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32451
06521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3245106521
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3654728468
Short name T1475
Test name
Test status
Simulation time 188784648 ps
CPU time 0.91 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207528 kb
Host smart-cca0d442-a631-4652-8b2f-041f5adb7025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36547
28468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3654728468
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.212479793
Short name T1422
Test name
Test status
Simulation time 1241733110 ps
CPU time 3.17 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 207600 kb
Host smart-b5a5ebd1-2dae-4985-b3f7-03146f2ca06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
9793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.212479793
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.4152421722
Short name T2723
Test name
Test status
Simulation time 2448252408 ps
CPU time 68.38 seconds
Started Aug 09 05:28:46 PM PDT 24
Finished Aug 09 05:29:54 PM PDT 24
Peak memory 217300 kb
Host smart-d093c6ec-a6c4-46c4-aba1-027e5ae51a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41524
21722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.4152421722
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.2910945233
Short name T1097
Test name
Test status
Simulation time 5572020688 ps
CPU time 38.22 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207732 kb
Host smart-371f4036-a9ff-4446-b64e-a292f7b6e9d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910945233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.2910945233
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.2265193292
Short name T1928
Test name
Test status
Simulation time 585894477 ps
CPU time 1.63 seconds
Started Aug 09 05:28:41 PM PDT 24
Finished Aug 09 05:28:43 PM PDT 24
Peak memory 207560 kb
Host smart-a1ddccbe-a9bd-41df-804b-26e64a825b87
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265193292 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.2265193292
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.2606091738
Short name T470
Test name
Test status
Simulation time 245305145 ps
CPU time 1.08 seconds
Started Aug 09 05:33:12 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207520 kb
Host smart-e26d36ee-8d6b-472d-bfd7-4f6e67b7e71e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2606091738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.2606091738
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.2602494020
Short name T1817
Test name
Test status
Simulation time 601412785 ps
CPU time 1.56 seconds
Started Aug 09 05:33:20 PM PDT 24
Finished Aug 09 05:33:22 PM PDT 24
Peak memory 207568 kb
Host smart-b88e5c09-fadc-482c-845e-dec819848f74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602494020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.2602494020
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.3956349385
Short name T398
Test name
Test status
Simulation time 289423107 ps
CPU time 1.05 seconds
Started Aug 09 05:33:22 PM PDT 24
Finished Aug 09 05:33:23 PM PDT 24
Peak memory 207412 kb
Host smart-371276d3-526f-4636-a413-f3e463c5cfe2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3956349385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3956349385
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.3861309206
Short name T2223
Test name
Test status
Simulation time 458813648 ps
CPU time 1.59 seconds
Started Aug 09 05:33:36 PM PDT 24
Finished Aug 09 05:33:37 PM PDT 24
Peak memory 207564 kb
Host smart-48b733e3-d5de-4a0b-8e5f-83fe436110be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861309206 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.3861309206
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.3490464770
Short name T390
Test name
Test status
Simulation time 302033274 ps
CPU time 1.06 seconds
Started Aug 09 05:33:14 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 207520 kb
Host smart-a629488d-3da0-4ddd-b567-759ed046f0c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3490464770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.3490464770
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.3175067039
Short name T3609
Test name
Test status
Simulation time 522482065 ps
CPU time 1.51 seconds
Started Aug 09 05:33:39 PM PDT 24
Finished Aug 09 05:33:41 PM PDT 24
Peak memory 207516 kb
Host smart-2477d2db-84d9-4809-90fb-4471bc99c005
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175067039 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.3175067039
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.1596684300
Short name T1256
Test name
Test status
Simulation time 599799700 ps
CPU time 1.52 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207516 kb
Host smart-3e956fad-ecad-4f72-a98c-26da04491210
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596684300 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.1596684300
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.502242691
Short name T3027
Test name
Test status
Simulation time 539011767 ps
CPU time 1.51 seconds
Started Aug 09 05:33:16 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207492 kb
Host smart-649a89f6-5f3b-451a-8077-8af8c549eef1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=502242691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.502242691
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.4047002925
Short name T1473
Test name
Test status
Simulation time 710721938 ps
CPU time 1.95 seconds
Started Aug 09 05:33:31 PM PDT 24
Finished Aug 09 05:33:33 PM PDT 24
Peak memory 207560 kb
Host smart-84242016-e334-446a-b58b-f710f7234801
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047002925 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.4047002925
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.2733538479
Short name T2605
Test name
Test status
Simulation time 560187596 ps
CPU time 1.56 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207488 kb
Host smart-cc403165-e59c-4e2c-81eb-35ec401ecb54
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733538479 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.2733538479
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.4129577295
Short name T363
Test name
Test status
Simulation time 453554394 ps
CPU time 1.45 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207420 kb
Host smart-fdc1f1b8-75f2-4bda-8268-f7386ac70052
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4129577295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.4129577295
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.1346445922
Short name T1460
Test name
Test status
Simulation time 455992796 ps
CPU time 1.43 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207532 kb
Host smart-2fee9b17-c4af-4790-8811-2b18b2667a56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346445922 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.1346445922
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.1990072167
Short name T459
Test name
Test status
Simulation time 521151053 ps
CPU time 1.35 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207516 kb
Host smart-62eb3021-30cd-4a7e-b804-942019586b9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1990072167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.1990072167
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.277596361
Short name T3619
Test name
Test status
Simulation time 510650592 ps
CPU time 1.6 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207440 kb
Host smart-70070607-d4c4-4b4b-8580-b6edb9554327
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277596361 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.277596361
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.2852795012
Short name T368
Test name
Test status
Simulation time 597835919 ps
CPU time 1.59 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207476 kb
Host smart-2d050f23-f75f-4f1d-a437-dc66bbe6c5b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2852795012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.2852795012
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.3678103376
Short name T2779
Test name
Test status
Simulation time 625523000 ps
CPU time 1.74 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 207440 kb
Host smart-37d5e39c-1c23-4031-aa5c-10f22ef9d869
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678103376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.3678103376
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.2832878192
Short name T424
Test name
Test status
Simulation time 527719749 ps
CPU time 1.49 seconds
Started Aug 09 05:33:31 PM PDT 24
Finished Aug 09 05:33:33 PM PDT 24
Peak memory 207384 kb
Host smart-4b158bba-f9fa-4c50-b64e-259f8212d9af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2832878192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.2832878192
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.2344409211
Short name T3410
Test name
Test status
Simulation time 476009250 ps
CPU time 1.43 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:38 PM PDT 24
Peak memory 207484 kb
Host smart-6baf9d56-c418-4cbe-8d25-09d4301a9be4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344409211 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.2344409211
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3892694715
Short name T2567
Test name
Test status
Simulation time 38219423 ps
CPU time 0.72 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207532 kb
Host smart-987f1a49-6d28-4042-8bbb-a321f9dd1d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3892694715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3892694715
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.424402368
Short name T1827
Test name
Test status
Simulation time 5161034079 ps
CPU time 6.59 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 215976 kb
Host smart-39a46d0e-f21e-44ee-86e5-4a3f44deb846
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424402368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_disconnect.424402368
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.868168885
Short name T2194
Test name
Test status
Simulation time 20986195613 ps
CPU time 27.32 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:26:18 PM PDT 24
Peak memory 207844 kb
Host smart-e766270f-a415-4636-bb66-67bf12eb49e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=868168885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.868168885
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1947648133
Short name T1183
Test name
Test status
Simulation time 30284550641 ps
CPU time 34.82 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207772 kb
Host smart-a5c7da72-bbd0-4c96-a20d-5f71161509da
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947648133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1947648133
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3979364621
Short name T3620
Test name
Test status
Simulation time 160580876 ps
CPU time 0.86 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:25:54 PM PDT 24
Peak memory 207788 kb
Host smart-bb773400-0a13-41d3-9793-88d8c7e3c9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
64621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3979364621
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2305145227
Short name T43
Test name
Test status
Simulation time 221994468 ps
CPU time 0.89 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207512 kb
Host smart-b679e6d9-f8b5-4d5b-a2cd-b173da860cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051
45227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2305145227
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1052162031
Short name T55
Test name
Test status
Simulation time 136563681 ps
CPU time 0.86 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:25:55 PM PDT 24
Peak memory 207492 kb
Host smart-88a56416-d9eb-4dca-b62c-bb16fbbcab88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
62031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1052162031
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1416191880
Short name T1211
Test name
Test status
Simulation time 148176376 ps
CPU time 0.86 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 207532 kb
Host smart-8826e8ea-7a8c-4b5f-b2fd-b069a2af25e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14161
91880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1416191880
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1160039033
Short name T646
Test name
Test status
Simulation time 381518213 ps
CPU time 1.38 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:25:53 PM PDT 24
Peak memory 207556 kb
Host smart-8e851ebd-c57b-4f53-ad3c-3a8bd11615ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11600
39033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1160039033
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2732634700
Short name T316
Test name
Test status
Simulation time 1156467326 ps
CPU time 3.16 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:25:55 PM PDT 24
Peak memory 207616 kb
Host smart-5ffc8d0e-49ff-491d-bee1-300f949f2382
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2732634700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2732634700
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1091695085
Short name T3319
Test name
Test status
Simulation time 21496412017 ps
CPU time 36.61 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:26:31 PM PDT 24
Peak memory 207832 kb
Host smart-f59cf71a-7ee6-417d-955b-6eef436132c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916
95085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1091695085
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.1193151840
Short name T52
Test name
Test status
Simulation time 846797025 ps
CPU time 19.61 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207972 kb
Host smart-d718a83c-b3fa-463e-a386-32246c108ce8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193151840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.1193151840
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2399301469
Short name T3526
Test name
Test status
Simulation time 513373884 ps
CPU time 1.55 seconds
Started Aug 09 05:25:55 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 207496 kb
Host smart-d2c5797e-a974-44ec-9f38-52c8ee4f77ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23993
01469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2399301469
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2132001700
Short name T3221
Test name
Test status
Simulation time 138355356 ps
CPU time 0.79 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:25:50 PM PDT 24
Peak memory 207472 kb
Host smart-4544ac39-991c-4fd6-bea0-5a91aabe6693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21320
01700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2132001700
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2805394270
Short name T583
Test name
Test status
Simulation time 33548757 ps
CPU time 0.69 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:25:49 PM PDT 24
Peak memory 207404 kb
Host smart-1d93b568-9990-485b-8bea-beffc1ce6555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
94270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2805394270
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2579417484
Short name T2006
Test name
Test status
Simulation time 877801004 ps
CPU time 2.39 seconds
Started Aug 09 05:25:50 PM PDT 24
Finished Aug 09 05:25:52 PM PDT 24
Peak memory 207768 kb
Host smart-dee7e80a-9680-4a91-93d8-02380d69b337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25794
17484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2579417484
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3229672584
Short name T864
Test name
Test status
Simulation time 241665784 ps
CPU time 1.93 seconds
Started Aug 09 05:25:53 PM PDT 24
Finished Aug 09 05:25:55 PM PDT 24
Peak memory 207728 kb
Host smart-1ee1ae72-452c-411a-b968-8b30de8c3bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
72584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3229672584
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1865713948
Short name T2630
Test name
Test status
Simulation time 87175139001 ps
CPU time 144.89 seconds
Started Aug 09 05:25:49 PM PDT 24
Finished Aug 09 05:28:14 PM PDT 24
Peak memory 207804 kb
Host smart-d91e0a94-76ef-4ef3-b432-04a3c2f95c36
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1865713948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1865713948
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2265861169
Short name T1638
Test name
Test status
Simulation time 115389391743 ps
CPU time 176.35 seconds
Started Aug 09 05:25:54 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207768 kb
Host smart-46cd78c1-d5d4-419e-8f64-ec3cb4b0aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265861169 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2265861169
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.2687623900
Short name T2989
Test name
Test status
Simulation time 100103457072 ps
CPU time 164.3 seconds
Started Aug 09 05:25:48 PM PDT 24
Finished Aug 09 05:28:33 PM PDT 24
Peak memory 207688 kb
Host smart-f6d1306e-4a78-49d9-945f-249e36cab4cf
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2687623900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2687623900
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1903300591
Short name T1044
Test name
Test status
Simulation time 107968237241 ps
CPU time 199.11 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:29:12 PM PDT 24
Peak memory 207780 kb
Host smart-fb6fceee-4517-436e-8142-e14f8bf07fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903300591 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1903300591
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.2296594897
Short name T506
Test name
Test status
Simulation time 107132084828 ps
CPU time 155.88 seconds
Started Aug 09 05:25:51 PM PDT 24
Finished Aug 09 05:28:27 PM PDT 24
Peak memory 207808 kb
Host smart-140466c4-3dd3-4ea0-86cc-908c7693898c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
94897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2296594897
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1732296157
Short name T113
Test name
Test status
Simulation time 233896140 ps
CPU time 1.33 seconds
Started Aug 09 05:26:01 PM PDT 24
Finished Aug 09 05:26:02 PM PDT 24
Peak memory 215888 kb
Host smart-5fcad46f-7add-4558-9f39-579fe2f72761
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1732296157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1732296157
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1896384047
Short name T2499
Test name
Test status
Simulation time 158209680 ps
CPU time 0.9 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207524 kb
Host smart-5b4611f0-de9c-4f62-afe2-4861c54c5c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
84047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1896384047
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.290855125
Short name T2777
Test name
Test status
Simulation time 197573987 ps
CPU time 0.94 seconds
Started Aug 09 05:26:05 PM PDT 24
Finished Aug 09 05:26:06 PM PDT 24
Peak memory 207440 kb
Host smart-73f97fdd-6365-4f66-bef3-726da273ecdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
5125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.290855125
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.211080066
Short name T2297
Test name
Test status
Simulation time 3932284171 ps
CPU time 32.98 seconds
Started Aug 09 05:26:02 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 217236 kb
Host smart-a6d5730f-467a-41fc-8a29-a0c964184356
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=211080066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.211080066
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.2149278671
Short name T2431
Test name
Test status
Simulation time 11748358961 ps
CPU time 146.12 seconds
Started Aug 09 05:25:57 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 207720 kb
Host smart-18724630-7f2f-4086-8f3e-153527e42fc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2149278671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2149278671
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3060012275
Short name T2662
Test name
Test status
Simulation time 196805441 ps
CPU time 0.93 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207432 kb
Host smart-fe310b22-654b-4a86-8313-46d5f4cb3ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30600
12275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3060012275
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2240427535
Short name T617
Test name
Test status
Simulation time 24474767419 ps
CPU time 36.32 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207760 kb
Host smart-01bb976f-791e-48f2-9009-c37854566448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
27535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2240427535
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2688889318
Short name T3063
Test name
Test status
Simulation time 4147467460 ps
CPU time 5.9 seconds
Started Aug 09 05:25:57 PM PDT 24
Finished Aug 09 05:26:03 PM PDT 24
Peak memory 207640 kb
Host smart-a3184be1-2b87-411d-8311-b5f8b86fb0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26888
89318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2688889318
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2196787535
Short name T714
Test name
Test status
Simulation time 3908219663 ps
CPU time 29.81 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 224156 kb
Host smart-b0ee385d-8abe-48fc-afe9-0059bbb7ad5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2196787535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2196787535
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3058350332
Short name T2437
Test name
Test status
Simulation time 3762829643 ps
CPU time 37.58 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 215940 kb
Host smart-0cc5de8b-2798-4d71-8756-60129087ca7c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3058350332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3058350332
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2483784773
Short name T2923
Test name
Test status
Simulation time 246377330 ps
CPU time 1.15 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207548 kb
Host smart-8829e780-f0b1-4321-9409-02e16818b953
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2483784773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2483784773
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3374350450
Short name T1763
Test name
Test status
Simulation time 210614664 ps
CPU time 1.01 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207388 kb
Host smart-daa92265-4692-4ab1-a4f1-b22c6776ad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33743
50450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3374350450
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.33649158
Short name T1633
Test name
Test status
Simulation time 2812355865 ps
CPU time 28.5 seconds
Started Aug 09 05:25:55 PM PDT 24
Finished Aug 09 05:26:24 PM PDT 24
Peak memory 224268 kb
Host smart-f9696878-cf49-4f08-a90a-d6a87d3fee0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.33649158
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1425664300
Short name T988
Test name
Test status
Simulation time 2679211802 ps
CPU time 79.86 seconds
Started Aug 09 05:25:59 PM PDT 24
Finished Aug 09 05:27:19 PM PDT 24
Peak memory 218260 kb
Host smart-32ca452b-fd58-4d41-96b3-40d6916382c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1425664300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1425664300
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.4125070877
Short name T2920
Test name
Test status
Simulation time 2377994273 ps
CPU time 65.56 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 216068 kb
Host smart-f0bf7ca9-8705-4716-b42b-637c19bbe220
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4125070877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.4125070877
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1722733797
Short name T3001
Test name
Test status
Simulation time 156469162 ps
CPU time 0.89 seconds
Started Aug 09 05:25:56 PM PDT 24
Finished Aug 09 05:25:57 PM PDT 24
Peak memory 207592 kb
Host smart-7263a2bf-ff69-48ae-8c9a-1e0615c54979
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1722733797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1722733797
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.582587243
Short name T1212
Test name
Test status
Simulation time 150003447 ps
CPU time 0.86 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207440 kb
Host smart-b3172d3a-0c15-4572-ac74-b8b45391e0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58258
7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.582587243
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.605851840
Short name T136
Test name
Test status
Simulation time 189324139 ps
CPU time 0.89 seconds
Started Aug 09 05:25:55 PM PDT 24
Finished Aug 09 05:25:56 PM PDT 24
Peak memory 207504 kb
Host smart-2b3c3f77-9805-4646-9abc-d61975dee89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60585
1840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.605851840
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.806066627
Short name T2980
Test name
Test status
Simulation time 177676652 ps
CPU time 0.88 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207512 kb
Host smart-9e401443-415f-452c-8f2c-15cf9c0851a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80606
6627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.806066627
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3929710552
Short name T623
Test name
Test status
Simulation time 198153619 ps
CPU time 1 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207556 kb
Host smart-233cc6d1-2570-478a-a22e-2809693a7f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39297
10552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3929710552
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1344072915
Short name T805
Test name
Test status
Simulation time 202858209 ps
CPU time 0.97 seconds
Started Aug 09 05:26:02 PM PDT 24
Finished Aug 09 05:26:03 PM PDT 24
Peak memory 207748 kb
Host smart-8db31099-40cf-47a5-9f32-69f1e4118020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
72915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1344072915
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.980059580
Short name T541
Test name
Test status
Simulation time 164679419 ps
CPU time 0.93 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207556 kb
Host smart-d6e486b1-c268-47ae-8cd2-bee31db2c400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98005
9580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.980059580
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2947274287
Short name T2856
Test name
Test status
Simulation time 249564862 ps
CPU time 1.13 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:02 PM PDT 24
Peak memory 207432 kb
Host smart-27317266-8ccb-4337-b971-e794580db5b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2947274287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2947274287
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1273456395
Short name T2356
Test name
Test status
Simulation time 224283722 ps
CPU time 1.07 seconds
Started Aug 09 05:25:57 PM PDT 24
Finished Aug 09 05:25:58 PM PDT 24
Peak memory 207428 kb
Host smart-34eb2c13-a579-45cd-ae52-3205b190926b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
56395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1273456395
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.309924787
Short name T2467
Test name
Test status
Simulation time 170389879 ps
CPU time 0.85 seconds
Started Aug 09 05:25:59 PM PDT 24
Finished Aug 09 05:26:00 PM PDT 24
Peak memory 207328 kb
Host smart-f15b4316-6cbd-4132-9879-22be75cf41de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.309924787
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2348399198
Short name T2891
Test name
Test status
Simulation time 45000527 ps
CPU time 0.74 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207404 kb
Host smart-fd421619-e527-45b9-8c04-304a46fcf604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
99198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2348399198
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2186053392
Short name T1001
Test name
Test status
Simulation time 14814651273 ps
CPU time 37.67 seconds
Started Aug 09 05:25:59 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 221060 kb
Host smart-5f2e82ad-402f-41eb-9ebd-9c31faebc030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21860
53392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2186053392
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2545173499
Short name T1160
Test name
Test status
Simulation time 174541451 ps
CPU time 0.9 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207424 kb
Host smart-2540e038-23b0-473f-b7cf-221a17e6c554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
73499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2545173499
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1939773155
Short name T2518
Test name
Test status
Simulation time 190531358 ps
CPU time 0.94 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207524 kb
Host smart-81e1b772-ee32-49fc-b50b-d84674645967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19397
73155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1939773155
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3441230446
Short name T2057
Test name
Test status
Simulation time 9377662642 ps
CPU time 50.95 seconds
Started Aug 09 05:26:06 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 215968 kb
Host smart-b41e3ee7-c0da-4fcf-b449-76448c611657
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441230446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3441230446
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3046605348
Short name T2955
Test name
Test status
Simulation time 7840669659 ps
CPU time 124.82 seconds
Started Aug 09 05:26:01 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 215984 kb
Host smart-76383d8d-0bd6-4ba2-985a-841f325e04d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046605348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3046605348
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.253195103
Short name T826
Test name
Test status
Simulation time 6126379092 ps
CPU time 23.89 seconds
Started Aug 09 05:25:57 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 215984 kb
Host smart-090047b8-75e3-41ac-ae33-4e7661863fda
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=253195103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.253195103
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.4232466331
Short name T1893
Test name
Test status
Simulation time 271069069 ps
CPU time 1.01 seconds
Started Aug 09 05:25:58 PM PDT 24
Finished Aug 09 05:25:59 PM PDT 24
Peak memory 207456 kb
Host smart-6c3e4755-c6c0-4e48-bcb7-9545a60aa25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
66331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.4232466331
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1955321417
Short name T1592
Test name
Test status
Simulation time 248041289 ps
CPU time 0.97 seconds
Started Aug 09 05:25:59 PM PDT 24
Finished Aug 09 05:26:00 PM PDT 24
Peak memory 207508 kb
Host smart-b82b5232-a319-4fc2-a993-f9e347216f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19553
21417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1955321417
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.108243054
Short name T3252
Test name
Test status
Simulation time 20177217360 ps
CPU time 28.55 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207868 kb
Host smart-b26fe43e-4998-4cbf-b884-dd0fd9d5bf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
3054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.108243054
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4254553330
Short name T3149
Test name
Test status
Simulation time 170251213 ps
CPU time 0.92 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207504 kb
Host smart-9bb7c78d-9871-4d2c-a2e5-d70d80719eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42545
53330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4254553330
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.1592620711
Short name T3215
Test name
Test status
Simulation time 409969210 ps
CPU time 1.28 seconds
Started Aug 09 05:26:03 PM PDT 24
Finished Aug 09 05:26:05 PM PDT 24
Peak memory 207504 kb
Host smart-e1ce0b17-66e3-41d1-a71c-668a4ed8ef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926
20711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.1592620711
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1454092717
Short name T2231
Test name
Test status
Simulation time 238191972 ps
CPU time 0.96 seconds
Started Aug 09 05:26:00 PM PDT 24
Finished Aug 09 05:26:01 PM PDT 24
Peak memory 207272 kb
Host smart-5eea2d87-cf86-40ab-b49c-bf5e184ad185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
92717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1454092717
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3626757428
Short name T214
Test name
Test status
Simulation time 634204415 ps
CPU time 1.62 seconds
Started Aug 09 05:26:05 PM PDT 24
Finished Aug 09 05:26:07 PM PDT 24
Peak memory 224780 kb
Host smart-9305ac4b-4088-46b2-a914-24aa11252c94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3626757428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3626757428
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3490273622
Short name T48
Test name
Test status
Simulation time 444679403 ps
CPU time 1.53 seconds
Started Aug 09 05:25:56 PM PDT 24
Finished Aug 09 05:25:58 PM PDT 24
Peak memory 207460 kb
Host smart-1800bb6e-b4b5-4136-8d20-5d9860fde615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34902
73622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3490273622
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.139166071
Short name T189
Test name
Test status
Simulation time 294736063 ps
CPU time 1.11 seconds
Started Aug 09 05:26:15 PM PDT 24
Finished Aug 09 05:26:17 PM PDT 24
Peak memory 207484 kb
Host smart-5c33594e-0a6d-4ba6-b59d-84caa07e8819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
6071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.139166071
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.771367776
Short name T1095
Test name
Test status
Simulation time 156881506 ps
CPU time 0.84 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207476 kb
Host smart-2178b2cb-1fd8-4529-bfe3-aed0d14f7b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77136
7776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.771367776
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3251572838
Short name T1078
Test name
Test status
Simulation time 153872760 ps
CPU time 0.87 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207496 kb
Host smart-ec8a9a1a-12a2-48b9-8aa2-40828af72505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32515
72838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3251572838
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4035607229
Short name T2797
Test name
Test status
Simulation time 248948518 ps
CPU time 1.1 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207432 kb
Host smart-c6a2d719-448c-4b3f-97fb-caa26d09ef98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
07229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4035607229
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1802407811
Short name T693
Test name
Test status
Simulation time 3253133792 ps
CPU time 31.94 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 218308 kb
Host smart-75dc74fb-9ac0-48bd-af1c-909f3973c11f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1802407811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1802407811
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2966170483
Short name T496
Test name
Test status
Simulation time 165298331 ps
CPU time 0.85 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207556 kb
Host smart-668256b8-ca7c-41ca-b0c7-653b0f836c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29661
70483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2966170483
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.737010211
Short name T1105
Test name
Test status
Simulation time 229189331 ps
CPU time 0.97 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207508 kb
Host smart-9171c1fb-a06e-4b56-abf8-af8485bd3562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73701
0211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.737010211
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.4192366955
Short name T3350
Test name
Test status
Simulation time 1365517002 ps
CPU time 3.16 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207700 kb
Host smart-19968e5e-c52f-45f5-b2dd-d335980ba843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41923
66955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.4192366955
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1721690341
Short name T1459
Test name
Test status
Simulation time 3058577591 ps
CPU time 24.69 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:26:31 PM PDT 24
Peak memory 217764 kb
Host smart-5eeadf7c-69d0-4d81-928f-9ff4d93157b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17216
90341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1721690341
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3065924181
Short name T104
Test name
Test status
Simulation time 10870044029 ps
CPU time 59.19 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:27:06 PM PDT 24
Peak memory 224252 kb
Host smart-7cebc646-da12-41c1-9ee4-f8dd913ec014
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065924181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3065924181
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.111274966
Short name T1143
Test name
Test status
Simulation time 4318072939 ps
CPU time 38.83 seconds
Started Aug 09 05:25:52 PM PDT 24
Finished Aug 09 05:26:31 PM PDT 24
Peak memory 208056 kb
Host smart-15263e58-f188-4489-bd98-988097a168e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111274966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.111274966
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.4184603727
Short name T979
Test name
Test status
Simulation time 440610789 ps
CPU time 1.33 seconds
Started Aug 09 05:26:05 PM PDT 24
Finished Aug 09 05:26:06 PM PDT 24
Peak memory 207528 kb
Host smart-a6f100fc-141f-4b0c-b5a1-2e422106a0d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184603727 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.4184603727
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3990521916
Short name T2270
Test name
Test status
Simulation time 41139976 ps
CPU time 0.67 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207480 kb
Host smart-c5526d24-7e71-430d-86f1-daf5a35a9985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3990521916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3990521916
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1783343047
Short name T2249
Test name
Test status
Simulation time 9377054370 ps
CPU time 11.05 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207852 kb
Host smart-83a62144-f016-4734-acb4-3f08b6e7f49d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783343047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.1783343047
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.411650328
Short name T1404
Test name
Test status
Simulation time 13564710980 ps
CPU time 16.53 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 215944 kb
Host smart-bf1a268f-8c4b-4c48-8ce1-53477131c463
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=411650328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.411650328
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2685185504
Short name T2967
Test name
Test status
Simulation time 30823689319 ps
CPU time 42.87 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207836 kb
Host smart-b5d1415c-c3af-427c-9415-8e5f55b13a2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685185504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.2685185504
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.423494917
Short name T1353
Test name
Test status
Simulation time 176531601 ps
CPU time 0.87 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207408 kb
Host smart-b6f725ab-1260-4597-93a5-567576029794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42349
4917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.423494917
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3501771709
Short name T2591
Test name
Test status
Simulation time 149088409 ps
CPU time 0.88 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207524 kb
Host smart-123d0732-f221-4952-992d-90c1b8cfd46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35017
71709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3501771709
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3752069904
Short name T2282
Test name
Test status
Simulation time 608124706 ps
CPU time 1.99 seconds
Started Aug 09 05:28:54 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207484 kb
Host smart-df360b7b-a1ba-4977-90ba-5c4b45679267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
69904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3752069904
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1378144701
Short name T1365
Test name
Test status
Simulation time 817950494 ps
CPU time 2.33 seconds
Started Aug 09 05:28:47 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207552 kb
Host smart-e1791cf5-9492-4e55-9418-3dda860599c8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1378144701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1378144701
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3392702058
Short name T3429
Test name
Test status
Simulation time 35735428613 ps
CPU time 62.76 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:29:55 PM PDT 24
Peak memory 207800 kb
Host smart-bfbaa795-c982-4e03-af70-e0791c5ea424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
02058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3392702058
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.271843478
Short name T3256
Test name
Test status
Simulation time 4372126157 ps
CPU time 32.82 seconds
Started Aug 09 05:28:43 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 207648 kb
Host smart-fd93b357-8c3b-44cc-a008-eabb1745a5a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271843478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.271843478
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3632220929
Short name T3084
Test name
Test status
Simulation time 729268003 ps
CPU time 1.87 seconds
Started Aug 09 05:28:42 PM PDT 24
Finished Aug 09 05:28:44 PM PDT 24
Peak memory 207524 kb
Host smart-d75f3331-f5e9-4d32-a418-58d39ff76c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36322
20929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3632220929
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2124000036
Short name T2104
Test name
Test status
Simulation time 141522983 ps
CPU time 0.84 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207496 kb
Host smart-419bc73d-b93f-4a31-b8d6-77a4080d948a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
00036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2124000036
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4040298798
Short name T3148
Test name
Test status
Simulation time 45670618 ps
CPU time 0.7 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207516 kb
Host smart-fd8d41b0-25b1-4c8d-a803-690e4571daf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402
98798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4040298798
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.4254800172
Short name T799
Test name
Test status
Simulation time 846386115 ps
CPU time 2.23 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207704 kb
Host smart-aa99e5c5-d381-4105-b0ea-057c33b47a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42548
00172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.4254800172
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.2701576362
Short name T370
Test name
Test status
Simulation time 489371705 ps
CPU time 1.36 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207520 kb
Host smart-4fec390a-a3b5-4b06-820b-6cdadf9dbbb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2701576362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.2701576362
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1391447229
Short name T3575
Test name
Test status
Simulation time 171740362 ps
CPU time 1.85 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207636 kb
Host smart-86a2ccdb-8b93-4795-9b0e-062440b4514a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
47229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1391447229
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3108574451
Short name T1521
Test name
Test status
Simulation time 238838647 ps
CPU time 1.25 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 215924 kb
Host smart-ee4f0851-4f36-49af-9bdb-950b66c108b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3108574451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3108574451
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4262131783
Short name T2927
Test name
Test status
Simulation time 168274861 ps
CPU time 0.86 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207524 kb
Host smart-edb40ca1-a2a2-42a0-82e9-a0d3389dc986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42621
31783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4262131783
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1921020924
Short name T1418
Test name
Test status
Simulation time 237006319 ps
CPU time 0.99 seconds
Started Aug 09 05:28:42 PM PDT 24
Finished Aug 09 05:28:43 PM PDT 24
Peak memory 207556 kb
Host smart-6af5ba7b-4207-4310-bee4-96efa2e2239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210
20924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1921020924
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2004876786
Short name T1009
Test name
Test status
Simulation time 4786378702 ps
CPU time 135.96 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 224108 kb
Host smart-e438cad8-ab5a-4578-b578-41f399db7078
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2004876786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2004876786
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.328954990
Short name T1363
Test name
Test status
Simulation time 4366850872 ps
CPU time 27.39 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:29:19 PM PDT 24
Peak memory 207784 kb
Host smart-76bd4143-3f06-4f08-8c15-faaec9737882
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=328954990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.328954990
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.741465930
Short name T3486
Test name
Test status
Simulation time 158349991 ps
CPU time 0.87 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:28:49 PM PDT 24
Peak memory 207432 kb
Host smart-dcba72f0-467e-4652-b10a-3a900e3add74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74146
5930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.741465930
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3199748190
Short name T510
Test name
Test status
Simulation time 28196505206 ps
CPU time 46.91 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207804 kb
Host smart-07f64b60-0535-49cd-9b00-e7d7fdffc489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31997
48190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3199748190
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.517858346
Short name T2318
Test name
Test status
Simulation time 4436541222 ps
CPU time 6.69 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 216088 kb
Host smart-6f915899-e866-44f0-bcfa-6b014c460acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51785
8346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.517858346
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.747853167
Short name T2789
Test name
Test status
Simulation time 4373100947 ps
CPU time 35.8 seconds
Started Aug 09 05:28:48 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 219452 kb
Host smart-96f5bf12-7033-40f4-8cf1-3d79b6ad2234
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=747853167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.747853167
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2229676535
Short name T1770
Test name
Test status
Simulation time 1718271009 ps
CPU time 17.03 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:29:09 PM PDT 24
Peak memory 217420 kb
Host smart-ad4f98f1-19e0-4909-8dbb-c5b23a4095e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2229676535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2229676535
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1501786696
Short name T1586
Test name
Test status
Simulation time 266238927 ps
CPU time 1.1 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207548 kb
Host smart-3b812898-105b-46ea-bcb0-23f6c43ad5dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1501786696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1501786696
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.817942507
Short name T3071
Test name
Test status
Simulation time 205867515 ps
CPU time 0.96 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207556 kb
Host smart-52739cdc-9254-43c8-a98e-a6199aa5ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81794
2507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.817942507
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.3930086121
Short name T2532
Test name
Test status
Simulation time 2483263673 ps
CPU time 71 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 216068 kb
Host smart-d6ba0efc-a91c-4450-8735-481ff8c69401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39300
86121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.3930086121
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2423063783
Short name T2801
Test name
Test status
Simulation time 3128284969 ps
CPU time 89.35 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:30:22 PM PDT 24
Peak memory 216008 kb
Host smart-4df9f379-7fd9-4638-92cb-95bc6ae16e4d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2423063783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2423063783
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.537958264
Short name T2748
Test name
Test status
Simulation time 162419664 ps
CPU time 0.87 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207540 kb
Host smart-d376634a-871c-4d53-8724-87753d058990
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=537958264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.537958264
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1522489551
Short name T1348
Test name
Test status
Simulation time 162783425 ps
CPU time 0.82 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207528 kb
Host smart-c4fb9bb7-ad6d-4d7e-97c7-ad203b76e420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15224
89551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1522489551
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1736010991
Short name T3091
Test name
Test status
Simulation time 218048994 ps
CPU time 0.94 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207404 kb
Host smart-ba843832-e554-45a6-966b-bd8361325ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
10991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1736010991
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3991317449
Short name T2173
Test name
Test status
Simulation time 163157112 ps
CPU time 0.86 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207592 kb
Host smart-42fb2c34-3d40-462b-9db0-941b51336224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39913
17449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3991317449
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1272801237
Short name T2682
Test name
Test status
Simulation time 209902456 ps
CPU time 0.93 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207552 kb
Host smart-8bb9f65e-8417-4af1-b46f-b1e1be00cb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
01237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1272801237
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3562271597
Short name T3097
Test name
Test status
Simulation time 148182438 ps
CPU time 0.84 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207364 kb
Host smart-35642d2f-f821-4aee-ae69-7c21893e882d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622
71597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3562271597
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3381263534
Short name T1295
Test name
Test status
Simulation time 229456508 ps
CPU time 1.03 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:51 PM PDT 24
Peak memory 207432 kb
Host smart-44a56a70-78a7-4945-9af1-1b861dc9add2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3381263534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3381263534
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2121794262
Short name T2082
Test name
Test status
Simulation time 215920510 ps
CPU time 0.95 seconds
Started Aug 09 05:28:49 PM PDT 24
Finished Aug 09 05:28:50 PM PDT 24
Peak memory 207352 kb
Host smart-beb44c13-2128-407a-a38b-3baa1fab9f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
94262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2121794262
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.4203200015
Short name T1471
Test name
Test status
Simulation time 38946286 ps
CPU time 0.7 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207516 kb
Host smart-61d517d0-ccd9-43fe-bff0-e639574b211b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42032
00015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.4203200015
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1108154076
Short name T2162
Test name
Test status
Simulation time 10654914149 ps
CPU time 26.09 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 220704 kb
Host smart-eaca7a5f-2c44-4752-b14c-5144a59b763e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
54076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1108154076
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.487448486
Short name T3153
Test name
Test status
Simulation time 234957012 ps
CPU time 1.05 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207472 kb
Host smart-d8e723ab-972d-42e6-b46f-fa1471c639eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48744
8486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.487448486
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.993209605
Short name T1960
Test name
Test status
Simulation time 222634088 ps
CPU time 0.96 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207444 kb
Host smart-453a6d80-98e6-404a-8cb4-7566e8d23543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99320
9605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.993209605
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3469851514
Short name T598
Test name
Test status
Simulation time 209313014 ps
CPU time 0.95 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207500 kb
Host smart-a40561b9-f94d-4d60-9a24-3af9dcbd326a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
51514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3469851514
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.68153607
Short name T3261
Test name
Test status
Simulation time 155492749 ps
CPU time 0.91 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207444 kb
Host smart-dea48713-5298-48d3-a72d-1190d7fc8a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68153
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.68153607
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3055300640
Short name T1604
Test name
Test status
Simulation time 149881811 ps
CPU time 0.81 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207380 kb
Host smart-779dbb04-bc82-42bf-834a-0ac4c21c2e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30553
00640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3055300640
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.3333742967
Short name T1483
Test name
Test status
Simulation time 399789671 ps
CPU time 1.36 seconds
Started Aug 09 05:28:50 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207428 kb
Host smart-b4017fa1-849f-46e0-8191-0c27f950f112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
42967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.3333742967
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3459868827
Short name T2208
Test name
Test status
Simulation time 172346879 ps
CPU time 0.88 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207476 kb
Host smart-5676caf5-a5ad-47d5-8e0f-f0f5d07e6aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34598
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3459868827
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1380961645
Short name T3068
Test name
Test status
Simulation time 203400557 ps
CPU time 0.93 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207800 kb
Host smart-e99c6736-0636-4460-8b26-61501f23e753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13809
61645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1380961645
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1890166829
Short name T3442
Test name
Test status
Simulation time 228659402 ps
CPU time 1.13 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207472 kb
Host smart-6f0b4ff8-9db5-41be-bef3-7d25d5fc22f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18901
66829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1890166829
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.57296609
Short name T3541
Test name
Test status
Simulation time 2913223895 ps
CPU time 29.31 seconds
Started Aug 09 05:28:54 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 217236 kb
Host smart-ca08a331-2cea-4afd-b974-e561d7b36086
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=57296609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.57296609
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2411148602
Short name T2229
Test name
Test status
Simulation time 173684302 ps
CPU time 0.85 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207464 kb
Host smart-aa24588c-bf44-4297-bcb8-088dd6cbbfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24111
48602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2411148602
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3676832225
Short name T2448
Test name
Test status
Simulation time 201125642 ps
CPU time 0.94 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207496 kb
Host smart-5f5356a0-3b0d-436f-a74a-c30512d556ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36768
32225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3676832225
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2814189304
Short name T2235
Test name
Test status
Simulation time 300676610 ps
CPU time 1.17 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207440 kb
Host smart-9bd4a7e6-c175-49db-a4ed-cfc327f3a994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
89304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2814189304
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3644517068
Short name T721
Test name
Test status
Simulation time 2437217630 ps
CPU time 18.08 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:18 PM PDT 24
Peak memory 207900 kb
Host smart-ac88c273-d27c-4338-a4cf-d8494d47ca77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
17068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3644517068
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.1662901553
Short name T1950
Test name
Test status
Simulation time 227540403 ps
CPU time 0.93 seconds
Started Aug 09 05:28:54 PM PDT 24
Finished Aug 09 05:28:55 PM PDT 24
Peak memory 207376 kb
Host smart-c85f3869-554a-4a79-892b-dc5ad6520b15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662901553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.1662901553
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2000008736
Short name T1005
Test name
Test status
Simulation time 516339324 ps
CPU time 1.62 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 207488 kb
Host smart-3917975d-2d8d-4872-9967-31802b15021b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000008736 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2000008736
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.2186719631
Short name T2520
Test name
Test status
Simulation time 584049417 ps
CPU time 1.66 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207536 kb
Host smart-0ed91643-78e4-4dc2-b98a-f865964e2e09
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186719631 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.2186719631
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.1768272073
Short name T1523
Test name
Test status
Simulation time 513107376 ps
CPU time 1.56 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207516 kb
Host smart-eb8fbb08-117e-45f2-be39-a73d86ec895b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768272073 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.1768272073
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.3624608437
Short name T930
Test name
Test status
Simulation time 550249226 ps
CPU time 1.53 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207388 kb
Host smart-5a6dc230-6f62-4851-999e-e1500b1bd00a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624608437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.3624608437
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.1150834681
Short name T3431
Test name
Test status
Simulation time 507377551 ps
CPU time 1.53 seconds
Started Aug 09 05:33:17 PM PDT 24
Finished Aug 09 05:33:19 PM PDT 24
Peak memory 207480 kb
Host smart-cece5b9c-950f-44ce-8958-50d1e2e91984
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150834681 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.1150834681
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.2711344397
Short name T2179
Test name
Test status
Simulation time 488285450 ps
CPU time 1.57 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207816 kb
Host smart-10eb45b3-aafd-4e7d-bab3-50522b106616
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711344397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.2711344397
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.337454982
Short name T3614
Test name
Test status
Simulation time 514537662 ps
CPU time 1.58 seconds
Started Aug 09 05:33:36 PM PDT 24
Finished Aug 09 05:33:37 PM PDT 24
Peak memory 207508 kb
Host smart-60284414-c2d5-470d-bf85-87849ef234c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337454982 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.337454982
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.4161046591
Short name T2442
Test name
Test status
Simulation time 488329563 ps
CPU time 1.48 seconds
Started Aug 09 05:33:22 PM PDT 24
Finished Aug 09 05:33:23 PM PDT 24
Peak memory 207480 kb
Host smart-c6a415d9-86f3-4a9e-8696-076749f4b6ec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161046591 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.4161046591
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.1768640439
Short name T2922
Test name
Test status
Simulation time 608342203 ps
CPU time 1.66 seconds
Started Aug 09 05:33:13 PM PDT 24
Finished Aug 09 05:33:14 PM PDT 24
Peak memory 207444 kb
Host smart-fcd5eebc-1257-4c8d-9f52-3ed976e0a631
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768640439 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.1768640439
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.3200576441
Short name T3441
Test name
Test status
Simulation time 602413383 ps
CPU time 1.65 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207800 kb
Host smart-8a581b5f-cbce-4d5d-a62d-2805f8340651
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200576441 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.3200576441
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.77228774
Short name T3498
Test name
Test status
Simulation time 568609633 ps
CPU time 1.58 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207512 kb
Host smart-06b7ef92-b639-48a3-9cd7-4f99ff84dbd4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77228774 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.77228774
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2611115559
Short name T3213
Test name
Test status
Simulation time 96013828 ps
CPU time 0.7 seconds
Started Aug 09 05:29:01 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207572 kb
Host smart-e93509f4-c7e1-4b0d-ab19-9af59ea7a129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2611115559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2611115559
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.424925206
Short name T1951
Test name
Test status
Simulation time 6665269761 ps
CPU time 8.56 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 215940 kb
Host smart-f7166bbc-7b6a-481a-8a2f-71213d1c6e4e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424925206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_disconnect.424925206
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1200175786
Short name T1678
Test name
Test status
Simulation time 13702846550 ps
CPU time 17.7 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 215944 kb
Host smart-64854cfc-2025-446c-a625-78f9ea6ef38f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200175786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1200175786
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1443186186
Short name T943
Test name
Test status
Simulation time 31100569329 ps
CPU time 46.29 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:29:38 PM PDT 24
Peak memory 207780 kb
Host smart-8450cf99-695c-47e8-b691-64fc176993ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443186186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.1443186186
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2519094046
Short name T3599
Test name
Test status
Simulation time 147876422 ps
CPU time 0.88 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207432 kb
Host smart-ab1c79f0-300b-43c9-831e-a2fe61d9a673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
94046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2519094046
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3044657500
Short name T2049
Test name
Test status
Simulation time 169355882 ps
CPU time 0.89 seconds
Started Aug 09 05:29:01 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 207440 kb
Host smart-20c99d9b-45f3-42c4-a213-2fe4aa6b0c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446
57500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3044657500
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1296982499
Short name T1992
Test name
Test status
Simulation time 350511608 ps
CPU time 1.39 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207440 kb
Host smart-daf27cd4-848d-4852-804f-bb0e1fbf5c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12969
82499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1296982499
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.4124997356
Short name T105
Test name
Test status
Simulation time 786367380 ps
CPU time 2.02 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 207564 kb
Host smart-c785413e-37ee-4ebe-ac8b-0be9e0bdccc9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4124997356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.4124997356
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3147090979
Short name T3555
Test name
Test status
Simulation time 37070584687 ps
CPU time 71.7 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:30:03 PM PDT 24
Peak memory 207804 kb
Host smart-72d1f0b1-ff49-4dac-b179-108678f211bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
90979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3147090979
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.2176318232
Short name T2707
Test name
Test status
Simulation time 282915709 ps
CPU time 4.41 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207544 kb
Host smart-4300bb85-9d9f-405c-9ca4-49394bf4ef85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176318232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.2176318232
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.301192563
Short name T1829
Test name
Test status
Simulation time 894740860 ps
CPU time 2.06 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 207412 kb
Host smart-d45e49ed-fe69-4ab1-bcd7-382d39f32d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30119
2563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.301192563
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3150459241
Short name T755
Test name
Test status
Simulation time 170467218 ps
CPU time 0.88 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207384 kb
Host smart-79d430d9-9acb-424c-a8e4-5a9d387b618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31504
59241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3150459241
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3201417181
Short name T577
Test name
Test status
Simulation time 37870089 ps
CPU time 0.7 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207384 kb
Host smart-09664e46-754e-4aa1-983f-5acfa480dbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
17181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3201417181
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2557099097
Short name T1377
Test name
Test status
Simulation time 895935628 ps
CPU time 2.26 seconds
Started Aug 09 05:28:58 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207640 kb
Host smart-89006d17-f479-41b1-9ce1-f94d1f2488f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25570
99097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2557099097
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.941095934
Short name T425
Test name
Test status
Simulation time 618119540 ps
CPU time 1.82 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207436 kb
Host smart-f84326fe-2b6b-4ce0-8241-0e67a8fad81d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=941095934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.941095934
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1069606928
Short name T1209
Test name
Test status
Simulation time 192392320 ps
CPU time 2.59 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207536 kb
Host smart-b280000b-5a0a-4ff7-889c-84bd314f971b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10696
06928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1069606928
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2397195072
Short name T656
Test name
Test status
Simulation time 165421492 ps
CPU time 0.92 seconds
Started Aug 09 05:28:52 PM PDT 24
Finished Aug 09 05:28:53 PM PDT 24
Peak memory 207552 kb
Host smart-d57c119e-ac69-4686-80db-f52d501c8e8b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2397195072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2397195072
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2520054120
Short name T795
Test name
Test status
Simulation time 144475223 ps
CPU time 0.84 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207468 kb
Host smart-8e110862-e151-44f5-8bd0-80a7d85c0425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
54120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2520054120
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1900991370
Short name T3050
Test name
Test status
Simulation time 189527192 ps
CPU time 0.94 seconds
Started Aug 09 05:28:51 PM PDT 24
Finished Aug 09 05:28:52 PM PDT 24
Peak memory 207476 kb
Host smart-0771a1a9-a898-4097-9632-c4798bfcc3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
91370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1900991370
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.2704146618
Short name T2335
Test name
Test status
Simulation time 4461462004 ps
CPU time 46.1 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 224224 kb
Host smart-0bf3dbe2-f32a-4fea-a19d-50bc2435552f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2704146618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2704146618
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.563094627
Short name T2982
Test name
Test status
Simulation time 5677641820 ps
CPU time 71.67 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207736 kb
Host smart-1feac2e1-b593-4e33-8430-3c23638a7447
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=563094627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.563094627
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.618333310
Short name T2023
Test name
Test status
Simulation time 230334498 ps
CPU time 1.08 seconds
Started Aug 09 05:28:53 PM PDT 24
Finished Aug 09 05:28:54 PM PDT 24
Peak memory 207504 kb
Host smart-7b1cb11c-1dc5-499b-8e11-f9c443a28570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61833
3310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.618333310
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2610231433
Short name T3488
Test name
Test status
Simulation time 31254992951 ps
CPU time 48.26 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207824 kb
Host smart-0b597e29-2207-4a38-9c75-a15731716edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
31433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2610231433
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.15593882
Short name T3391
Test name
Test status
Simulation time 8481816793 ps
CPU time 10.05 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:29:07 PM PDT 24
Peak memory 207772 kb
Host smart-ce9bbeb6-7c3b-4862-b7dd-b6bb3b4d4d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15593
882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.15593882
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2810247380
Short name T594
Test name
Test status
Simulation time 3373538107 ps
CPU time 95.74 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:30:53 PM PDT 24
Peak memory 218400 kb
Host smart-67421965-1485-4fa5-bcba-3577e53749a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2810247380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2810247380
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3485658849
Short name T3140
Test name
Test status
Simulation time 3027485006 ps
CPU time 86.15 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 216040 kb
Host smart-1892017d-874d-45f3-a13f-bad0546a2a25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3485658849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3485658849
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1769716404
Short name T152
Test name
Test status
Simulation time 242088406 ps
CPU time 1.08 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 207544 kb
Host smart-bc4d20f6-3d7b-4b77-bc4b-bb6ec174375a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1769716404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1769716404
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2883535392
Short name T1607
Test name
Test status
Simulation time 187665434 ps
CPU time 0.92 seconds
Started Aug 09 05:29:06 PM PDT 24
Finished Aug 09 05:29:07 PM PDT 24
Peak memory 207480 kb
Host smart-becc3ae4-9214-4a23-bb02-0ffad1cded72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835
35392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2883535392
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.4159512654
Short name T2868
Test name
Test status
Simulation time 1962579105 ps
CPU time 19.51 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 223084 kb
Host smart-6213395e-7226-4f9e-a3f4-c88f97552850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595
12654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.4159512654
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1021185521
Short name T1409
Test name
Test status
Simulation time 3029241513 ps
CPU time 89.92 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 217528 kb
Host smart-57245583-3418-4de7-93af-8b17d63fd859
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1021185521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1021185521
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2505771274
Short name T1272
Test name
Test status
Simulation time 156085036 ps
CPU time 0.87 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207544 kb
Host smart-5b360f4b-65ad-4a1d-9c8c-a9e421c9a697
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2505771274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2505771274
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3639229259
Short name T883
Test name
Test status
Simulation time 154413169 ps
CPU time 0.81 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207488 kb
Host smart-d895d8e8-52f5-444b-a927-0bcdeb554f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36392
29259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3639229259
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3539197410
Short name T120
Test name
Test status
Simulation time 287714103 ps
CPU time 1.01 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207504 kb
Host smart-505f1e41-393b-4a72-97e2-5e5b9c220d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35391
97410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3539197410
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.4199708697
Short name T2421
Test name
Test status
Simulation time 191621867 ps
CPU time 0.92 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:28:58 PM PDT 24
Peak memory 206484 kb
Host smart-e20c9388-9455-49a1-80f1-bf93c270f47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
08697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.4199708697
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1816126983
Short name T3521
Test name
Test status
Simulation time 176988575 ps
CPU time 0.86 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207368 kb
Host smart-9ea545e4-2a71-49c1-8aae-97b774955e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18161
26983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1816126983
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.394848391
Short name T2919
Test name
Test status
Simulation time 158110930 ps
CPU time 0.93 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 207452 kb
Host smart-1c957395-b3af-4c13-8459-f70ee00f34b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39484
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.394848391
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3318282175
Short name T2638
Test name
Test status
Simulation time 173727034 ps
CPU time 0.9 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207440 kb
Host smart-ec10bc41-5ad1-4467-a71b-7d9be0fb8c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33182
82175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3318282175
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1055110908
Short name T3258
Test name
Test status
Simulation time 222854866 ps
CPU time 1.04 seconds
Started Aug 09 05:29:01 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 207532 kb
Host smart-69b1f619-5542-4736-b89c-eae9729cbe1d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1055110908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1055110908
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.159236423
Short name T1693
Test name
Test status
Simulation time 138555888 ps
CPU time 0.8 seconds
Started Aug 09 05:29:02 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207328 kb
Host smart-c6ab02e1-9ed8-424b-a45b-cdf9ebb9cb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15923
6423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.159236423
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2576873936
Short name T1280
Test name
Test status
Simulation time 41771695 ps
CPU time 0.7 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207512 kb
Host smart-508313a4-bf09-4b07-8cee-30be4290828e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
73936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2576873936
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.512539435
Short name T3401
Test name
Test status
Simulation time 8117545096 ps
CPU time 20.75 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:29 PM PDT 24
Peak memory 215940 kb
Host smart-04e05816-f60d-4046-bbd7-098e284faf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51253
9435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.512539435
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.423404512
Short name T1485
Test name
Test status
Simulation time 170451485 ps
CPU time 0.86 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207528 kb
Host smart-7d7960c2-5452-429c-8c49-05f22f65e972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42340
4512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.423404512
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2196604511
Short name T3300
Test name
Test status
Simulation time 161562731 ps
CPU time 0.87 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207528 kb
Host smart-2586b40d-c7d3-4d44-9808-8d208eb6ce67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21966
04511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2196604511
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1770141740
Short name T1013
Test name
Test status
Simulation time 228718574 ps
CPU time 0.99 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207408 kb
Host smart-d0af1cf3-e51f-4097-96b4-578a901a2aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17701
41740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1770141740
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.2503511164
Short name T1945
Test name
Test status
Simulation time 206467484 ps
CPU time 0.93 seconds
Started Aug 09 05:29:01 PM PDT 24
Finished Aug 09 05:29:02 PM PDT 24
Peak memory 207452 kb
Host smart-b4853a19-b442-4914-b82e-c98001565c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25035
11164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2503511164
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3722628249
Short name T660
Test name
Test status
Simulation time 147885974 ps
CPU time 0.82 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207460 kb
Host smart-968ba758-27bd-4638-8fd0-da194697411d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37226
28249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3722628249
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.2249444658
Short name T1988
Test name
Test status
Simulation time 311180552 ps
CPU time 1.13 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207352 kb
Host smart-8577e73b-e89a-4636-89b0-ab7ca2f08ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
44658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.2249444658
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.664531718
Short name T584
Test name
Test status
Simulation time 154369203 ps
CPU time 0.83 seconds
Started Aug 09 05:29:10 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207424 kb
Host smart-812efbd6-1b76-45c9-b59d-3fd6cb51570c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66453
1718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.664531718
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1622460370
Short name T3073
Test name
Test status
Simulation time 150782292 ps
CPU time 0.88 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 207392 kb
Host smart-cb0f037b-a6cb-4e7c-a223-bea175fa37b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16224
60370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1622460370
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3671639138
Short name T2699
Test name
Test status
Simulation time 221174458 ps
CPU time 1.02 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207508 kb
Host smart-107ad131-c7f7-44dd-ac5c-004d78e82d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36716
39138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3671639138
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2842569422
Short name T990
Test name
Test status
Simulation time 2161367972 ps
CPU time 17.34 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 217736 kb
Host smart-07db08b6-ac34-4fc9-83f4-491fab16d390
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2842569422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2842569422
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.904160291
Short name T494
Test name
Test status
Simulation time 152475765 ps
CPU time 0.86 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:09 PM PDT 24
Peak memory 207384 kb
Host smart-63cd4e39-eea9-46a8-a21e-8132a409fd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90416
0291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.904160291
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2770412622
Short name T743
Test name
Test status
Simulation time 183531706 ps
CPU time 0.87 seconds
Started Aug 09 05:28:59 PM PDT 24
Finished Aug 09 05:29:00 PM PDT 24
Peak memory 207428 kb
Host smart-24241fca-1ddb-4c55-98ba-0398d047d384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27704
12622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2770412622
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3158976053
Short name T2546
Test name
Test status
Simulation time 1030666284 ps
CPU time 3 seconds
Started Aug 09 05:29:00 PM PDT 24
Finished Aug 09 05:29:03 PM PDT 24
Peak memory 207540 kb
Host smart-9fbf9a97-519e-4515-af2a-f35ba47806d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31589
76053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3158976053
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1259103459
Short name T3172
Test name
Test status
Simulation time 1798506228 ps
CPU time 52.47 seconds
Started Aug 09 05:28:55 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 224028 kb
Host smart-f4d57797-3049-415e-8f17-a813ab18f821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591
03459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1259103459
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.333081073
Short name T3584
Test name
Test status
Simulation time 4824171809 ps
CPU time 43.27 seconds
Started Aug 09 05:28:54 PM PDT 24
Finished Aug 09 05:29:38 PM PDT 24
Peak memory 207784 kb
Host smart-b4bd0a11-a8b2-4daa-a3ab-a6e0c1e77909
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333081073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_host
_handshake.333081073
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.1553031837
Short name T1620
Test name
Test status
Simulation time 523294154 ps
CPU time 1.57 seconds
Started Aug 09 05:28:57 PM PDT 24
Finished Aug 09 05:28:59 PM PDT 24
Peak memory 207560 kb
Host smart-e4a4d05f-c755-4d54-b209-946727f6b578
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553031837 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.1553031837
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.968093839
Short name T770
Test name
Test status
Simulation time 554503555 ps
CPU time 1.49 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207412 kb
Host smart-2d925537-d9fb-4601-8f2e-bfb34983f595
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968093839 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.968093839
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.4087317318
Short name T3067
Test name
Test status
Simulation time 540752734 ps
CPU time 1.61 seconds
Started Aug 09 05:33:36 PM PDT 24
Finished Aug 09 05:33:38 PM PDT 24
Peak memory 207520 kb
Host smart-a6891ccd-fb34-4a01-9365-fa20672cbe05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087317318 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.4087317318
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.929216353
Short name T1227
Test name
Test status
Simulation time 498286918 ps
CPU time 1.5 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:25 PM PDT 24
Peak memory 207440 kb
Host smart-308a2a83-c174-40b5-8fbd-531c512c9889
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929216353 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.929216353
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.3393749536
Short name T2197
Test name
Test status
Simulation time 574837470 ps
CPU time 1.68 seconds
Started Aug 09 05:33:32 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207516 kb
Host smart-a3420464-9421-4b05-9c6f-7cc3d60d0c35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393749536 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.3393749536
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.413616164
Short name T1606
Test name
Test status
Simulation time 509319553 ps
CPU time 1.53 seconds
Started Aug 09 05:33:44 PM PDT 24
Finished Aug 09 05:33:45 PM PDT 24
Peak memory 207824 kb
Host smart-c28eb554-9221-4f1e-87a2-099e5a33f705
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413616164 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.413616164
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.3672805122
Short name T2110
Test name
Test status
Simulation time 481854094 ps
CPU time 1.57 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207508 kb
Host smart-48b1ca5f-bcdf-465e-be04-896b1b81211d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672805122 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.3672805122
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.557068082
Short name T854
Test name
Test status
Simulation time 554846476 ps
CPU time 1.64 seconds
Started Aug 09 05:33:39 PM PDT 24
Finished Aug 09 05:33:41 PM PDT 24
Peak memory 207512 kb
Host smart-12c3da9a-d11c-400a-b9dd-9e808edc566c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557068082 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.557068082
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.1758721092
Short name T174
Test name
Test status
Simulation time 634707013 ps
CPU time 1.79 seconds
Started Aug 09 05:33:38 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207400 kb
Host smart-03690944-44ca-4843-a838-f16bf60d0fa6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758721092 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.1758721092
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.1109691435
Short name T736
Test name
Test status
Simulation time 508518755 ps
CPU time 1.55 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207564 kb
Host smart-ce3669ce-fa24-494b-8460-067e922f0447
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109691435 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.1109691435
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.3721540561
Short name T2149
Test name
Test status
Simulation time 541013380 ps
CPU time 1.66 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207556 kb
Host smart-7a80f6cf-b0aa-4322-89f6-235cc39387df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721540561 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.3721540561
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1511266441
Short name T2269
Test name
Test status
Simulation time 29674701 ps
CPU time 0.64 seconds
Started Aug 09 05:29:16 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207536 kb
Host smart-f158962b-fa2c-4b82-bdf7-176eb69edd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1511266441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1511266441
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3104218847
Short name T2027
Test name
Test status
Simulation time 14107027230 ps
CPU time 16.76 seconds
Started Aug 09 05:29:14 PM PDT 24
Finished Aug 09 05:29:31 PM PDT 24
Peak memory 215948 kb
Host smart-cce886bc-089b-4117-ab94-9ac82b2cca1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104218847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3104218847
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.157219964
Short name T3209
Test name
Test status
Simulation time 23735313777 ps
CPU time 30.48 seconds
Started Aug 09 05:28:56 PM PDT 24
Finished Aug 09 05:29:27 PM PDT 24
Peak memory 215964 kb
Host smart-7cb4ef5f-3649-4ad4-a980-ddcedcce4361
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157219964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_ao
n_wake_resume.157219964
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3109606861
Short name T1821
Test name
Test status
Simulation time 172883194 ps
CPU time 0.89 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207528 kb
Host smart-29640aa7-5e8c-4267-9bb9-36007b6c026d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31096
06861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3109606861
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3468281919
Short name T2192
Test name
Test status
Simulation time 159676958 ps
CPU time 0.85 seconds
Started Aug 09 05:29:10 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207468 kb
Host smart-54ab8a4a-6f0c-455a-a7bb-605808938eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
81919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3468281919
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1626616152
Short name T935
Test name
Test status
Simulation time 484892743 ps
CPU time 1.56 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207480 kb
Host smart-d56dd186-1534-4731-8426-87da2e88b9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266
16152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1626616152
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.4262987515
Short name T1444
Test name
Test status
Simulation time 1058796353 ps
CPU time 2.8 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207644 kb
Host smart-117bdf9f-8817-4b95-9f81-b2d03cb7f2c7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4262987515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.4262987515
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1569488298
Short name T3337
Test name
Test status
Simulation time 50705822376 ps
CPU time 75.55 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:30:19 PM PDT 24
Peak memory 207740 kb
Host smart-e098282e-717a-4811-bf2a-ad5de69200d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
88298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1569488298
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.2140023775
Short name T1998
Test name
Test status
Simulation time 5512937958 ps
CPU time 38.83 seconds
Started Aug 09 05:29:10 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207792 kb
Host smart-c67a89ba-6cc7-4b6e-b6fa-393fb3a5965c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140023775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.2140023775
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.844935321
Short name T1758
Test name
Test status
Simulation time 913977425 ps
CPU time 1.98 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207412 kb
Host smart-e03ce42c-52cf-4299-b465-736914b1208f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84493
5321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.844935321
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1122752778
Short name T1580
Test name
Test status
Simulation time 147773365 ps
CPU time 0.82 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207408 kb
Host smart-517fdcf6-6b94-4631-b474-8e6470cac3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
52778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1122752778
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1287127227
Short name T3597
Test name
Test status
Simulation time 31549626 ps
CPU time 0.7 seconds
Started Aug 09 05:29:06 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207400 kb
Host smart-14880a2a-767c-40e1-96e0-fa09343c8baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
27227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1287127227
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2946684505
Short name T1798
Test name
Test status
Simulation time 815190557 ps
CPU time 2.42 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207704 kb
Host smart-fb165685-d605-48bf-a29b-4f759be7bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466
84505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2946684505
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.3713650137
Short name T493
Test name
Test status
Simulation time 513642104 ps
CPU time 1.47 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207464 kb
Host smart-7cca85bb-b4a6-4a14-a82b-4961147f3f27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3713650137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.3713650137
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4246103946
Short name T3277
Test name
Test status
Simulation time 316156020 ps
CPU time 1.9 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207532 kb
Host smart-f637ce10-1c30-42d1-9c68-59753ea5b8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
03946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4246103946
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1751540053
Short name T3454
Test name
Test status
Simulation time 172927102 ps
CPU time 0.89 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207376 kb
Host smart-72d6d060-e685-404d-b224-34e30faa7d8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1751540053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1751540053
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3872316255
Short name T220
Test name
Test status
Simulation time 194201580 ps
CPU time 0.89 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207404 kb
Host smart-5e1de6f1-087d-43a9-b1d5-1a2c1a9c26f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
16255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3872316255
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2537449168
Short name T1543
Test name
Test status
Simulation time 183394275 ps
CPU time 0.9 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:06 PM PDT 24
Peak memory 207512 kb
Host smart-f1e898d2-25cf-4819-b7fc-bb0ab295a2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
49168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2537449168
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2102971268
Short name T1453
Test name
Test status
Simulation time 3797620869 ps
CPU time 112.4 seconds
Started Aug 09 05:29:14 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 218060 kb
Host smart-0471185d-6b36-4b06-ba0b-611de96c0ca9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2102971268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2102971268
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.1305271640
Short name T2458
Test name
Test status
Simulation time 3786718105 ps
CPU time 43.09 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 207748 kb
Host smart-7d720404-474c-48f7-ac44-499dc3b00ba4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1305271640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1305271640
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1453943684
Short name T3181
Test name
Test status
Simulation time 201224847 ps
CPU time 0.92 seconds
Started Aug 09 05:29:15 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 207500 kb
Host smart-ee481de2-36f6-4cbf-a478-7bb1ecd5fc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
43684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1453943684
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3955088908
Short name T1650
Test name
Test status
Simulation time 23833724796 ps
CPU time 42.85 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207764 kb
Host smart-abd2d248-19c9-4c1b-b4ea-cc587ac81e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
88908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3955088908
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2296109804
Short name T562
Test name
Test status
Simulation time 3790667123 ps
CPU time 6.62 seconds
Started Aug 09 05:29:16 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207636 kb
Host smart-ae9b8117-4455-4875-9db8-8c8e1b000d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
09804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2296109804
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2571860321
Short name T3435
Test name
Test status
Simulation time 3031976851 ps
CPU time 23.58 seconds
Started Aug 09 05:29:12 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 219528 kb
Host smart-40b98688-56cc-435c-aeba-0b3d7829640c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2571860321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2571860321
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.340857232
Short name T2195
Test name
Test status
Simulation time 1752943200 ps
CPU time 51.94 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 224376 kb
Host smart-2448c443-0e26-4dc9-a1c5-4e037521a686
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=340857232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.340857232
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.1599267126
Short name T1407
Test name
Test status
Simulation time 241213684 ps
CPU time 1.02 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207388 kb
Host smart-d55162ad-c106-4715-a726-351707cc029a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1599267126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.1599267126
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2792572918
Short name T673
Test name
Test status
Simulation time 205274640 ps
CPU time 1.02 seconds
Started Aug 09 05:29:07 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207500 kb
Host smart-e8bcb13c-2913-462a-a7ac-85e0035b0abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27925
72918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2792572918
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.3474197206
Short name T636
Test name
Test status
Simulation time 3204529342 ps
CPU time 93.57 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 217744 kb
Host smart-a09a3d24-7e03-40c0-b237-7865617f82c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741
97206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.3474197206
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1273877327
Short name T3506
Test name
Test status
Simulation time 3435623656 ps
CPU time 33.56 seconds
Started Aug 09 05:29:07 PM PDT 24
Finished Aug 09 05:29:40 PM PDT 24
Peak memory 217632 kb
Host smart-ade178bc-59ae-41d5-9a36-fd2205b8a27e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1273877327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1273877327
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1766227689
Short name T1803
Test name
Test status
Simulation time 155388524 ps
CPU time 1 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207592 kb
Host smart-1edf0081-3880-43f7-acaf-398b73f7b187
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1766227689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1766227689
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3138083653
Short name T2334
Test name
Test status
Simulation time 155982169 ps
CPU time 0.86 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207524 kb
Host smart-4021e86a-ce55-4926-8569-6bced0735511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31380
83653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3138083653
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1655539626
Short name T148
Test name
Test status
Simulation time 222238067 ps
CPU time 1.01 seconds
Started Aug 09 05:29:06 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207508 kb
Host smart-50e5d968-6ffb-47cf-b6fa-9af7206b91da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16555
39626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1655539626
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2169434107
Short name T1728
Test name
Test status
Simulation time 241053885 ps
CPU time 1.08 seconds
Started Aug 09 05:29:13 PM PDT 24
Finished Aug 09 05:29:14 PM PDT 24
Peak memory 207420 kb
Host smart-6f4bfa18-cca4-4a27-8ee3-cb607314543e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21694
34107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2169434107
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3366814008
Short name T582
Test name
Test status
Simulation time 181735444 ps
CPU time 0.9 seconds
Started Aug 09 05:29:16 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207448 kb
Host smart-584d376b-e4e1-4f75-b8b6-c1447337fe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33668
14008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3366814008
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3208625782
Short name T1190
Test name
Test status
Simulation time 186789883 ps
CPU time 0.92 seconds
Started Aug 09 05:29:13 PM PDT 24
Finished Aug 09 05:29:14 PM PDT 24
Peak memory 207508 kb
Host smart-0abae94f-e9d8-49f1-b53d-e3a6650d4b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
25782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3208625782
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1057695022
Short name T899
Test name
Test status
Simulation time 149735755 ps
CPU time 0.87 seconds
Started Aug 09 05:29:15 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 207448 kb
Host smart-37d2940d-7627-48b3-98c1-bc23f52f1571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10576
95022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1057695022
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3939031070
Short name T1165
Test name
Test status
Simulation time 209599616 ps
CPU time 0.96 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207476 kb
Host smart-cc70e176-a21e-4674-81fd-575583e73e05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3939031070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3939031070
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1704123287
Short name T3349
Test name
Test status
Simulation time 137358850 ps
CPU time 0.86 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207380 kb
Host smart-ecf8ae74-c84b-41e3-b19b-1ea503acee2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17041
23287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1704123287
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1455274313
Short name T34
Test name
Test status
Simulation time 48591066 ps
CPU time 0.72 seconds
Started Aug 09 05:29:16 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207376 kb
Host smart-1f39d279-fc52-427f-96ae-1aa7451e6db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
74313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1455274313
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4069504870
Short name T1449
Test name
Test status
Simulation time 15768437100 ps
CPU time 39.87 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 215960 kb
Host smart-3ad40497-82c3-45db-a111-e81b4c8f07e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40695
04870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4069504870
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.513156646
Short name T2819
Test name
Test status
Simulation time 207676829 ps
CPU time 1.02 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207380 kb
Host smart-1eccdcf8-76f7-4ecc-aa7b-40fe7920b6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51315
6646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.513156646
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.384945929
Short name T2462
Test name
Test status
Simulation time 231586192 ps
CPU time 0.94 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207408 kb
Host smart-e017e8ee-3a1f-4e2e-b322-c38854ff987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
5929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.384945929
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.3640658229
Short name T2418
Test name
Test status
Simulation time 224114604 ps
CPU time 1.01 seconds
Started Aug 09 05:29:16 PM PDT 24
Finished Aug 09 05:29:17 PM PDT 24
Peak memory 207508 kb
Host smart-8e294b93-bd55-4cce-82cb-c2e098ea1b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
58229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.3640658229
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3230266244
Short name T514
Test name
Test status
Simulation time 151465864 ps
CPU time 0.88 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207512 kb
Host smart-b910423c-120a-470a-ab6e-72992ff4e904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
66244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3230266244
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1903679565
Short name T1427
Test name
Test status
Simulation time 229811366 ps
CPU time 0.97 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:29:18 PM PDT 24
Peak memory 207472 kb
Host smart-9e57cf46-b5b8-46a5-9119-8fb8e64e4957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
79565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1903679565
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.1182873205
Short name T710
Test name
Test status
Simulation time 376677699 ps
CPU time 1.29 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207492 kb
Host smart-09da0666-936e-4e8c-bdc5-fde3b73f030c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
73205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.1182873205
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4018118100
Short name T2500
Test name
Test status
Simulation time 166926241 ps
CPU time 0.85 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:12 PM PDT 24
Peak memory 207444 kb
Host smart-e687dd1e-2a8c-421c-9729-b2b7577d90bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40181
18100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4018118100
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.692703334
Short name T1587
Test name
Test status
Simulation time 153216246 ps
CPU time 0.87 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207552 kb
Host smart-46876673-e3dd-448e-bd1f-97508796c514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69270
3334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.692703334
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4270361912
Short name T1488
Test name
Test status
Simulation time 238746982 ps
CPU time 1.07 seconds
Started Aug 09 05:29:12 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207500 kb
Host smart-f2ebc375-0af9-41bc-8ab0-7bcee2a5f33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
61912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4270361912
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1991684380
Short name T3365
Test name
Test status
Simulation time 2532943546 ps
CPU time 25.15 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:30 PM PDT 24
Peak memory 224204 kb
Host smart-6296d231-fb72-4656-8f83-75ef6a3d9ec2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1991684380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1991684380
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2777638040
Short name T1344
Test name
Test status
Simulation time 167812822 ps
CPU time 0.86 seconds
Started Aug 09 05:29:04 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207424 kb
Host smart-da201d0a-36c6-4427-9e8e-016e09682230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
38040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2777638040
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2719894880
Short name T1955
Test name
Test status
Simulation time 188195057 ps
CPU time 0.92 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207472 kb
Host smart-3eedd7ae-0312-46f5-a912-7cd40f7b5f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
94880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2719894880
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3790519698
Short name T3480
Test name
Test status
Simulation time 727594873 ps
CPU time 1.77 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207484 kb
Host smart-5d5bc62b-df35-44d0-8352-0675eaa3f39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
19698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3790519698
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3626662331
Short name T3586
Test name
Test status
Simulation time 2387447604 ps
CPU time 23.61 seconds
Started Aug 09 05:29:05 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 216068 kb
Host smart-2041700b-3441-49f9-83a9-bdb6938a9406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266
62331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3626662331
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2379934839
Short name T2746
Test name
Test status
Simulation time 2933186525 ps
CPU time 26.72 seconds
Started Aug 09 05:29:06 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207744 kb
Host smart-17ed5867-af4a-400e-92d6-7d4447ab1bb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379934839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.2379934839
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.332514557
Short name T2970
Test name
Test status
Simulation time 729461455 ps
CPU time 1.89 seconds
Started Aug 09 05:29:18 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207528 kb
Host smart-de194b09-4a9c-44e6-9845-489a54da6c63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332514557 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.332514557
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.2054497090
Short name T188
Test name
Test status
Simulation time 635218516 ps
CPU time 1.77 seconds
Started Aug 09 05:33:28 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 207504 kb
Host smart-87534c90-7264-4109-98fb-fc7d544392da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054497090 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.2054497090
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.2700063420
Short name T1379
Test name
Test status
Simulation time 583308925 ps
CPU time 1.74 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207428 kb
Host smart-09753314-a22f-4cc9-a0d4-c6494fa0d62e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700063420 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.2700063420
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.1358032810
Short name T2480
Test name
Test status
Simulation time 611643845 ps
CPU time 1.89 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207600 kb
Host smart-e5ad4641-039f-4aca-b472-e0467539a46d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358032810 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.1358032810
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.2591522486
Short name T720
Test name
Test status
Simulation time 476429024 ps
CPU time 1.45 seconds
Started Aug 09 05:33:19 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 207464 kb
Host smart-20b13be7-1d70-4377-8da7-a040da737ec5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591522486 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.2591522486
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.2496648310
Short name T728
Test name
Test status
Simulation time 617117045 ps
CPU time 1.64 seconds
Started Aug 09 05:33:26 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207512 kb
Host smart-be36654f-fbdb-4a76-a8a6-c47ce7c78c0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496648310 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.2496648310
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.1243501025
Short name T3115
Test name
Test status
Simulation time 626055272 ps
CPU time 1.69 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:45 PM PDT 24
Peak memory 207564 kb
Host smart-a7fef687-9cad-4638-b543-72811e8563d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243501025 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.1243501025
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.459481690
Short name T1421
Test name
Test status
Simulation time 536577676 ps
CPU time 1.8 seconds
Started Aug 09 05:33:36 PM PDT 24
Finished Aug 09 05:33:38 PM PDT 24
Peak memory 207464 kb
Host smart-6f1bc6d0-9a96-4d17-b4d5-9513f02cb2d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459481690 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.459481690
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.842775595
Short name T1582
Test name
Test status
Simulation time 674842951 ps
CPU time 1.72 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207432 kb
Host smart-8afc8337-67c3-4e8b-a721-a9f4b761a21f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842775595 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.842775595
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.709162794
Short name T89
Test name
Test status
Simulation time 503716006 ps
CPU time 1.49 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207460 kb
Host smart-b0f66ac0-f03a-48f9-9bd5-19852aef6879
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709162794 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.709162794
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.2726648763
Short name T1413
Test name
Test status
Simulation time 543547980 ps
CPU time 1.55 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207500 kb
Host smart-d6dc24b8-285f-4fd0-af89-ea6f05a46d0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726648763 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.2726648763
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2089071774
Short name T1278
Test name
Test status
Simulation time 45717516 ps
CPU time 0.66 seconds
Started Aug 09 05:29:23 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207428 kb
Host smart-8e578a31-349e-4ff6-841e-af6229d0a03d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2089071774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2089071774
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2498512509
Short name T2472
Test name
Test status
Simulation time 6641067193 ps
CPU time 9.3 seconds
Started Aug 09 05:29:23 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 216032 kb
Host smart-960cdd0d-6ed8-465c-8db0-9f1ca3d81cff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498512509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.2498512509
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3063142812
Short name T3598
Test name
Test status
Simulation time 16237741277 ps
CPU time 18.32 seconds
Started Aug 09 05:29:14 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 215944 kb
Host smart-d96ea30c-91d5-4380-9fa9-67c85ff1c42f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063142812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3063142812
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.4202469795
Short name T2150
Test name
Test status
Simulation time 28445991518 ps
CPU time 33.26 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207780 kb
Host smart-793c8c47-b0eb-43da-8e94-fc98f7031d52
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202469795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.4202469795
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.570435176
Short name T28
Test name
Test status
Simulation time 160011310 ps
CPU time 0.88 seconds
Started Aug 09 05:29:03 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 207508 kb
Host smart-382f699b-c3a8-455e-860f-bbcb23380c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57043
5176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.570435176
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.5771943
Short name T2531
Test name
Test status
Simulation time 142850699 ps
CPU time 0.82 seconds
Started Aug 09 05:29:11 PM PDT 24
Finished Aug 09 05:29:12 PM PDT 24
Peak memory 207476 kb
Host smart-721123d3-ae1d-4bc4-a3c8-9505be1f41ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57719
43 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.5771943
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.55224926
Short name T1362
Test name
Test status
Simulation time 184054929 ps
CPU time 0.98 seconds
Started Aug 09 05:29:12 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207424 kb
Host smart-cf46589b-7a5d-44ba-b895-3ec3b2412048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55224
926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.55224926
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1096924324
Short name T2013
Test name
Test status
Simulation time 1138764616 ps
CPU time 2.82 seconds
Started Aug 09 05:29:06 PM PDT 24
Finished Aug 09 05:29:09 PM PDT 24
Peak memory 207696 kb
Host smart-9ca6f5aa-126f-410d-bbe8-8da1042da45d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1096924324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1096924324
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.1443311930
Short name T2657
Test name
Test status
Simulation time 2082024301 ps
CPU time 50.47 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207580 kb
Host smart-f6136bfd-5e38-4fdf-bb27-671d22a52f90
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443311930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1443311930
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2372661698
Short name T1937
Test name
Test status
Simulation time 662500750 ps
CPU time 1.71 seconds
Started Aug 09 05:29:24 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207360 kb
Host smart-68135fb9-eae3-4d7e-968f-87a39b6a2a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23726
61698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2372661698
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.445293388
Short name T2395
Test name
Test status
Simulation time 141349611 ps
CPU time 0.83 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207512 kb
Host smart-ae43f3a1-dd78-4a27-b49e-8a2486a0bb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44529
3388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.445293388
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.88044001
Short name T1689
Test name
Test status
Simulation time 79849509 ps
CPU time 0.78 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207380 kb
Host smart-909ce69b-0663-4314-b620-b467b53dae9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88044
001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.88044001
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2147630635
Short name T1102
Test name
Test status
Simulation time 904329815 ps
CPU time 2.54 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207664 kb
Host smart-7cc3976c-aec8-4906-a722-934022344abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
30635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2147630635
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.3613392236
Short name T454
Test name
Test status
Simulation time 287027988 ps
CPU time 1.08 seconds
Started Aug 09 05:29:23 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207452 kb
Host smart-e7b16d14-43d2-4c3d-9696-b9a2dd4d2c91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3613392236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3613392236
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2752424650
Short name T1352
Test name
Test status
Simulation time 201839569 ps
CPU time 1.49 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:27 PM PDT 24
Peak memory 207556 kb
Host smart-cd0ed123-53f7-4700-9a2f-48fdf11e72d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27524
24650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2752424650
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.923666805
Short name T3366
Test name
Test status
Simulation time 194492822 ps
CPU time 1.02 seconds
Started Aug 09 05:29:21 PM PDT 24
Finished Aug 09 05:29:22 PM PDT 24
Peak memory 215832 kb
Host smart-fa3b18b9-f9a0-4a9b-8e0a-d69ed2cc87f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=923666805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.923666805
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1907661549
Short name T772
Test name
Test status
Simulation time 143336315 ps
CPU time 0.81 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207428 kb
Host smart-a31c23ef-75f3-4b85-8036-e21c405cff0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
61549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1907661549
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3925788622
Short name T3094
Test name
Test status
Simulation time 174503438 ps
CPU time 0.87 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 207352 kb
Host smart-58d280a0-4505-4628-ad22-17cf19ba4b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
88622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3925788622
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.123934262
Short name T2259
Test name
Test status
Simulation time 4829632281 ps
CPU time 143.08 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:31:42 PM PDT 24
Peak memory 218484 kb
Host smart-21451669-0bf7-4c9a-a4ef-3f89cf066e71
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=123934262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.123934262
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.1720811024
Short name T2137
Test name
Test status
Simulation time 11952581557 ps
CPU time 81 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:30:40 PM PDT 24
Peak memory 207760 kb
Host smart-b424a577-a9cb-4ce4-a327-59964e2e3e30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1720811024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1720811024
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1441424373
Short name T585
Test name
Test status
Simulation time 190481399 ps
CPU time 0.94 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207548 kb
Host smart-8f697008-f6e9-4055-b409-9266df8eddca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14414
24373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1441424373
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2762038137
Short name T533
Test name
Test status
Simulation time 7459445271 ps
CPU time 10.92 seconds
Started Aug 09 05:29:10 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 216008 kb
Host smart-84f79a84-490c-48e6-af59-a0dcf4a1c63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
38137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2762038137
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1247265183
Short name T201
Test name
Test status
Simulation time 4964930399 ps
CPU time 6.76 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 207652 kb
Host smart-84d3b6d3-b978-4a08-a898-265411769cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12472
65183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1247265183
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3295673655
Short name T2969
Test name
Test status
Simulation time 4392055975 ps
CPU time 41.39 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 224188 kb
Host smart-ece537b8-0b8c-4621-8f54-ae6ad1fc916d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3295673655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3295673655
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.337568678
Short name T1705
Test name
Test status
Simulation time 1828083817 ps
CPU time 49.78 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 224128 kb
Host smart-9566c3a0-a4b1-488b-9c10-c00693c85315
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=337568678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.337568678
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.4286517032
Short name T3422
Test name
Test status
Simulation time 240446487 ps
CPU time 0.95 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207500 kb
Host smart-31ac6899-066c-40af-9f44-30dd4ee2a694
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4286517032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.4286517032
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3715970486
Short name T2892
Test name
Test status
Simulation time 185392271 ps
CPU time 0.93 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207500 kb
Host smart-a17854a9-a31e-4f98-9268-305a064bcc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159
70486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3715970486
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.352818716
Short name T631
Test name
Test status
Simulation time 3301677699 ps
CPU time 25.55 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 217796 kb
Host smart-7e7339ff-1400-4d45-8cf7-d6195574d91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
8716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.352818716
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2397976956
Short name T2069
Test name
Test status
Simulation time 3194899033 ps
CPU time 32.83 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:30:19 PM PDT 24
Peak memory 217748 kb
Host smart-8975673c-0814-462e-981a-7835e4dc0c71
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2397976956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2397976956
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.700734103
Short name T2963
Test name
Test status
Simulation time 166246168 ps
CPU time 0.85 seconds
Started Aug 09 05:29:29 PM PDT 24
Finished Aug 09 05:29:30 PM PDT 24
Peak memory 207536 kb
Host smart-ccd13e63-6d57-4032-85a4-7c947d61db82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=700734103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.700734103
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2578749707
Short name T1601
Test name
Test status
Simulation time 149721238 ps
CPU time 0.83 seconds
Started Aug 09 05:29:14 PM PDT 24
Finished Aug 09 05:29:15 PM PDT 24
Peak memory 207440 kb
Host smart-73eda65e-26bc-4e68-946d-aad62c08b408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
49707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2578749707
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2984023242
Short name T1329
Test name
Test status
Simulation time 183221080 ps
CPU time 0.97 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207504 kb
Host smart-6338674f-1f97-4788-bb34-17ae8d5708ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29840
23242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2984023242
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1173641867
Short name T2170
Test name
Test status
Simulation time 152528668 ps
CPU time 0.86 seconds
Started Aug 09 05:29:09 PM PDT 24
Finished Aug 09 05:29:10 PM PDT 24
Peak memory 207472 kb
Host smart-cb805cf7-e80f-4d41-b18f-3249639549ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11736
41867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1173641867
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2324653159
Short name T2156
Test name
Test status
Simulation time 193195624 ps
CPU time 0.95 seconds
Started Aug 09 05:29:15 PM PDT 24
Finished Aug 09 05:29:16 PM PDT 24
Peak memory 207788 kb
Host smart-c2fd5879-97e1-48ae-8e1a-125ddcd1322c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23246
53159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2324653159
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.975894229
Short name T2078
Test name
Test status
Simulation time 198097458 ps
CPU time 0.85 seconds
Started Aug 09 05:29:18 PM PDT 24
Finished Aug 09 05:29:19 PM PDT 24
Peak memory 207500 kb
Host smart-72d09c7e-8054-4695-a791-77130a290521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97589
4229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.975894229
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3734166387
Short name T963
Test name
Test status
Simulation time 195206312 ps
CPU time 1.03 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:29 PM PDT 24
Peak memory 207464 kb
Host smart-06646a86-7fa1-4630-bd56-bd2256f5c4c3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3734166387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3734166387
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3001271630
Short name T958
Test name
Test status
Simulation time 147496284 ps
CPU time 0.85 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207428 kb
Host smart-20213b4c-6906-4d0f-bc86-be56fc06bd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30012
71630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3001271630
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2497637265
Short name T3220
Test name
Test status
Simulation time 42687147 ps
CPU time 0.69 seconds
Started Aug 09 05:29:10 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 207344 kb
Host smart-f9118a18-36a1-4757-9648-12ace0f99a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
37265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2497637265
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.754574818
Short name T2112
Test name
Test status
Simulation time 11060986781 ps
CPU time 29.28 seconds
Started Aug 09 05:29:15 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 216124 kb
Host smart-4ba82e72-7178-4240-8b2f-e1eb18523b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75457
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.754574818
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.463556718
Short name T2482
Test name
Test status
Simulation time 220326032 ps
CPU time 0.98 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207396 kb
Host smart-caa925b8-a5d5-4d0d-8045-575c1e401e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46355
6718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.463556718
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3863277932
Short name T1215
Test name
Test status
Simulation time 224170813 ps
CPU time 0.93 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207516 kb
Host smart-09f23b89-2373-4b5d-929b-b522d8c8d342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
77932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3863277932
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3169496860
Short name T2644
Test name
Test status
Simulation time 175791350 ps
CPU time 0.9 seconds
Started Aug 09 05:29:27 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207472 kb
Host smart-5dd26106-6d0b-4b83-9c0f-9afc4f315a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
96860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3169496860
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3504995752
Short name T2995
Test name
Test status
Simulation time 215174133 ps
CPU time 0.97 seconds
Started Aug 09 05:29:36 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207384 kb
Host smart-17adbd24-cd0a-4e48-8e52-444ae933bfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35049
95752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3504995752
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1798542622
Short name T1043
Test name
Test status
Simulation time 176197888 ps
CPU time 0.92 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207548 kb
Host smart-07797aa0-8976-4cda-929e-7b1bf747fab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
42622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1798542622
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.287910366
Short name T695
Test name
Test status
Simulation time 154916284 ps
CPU time 0.9 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:29:18 PM PDT 24
Peak memory 207480 kb
Host smart-cfee8902-6f16-4b8e-a42c-732fa3ef98b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
0366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.287910366
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2238940034
Short name T578
Test name
Test status
Simulation time 172190808 ps
CPU time 0.84 seconds
Started Aug 09 05:29:18 PM PDT 24
Finished Aug 09 05:29:19 PM PDT 24
Peak memory 207452 kb
Host smart-67ecdd36-4f55-4455-a317-2bcae45d134e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22389
40034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2238940034
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2493755499
Short name T3237
Test name
Test status
Simulation time 241104341 ps
CPU time 1.24 seconds
Started Aug 09 05:29:24 PM PDT 24
Finished Aug 09 05:29:25 PM PDT 24
Peak memory 207444 kb
Host smart-d0536f67-3716-4b0f-b547-144d70def414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24937
55499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2493755499
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.656792748
Short name T1285
Test name
Test status
Simulation time 2060674311 ps
CPU time 16.49 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 217684 kb
Host smart-5892938e-2581-4d5d-96ac-97c0624269e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=656792748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.656792748
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2093878636
Short name T1299
Test name
Test status
Simulation time 154615374 ps
CPU time 0.96 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:20 PM PDT 24
Peak memory 207552 kb
Host smart-fe0f82e0-9adf-44c3-ac98-f0eb6d512059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20938
78636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2093878636
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3831084986
Short name T1268
Test name
Test status
Simulation time 189468543 ps
CPU time 0.89 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207500 kb
Host smart-7848c982-23d7-42aa-b59a-dc3627728954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38310
84986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3831084986
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.699534726
Short name T1397
Test name
Test status
Simulation time 1258071106 ps
CPU time 3.07 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207732 kb
Host smart-41ed9392-153d-46d5-8179-54f6b6dace19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69953
4726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.699534726
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2733298998
Short name T3495
Test name
Test status
Simulation time 2119777113 ps
CPU time 16.12 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207736 kb
Host smart-b58084d6-94e5-4b3e-aeec-32bdeeff239f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27332
98998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2733298998
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.1150956277
Short name T1336
Test name
Test status
Simulation time 2968388696 ps
CPU time 26.57 seconds
Started Aug 09 05:29:08 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207860 kb
Host smart-7c9c7821-6b54-4c22-ba30-cc423e381dd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150956277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.1150956277
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.958644869
Short name T1175
Test name
Test status
Simulation time 521482156 ps
CPU time 1.5 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207496 kb
Host smart-97bdebb7-12ca-46a2-bbff-e66a89f5dd28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958644869 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.958644869
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.3524530589
Short name T1871
Test name
Test status
Simulation time 496216914 ps
CPU time 1.58 seconds
Started Aug 09 05:33:26 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207388 kb
Host smart-b86dcd2f-021a-42a0-b7c4-3ab0c11eaf32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524530589 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.3524530589
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.3481215547
Short name T3589
Test name
Test status
Simulation time 540629445 ps
CPU time 1.49 seconds
Started Aug 09 05:33:38 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207460 kb
Host smart-b74dee9f-b5ab-4e2f-929c-8e08bd803e4d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481215547 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.3481215547
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.1906084101
Short name T1825
Test name
Test status
Simulation time 608285905 ps
CPU time 1.8 seconds
Started Aug 09 05:33:24 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 207512 kb
Host smart-5f90ab22-f3ab-4d37-a01d-7127718b1a26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906084101 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.1906084101
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.2765915833
Short name T3105
Test name
Test status
Simulation time 523895192 ps
CPU time 1.6 seconds
Started Aug 09 05:33:45 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207464 kb
Host smart-c3658dd9-82dd-47f5-b45e-f079b24d7ee4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765915833 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.2765915833
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.224999580
Short name T3004
Test name
Test status
Simulation time 492182582 ps
CPU time 1.49 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207460 kb
Host smart-433406af-cbdb-476a-9b32-e0168e62cb47
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224999580 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.224999580
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.1447329913
Short name T3564
Test name
Test status
Simulation time 564350829 ps
CPU time 1.63 seconds
Started Aug 09 05:33:40 PM PDT 24
Finished Aug 09 05:33:42 PM PDT 24
Peak memory 207460 kb
Host smart-f4ab89fa-3c44-4548-8ad5-7a6238a66e30
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447329913 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.1447329913
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.1893536849
Short name T999
Test name
Test status
Simulation time 485250425 ps
CPU time 1.44 seconds
Started Aug 09 05:33:23 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207512 kb
Host smart-9f243109-aee1-4114-b10a-e7517450d6c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893536849 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.1893536849
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.1835707366
Short name T1000
Test name
Test status
Simulation time 486456756 ps
CPU time 1.6 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 207460 kb
Host smart-638c23db-c10e-43b0-bea1-1f02ca202c2b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835707366 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.1835707366
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.2409818261
Short name T2479
Test name
Test status
Simulation time 505666131 ps
CPU time 1.58 seconds
Started Aug 09 05:33:35 PM PDT 24
Finished Aug 09 05:33:37 PM PDT 24
Peak memory 207440 kb
Host smart-fb5748e6-5fc7-4fc4-b026-53f6c1fcfc81
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409818261 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.2409818261
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.3786588114
Short name T182
Test name
Test status
Simulation time 496358632 ps
CPU time 1.47 seconds
Started Aug 09 05:33:27 PM PDT 24
Finished Aug 09 05:33:28 PM PDT 24
Peak memory 207488 kb
Host smart-e0d7e82d-aa73-427c-8885-5c446907abfc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786588114 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.3786588114
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1485841747
Short name T622
Test name
Test status
Simulation time 63557167 ps
CPU time 0.69 seconds
Started Aug 09 05:29:29 PM PDT 24
Finished Aug 09 05:29:30 PM PDT 24
Peak memory 207532 kb
Host smart-af34f340-0f44-45d3-bd5b-6a646e9a2bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1485841747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1485841747
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2795988283
Short name T2381
Test name
Test status
Simulation time 5503979385 ps
CPU time 7.49 seconds
Started Aug 09 05:29:17 PM PDT 24
Finished Aug 09 05:29:25 PM PDT 24
Peak memory 215992 kb
Host smart-cf3e176d-7922-40a9-9ec0-ff7c837aa80e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795988283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.2795988283
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2204383974
Short name T862
Test name
Test status
Simulation time 20427319234 ps
CPU time 22.42 seconds
Started Aug 09 05:29:33 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207660 kb
Host smart-3f721db2-1e71-4f02-9179-0ed25e77d151
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204383974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2204383974
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2928921417
Short name T1042
Test name
Test status
Simulation time 30945181987 ps
CPU time 45.94 seconds
Started Aug 09 05:29:29 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207752 kb
Host smart-76854713-a9f6-4c74-baeb-a52a15b1a8cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928921417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.2928921417
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.674492078
Short name T1385
Test name
Test status
Simulation time 166028290 ps
CPU time 0.88 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:29:27 PM PDT 24
Peak memory 207472 kb
Host smart-7a5402ea-93f1-4f0d-abd9-353c5a3a280d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67449
2078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.674492078
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.824579095
Short name T1126
Test name
Test status
Simulation time 155029700 ps
CPU time 0.86 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207496 kb
Host smart-db9f7283-336a-4762-a362-81bf7aa07e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82457
9095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.824579095
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.4057082024
Short name T2153
Test name
Test status
Simulation time 194591317 ps
CPU time 1 seconds
Started Aug 09 05:29:23 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207508 kb
Host smart-db2b9cbd-fdd5-4a89-880d-171ce01d5333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40570
82024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.4057082024
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2557783213
Short name T3273
Test name
Test status
Simulation time 974790927 ps
CPU time 2.59 seconds
Started Aug 09 05:29:19 PM PDT 24
Finished Aug 09 05:29:22 PM PDT 24
Peak memory 207680 kb
Host smart-2b4ad89f-26ff-425d-b8ab-722090523725
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2557783213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2557783213
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.22091576
Short name T233
Test name
Test status
Simulation time 16406913217 ps
CPU time 26.93 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207796 kb
Host smart-61b3b2b4-5886-4181-99f5-3b4c4075be03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.22091576
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.2833815564
Short name T3510
Test name
Test status
Simulation time 738580147 ps
CPU time 15.68 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207928 kb
Host smart-1b4e3bcb-f5af-497e-9568-adaaa2492009
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833815564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.2833815564
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3907638173
Short name T2983
Test name
Test status
Simulation time 837360077 ps
CPU time 1.95 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:30 PM PDT 24
Peak memory 207528 kb
Host smart-2caf0ae7-e0ac-4a66-8a16-9b82775c0638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39076
38173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3907638173
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3774669947
Short name T2084
Test name
Test status
Simulation time 150653607 ps
CPU time 0.83 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207472 kb
Host smart-08679d45-2d55-4b2c-a5d9-620b0effa524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37746
69947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3774669947
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.859442822
Short name T1664
Test name
Test status
Simulation time 37938353 ps
CPU time 0.7 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:31 PM PDT 24
Peak memory 207436 kb
Host smart-fe836d38-5af4-43d5-ac62-896fbcc97f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85944
2822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.859442822
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3216919330
Short name T724
Test name
Test status
Simulation time 963621905 ps
CPU time 2.42 seconds
Started Aug 09 05:29:40 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207704 kb
Host smart-c4f74790-84c1-4a69-96b6-d5f5736b50d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32169
19330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3216919330
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.1265574728
Short name T765
Test name
Test status
Simulation time 154357759 ps
CPU time 0.83 seconds
Started Aug 09 05:29:27 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207376 kb
Host smart-791788e9-a95c-49c0-8db4-7e1246b33552
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1265574728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.1265574728
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.195810063
Short name T2151
Test name
Test status
Simulation time 202097125 ps
CPU time 2.12 seconds
Started Aug 09 05:29:37 PM PDT 24
Finished Aug 09 05:29:40 PM PDT 24
Peak memory 207656 kb
Host smart-25a9bb96-9f09-4265-8445-acd521fbdae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
0063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.195810063
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.573977373
Short name T1022
Test name
Test status
Simulation time 168796388 ps
CPU time 0.94 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207780 kb
Host smart-bde3ede6-6cec-4642-aac5-98d10c357b33
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=573977373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.573977373
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.4205648008
Short name T2736
Test name
Test status
Simulation time 195569796 ps
CPU time 0.91 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:31 PM PDT 24
Peak memory 207476 kb
Host smart-42e0dfd2-6427-4f0b-a017-b44a22740a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42056
48008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.4205648008
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.233416217
Short name T3240
Test name
Test status
Simulation time 180069542 ps
CPU time 0.94 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:29 PM PDT 24
Peak memory 207792 kb
Host smart-4e3c6e65-8dc9-4dc0-a75c-e997fb51a3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341
6217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.233416217
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2543824023
Short name T2439
Test name
Test status
Simulation time 2535246006 ps
CPU time 19.17 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 224280 kb
Host smart-99568a82-0bbb-4afa-855d-d5cac5077c34
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2543824023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2543824023
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2003368562
Short name T2108
Test name
Test status
Simulation time 191251641 ps
CPU time 0.93 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207512 kb
Host smart-bf14b311-7bba-48b4-91a5-00083f9318c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
68562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2003368562
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.4249362452
Short name T1081
Test name
Test status
Simulation time 29727239883 ps
CPU time 45.59 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207672 kb
Host smart-1d0b6d0e-48b8-47eb-b0bf-a22f561c0ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
62452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.4249362452
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1724507085
Short name T40
Test name
Test status
Simulation time 9192480082 ps
CPU time 11.03 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 208084 kb
Host smart-904b86a9-457c-40d1-b905-d42fa8212f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
07085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1724507085
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3008691170
Short name T2664
Test name
Test status
Simulation time 2808049658 ps
CPU time 82.08 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 216072 kb
Host smart-2b75c8de-d81d-481d-bb3c-f311bba3948b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3008691170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3008691170
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.478030738
Short name T957
Test name
Test status
Simulation time 2939340512 ps
CPU time 84.1 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 215940 kb
Host smart-d915a3ec-8e8c-49ef-8c9c-9aaa0e64b5d3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=478030738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.478030738
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3138424023
Short name T1060
Test name
Test status
Simulation time 272958089 ps
CPU time 1.06 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207488 kb
Host smart-9b712e02-a910-47c5-b2cf-1410e4ad1824
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3138424023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3138424023
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3726329438
Short name T729
Test name
Test status
Simulation time 194692269 ps
CPU time 0.95 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207508 kb
Host smart-b2e4bc40-2cb1-48a5-8206-5da55cd9db9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
29438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3726329438
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.1192649374
Short name T3010
Test name
Test status
Simulation time 2609043297 ps
CPU time 73.85 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 216060 kb
Host smart-d66de74d-dd6c-422c-b43b-730e875cbf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
49374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.1192649374
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3772599236
Short name T187
Test name
Test status
Simulation time 2404778845 ps
CPU time 21.3 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 216012 kb
Host smart-bec4fd29-3698-4172-8e9f-dc60c19e532c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3772599236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3772599236
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.750942964
Short name T3352
Test name
Test status
Simulation time 154857221 ps
CPU time 0.88 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207496 kb
Host smart-7b06cdc3-5e67-4507-9fbe-afaadbbd113d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=750942964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.750942964
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3536618512
Short name T3275
Test name
Test status
Simulation time 140826210 ps
CPU time 0.86 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207504 kb
Host smart-9edb81ea-b360-4b9a-a6eb-34c4ac80bdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
18512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3536618512
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1399249719
Short name T135
Test name
Test status
Simulation time 197421509 ps
CPU time 0.9 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207464 kb
Host smart-b282eb42-9670-433c-b548-22b499538387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13992
49719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1399249719
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.4083672942
Short name T676
Test name
Test status
Simulation time 185383819 ps
CPU time 0.91 seconds
Started Aug 09 05:29:20 PM PDT 24
Finished Aug 09 05:29:21 PM PDT 24
Peak memory 207508 kb
Host smart-0539849d-b752-43e7-bb85-6bc98d4050d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
72942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.4083672942
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2420261121
Short name T1712
Test name
Test status
Simulation time 191316978 ps
CPU time 0.97 seconds
Started Aug 09 05:29:21 PM PDT 24
Finished Aug 09 05:29:22 PM PDT 24
Peak memory 207556 kb
Host smart-8061e360-dae7-47bf-b03c-d5a2618541c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
61121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2420261121
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2024411691
Short name T3191
Test name
Test status
Simulation time 175405033 ps
CPU time 0.86 seconds
Started Aug 09 05:29:25 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207596 kb
Host smart-f300279c-e240-4f80-ac1c-5ff82b6c9002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
11691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2024411691
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.158681498
Short name T1247
Test name
Test status
Simulation time 145503808 ps
CPU time 0.83 seconds
Started Aug 09 05:29:21 PM PDT 24
Finished Aug 09 05:29:22 PM PDT 24
Peak memory 207548 kb
Host smart-c7e5f724-35b5-489a-b299-5c942576b8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15868
1498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.158681498
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3724195907
Short name T2379
Test name
Test status
Simulation time 228559583 ps
CPU time 1.05 seconds
Started Aug 09 05:29:29 PM PDT 24
Finished Aug 09 05:29:30 PM PDT 24
Peak memory 207808 kb
Host smart-7fed61ab-b312-46f1-995b-d92ef6fa531c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3724195907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3724195907
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2049871662
Short name T2047
Test name
Test status
Simulation time 164709146 ps
CPU time 0.87 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 207352 kb
Host smart-9fd0ef76-1fd1-40f2-ae63-f950288147e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20498
71662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2049871662
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3178711462
Short name T1371
Test name
Test status
Simulation time 93455802 ps
CPU time 0.77 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207520 kb
Host smart-dd0d92b7-3724-42ae-801b-6561646ac0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787
11462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3178711462
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2998910107
Short name T1107
Test name
Test status
Simulation time 21638455396 ps
CPU time 51.18 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 220704 kb
Host smart-62ea783d-0771-4a7f-a52d-7e548410dcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29989
10107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2998910107
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2353446494
Short name T1572
Test name
Test status
Simulation time 248338342 ps
CPU time 0.98 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:24 PM PDT 24
Peak memory 207476 kb
Host smart-6afbf9b1-9432-4a09-aab4-2edd297a5431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
46494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2353446494
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.336387643
Short name T2849
Test name
Test status
Simulation time 248652691 ps
CPU time 1.03 seconds
Started Aug 09 05:29:24 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207548 kb
Host smart-69773e32-cf9e-4911-86c5-c855ac689c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33638
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.336387643
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2683836499
Short name T2815
Test name
Test status
Simulation time 231104982 ps
CPU time 1 seconds
Started Aug 09 05:29:37 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207444 kb
Host smart-e883bcf0-b93f-4fc8-a9e0-0fbcfecc6ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838
36499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2683836499
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2081165325
Short name T1809
Test name
Test status
Simulation time 182175812 ps
CPU time 0.93 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207484 kb
Host smart-5e9205a6-81a7-4328-b36e-371f8a6d23d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20811
65325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2081165325
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.7792505
Short name T616
Test name
Test status
Simulation time 205206207 ps
CPU time 0.93 seconds
Started Aug 09 05:29:32 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 207496 kb
Host smart-7c202278-7952-4899-b119-4425cad841d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77925
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.7792505
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.3860819263
Short name T2410
Test name
Test status
Simulation time 254302301 ps
CPU time 1.09 seconds
Started Aug 09 05:29:33 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207496 kb
Host smart-059e7854-ee13-4813-886d-549f168379bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
19263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.3860819263
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1456370338
Short name T839
Test name
Test status
Simulation time 153374281 ps
CPU time 0.88 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207496 kb
Host smart-937dec59-9334-4680-ae39-8cf5f4afd3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14563
70338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1456370338
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1191198749
Short name T2378
Test name
Test status
Simulation time 164959115 ps
CPU time 0.88 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207432 kb
Host smart-8acf00f2-2763-462c-9368-94ee92f7c48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
98749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1191198749
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.478031058
Short name T2116
Test name
Test status
Simulation time 205316131 ps
CPU time 1.02 seconds
Started Aug 09 05:29:27 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207560 kb
Host smart-03bf2a10-ca83-4b0e-ab12-f3b8e3424c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47803
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.478031058
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.773446919
Short name T1167
Test name
Test status
Simulation time 2107363803 ps
CPU time 60.66 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:30:33 PM PDT 24
Peak memory 217608 kb
Host smart-0b988bc1-ab60-4695-a913-b31f7a3ed7d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=773446919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.773446919
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3220812119
Short name T495
Test name
Test status
Simulation time 169045646 ps
CPU time 0.86 seconds
Started Aug 09 05:29:39 PM PDT 24
Finished Aug 09 05:29:40 PM PDT 24
Peak memory 207492 kb
Host smart-f9fb0701-67fb-439a-8d66-16f13c62b58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
12119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3220812119
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2078063326
Short name T2481
Test name
Test status
Simulation time 158611917 ps
CPU time 0.85 seconds
Started Aug 09 05:29:39 PM PDT 24
Finished Aug 09 05:29:40 PM PDT 24
Peak memory 207428 kb
Host smart-412c454a-050a-4d92-9096-fd87c2ac69af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20780
63326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2078063326
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.779963010
Short name T2998
Test name
Test status
Simulation time 633905214 ps
CPU time 1.98 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:29:55 PM PDT 24
Peak memory 207448 kb
Host smart-c89bc283-fe07-4c10-8226-7711c1ead3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77996
3010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.779963010
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.328848759
Short name T2556
Test name
Test status
Simulation time 1593851390 ps
CPU time 11.84 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207696 kb
Host smart-59946a02-0fd6-4629-b461-11c3560acaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
8759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.328848759
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.1606637668
Short name T2317
Test name
Test status
Simulation time 891382590 ps
CPU time 19.69 seconds
Started Aug 09 05:29:24 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207684 kb
Host smart-b2f91d00-7484-4773-bb27-144895c49490
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606637668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.1606637668
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.3743879495
Short name T2308
Test name
Test status
Simulation time 581303731 ps
CPU time 1.57 seconds
Started Aug 09 05:29:33 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207560 kb
Host smart-e8027e98-4470-4a7b-9880-4205ccd1e11a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743879495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.3743879495
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.2692420331
Short name T3514
Test name
Test status
Simulation time 510674456 ps
CPU time 1.47 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:44 PM PDT 24
Peak memory 207440 kb
Host smart-08c7ffb9-2a61-43a2-9f12-03b12c1b6b67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692420331 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.2692420331
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.2682933417
Short name T1686
Test name
Test status
Simulation time 561444301 ps
CPU time 1.56 seconds
Started Aug 09 05:33:40 PM PDT 24
Finished Aug 09 05:33:42 PM PDT 24
Peak memory 207464 kb
Host smart-f67da0a6-282b-469d-9ce8-2d47ee925a5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682933417 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.2682933417
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.3567947906
Short name T2760
Test name
Test status
Simulation time 475460435 ps
CPU time 1.52 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 207500 kb
Host smart-849748d8-da13-4fcc-8005-d7490df9a22d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567947906 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.3567947906
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.969363801
Short name T2990
Test name
Test status
Simulation time 648647303 ps
CPU time 1.74 seconds
Started Aug 09 05:33:40 PM PDT 24
Finished Aug 09 05:33:42 PM PDT 24
Peak memory 207444 kb
Host smart-806cf3c4-c8bc-4cfc-a51b-9f4814a6ab48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969363801 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.969363801
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.3157708128
Short name T618
Test name
Test status
Simulation time 484814415 ps
CPU time 1.39 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207392 kb
Host smart-fe61990d-8932-48c9-8dfb-fdcbd26fe13f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157708128 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.3157708128
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.2620856552
Short name T1332
Test name
Test status
Simulation time 602778501 ps
CPU time 1.75 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207412 kb
Host smart-9b15768a-a9e4-435c-b7be-4964f7a23adb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620856552 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.2620856552
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.3027260940
Short name T3608
Test name
Test status
Simulation time 635436259 ps
CPU time 1.85 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 206496 kb
Host smart-18e10fc6-ee98-4cc6-bd26-c77814075d44
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027260940 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.3027260940
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.3797968545
Short name T177
Test name
Test status
Simulation time 628720065 ps
CPU time 1.67 seconds
Started Aug 09 05:33:45 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207508 kb
Host smart-fcafe36d-d50e-4369-a39d-29bc77209d42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797968545 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.3797968545
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.1084424320
Short name T2708
Test name
Test status
Simulation time 466449761 ps
CPU time 1.54 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207408 kb
Host smart-bc6bafc0-dc59-4187-a148-607619ea3670
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084424320 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.1084424320
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1314046201
Short name T3299
Test name
Test status
Simulation time 33476213 ps
CPU time 0.65 seconds
Started Aug 09 05:29:50 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 207572 kb
Host smart-59c895d0-0663-4d94-8b0e-b423ccf6ab94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1314046201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1314046201
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1667492441
Short name T1503
Test name
Test status
Simulation time 9952833878 ps
CPU time 12.29 seconds
Started Aug 09 05:29:26 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207804 kb
Host smart-44709595-2526-4ecc-a6e0-e92bf0cb6a4f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667492441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.1667492441
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3619706286
Short name T2076
Test name
Test status
Simulation time 15126628703 ps
CPU time 17.91 seconds
Started Aug 09 05:29:52 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 216252 kb
Host smart-7ac4097a-552b-497c-8c70-d6ab14208810
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619706286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3619706286
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1104698021
Short name T1707
Test name
Test status
Simulation time 28899276323 ps
CPU time 36.27 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207732 kb
Host smart-00235c62-0700-4af2-9978-ab28f73b6260
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104698021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.1104698021
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2679793004
Short name T543
Test name
Test status
Simulation time 183639556 ps
CPU time 0.93 seconds
Started Aug 09 05:29:22 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 207552 kb
Host smart-2a0b20ef-fd8b-49b6-b67a-864eb56c80e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797
93004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2679793004
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2211865189
Short name T2118
Test name
Test status
Simulation time 143060463 ps
CPU time 0.85 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207556 kb
Host smart-3d13be76-4849-4054-987e-538876e58672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22118
65189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2211865189
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1979385915
Short name T639
Test name
Test status
Simulation time 422959776 ps
CPU time 1.53 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207412 kb
Host smart-9ff4b143-5bce-4a61-aa9d-6f7a650a1e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19793
85915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1979385915
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2156893764
Short name T2115
Test name
Test status
Simulation time 15531404638 ps
CPU time 22.95 seconds
Started Aug 09 05:29:32 PM PDT 24
Finished Aug 09 05:29:55 PM PDT 24
Peak memory 207852 kb
Host smart-848e2925-95f8-4627-a308-bc9779ab31a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
93764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2156893764
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.2261996413
Short name T1284
Test name
Test status
Simulation time 894406283 ps
CPU time 18.44 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207536 kb
Host smart-2fe02f7b-26b3-4541-8b1a-9005c35f8dfa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261996413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.2261996413
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.837656383
Short name T1667
Test name
Test status
Simulation time 477032010 ps
CPU time 1.41 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207328 kb
Host smart-c858e539-0c62-489e-8cc9-0460831e19e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83765
6383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.837656383
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.640514363
Short name T1843
Test name
Test status
Simulation time 133186883 ps
CPU time 0.8 seconds
Started Aug 09 05:29:28 PM PDT 24
Finished Aug 09 05:29:29 PM PDT 24
Peak memory 207464 kb
Host smart-d124a59c-8e7b-41e2-b7ff-e88356ddd4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64051
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.640514363
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1968232198
Short name T3077
Test name
Test status
Simulation time 79003917 ps
CPU time 0.74 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207440 kb
Host smart-ca749d3d-938b-4b2c-be14-e9bc93a8c7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
32198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1968232198
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2496093632
Short name T1575
Test name
Test status
Simulation time 612822932 ps
CPU time 1.86 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207676 kb
Host smart-2072df43-dafe-469b-b551-be744fd45a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
93632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2496093632
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.445703682
Short name T475
Test name
Test status
Simulation time 554657960 ps
CPU time 1.53 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207512 kb
Host smart-de0e82f4-55c5-460f-86d8-68933643bcda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=445703682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.445703682
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2295629739
Short name T1468
Test name
Test status
Simulation time 222442764 ps
CPU time 1.4 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207532 kb
Host smart-9c281cfd-6226-4f5d-bc64-0c7ee27a93de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
29739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2295629739
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3786377328
Short name T1131
Test name
Test status
Simulation time 231238818 ps
CPU time 1.07 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 215864 kb
Host smart-1b547e84-88e4-4006-a8ad-f2b5d96ebc36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3786377328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3786377328
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3807394753
Short name T3099
Test name
Test status
Simulation time 168572414 ps
CPU time 0.89 seconds
Started Aug 09 05:29:37 PM PDT 24
Finished Aug 09 05:29:38 PM PDT 24
Peak memory 207376 kb
Host smart-04e85318-6036-4d69-9d09-bd8ebe4fede8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
94753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3807394753
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2417245453
Short name T1864
Test name
Test status
Simulation time 227981749 ps
CPU time 1.01 seconds
Started Aug 09 05:29:27 PM PDT 24
Finished Aug 09 05:29:28 PM PDT 24
Peak memory 207556 kb
Host smart-ab862c49-0628-4473-b6a9-2c5eff752a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24172
45453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2417245453
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.2569165647
Short name T1711
Test name
Test status
Simulation time 3237439148 ps
CPU time 26.52 seconds
Started Aug 09 05:29:39 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 218696 kb
Host smart-52ca3a80-1216-4796-b563-6e8676b968de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2569165647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2569165647
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.2437687608
Short name T2842
Test name
Test status
Simulation time 14653851420 ps
CPU time 107.58 seconds
Started Aug 09 05:29:37 PM PDT 24
Finished Aug 09 05:31:24 PM PDT 24
Peak memory 207696 kb
Host smart-55a7b6be-0699-4732-b4b1-3a7749471876
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2437687608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2437687608
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3675745224
Short name T1064
Test name
Test status
Simulation time 231458254 ps
CPU time 0.99 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207456 kb
Host smart-777b5f12-1985-40a6-96aa-c3d7443d2065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36757
45224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3675745224
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.1950854472
Short name T3342
Test name
Test status
Simulation time 30601983920 ps
CPU time 46.94 seconds
Started Aug 09 05:29:23 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207852 kb
Host smart-ee53ea1a-d690-4db6-834b-1cdc391adc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
54472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.1950854472
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2949994302
Short name T2099
Test name
Test status
Simulation time 5560273071 ps
CPU time 8.4 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207848 kb
Host smart-d35ce652-3395-4a9b-b2fe-f98e592f40b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
94302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2949994302
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3405599487
Short name T1378
Test name
Test status
Simulation time 5091724819 ps
CPU time 43.46 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 219324 kb
Host smart-b2792ad9-166a-4da7-a530-759c2e8a61fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3405599487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3405599487
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3327127216
Short name T2563
Test name
Test status
Simulation time 2934895504 ps
CPU time 83.77 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 217544 kb
Host smart-5afe7fcd-4054-4009-88f9-60f11c3affc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3327127216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3327127216
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2430506686
Short name T1746
Test name
Test status
Simulation time 245072298 ps
CPU time 1.14 seconds
Started Aug 09 05:29:24 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207588 kb
Host smart-3a574ca5-fa92-4b90-86ce-312984dd1967
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2430506686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2430506686
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1877340612
Short name T1718
Test name
Test status
Simulation time 190857169 ps
CPU time 0.93 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207504 kb
Host smart-ebd4af6a-70e0-4e9d-a1d4-07f01bccd3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
40612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1877340612
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2690389828
Short name T2947
Test name
Test status
Simulation time 4422100950 ps
CPU time 44.98 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 217716 kb
Host smart-fa20bb0d-a6d4-4bd6-abdf-62d9ca41419e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2690389828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2690389828
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2903007485
Short name T2547
Test name
Test status
Simulation time 159984934 ps
CPU time 0.88 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207500 kb
Host smart-e3b349b7-6b98-4be2-b2c0-aca63ea9bde9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2903007485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2903007485
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.929909106
Short name T3194
Test name
Test status
Simulation time 149614212 ps
CPU time 0.82 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:29:42 PM PDT 24
Peak memory 207528 kb
Host smart-f4ac9c07-175c-4791-89f5-44c1af06d8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92990
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.929909106
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1650085647
Short name T1679
Test name
Test status
Simulation time 165873093 ps
CPU time 0.88 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207552 kb
Host smart-9b53093a-d9a1-4531-a795-a2c503479f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16500
85647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1650085647
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4014676046
Short name T1246
Test name
Test status
Simulation time 153457254 ps
CPU time 0.83 seconds
Started Aug 09 05:29:40 PM PDT 24
Finished Aug 09 05:29:41 PM PDT 24
Peak memory 207448 kb
Host smart-9cf8b111-bb33-47e5-b959-de48076c3887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40146
76046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4014676046
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.590765945
Short name T2374
Test name
Test status
Simulation time 171965825 ps
CPU time 0.91 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207508 kb
Host smart-49c495dd-c5ad-48f4-a185-59e912311e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59076
5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.590765945
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.959081152
Short name T184
Test name
Test status
Simulation time 151094000 ps
CPU time 0.89 seconds
Started Aug 09 05:29:36 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207556 kb
Host smart-8616ed29-61d7-4189-94ca-388a257fb1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95908
1152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.959081152
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2066174926
Short name T2181
Test name
Test status
Simulation time 230451130 ps
CPU time 1 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 207464 kb
Host smart-de26a5cb-f2fc-412a-bf46-b2c40c9049bf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2066174926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2066174926
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2564215795
Short name T3044
Test name
Test status
Simulation time 142011294 ps
CPU time 0.86 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207472 kb
Host smart-86ba280b-9fb5-4053-96e4-373a12fcd8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
15795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2564215795
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2114551900
Short name T1437
Test name
Test status
Simulation time 40603913 ps
CPU time 0.7 seconds
Started Aug 09 05:29:33 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207464 kb
Host smart-16cc1c93-0362-48ba-b8db-02ebd36315b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21145
51900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2114551900
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.111069834
Short name T267
Test name
Test status
Simulation time 21694712730 ps
CPU time 53.93 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 215932 kb
Host smart-cb7096a5-abb6-433f-afc6-a7632c59912d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
9834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.111069834
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.612834534
Short name T2537
Test name
Test status
Simulation time 207191037 ps
CPU time 1.01 seconds
Started Aug 09 05:29:36 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207524 kb
Host smart-7c98c86f-48f4-4f81-880d-fe16692807f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61283
4534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.612834534
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3055708772
Short name T1640
Test name
Test status
Simulation time 190751014 ps
CPU time 0.93 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207472 kb
Host smart-40400424-0d94-4c75-9918-9ea281e2acbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
08772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3055708772
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.275329717
Short name T3616
Test name
Test status
Simulation time 168908718 ps
CPU time 0.87 seconds
Started Aug 09 05:29:33 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207556 kb
Host smart-cc5821c4-5132-486f-8be7-e608fedb040e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
9717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.275329717
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1758068153
Short name T3167
Test name
Test status
Simulation time 233921817 ps
CPU time 1.04 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207528 kb
Host smart-55e17c4a-59e0-4ce2-8e09-1c88b1e7ae90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580
68153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1758068153
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1193629564
Short name T2138
Test name
Test status
Simulation time 153064565 ps
CPU time 0.78 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:32 PM PDT 24
Peak memory 207400 kb
Host smart-6265e60a-5b6c-48f9-9724-aed85e4108db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
29564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1193629564
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.3624932683
Short name T304
Test name
Test status
Simulation time 284587806 ps
CPU time 1.1 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207552 kb
Host smart-68a3bf36-aaec-4cc6-80fb-94c5f3bba45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
32683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.3624932683
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1580441550
Short name T807
Test name
Test status
Simulation time 150878733 ps
CPU time 0.81 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207524 kb
Host smart-7571c0f2-eb19-49e3-932c-7778815e0743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15804
41550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1580441550
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2072993828
Short name T1591
Test name
Test status
Simulation time 160549332 ps
CPU time 0.87 seconds
Started Aug 09 05:29:37 PM PDT 24
Finished Aug 09 05:29:38 PM PDT 24
Peak memory 207496 kb
Host smart-300cf5c9-3600-4b25-a9bd-ae525782c2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
93828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2072993828
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1836199548
Short name T1162
Test name
Test status
Simulation time 193208036 ps
CPU time 0.91 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207472 kb
Host smart-19c3b7bc-a7d3-4845-a96b-464e9765ba41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361
99548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1836199548
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.782779096
Short name T2081
Test name
Test status
Simulation time 3517048448 ps
CPU time 101.19 seconds
Started Aug 09 05:29:32 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 217864 kb
Host smart-7e4c8814-5df5-490d-9fa2-b5a4e781b183
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=782779096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.782779096
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3345482583
Short name T1824
Test name
Test status
Simulation time 193862332 ps
CPU time 0.94 seconds
Started Aug 09 05:29:36 PM PDT 24
Finished Aug 09 05:29:37 PM PDT 24
Peak memory 207496 kb
Host smart-7bde23a4-b02f-45aa-bc0f-24581a345205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33454
82583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3345482583
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.316401866
Short name T2471
Test name
Test status
Simulation time 229824145 ps
CPU time 0.94 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207504 kb
Host smart-1e32f410-7ee8-4eff-9688-0e9a800d9b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31640
1866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.316401866
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2588985730
Short name T2316
Test name
Test status
Simulation time 589545146 ps
CPU time 1.65 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:33 PM PDT 24
Peak memory 207472 kb
Host smart-b7fb9f16-fb84-434b-8bd8-6a83f5dc82e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
85730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2588985730
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2868194329
Short name T1958
Test name
Test status
Simulation time 3721150814 ps
CPU time 39.66 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 216052 kb
Host smart-86507126-05e6-4988-9b7e-ad2055c8ff2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28681
94329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2868194329
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.2127682386
Short name T1339
Test name
Test status
Simulation time 5018335377 ps
CPU time 31.94 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207812 kb
Host smart-e538fd38-a3af-4c83-a6aa-e9f8e70ac5fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127682386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.2127682386
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.2479070211
Short name T3463
Test name
Test status
Simulation time 525150278 ps
CPU time 1.7 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207496 kb
Host smart-3ec86b3d-8bdf-469e-b44d-3cf7206935e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479070211 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.2479070211
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.3726875585
Short name T2641
Test name
Test status
Simulation time 576468975 ps
CPU time 1.64 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 206492 kb
Host smart-57f42012-3c12-4191-a606-da17243e8c26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726875585 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.3726875585
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.1959445375
Short name T2322
Test name
Test status
Simulation time 648622979 ps
CPU time 1.73 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:35 PM PDT 24
Peak memory 207480 kb
Host smart-3850ef97-8e68-4296-8e2b-92c57e5eeff8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959445375 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.1959445375
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.343784048
Short name T2554
Test name
Test status
Simulation time 580000458 ps
CPU time 1.72 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:47 PM PDT 24
Peak memory 207440 kb
Host smart-58c1a20a-bf4d-4ee3-934a-dceea82f615e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343784048 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.343784048
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.385182142
Short name T2121
Test name
Test status
Simulation time 546470039 ps
CPU time 1.52 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207464 kb
Host smart-29092bf2-e6fc-4412-bd80-0232555a1f9b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385182142 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.385182142
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.2885800158
Short name T2578
Test name
Test status
Simulation time 645568443 ps
CPU time 1.63 seconds
Started Aug 09 05:33:38 PM PDT 24
Finished Aug 09 05:33:40 PM PDT 24
Peak memory 207364 kb
Host smart-035405e3-0d89-4eb2-8f5e-6f38374662c8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885800158 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.2885800158
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.1718354526
Short name T3552
Test name
Test status
Simulation time 535144742 ps
CPU time 1.57 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207532 kb
Host smart-87cae90d-2fbf-4d55-84aa-152aa05de383
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718354526 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.1718354526
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.205192227
Short name T3163
Test name
Test status
Simulation time 632199518 ps
CPU time 1.71 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207564 kb
Host smart-29071272-2432-4790-b9c7-55eafd832a34
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205192227 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.205192227
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.1455677417
Short name T707
Test name
Test status
Simulation time 597250764 ps
CPU time 1.7 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207440 kb
Host smart-83ce28d7-fb53-4908-b627-9a41602330a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455677417 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.1455677417
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.1520787623
Short name T2829
Test name
Test status
Simulation time 463507459 ps
CPU time 1.45 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207392 kb
Host smart-18d9d1b4-5c7f-4889-8446-55b28e59988d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520787623 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.1520787623
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.556961394
Short name T956
Test name
Test status
Simulation time 45556386 ps
CPU time 0.66 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207400 kb
Host smart-8016f392-753f-45c0-b25c-c70b5240e524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=556961394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.556961394
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3431840680
Short name T895
Test name
Test status
Simulation time 10981042202 ps
CPU time 13.63 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207800 kb
Host smart-893bf336-0821-46bd-9417-8353e79cdaa5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431840680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.3431840680
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3687457363
Short name T12
Test name
Test status
Simulation time 15205292530 ps
CPU time 18.28 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:53 PM PDT 24
Peak memory 215892 kb
Host smart-00c8ed8e-5450-4c2d-9107-ea40511791d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687457363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3687457363
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.436305595
Short name T1383
Test name
Test status
Simulation time 26493145121 ps
CPU time 31.76 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 215960 kb
Host smart-837db3e9-34ab-439f-a564-9560d81014d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436305595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_resume.436305595
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3715116405
Short name T1149
Test name
Test status
Simulation time 199099210 ps
CPU time 0.9 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207432 kb
Host smart-a133a6e4-4f07-413e-bead-9d2d350ebfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37151
16405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3715116405
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.956125250
Short name T2385
Test name
Test status
Simulation time 157594760 ps
CPU time 0.9 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207532 kb
Host smart-7da994de-f46c-444e-938e-26bd91918578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95612
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.956125250
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.1036138329
Short name T2850
Test name
Test status
Simulation time 491938203 ps
CPU time 1.49 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207508 kb
Host smart-df3122fd-a7b2-4927-91de-d23d315945e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361
38329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.1036138329
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1129076007
Short name T315
Test name
Test status
Simulation time 608830803 ps
CPU time 1.77 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207464 kb
Host smart-bdc1944e-d15a-4985-a3f0-49e94757d636
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1129076007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1129076007
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1624329255
Short name T2734
Test name
Test status
Simulation time 17546193151 ps
CPU time 29.61 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207812 kb
Host smart-6b86761a-aaa8-4cfe-bcdd-40e168d96f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16243
29255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1624329255
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3186085477
Short name T1148
Test name
Test status
Simulation time 986294231 ps
CPU time 23.74 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:59 PM PDT 24
Peak memory 207576 kb
Host smart-f1ca9647-7b7e-4c35-a14b-9a20727f4f8f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186085477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3186085477
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.4248456791
Short name T393
Test name
Test status
Simulation time 812446835 ps
CPU time 1.95 seconds
Started Aug 09 05:29:32 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207476 kb
Host smart-3ec83214-79bb-4b36-a7ac-0fdd5e404391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42484
56791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.4248456791
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.120437981
Short name T3228
Test name
Test status
Simulation time 142449184 ps
CPU time 0.79 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207440 kb
Host smart-3ad2da1e-52e4-44d9-b886-20c2ba6cd94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.120437981
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2676794926
Short name T2292
Test name
Test status
Simulation time 29858451 ps
CPU time 0.72 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207344 kb
Host smart-341f5b23-7e7c-4668-a60c-6de970063e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
94926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2676794926
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.172945053
Short name T3259
Test name
Test status
Simulation time 835537331 ps
CPU time 2.31 seconds
Started Aug 09 05:29:31 PM PDT 24
Finished Aug 09 05:29:34 PM PDT 24
Peak memory 207608 kb
Host smart-4c6d22aa-9c07-404b-88fd-da49742e26ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17294
5053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.172945053
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.81538012
Short name T2626
Test name
Test status
Simulation time 152169767 ps
CPU time 0.9 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207488 kb
Host smart-758d3d12-4351-4595-bc31-4ecc12790980
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=81538012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.81538012
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.662683713
Short name T1402
Test name
Test status
Simulation time 187591978 ps
CPU time 2.23 seconds
Started Aug 09 05:29:40 PM PDT 24
Finished Aug 09 05:29:42 PM PDT 24
Peak memory 207612 kb
Host smart-e4712a7f-4d52-4a67-9e79-bdd8ab12d0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66268
3713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.662683713
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.4121549334
Short name T30
Test name
Test status
Simulation time 238661592 ps
CPU time 1.31 seconds
Started Aug 09 05:29:50 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 215752 kb
Host smart-cd66db2c-455f-4bd3-a4a2-bca21ec73105
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4121549334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.4121549334
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3936366304
Short name T2600
Test name
Test status
Simulation time 136677863 ps
CPU time 0.79 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207472 kb
Host smart-606526fa-4948-4156-961c-3a36ee96a63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
66304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3936366304
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1373171649
Short name T2878
Test name
Test status
Simulation time 213770004 ps
CPU time 1 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:29:50 PM PDT 24
Peak memory 207432 kb
Host smart-4b6620d7-bb8c-429e-ba14-18694ebe0081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
71649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1373171649
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1223082870
Short name T1675
Test name
Test status
Simulation time 4022652782 ps
CPU time 30.69 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 218452 kb
Host smart-3d33afab-51a6-4d62-ae3b-560f5d819979
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1223082870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1223082870
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.1551587254
Short name T3418
Test name
Test status
Simulation time 3704116671 ps
CPU time 44.8 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207652 kb
Host smart-60897ff2-ff83-4db7-a6af-013da461c91a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1551587254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.1551587254
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.4015091969
Short name T2799
Test name
Test status
Simulation time 239229507 ps
CPU time 1.03 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207428 kb
Host smart-854af5f8-a283-4938-a668-c115b0925fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40150
91969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.4015091969
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1294829315
Short name T927
Test name
Test status
Simulation time 5710500927 ps
CPU time 8.84 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 216052 kb
Host smart-c82cfe9c-8849-48e0-acbb-240ca4b10808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12948
29315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1294829315
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1261208540
Short name T2898
Test name
Test status
Simulation time 3374086226 ps
CPU time 32.32 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 217516 kb
Host smart-f0ff4ec6-8398-4e9f-8b24-f577ad22ac49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1261208540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1261208540
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1728122735
Short name T3340
Test name
Test status
Simulation time 1619584755 ps
CPU time 44.35 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:30:35 PM PDT 24
Peak memory 224376 kb
Host smart-60942a63-a3de-49ae-babe-6b0eec820d2a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1728122735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1728122735
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.194411533
Short name T934
Test name
Test status
Simulation time 279855238 ps
CPU time 0.99 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207392 kb
Host smart-c4b785b8-c80c-4a49-9173-0b96bb5d5991
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=194411533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.194411533
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1760568547
Short name T1172
Test name
Test status
Simulation time 190646816 ps
CPU time 0.96 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207432 kb
Host smart-aaf9dddf-9df8-4106-bff8-5a790c9856ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17605
68547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1760568547
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.903938002
Short name T681
Test name
Test status
Simulation time 2463173139 ps
CPU time 25.58 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 224180 kb
Host smart-3cd65da2-1059-4ff8-9bfa-9c61c948d555
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=903938002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.903938002
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3130638903
Short name T1129
Test name
Test status
Simulation time 150556243 ps
CPU time 0.86 seconds
Started Aug 09 05:29:34 PM PDT 24
Finished Aug 09 05:29:35 PM PDT 24
Peak memory 207520 kb
Host smart-4f641aff-80cb-450e-871e-a4c5d7e22ffc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3130638903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3130638903
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1879425557
Short name T690
Test name
Test status
Simulation time 218973854 ps
CPU time 0.91 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:29:50 PM PDT 24
Peak memory 207592 kb
Host smart-3b931724-d022-4f31-a2b0-daa773ee4f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18794
25557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1879425557
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3124917839
Short name T119
Test name
Test status
Simulation time 214868828 ps
CPU time 0.96 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207376 kb
Host smart-3f5d004e-34d7-4329-a10f-c88ef7b49041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249
17839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3124917839
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2443371304
Short name T3316
Test name
Test status
Simulation time 168535587 ps
CPU time 0.91 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207472 kb
Host smart-3ebee4cb-f17c-4da4-91ba-7bd8e6b47a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24433
71304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2443371304
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2024829571
Short name T2205
Test name
Test status
Simulation time 205424207 ps
CPU time 0.91 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207432 kb
Host smart-4bae729d-225a-4c7f-9443-5e6164f03b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20248
29571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2024829571
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2256768024
Short name T3517
Test name
Test status
Simulation time 216173474 ps
CPU time 0.93 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 207496 kb
Host smart-0c3df64c-f699-4554-a42f-affe32da4641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22567
68024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2256768024
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2369176070
Short name T2261
Test name
Test status
Simulation time 178570163 ps
CPU time 0.88 seconds
Started Aug 09 05:29:52 PM PDT 24
Finished Aug 09 05:29:53 PM PDT 24
Peak memory 207428 kb
Host smart-002b1a1f-3343-4740-a6ce-1587b2999321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
76070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2369176070
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2911368830
Short name T1333
Test name
Test status
Simulation time 243713974 ps
CPU time 1.08 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207428 kb
Host smart-1223750d-752f-4e45-bb5c-f6c9af51240f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2911368830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2911368830
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3617531763
Short name T2884
Test name
Test status
Simulation time 149911786 ps
CPU time 0.83 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:29:44 PM PDT 24
Peak memory 207520 kb
Host smart-86a3c905-85e9-4c28-b33c-1b664fa6413d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
31763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3617531763
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2047041398
Short name T1420
Test name
Test status
Simulation time 88144481 ps
CPU time 0.78 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207320 kb
Host smart-316702a4-bec4-4878-9d9c-927eb29128dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470
41398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2047041398
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1140374013
Short name T740
Test name
Test status
Simulation time 7077644857 ps
CPU time 18.24 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 216020 kb
Host smart-eac83fd0-c2d1-4864-ae6a-a0c7e10946bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11403
74013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1140374013
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.4223109506
Short name T2264
Test name
Test status
Simulation time 186215938 ps
CPU time 0.9 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207484 kb
Host smart-0b6f2609-a121-4860-99b7-cc2d1c6049ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42231
09506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4223109506
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2505176161
Short name T1681
Test name
Test status
Simulation time 215530773 ps
CPU time 0.97 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207552 kb
Host smart-a38ce36e-3bbc-4648-8533-449393cfdbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
76161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2505176161
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.272344642
Short name T621
Test name
Test status
Simulation time 241663782 ps
CPU time 0.94 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207408 kb
Host smart-9fedd8cf-5053-4b33-b893-a71c8c37b4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
4642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.272344642
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.385916479
Short name T3320
Test name
Test status
Simulation time 162925018 ps
CPU time 0.85 seconds
Started Aug 09 05:29:39 PM PDT 24
Finished Aug 09 05:29:39 PM PDT 24
Peak memory 207488 kb
Host smart-2daf0523-5eb5-4ce1-8bde-ca53bbdcfc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38591
6479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.385916479
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3761284307
Short name T966
Test name
Test status
Simulation time 131623548 ps
CPU time 0.87 seconds
Started Aug 09 05:29:35 PM PDT 24
Finished Aug 09 05:29:36 PM PDT 24
Peak memory 207404 kb
Host smart-015af81c-6910-4b74-a369-86b3dbfe622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37612
84307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3761284307
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.4035954240
Short name T2976
Test name
Test status
Simulation time 249623771 ps
CPU time 1.1 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207448 kb
Host smart-35d29abc-27e8-40b1-a082-dfbde01ab43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
54240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.4035954240
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2728677129
Short name T1098
Test name
Test status
Simulation time 160882127 ps
CPU time 0.84 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207524 kb
Host smart-aafe2764-d8d9-446f-a91b-4e931da647ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27286
77129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2728677129
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1717018554
Short name T1735
Test name
Test status
Simulation time 163592613 ps
CPU time 0.88 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207552 kb
Host smart-d2d9d577-7ee8-49e5-9bb1-ddc893fde95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17170
18554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1717018554
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1414273425
Short name T666
Test name
Test status
Simulation time 221893748 ps
CPU time 1.07 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207436 kb
Host smart-3a18dae3-ddbc-4ac7-a043-933ae1ec0f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
73425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1414273425
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1255006990
Short name T977
Test name
Test status
Simulation time 2232051115 ps
CPU time 21.93 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 217920 kb
Host smart-8f7d4eeb-2678-43b6-b81d-2170279d8f5f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1255006990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1255006990
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1565867606
Short name T1567
Test name
Test status
Simulation time 191794436 ps
CPU time 0.93 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207424 kb
Host smart-55c39f1f-ae56-44a0-a4d2-3f70f9368015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15658
67606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1565867606
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1661667330
Short name T2880
Test name
Test status
Simulation time 160411438 ps
CPU time 0.89 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207372 kb
Host smart-d9818a6e-aaf9-4490-9ebc-e8dcda8736cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16616
67330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1661667330
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3449212648
Short name T2986
Test name
Test status
Simulation time 1292827525 ps
CPU time 2.75 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 207644 kb
Host smart-91ef8244-e521-41bb-b083-cbaba370de88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
12648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3449212648
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.258751409
Short name T1694
Test name
Test status
Simulation time 2418547953 ps
CPU time 17.08 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 217592 kb
Host smart-55a6bfe5-45f4-429a-8f27-c975cda896dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25875
1409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.258751409
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.831172331
Short name T1819
Test name
Test status
Simulation time 1581043128 ps
CPU time 9.99 seconds
Started Aug 09 05:29:30 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207676 kb
Host smart-194cd1fa-de3a-4944-ad94-a7b4618e9cd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831172331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_host
_handshake.831172331
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.2865620061
Short name T762
Test name
Test status
Simulation time 496271324 ps
CPU time 1.44 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207532 kb
Host smart-74bfc5ea-027a-4dc4-ad8d-7b059edff852
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865620061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.2865620061
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.2783646617
Short name T2185
Test name
Test status
Simulation time 627278346 ps
CPU time 1.68 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207564 kb
Host smart-66e43e13-d6c1-4436-98a1-ec0091a033d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783646617 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.2783646617
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.1510093225
Short name T3462
Test name
Test status
Simulation time 458386531 ps
CPU time 1.46 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207516 kb
Host smart-990a2989-bd34-48e4-a253-6082669f6924
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510093225 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.1510093225
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.3760560958
Short name T3325
Test name
Test status
Simulation time 624494617 ps
CPU time 1.7 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207392 kb
Host smart-040a22cb-a603-417b-b80d-3249db7b5a01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760560958 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.3760560958
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.3159344206
Short name T2586
Test name
Test status
Simulation time 549143011 ps
CPU time 1.56 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207560 kb
Host smart-c2aa3ca6-dcef-4090-8170-ea33d807f4ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159344206 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.3159344206
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.1605723923
Short name T1999
Test name
Test status
Simulation time 560950333 ps
CPU time 1.57 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207408 kb
Host smart-8c9ec1fa-7ac7-449c-bb5e-0104337a64f5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605723923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.1605723923
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.4286319682
Short name T3596
Test name
Test status
Simulation time 492052257 ps
CPU time 1.45 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207508 kb
Host smart-f0faba4e-e607-4bdc-8b2c-43eefb3d40af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286319682 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.4286319682
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.1924092884
Short name T1546
Test name
Test status
Simulation time 526690600 ps
CPU time 1.66 seconds
Started Aug 09 05:33:47 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207600 kb
Host smart-65d4f240-ca91-4bd5-a7d4-4e02c6699b43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924092884 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.1924092884
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.1923142109
Short name T1094
Test name
Test status
Simulation time 623720308 ps
CPU time 1.73 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207560 kb
Host smart-8b2ca31c-67b8-478e-9689-e0d8512ef267
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923142109 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.1923142109
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.1200922711
Short name T1753
Test name
Test status
Simulation time 494612696 ps
CPU time 1.57 seconds
Started Aug 09 05:33:35 PM PDT 24
Finished Aug 09 05:33:37 PM PDT 24
Peak memory 207448 kb
Host smart-2cf524a7-141f-4f76-9a16-6934413aa45f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200922711 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.1200922711
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.928631970
Short name T1310
Test name
Test status
Simulation time 672780495 ps
CPU time 1.78 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207508 kb
Host smart-d22e174a-a086-4bce-9aae-3320f19c82bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928631970 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.928631970
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3023419506
Short name T2463
Test name
Test status
Simulation time 49523698 ps
CPU time 0.71 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207480 kb
Host smart-fdd94693-aba0-4ddc-9872-8a76f4b7cbe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3023419506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3023419506
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3534864214
Short name T3470
Test name
Test status
Simulation time 11026231616 ps
CPU time 16.69 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:29:59 PM PDT 24
Peak memory 207796 kb
Host smart-f64c91fc-9b65-4900-a7d1-86f58f6721f6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534864214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.3534864214
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.192902545
Short name T2344
Test name
Test status
Simulation time 16084473288 ps
CPU time 21.49 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 215888 kb
Host smart-5c0a9295-cf0f-48e2-a061-0fb13a04ed31
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=192902545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.192902545
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3311854673
Short name T9
Test name
Test status
Simulation time 25949897968 ps
CPU time 31.14 seconds
Started Aug 09 05:29:43 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 215836 kb
Host smart-f8018516-246d-4617-bfd7-c0da3dd4c1b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311854673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3311854673
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2770758432
Short name T2217
Test name
Test status
Simulation time 164810900 ps
CPU time 0.88 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207432 kb
Host smart-817015fb-af0f-4d54-8272-2208cb563bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27707
58432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2770758432
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1212471698
Short name T2519
Test name
Test status
Simulation time 163192007 ps
CPU time 0.87 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207380 kb
Host smart-5a415d7b-4860-46ad-a219-114cbc97b7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
71698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1212471698
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1527075764
Short name T2215
Test name
Test status
Simulation time 285927063 ps
CPU time 1.22 seconds
Started Aug 09 05:29:50 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 207552 kb
Host smart-852575e1-dad4-42f1-9bab-7d765e311f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270
75764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1527075764
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.727773495
Short name T314
Test name
Test status
Simulation time 1182207803 ps
CPU time 2.74 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:51 PM PDT 24
Peak memory 207764 kb
Host smart-4cbfb12a-c039-413c-bec8-ad181fa0b7ec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=727773495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.727773495
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2650533346
Short name T3570
Test name
Test status
Simulation time 24740968533 ps
CPU time 40.34 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207724 kb
Host smart-ae6fc6e1-a130-4682-8b4e-cf7da4164c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
33346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2650533346
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.2632124883
Short name T1124
Test name
Test status
Simulation time 162268034 ps
CPU time 0.87 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 207396 kb
Host smart-c1441fa4-8f3c-4218-b7e8-e93d358e97b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632124883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.2632124883
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3270945685
Short name T1647
Test name
Test status
Simulation time 915121014 ps
CPU time 2.05 seconds
Started Aug 09 05:29:38 PM PDT 24
Finished Aug 09 05:29:40 PM PDT 24
Peak memory 207400 kb
Host smart-a13e986a-4872-44cb-a6a8-5e0456323b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
45685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3270945685
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1727982387
Short name T1528
Test name
Test status
Simulation time 136086210 ps
CPU time 0.8 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207324 kb
Host smart-426d94ca-465a-4ac3-aa3d-fd571f6af2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17279
82387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1727982387
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1743115610
Short name T944
Test name
Test status
Simulation time 51675852 ps
CPU time 0.71 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207472 kb
Host smart-a20e92b9-0ac9-4e05-a3db-eb910a7db0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
15610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1743115610
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3594255469
Short name T3192
Test name
Test status
Simulation time 915785763 ps
CPU time 2.32 seconds
Started Aug 09 05:29:39 PM PDT 24
Finished Aug 09 05:29:42 PM PDT 24
Peak memory 207612 kb
Host smart-5503db4b-5da2-479b-a4c7-48b57eb6076e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35942
55469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3594255469
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.2252840921
Short name T487
Test name
Test status
Simulation time 413010171 ps
CPU time 1.32 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207392 kb
Host smart-bc5b2a00-5d32-44ef-9553-90a7dae6f0a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2252840921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.2252840921
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2785927020
Short name T1973
Test name
Test status
Simulation time 195004995 ps
CPU time 2.46 seconds
Started Aug 09 05:29:54 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207572 kb
Host smart-391f9025-c457-43f8-bd62-9f212b690d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
27020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2785927020
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3467404141
Short name T1524
Test name
Test status
Simulation time 243551702 ps
CPU time 1.3 seconds
Started Aug 09 05:29:41 PM PDT 24
Finished Aug 09 05:29:42 PM PDT 24
Peak memory 215872 kb
Host smart-f78beab4-0418-4e21-bbde-d529c9ce86dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3467404141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3467404141
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2851042657
Short name T1697
Test name
Test status
Simulation time 142951534 ps
CPU time 0.8 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207324 kb
Host smart-1565511d-516d-4892-bcc0-0632a6eda2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
42657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2851042657
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.613796104
Short name T3453
Test name
Test status
Simulation time 202832444 ps
CPU time 0.94 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207476 kb
Host smart-a95fe114-3b28-4b6e-90be-d6fdae0cca05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61379
6104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.613796104
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1498673626
Short name T3086
Test name
Test status
Simulation time 2852618192 ps
CPU time 28.15 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 216020 kb
Host smart-5f0157ba-5461-4b31-bde4-753305e6d359
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1498673626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1498673626
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.978075298
Short name T1045
Test name
Test status
Simulation time 13436297971 ps
CPU time 88.7 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207668 kb
Host smart-8de7dbfe-c9c4-4ac1-9604-d03fe581c33f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=978075298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.978075298
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.437981687
Short name T1520
Test name
Test status
Simulation time 217307351 ps
CPU time 0.92 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207556 kb
Host smart-8d0bac18-7bc7-41f7-a850-ced81e552b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43798
1687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.437981687
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3105061555
Short name T64
Test name
Test status
Simulation time 28756485720 ps
CPU time 44.56 seconds
Started Aug 09 05:30:00 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 216016 kb
Host smart-2b1a42bc-3d62-4bdc-a341-a5954c87c664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31050
61555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3105061555
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.309162143
Short name T3211
Test name
Test status
Simulation time 6191349584 ps
CPU time 8.31 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:55 PM PDT 24
Peak memory 216128 kb
Host smart-e14a2dc2-9106-4c06-a033-19e4066945a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
2143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.309162143
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3434979149
Short name T886
Test name
Test status
Simulation time 2726886705 ps
CPU time 28.21 seconds
Started Aug 09 05:30:00 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 224140 kb
Host smart-1556f5a8-f641-410a-8ab6-f914661add1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3434979149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3434979149
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.548740568
Short name T1687
Test name
Test status
Simulation time 3396856496 ps
CPU time 25.07 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 215940 kb
Host smart-796cc94a-d479-4c07-a835-9b43d01898c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=548740568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.548740568
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2100465332
Short name T1565
Test name
Test status
Simulation time 237794693 ps
CPU time 0.97 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207448 kb
Host smart-508ab71a-7c0c-4d6e-8ffd-d679b4c0f2bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2100465332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2100465332
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1070786117
Short name T1964
Test name
Test status
Simulation time 195677894 ps
CPU time 0.87 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207408 kb
Host smart-3ef639d3-b7f2-4cbf-9143-96276dedf058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10707
86117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1070786117
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3292784454
Short name T1914
Test name
Test status
Simulation time 3391383511 ps
CPU time 99.71 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 216076 kb
Host smart-7f303c81-3092-4348-85bf-b4e72947aa24
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3292784454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3292784454
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3006673670
Short name T1574
Test name
Test status
Simulation time 195129681 ps
CPU time 0.95 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207432 kb
Host smart-3ab32e18-8c59-4d65-bfdf-463eda634953
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3006673670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3006673670
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4264453228
Short name T1961
Test name
Test status
Simulation time 161312665 ps
CPU time 0.84 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:29:53 PM PDT 24
Peak memory 207432 kb
Host smart-8b6f7943-379e-41e2-ba2b-b05438de3fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644
53228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4264453228
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1660954089
Short name T3007
Test name
Test status
Simulation time 238858805 ps
CPU time 1.01 seconds
Started Aug 09 05:29:42 PM PDT 24
Finished Aug 09 05:29:43 PM PDT 24
Peak memory 207396 kb
Host smart-ae085ddc-fa8e-487f-8025-234655cd858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16609
54089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1660954089
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3876546883
Short name T2183
Test name
Test status
Simulation time 178374516 ps
CPU time 0.96 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:29:54 PM PDT 24
Peak memory 207352 kb
Host smart-95f0fbad-4317-4335-bb95-4b0baa7770f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38765
46883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3876546883
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.714371472
Short name T2396
Test name
Test status
Simulation time 184803704 ps
CPU time 0.87 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207440 kb
Host smart-302e5ece-818c-4951-b32e-9c6c73f375dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71437
1472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.714371472
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3689482403
Short name T2328
Test name
Test status
Simulation time 232898953 ps
CPU time 0.93 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207424 kb
Host smart-40e183a0-ccce-4fff-a618-a7a538aafc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
82403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3689482403
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.107209681
Short name T3276
Test name
Test status
Simulation time 150437005 ps
CPU time 0.84 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:29:50 PM PDT 24
Peak memory 207440 kb
Host smart-1d11c791-9f00-49ec-b9b5-aaf25ab9f5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10720
9681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.107209681
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1035228303
Short name T1699
Test name
Test status
Simulation time 212747010 ps
CPU time 0.99 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207552 kb
Host smart-88fe044d-e0e9-403e-967d-8af61a26f7c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1035228303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1035228303
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3712517159
Short name T1649
Test name
Test status
Simulation time 171593212 ps
CPU time 0.89 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207396 kb
Host smart-7df375a0-ac1f-419b-aa13-48fcace765be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
17159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3712517159
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2962698149
Short name T1616
Test name
Test status
Simulation time 76101618 ps
CPU time 0.74 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207524 kb
Host smart-1540153c-47bd-4d36-996d-d949d05babf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
98149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2962698149
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2766620915
Short name T865
Test name
Test status
Simulation time 16015119566 ps
CPU time 41.22 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:30:42 PM PDT 24
Peak memory 215920 kb
Host smart-b2189037-184d-495a-b0b3-8a70c8a04b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
20915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2766620915
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1438965137
Short name T3
Test name
Test status
Simulation time 187882214 ps
CPU time 0.96 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207440 kb
Host smart-5f713801-9b15-4a69-98c5-838860b5d4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
65137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1438965137
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.638887914
Short name T2865
Test name
Test status
Simulation time 212878235 ps
CPU time 0.92 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207544 kb
Host smart-ec48bbd3-0b84-4d4a-9d35-d56715559171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63888
7914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.638887914
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.295530438
Short name T1223
Test name
Test status
Simulation time 194225212 ps
CPU time 0.91 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207556 kb
Host smart-557ab7a8-af1b-46f6-b35f-f283ec5d5215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29553
0438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.295530438
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.335937319
Short name T1940
Test name
Test status
Simulation time 181428205 ps
CPU time 0.9 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207384 kb
Host smart-d67afed2-bea9-47e2-a2be-5216dec028c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
7319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.335937319
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.4157474309
Short name T71
Test name
Test status
Simulation time 154422648 ps
CPU time 0.85 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207528 kb
Host smart-68c84682-0bda-4eab-960e-34f4319c7138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
74309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.4157474309
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.4206516717
Short name T308
Test name
Test status
Simulation time 395462337 ps
CPU time 1.3 seconds
Started Aug 09 05:29:58 PM PDT 24
Finished Aug 09 05:29:59 PM PDT 24
Peak memory 207404 kb
Host smart-2eb38408-8786-4f3e-aba6-5d8318c45ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42065
16717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.4206516717
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1914783244
Short name T3446
Test name
Test status
Simulation time 244786413 ps
CPU time 0.99 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207528 kb
Host smart-b4db4396-d34b-4279-bcab-87795cee7050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19147
83244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1914783244
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.720024714
Short name T1070
Test name
Test status
Simulation time 198576260 ps
CPU time 0.9 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207436 kb
Host smart-369054ef-accb-4513-ba92-510d4d4291d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72002
4714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.720024714
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3355828310
Short name T1308
Test name
Test status
Simulation time 200736587 ps
CPU time 0.98 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207556 kb
Host smart-d8572f1d-13fa-4c41-bdd3-3b202455b71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33558
28310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3355828310
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2309271815
Short name T2890
Test name
Test status
Simulation time 2747699202 ps
CPU time 20.55 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 224236 kb
Host smart-a33eb870-def1-48f3-84b0-dbc0322ae3f3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2309271815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2309271815
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2018984396
Short name T3417
Test name
Test status
Simulation time 153614351 ps
CPU time 0.86 seconds
Started Aug 09 05:29:54 PM PDT 24
Finished Aug 09 05:29:55 PM PDT 24
Peak memory 207560 kb
Host smart-9868ebad-c746-40c9-9c17-d07c5a68d585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20189
84396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2018984396
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.415336961
Short name T1704
Test name
Test status
Simulation time 175843483 ps
CPU time 0.87 seconds
Started Aug 09 05:30:05 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 207560 kb
Host smart-58ce8cf4-8ec7-4b62-b5fc-a2d1516d854d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41533
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.415336961
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1542382860
Short name T1713
Test name
Test status
Simulation time 1199548158 ps
CPU time 3.08 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207544 kb
Host smart-ddcbd02a-8d19-4d22-93e0-92da84da7130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15423
82860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1542382860
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.340736073
Short name T3139
Test name
Test status
Simulation time 2374686330 ps
CPU time 69.57 seconds
Started Aug 09 05:30:00 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 216076 kb
Host smart-00af4a57-099c-4c02-acb5-3866529a7211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
6073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.340736073
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2427210360
Short name T2250
Test name
Test status
Simulation time 3854682862 ps
CPU time 32.6 seconds
Started Aug 09 05:29:44 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207724 kb
Host smart-f0238382-9b2b-4056-884d-7d0a20c4c1d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427210360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2427210360
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.2577495681
Short name T2614
Test name
Test status
Simulation time 511410823 ps
CPU time 1.63 seconds
Started Aug 09 05:29:54 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207564 kb
Host smart-69bb1362-b5a4-44c1-812c-06a0db2df6a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577495681 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.2577495681
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.3649529397
Short name T1522
Test name
Test status
Simulation time 608226198 ps
CPU time 1.54 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207460 kb
Host smart-0a021fca-b6c6-4178-a1a7-b048f9d3c1ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649529397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.3649529397
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.1361943565
Short name T3381
Test name
Test status
Simulation time 483869776 ps
CPU time 1.48 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207444 kb
Host smart-76e4cf49-fc7a-46cb-a316-62f835f13c1c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361943565 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.1361943565
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.3105872863
Short name T1368
Test name
Test status
Simulation time 482209947 ps
CPU time 1.48 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207516 kb
Host smart-d54624f1-2f40-40d0-8e30-4380d59ef9cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105872863 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.3105872863
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.2403823235
Short name T1983
Test name
Test status
Simulation time 532854427 ps
CPU time 1.54 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207516 kb
Host smart-774ae38a-c17f-43e5-8580-25ee50fa494f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403823235 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.2403823235
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.845355362
Short name T798
Test name
Test status
Simulation time 478489141 ps
CPU time 1.46 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207400 kb
Host smart-92e588d6-f5c0-40cc-8b42-30e6b55bee29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845355362 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.845355362
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.997328413
Short name T1856
Test name
Test status
Simulation time 522361696 ps
CPU time 1.54 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207432 kb
Host smart-f4c055fc-24ec-4b4f-84b3-c019d1fd5e54
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997328413 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.997328413
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.1200522380
Short name T2005
Test name
Test status
Simulation time 569320707 ps
CPU time 1.57 seconds
Started Aug 09 05:33:29 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 207484 kb
Host smart-549c8d9c-cbe0-4227-8978-c5db5f335d4c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200522380 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.1200522380
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.3883480362
Short name T1192
Test name
Test status
Simulation time 519944129 ps
CPU time 1.58 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:45 PM PDT 24
Peak memory 207440 kb
Host smart-84893e0c-892f-4f4a-9e2a-bd2bba921dac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883480362 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.3883480362
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.3088689298
Short name T905
Test name
Test status
Simulation time 553757893 ps
CPU time 1.58 seconds
Started Aug 09 05:33:33 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207484 kb
Host smart-4647e5eb-6455-4499-9be4-005ce5375089
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088689298 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.3088689298
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.150585023
Short name T1053
Test name
Test status
Simulation time 502666360 ps
CPU time 1.56 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 207520 kb
Host smart-4f1c27cf-29eb-4bc6-b86c-37c21fcf0205
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150585023 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.150585023
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.455520143
Short name T834
Test name
Test status
Simulation time 51619055 ps
CPU time 0.69 seconds
Started Aug 09 05:30:05 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 207556 kb
Host smart-5c0812a7-665d-4b2a-83cb-17bdfec1cc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=455520143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.455520143
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.430614630
Short name T1016
Test name
Test status
Simulation time 9726473049 ps
CPU time 14.6 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207824 kb
Host smart-576e6b25-4eea-4fd4-a3b7-322517988f29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430614630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_disconnect.430614630
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3449814398
Short name T1166
Test name
Test status
Simulation time 14133254511 ps
CPU time 20.2 seconds
Started Aug 09 05:29:58 PM PDT 24
Finished Aug 09 05:30:19 PM PDT 24
Peak memory 215960 kb
Host smart-f016e30c-3af7-4545-99a7-67c8e5aa6a61
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449814398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3449814398
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.576244254
Short name T3008
Test name
Test status
Simulation time 28922044468 ps
CPU time 39.24 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 207816 kb
Host smart-7843d8d9-cb6e-4faf-adb4-bfd4316982a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576244254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_ao
n_wake_resume.576244254
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3748928554
Short name T1476
Test name
Test status
Simulation time 215546669 ps
CPU time 0.88 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207408 kb
Host smart-2d8e9921-d10d-4edf-b86f-28ab79c63e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
28554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3748928554
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4174396048
Short name T3023
Test name
Test status
Simulation time 141798127 ps
CPU time 0.87 seconds
Started Aug 09 05:29:46 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207376 kb
Host smart-86d9240f-3b56-48f4-9a26-f0ac84f6a11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
96048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4174396048
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2198633948
Short name T2824
Test name
Test status
Simulation time 166552119 ps
CPU time 0.86 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:45 PM PDT 24
Peak memory 207416 kb
Host smart-ce16a0cf-f262-4936-b205-ff147a6961a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21986
33948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2198633948
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2520830083
Short name T3255
Test name
Test status
Simulation time 1086491295 ps
CPU time 2.89 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:59 PM PDT 24
Peak memory 207708 kb
Host smart-3e096ff0-9ec0-46ca-9da2-c4b4bd91d61b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2520830083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2520830083
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2646642982
Short name T3233
Test name
Test status
Simulation time 24764315558 ps
CPU time 40.46 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207712 kb
Host smart-69de0e90-f380-43e8-8c5e-9c298d8352d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26466
42982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2646642982
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.3768924640
Short name T2781
Test name
Test status
Simulation time 1403871573 ps
CPU time 9.77 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:30:03 PM PDT 24
Peak memory 207612 kb
Host smart-4d2e49fd-374c-4728-af57-c7c5048413f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768924640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.3768924640
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3046153397
Short name T3176
Test name
Test status
Simulation time 736510623 ps
CPU time 1.75 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:47 PM PDT 24
Peak memory 207472 kb
Host smart-b17e816f-b167-4bbc-8070-7053dc93f290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30461
53397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3046153397
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3454273652
Short name T3297
Test name
Test status
Simulation time 174862235 ps
CPU time 0.84 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207416 kb
Host smart-0ffc9a1d-0578-4d7a-aeda-1c197f277604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34542
73652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3454273652
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3480551109
Short name T2747
Test name
Test status
Simulation time 36423810 ps
CPU time 0.69 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207368 kb
Host smart-7963f068-eb8d-4fc0-bb52-76ad985e9ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34805
51109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3480551109
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2883337586
Short name T1804
Test name
Test status
Simulation time 916041873 ps
CPU time 2.35 seconds
Started Aug 09 05:30:00 PM PDT 24
Finished Aug 09 05:30:03 PM PDT 24
Peak memory 207712 kb
Host smart-f2730748-cef1-4af9-8fbf-e5e5638b5b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
37586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2883337586
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.156985994
Short name T369
Test name
Test status
Simulation time 381350035 ps
CPU time 1.17 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207424 kb
Host smart-f26972fb-80d1-4b4e-9023-9ee73384beec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=156985994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.156985994
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1542622786
Short name T938
Test name
Test status
Simulation time 230424217 ps
CPU time 1.96 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:01 PM PDT 24
Peak memory 207592 kb
Host smart-9f15b92a-0b7b-40e4-be30-7050f99f39b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15426
22786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1542622786
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1985874487
Short name T965
Test name
Test status
Simulation time 202681145 ps
CPU time 0.99 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 216156 kb
Host smart-b3348f63-7eea-47bf-ab64-631d98f3c071
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1985874487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1985874487
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2788398347
Short name T2584
Test name
Test status
Simulation time 136629339 ps
CPU time 0.83 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207356 kb
Host smart-5c6b7d38-66b5-4ae7-8c25-93a8e4df8c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
98347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2788398347
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3724014428
Short name T3356
Test name
Test status
Simulation time 245738179 ps
CPU time 1.02 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207436 kb
Host smart-4c416827-a822-4889-b3c1-fda5fcb6358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240
14428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3724014428
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3500242761
Short name T1723
Test name
Test status
Simulation time 4276626761 ps
CPU time 126.26 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 217884 kb
Host smart-bb7655ee-4d0e-44c0-b9fb-6bb39b33b4d9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3500242761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3500242761
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.346027998
Short name T1506
Test name
Test status
Simulation time 11476019235 ps
CPU time 146.53 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207712 kb
Host smart-eddff548-221a-4265-b7dc-a446a5c7290a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=346027998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.346027998
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2813433926
Short name T1603
Test name
Test status
Simulation time 222884822 ps
CPU time 0.98 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207476 kb
Host smart-405dd187-94d1-42d2-95fb-d0e3e2cb50cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
33926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2813433926
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1489243894
Short name T801
Test name
Test status
Simulation time 28735256480 ps
CPU time 40.49 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 207828 kb
Host smart-390f6dc8-6f54-4494-ae95-136f413b3e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
43894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1489243894
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.154538169
Short name T95
Test name
Test status
Simulation time 10456431660 ps
CPU time 13.62 seconds
Started Aug 09 05:30:02 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207800 kb
Host smart-baec5850-fa4b-48b7-acb0-ea4c8efd6a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
8169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.154538169
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.582621410
Short name T1975
Test name
Test status
Simulation time 2676622707 ps
CPU time 19.86 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 216112 kb
Host smart-babf4a28-1584-49da-b673-4370201a00d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=582621410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.582621410
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2411997826
Short name T1194
Test name
Test status
Simulation time 3156689724 ps
CPU time 93.34 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 217516 kb
Host smart-7c507352-e91e-4b76-840d-2bb6fcf7659d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2411997826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2411997826
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2659166965
Short name T876
Test name
Test status
Simulation time 276198405 ps
CPU time 1.06 seconds
Started Aug 09 05:30:03 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207428 kb
Host smart-894f676f-3f15-4a8f-b63e-9e88083c49d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2659166965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2659166965
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2217708247
Short name T3313
Test name
Test status
Simulation time 210105945 ps
CPU time 0.95 seconds
Started Aug 09 05:30:05 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 207504 kb
Host smart-59870307-2b16-438a-b9b4-ee95e4b8a145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22177
08247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2217708247
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3445832510
Short name T1238
Test name
Test status
Simulation time 3585474169 ps
CPU time 36.09 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 216056 kb
Host smart-fdd9189a-4c19-4957-96e3-63590ebb4ddc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3445832510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3445832510
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.874556201
Short name T2245
Test name
Test status
Simulation time 148448076 ps
CPU time 0.85 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207504 kb
Host smart-7d0b0b2c-7182-4ada-a824-584901a9ad0f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=874556201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.874556201
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.796821663
Short name T2253
Test name
Test status
Simulation time 170267564 ps
CPU time 0.84 seconds
Started Aug 09 05:29:56 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207364 kb
Host smart-595c3704-24cc-4e8b-b4e3-3e11a0c97c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79682
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.796821663
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2605096927
Short name T125
Test name
Test status
Simulation time 200666320 ps
CPU time 0.96 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207504 kb
Host smart-1bae43ae-e6fa-431b-808a-a1448b06481b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
96927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2605096927
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3399797087
Short name T634
Test name
Test status
Simulation time 190622722 ps
CPU time 0.93 seconds
Started Aug 09 05:29:48 PM PDT 24
Finished Aug 09 05:29:49 PM PDT 24
Peak memory 207508 kb
Host smart-72629722-cabd-4f64-a199-474a79da2c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33997
97087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3399797087
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3917258930
Short name T928
Test name
Test status
Simulation time 214647132 ps
CPU time 0.93 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207492 kb
Host smart-e5f1d7a7-ca68-4e81-88e2-9a638379d3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
58930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3917258930
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4104462247
Short name T3285
Test name
Test status
Simulation time 145908512 ps
CPU time 0.86 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 207528 kb
Host smart-a8cc132b-805a-4b76-9d58-50ab903e0cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
62247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4104462247
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2990589610
Short name T2052
Test name
Test status
Simulation time 163536318 ps
CPU time 0.86 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207516 kb
Host smart-7dd2d5e7-6be4-4730-9267-d0c45ceafeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29905
89610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2990589610
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.331299051
Short name T926
Test name
Test status
Simulation time 221699434 ps
CPU time 0.99 seconds
Started Aug 09 05:30:05 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 207552 kb
Host smart-50dc0af9-16a7-432d-ab04-78cad92c531e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=331299051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.331299051
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1301295495
Short name T973
Test name
Test status
Simulation time 139827908 ps
CPU time 0.82 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:56 PM PDT 24
Peak memory 207452 kb
Host smart-a7929f46-744a-4459-b4be-8dbfdbe9b134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
95495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1301295495
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.346810150
Short name T917
Test name
Test status
Simulation time 69681474 ps
CPU time 0.7 seconds
Started Aug 09 05:29:49 PM PDT 24
Finished Aug 09 05:29:50 PM PDT 24
Peak memory 207384 kb
Host smart-d5ed0d2f-392f-4c05-b92e-e318415462c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34681
0150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.346810150
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1713972844
Short name T2992
Test name
Test status
Simulation time 11738812596 ps
CPU time 28.8 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 216004 kb
Host smart-c4ecc286-4302-426d-a724-06fca4f31a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
72844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1713972844
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3062220482
Short name T2633
Test name
Test status
Simulation time 164922810 ps
CPU time 0.88 seconds
Started Aug 09 05:29:45 PM PDT 24
Finished Aug 09 05:29:46 PM PDT 24
Peak memory 207384 kb
Host smart-ae1cf55d-4b05-42dc-a071-4fccd2c32fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30622
20482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3062220482
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.354615988
Short name T2831
Test name
Test status
Simulation time 165902430 ps
CPU time 0.83 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:29:52 PM PDT 24
Peak memory 207472 kb
Host smart-257cc2fd-357c-4979-8e55-5eb6adde387f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
5988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.354615988
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1984559753
Short name T3543
Test name
Test status
Simulation time 157638049 ps
CPU time 0.86 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:29:58 PM PDT 24
Peak memory 207436 kb
Host smart-25a2bfbd-4392-4327-83da-c9213a19cbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
59753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1984559753
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.346237271
Short name T2930
Test name
Test status
Simulation time 188961260 ps
CPU time 0.93 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207444 kb
Host smart-897e195e-396c-4781-826e-a0b7a39849a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34623
7271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.346237271
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1355450893
Short name T781
Test name
Test status
Simulation time 149905066 ps
CPU time 0.88 seconds
Started Aug 09 05:29:47 PM PDT 24
Finished Aug 09 05:29:48 PM PDT 24
Peak memory 207496 kb
Host smart-077bb6ac-35e1-4afd-8d1f-3e63fc3a433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
50893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1355450893
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.1117751108
Short name T2987
Test name
Test status
Simulation time 320048240 ps
CPU time 1.17 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:30:03 PM PDT 24
Peak memory 207452 kb
Host smart-8c1b4172-0349-42fd-a9bf-fd6070690ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177
51108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.1117751108
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2965890958
Short name T1204
Test name
Test status
Simulation time 208411940 ps
CPU time 0.86 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207428 kb
Host smart-ffd238a7-9c82-4aaf-bb80-6e4377efc015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29658
90958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2965890958
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.471166465
Short name T2751
Test name
Test status
Simulation time 179665889 ps
CPU time 0.89 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207428 kb
Host smart-25ef53bc-6277-4dde-b62b-8f85936914e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47116
6465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.471166465
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1669318761
Short name T566
Test name
Test status
Simulation time 208756358 ps
CPU time 0.99 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207512 kb
Host smart-f0afa72b-d127-4e4a-9e39-e098615e3587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16693
18761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1669318761
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2517403596
Short name T3334
Test name
Test status
Simulation time 1489366411 ps
CPU time 14.04 seconds
Started Aug 09 05:29:51 PM PDT 24
Finished Aug 09 05:30:06 PM PDT 24
Peak memory 217648 kb
Host smart-6f706a97-45f9-466e-be1f-7593b71ff6d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2517403596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2517403596
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3308689646
Short name T1701
Test name
Test status
Simulation time 187712809 ps
CPU time 0.93 seconds
Started Aug 09 05:29:59 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207552 kb
Host smart-cfc83ea6-f3fe-4cc9-af86-5c368d8bbc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
89646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3308689646
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.4277865801
Short name T1791
Test name
Test status
Simulation time 147061637 ps
CPU time 0.83 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207444 kb
Host smart-dd8eb362-ce19-4b12-8c65-646bfd1acadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
65801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.4277865801
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1899316817
Short name T885
Test name
Test status
Simulation time 685974366 ps
CPU time 1.81 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207376 kb
Host smart-b16652a7-9a1d-4461-a8c8-2cf4088f476a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18993
16817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1899316817
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.268986530
Short name T675
Test name
Test status
Simulation time 1843702899 ps
CPU time 17.58 seconds
Started Aug 09 05:30:02 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 216760 kb
Host smart-bc61c656-feb0-44ca-9037-44fffaa6ccc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
6530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.268986530
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.2240553270
Short name T2629
Test name
Test status
Simulation time 618227416 ps
CPU time 11.38 seconds
Started Aug 09 05:29:50 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 207596 kb
Host smart-a966f1ab-dc5c-487b-bfad-58bfcca5ab6f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240553270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.2240553270
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.2804939911
Short name T1408
Test name
Test status
Simulation time 543914482 ps
CPU time 1.68 seconds
Started Aug 09 05:29:52 PM PDT 24
Finished Aug 09 05:29:54 PM PDT 24
Peak memory 207560 kb
Host smart-b6a6d822-3063-4043-aa43-c264b710e771
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804939911 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.2804939911
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.895921059
Short name T1680
Test name
Test status
Simulation time 541881952 ps
CPU time 1.51 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207520 kb
Host smart-29a7e023-7db5-4a60-99e1-4f6b68bddeca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895921059 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.895921059
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.702340729
Short name T1768
Test name
Test status
Simulation time 496347123 ps
CPU time 1.65 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207488 kb
Host smart-bf63002c-1085-4c6c-8207-20764bdc6f8b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702340729 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.702340729
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.4108615219
Short name T881
Test name
Test status
Simulation time 643914029 ps
CPU time 1.75 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 207512 kb
Host smart-e90dacbe-8d91-4e94-8b95-b1272f8de443
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108615219 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.4108615219
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.1790852093
Short name T3473
Test name
Test status
Simulation time 493240287 ps
CPU time 1.55 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207480 kb
Host smart-25dda5cc-fc56-46dd-8532-6545d7be80ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790852093 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.1790852093
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.224952401
Short name T2180
Test name
Test status
Simulation time 477099061 ps
CPU time 1.53 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207508 kb
Host smart-677a27e3-f437-4b3d-9e3c-8a86a52e985e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224952401 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.224952401
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.3111935599
Short name T2899
Test name
Test status
Simulation time 614512491 ps
CPU time 1.8 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207536 kb
Host smart-a6a0945e-8303-4662-9387-e47077f5c94b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111935599 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.3111935599
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.1802235471
Short name T1037
Test name
Test status
Simulation time 567873568 ps
CPU time 1.67 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207380 kb
Host smart-19f471e5-3db6-4872-b5f5-83a567194198
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802235471 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.1802235471
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.944068544
Short name T925
Test name
Test status
Simulation time 463188124 ps
CPU time 1.5 seconds
Started Aug 09 05:33:31 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207524 kb
Host smart-672ccc6b-37d9-4b34-ae9a-c0d343f8c101
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944068544 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.944068544
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.297566338
Short name T1796
Test name
Test status
Simulation time 584238979 ps
CPU time 1.57 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207440 kb
Host smart-5ccd5869-12ae-4ea2-a908-9e182adc8204
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297566338 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.297566338
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.747837757
Short name T522
Test name
Test status
Simulation time 505719921 ps
CPU time 1.55 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207496 kb
Host smart-2c294e55-d72d-466e-ab10-45c9f736d884
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747837757 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.747837757
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3330868780
Short name T3206
Test name
Test status
Simulation time 60369187 ps
CPU time 0.71 seconds
Started Aug 09 05:30:01 PM PDT 24
Finished Aug 09 05:30:02 PM PDT 24
Peak memory 207504 kb
Host smart-a1de9c82-0b1b-4852-80bd-4e10bff99225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3330868780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3330868780
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.620525832
Short name T3535
Test name
Test status
Simulation time 9555012335 ps
CPU time 12.62 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207708 kb
Host smart-66566677-4917-451c-8ab1-e67936c1c064
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620525832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.620525832
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.4273793313
Short name T3238
Test name
Test status
Simulation time 19974165252 ps
CPU time 24.58 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207820 kb
Host smart-311a1f0e-e0d1-45de-ab4d-c3476e0d36c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273793313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.4273793313
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2927857342
Short name T2484
Test name
Test status
Simulation time 24088376224 ps
CPU time 34.12 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 215856 kb
Host smart-984c09b5-c726-488e-a794-16947dd7038c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927857342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.2927857342
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1230653722
Short name T869
Test name
Test status
Simulation time 196118841 ps
CPU time 0.91 seconds
Started Aug 09 05:30:17 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207464 kb
Host smart-9e68c9d7-9867-4d0d-aa77-0e8755610838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
53722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1230653722
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2112267046
Short name T1184
Test name
Test status
Simulation time 168694687 ps
CPU time 0.84 seconds
Started Aug 09 05:29:58 PM PDT 24
Finished Aug 09 05:29:59 PM PDT 24
Peak memory 207448 kb
Host smart-fb589b34-7138-49c3-aacb-e2ee03ef6bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122
67046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2112267046
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.749984175
Short name T116
Test name
Test status
Simulation time 319549670 ps
CPU time 1.37 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207440 kb
Host smart-55ca382e-ac1a-4afc-8769-52c9d823a431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74998
4175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.749984175
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3083519527
Short name T1847
Test name
Test status
Simulation time 1002950549 ps
CPU time 2.51 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207752 kb
Host smart-50139527-ce91-42bc-b709-c588129dec8c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3083519527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3083519527
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1366067983
Short name T2716
Test name
Test status
Simulation time 16885637542 ps
CPU time 26.37 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:40 PM PDT 24
Peak memory 207792 kb
Host smart-44a09f8f-6d56-4013-8fd6-78242b7a6869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
67983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1366067983
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.771832309
Short name T2489
Test name
Test status
Simulation time 1162227411 ps
CPU time 27.35 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:30:22 PM PDT 24
Peak memory 207688 kb
Host smart-16182c38-6015-4487-a9eb-893a9ad06598
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771832309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.771832309
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.3671023516
Short name T1724
Test name
Test status
Simulation time 702800836 ps
CPU time 1.81 seconds
Started Aug 09 05:29:55 PM PDT 24
Finished Aug 09 05:29:57 PM PDT 24
Peak memory 207508 kb
Host smart-c60079e2-a0f6-4f50-9f9b-918f4d350d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
23516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.3671023516
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3730020789
Short name T628
Test name
Test status
Simulation time 154336950 ps
CPU time 0.81 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 207452 kb
Host smart-fd1d2e9c-2ba4-4c9a-a971-0bff23db5314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
20789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3730020789
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2247646920
Short name T1765
Test name
Test status
Simulation time 35403142 ps
CPU time 0.76 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207520 kb
Host smart-70f74048-32d9-4efa-988b-6d2bb52a38fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22476
46920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2247646920
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4173869572
Short name T3283
Test name
Test status
Simulation time 813147328 ps
CPU time 2.51 seconds
Started Aug 09 05:30:05 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207572 kb
Host smart-2b679931-9bcb-4901-819e-635409f5d166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41738
69572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4173869572
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.1883716754
Short name T397
Test name
Test status
Simulation time 669746107 ps
CPU time 1.57 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207464 kb
Host smart-20927b2e-2787-4125-ac0e-d1619665314a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1883716754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.1883716754
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.119346162
Short name T2809
Test name
Test status
Simulation time 179022433 ps
CPU time 2.03 seconds
Started Aug 09 05:29:57 PM PDT 24
Finished Aug 09 05:30:00 PM PDT 24
Peak memory 207648 kb
Host smart-e3c9b02d-330e-44cc-9308-d4a095249f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
6162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.119346162
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1189280315
Short name T1458
Test name
Test status
Simulation time 229060755 ps
CPU time 1.17 seconds
Started Aug 09 05:29:53 PM PDT 24
Finished Aug 09 05:29:54 PM PDT 24
Peak memory 224116 kb
Host smart-1457847d-5fe2-4264-aa2a-c62040c278db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1189280315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1189280315
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1392758078
Short name T1041
Test name
Test status
Simulation time 143804077 ps
CPU time 0.85 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 207352 kb
Host smart-3772f2c1-8881-4622-8f0a-f998e6e6cc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
58078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1392758078
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3502193516
Short name T3296
Test name
Test status
Simulation time 197935982 ps
CPU time 0.91 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207512 kb
Host smart-7602beb2-ab15-4c01-af00-25d38faadbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
93516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3502193516
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1912103362
Short name T3199
Test name
Test status
Simulation time 4594232413 ps
CPU time 134.35 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:32:18 PM PDT 24
Peak memory 217940 kb
Host smart-b73f66b7-8ef0-4cec-8629-b84ec3b58534
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1912103362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1912103362
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.4095366102
Short name T3482
Test name
Test status
Simulation time 10145704106 ps
CPU time 67.03 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207756 kb
Host smart-70e87873-3697-4222-af8c-f4ef3dd58d3e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4095366102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.4095366102
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.4005712674
Short name T937
Test name
Test status
Simulation time 228291610 ps
CPU time 1.01 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207552 kb
Host smart-08374e35-cee8-4d92-a17b-af0f425364ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
12674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.4005712674
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3317040633
Short name T2287
Test name
Test status
Simulation time 28152010513 ps
CPU time 44.53 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207776 kb
Host smart-08991534-9188-43af-b895-893a3638af90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33170
40633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3317040633
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1373786344
Short name T1516
Test name
Test status
Simulation time 6206852464 ps
CPU time 8.39 seconds
Started Aug 09 05:30:02 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207688 kb
Host smart-18c0a921-c62c-4ebf-96fa-6555c465f6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13737
86344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1373786344
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3435760933
Short name T2059
Test name
Test status
Simulation time 2830581026 ps
CPU time 81.48 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 216344 kb
Host smart-c2bec092-67d3-4277-8a63-f5f41e232716
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3435760933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3435760933
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2804033331
Short name T3251
Test name
Test status
Simulation time 3435649165 ps
CPU time 26.43 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 217740 kb
Host smart-ba544323-5418-43c2-9793-408ba2ddcaac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2804033331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2804033331
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1605557711
Short name T2577
Test name
Test status
Simulation time 273762844 ps
CPU time 0.99 seconds
Started Aug 09 05:30:02 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207500 kb
Host smart-01da0713-77dc-4f71-9dae-4b09104c12ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1605557711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1605557711
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.4080813966
Short name T599
Test name
Test status
Simulation time 199230412 ps
CPU time 0.94 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207360 kb
Host smart-b2fc9657-ba25-42d1-bebb-bba53e9854db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40808
13966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.4080813966
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1762623907
Short name T1917
Test name
Test status
Simulation time 3016437819 ps
CPU time 88.97 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:31:37 PM PDT 24
Peak memory 217436 kb
Host smart-06e231c9-74d0-43fe-ab26-56fc6947d849
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1762623907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1762623907
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3070832864
Short name T1117
Test name
Test status
Simulation time 162372709 ps
CPU time 0.89 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207376 kb
Host smart-065a87d3-5cb7-41a9-90d3-63d777bfee76
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3070832864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3070832864
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3792811272
Short name T3328
Test name
Test status
Simulation time 143767951 ps
CPU time 0.82 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207444 kb
Host smart-052e1e7b-ab30-48b1-adc2-871491f740ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
11272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3792811272
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1663793930
Short name T142
Test name
Test status
Simulation time 237406920 ps
CPU time 1 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207508 kb
Host smart-422a9d9f-85cb-4060-ad3d-fb3df67847d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
93930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1663793930
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1123167878
Short name T1551
Test name
Test status
Simulation time 206426206 ps
CPU time 0.91 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207512 kb
Host smart-70848df9-3004-4568-ba28-40984d83debd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11231
67878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1123167878
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3582962336
Short name T1182
Test name
Test status
Simulation time 155360912 ps
CPU time 0.85 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207548 kb
Host smart-c46dd292-14b2-4edc-b404-9221a267ef0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35829
62336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3582962336
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1936526271
Short name T784
Test name
Test status
Simulation time 156860490 ps
CPU time 0.87 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207504 kb
Host smart-591a98a9-03e2-4ec0-a711-67c8d92d6ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
26271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1936526271
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1132959506
Short name T1550
Test name
Test status
Simulation time 161430986 ps
CPU time 0.89 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207496 kb
Host smart-7005a68c-1936-469b-8114-4cc28b29b42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
59506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1132959506
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3566975746
Short name T3455
Test name
Test status
Simulation time 219238670 ps
CPU time 0.98 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207468 kb
Host smart-7c133aa8-ce45-4d5a-853b-4a00b060fa11
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3566975746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3566975746
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1019149760
Short name T1322
Test name
Test status
Simulation time 143193039 ps
CPU time 0.82 seconds
Started Aug 09 05:30:24 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207328 kb
Host smart-8a56b632-b0e2-4e53-9fc3-68011fa16595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10191
49760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1019149760
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.324364522
Short name T2832
Test name
Test status
Simulation time 55381024 ps
CPU time 0.74 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:11 PM PDT 24
Peak memory 207516 kb
Host smart-aa81ea49-188a-495d-9f7c-8e7d006336ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
4522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.324364522
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1925150006
Short name T3146
Test name
Test status
Simulation time 17512893595 ps
CPU time 43.15 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:56 PM PDT 24
Peak memory 216048 kb
Host smart-9443204a-f03f-4656-8473-47dc6dbc874b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251
50006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1925150006
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2647846905
Short name T1920
Test name
Test status
Simulation time 169198466 ps
CPU time 0.88 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207508 kb
Host smart-6c254d61-bd9d-4019-b7e4-ce20e003e4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
46905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2647846905
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3468373857
Short name T2916
Test name
Test status
Simulation time 249008172 ps
CPU time 0.95 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:07 PM PDT 24
Peak memory 207436 kb
Host smart-9e602363-e768-41b4-bd4f-dcdeb53caa08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
73857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3468373857
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1084782070
Short name T768
Test name
Test status
Simulation time 197228256 ps
CPU time 0.93 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207512 kb
Host smart-d606b993-3ae9-41bb-b236-7a027dee8aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
82070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1084782070
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.529977021
Short name T1298
Test name
Test status
Simulation time 169969053 ps
CPU time 0.88 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207488 kb
Host smart-5095dd9c-9497-4807-8df0-ecc27de77bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52997
7021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.529977021
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2083635205
Short name T2685
Test name
Test status
Simulation time 183354806 ps
CPU time 0.88 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207472 kb
Host smart-387c6ec7-e45b-4889-90a3-6fdb6a7fe1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20836
35205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2083635205
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.628175379
Short name T842
Test name
Test status
Simulation time 415748566 ps
CPU time 1.32 seconds
Started Aug 09 05:30:04 PM PDT 24
Finished Aug 09 05:30:05 PM PDT 24
Peak memory 207440 kb
Host smart-2a5856aa-b70f-4e1c-984d-5ae9184d0db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62817
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.628175379
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2265854182
Short name T2575
Test name
Test status
Simulation time 154982979 ps
CPU time 0.86 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207400 kb
Host smart-0c5ca09d-e2cd-4583-b0bd-052f0750ac40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22658
54182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2265854182
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2380887981
Short name T1198
Test name
Test status
Simulation time 203017590 ps
CPU time 0.93 seconds
Started Aug 09 05:30:02 PM PDT 24
Finished Aug 09 05:30:04 PM PDT 24
Peak memory 207520 kb
Host smart-c4e8f9b5-a8ae-4d0d-9d63-875df301a565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23808
87981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2380887981
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1951732360
Short name T3605
Test name
Test status
Simulation time 257946926 ps
CPU time 1.1 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:09 PM PDT 24
Peak memory 207456 kb
Host smart-3d232feb-a8d7-4dff-bbcb-8202c89e0817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19517
32360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1951732360
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3543333462
Short name T2248
Test name
Test status
Simulation time 1935057105 ps
CPU time 51.64 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 215936 kb
Host smart-6305f803-746b-4d8e-b618-3338f6186224
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3543333462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3543333462
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2154024871
Short name T1560
Test name
Test status
Simulation time 162445512 ps
CPU time 0.88 seconds
Started Aug 09 05:30:17 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207500 kb
Host smart-cb850f30-9a7c-4bda-96a8-051a4738dbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
24871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2154024871
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3530016335
Short name T1260
Test name
Test status
Simulation time 190601520 ps
CPU time 0.87 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:10 PM PDT 24
Peak memory 207532 kb
Host smart-66e70c2f-7477-478a-bb16-d026df58a6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
16335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3530016335
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1413258733
Short name T3603
Test name
Test status
Simulation time 1164514309 ps
CPU time 2.74 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207652 kb
Host smart-8d90a578-1603-4704-8dbc-a3b85f969adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
58733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1413258733
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3738705843
Short name T1866
Test name
Test status
Simulation time 3471837383 ps
CPU time 35.54 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 217704 kb
Host smart-2ad1af3c-f3c3-408e-a881-52105cfac5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
05843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3738705843
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.2104987038
Short name T783
Test name
Test status
Simulation time 1155551452 ps
CPU time 25.65 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207548 kb
Host smart-9e42fa0e-efb5-4762-ae6d-f3ff9b852ad5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104987038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.2104987038
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.3458497031
Short name T1805
Test name
Test status
Simulation time 539455186 ps
CPU time 1.57 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207528 kb
Host smart-144fd15d-2450-481d-8571-e6ee4fbe1f5d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458497031 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.3458497031
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.3891098100
Short name T850
Test name
Test status
Simulation time 573212794 ps
CPU time 1.79 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207512 kb
Host smart-45beed1f-1ed4-477c-9a9d-f8c2531e3f4d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891098100 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.3891098100
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.111713681
Short name T1800
Test name
Test status
Simulation time 464162834 ps
CPU time 1.36 seconds
Started Aug 09 05:33:38 PM PDT 24
Finished Aug 09 05:33:40 PM PDT 24
Peak memory 207432 kb
Host smart-de7bf890-f188-4c0a-aeab-4d2c10c5dee0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111713681 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.111713681
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.3192164253
Short name T1376
Test name
Test status
Simulation time 582529304 ps
CPU time 1.61 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207564 kb
Host smart-304cb831-c28b-44d3-aad2-def92a8a34d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192164253 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.3192164253
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.2310470330
Short name T2701
Test name
Test status
Simulation time 444370698 ps
CPU time 1.42 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207516 kb
Host smart-6ccb5da5-b326-4176-ad6b-7f5e8a456b9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310470330 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.2310470330
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.393198781
Short name T2426
Test name
Test status
Simulation time 474170567 ps
CPU time 1.5 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:42 PM PDT 24
Peak memory 207824 kb
Host smart-bf327afd-9f83-48d8-b49b-7e3bfb7128f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393198781 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.393198781
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.3945845642
Short name T1382
Test name
Test status
Simulation time 719642560 ps
CPU time 1.93 seconds
Started Aug 09 05:33:31 PM PDT 24
Finished Aug 09 05:33:33 PM PDT 24
Peak memory 207484 kb
Host smart-ddce5141-cb08-4c8b-8b8a-7c4c3522fb85
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945845642 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.3945845642
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.1347314215
Short name T2375
Test name
Test status
Simulation time 544703062 ps
CPU time 1.58 seconds
Started Aug 09 05:33:30 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207532 kb
Host smart-99f46edc-a71c-4d57-a48c-ec4692675264
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347314215 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1347314215
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.110698796
Short name T3186
Test name
Test status
Simulation time 578242135 ps
CPU time 1.51 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:45 PM PDT 24
Peak memory 207452 kb
Host smart-a989abff-7171-4999-91fa-5cb74090b975
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110698796 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.110698796
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.3541109396
Short name T159
Test name
Test status
Simulation time 737366099 ps
CPU time 1.84 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207484 kb
Host smart-c6d88ccc-2693-4819-8a6b-346579f164c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541109396 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.3541109396
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.1956978677
Short name T3338
Test name
Test status
Simulation time 565406715 ps
CPU time 1.53 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207532 kb
Host smart-c16fa498-e6ad-4e48-8d62-0bce4cba8aec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956978677 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.1956978677
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2756100192
Short name T1245
Test name
Test status
Simulation time 38383833 ps
CPU time 0.65 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207532 kb
Host smart-60ca7a92-2c20-4342-a601-0d00e92ce73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2756100192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2756100192
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.351834841
Short name T3133
Test name
Test status
Simulation time 9773093605 ps
CPU time 15.31 seconds
Started Aug 09 05:26:05 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 207780 kb
Host smart-d2f426d7-d9e3-4b70-8881-f9c1f8bff0f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351834841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_disconnect.351834841
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.184942187
Short name T1851
Test name
Test status
Simulation time 19019379030 ps
CPU time 22.24 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:31 PM PDT 24
Peak memory 207724 kb
Host smart-19aafbbf-ea5f-4d6c-8568-14dc8cfc95f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=184942187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.184942187
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1997214922
Short name T3622
Test name
Test status
Simulation time 30312011212 ps
CPU time 37.5 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207808 kb
Host smart-969c7791-dcc3-4d2a-9cd1-644d0f4f164d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997214922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.1997214922
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1207865246
Short name T2961
Test name
Test status
Simulation time 144987136 ps
CPU time 0.9 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207504 kb
Host smart-3f9cd5c3-9680-4f9e-ac9a-39181021c3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12078
65246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1207865246
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.4140245159
Short name T41
Test name
Test status
Simulation time 183216118 ps
CPU time 0.92 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207376 kb
Host smart-2dc622e8-8a0f-457c-9acc-8256f7f3838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
45159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.4140245159
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.838602155
Short name T3247
Test name
Test status
Simulation time 141001888 ps
CPU time 0.86 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207440 kb
Host smart-e176f23d-15f8-44a0-8721-274f46fe6093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83860
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.838602155
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.297320518
Short name T2070
Test name
Test status
Simulation time 142653435 ps
CPU time 0.86 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207364 kb
Host smart-d76d7471-cd8b-458e-9dfa-4b4a034d4954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29732
0518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.297320518
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3865023098
Short name T877
Test name
Test status
Simulation time 277868902 ps
CPU time 1.24 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207556 kb
Host smart-b84efcd8-2464-45d5-ab7e-38d966b887f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38650
23098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3865023098
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3500640397
Short name T1497
Test name
Test status
Simulation time 924705576 ps
CPU time 2.63 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207660 kb
Host smart-847bd02e-c68e-40bb-8503-510354bc0851
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3500640397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3500640397
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.73411231
Short name T3026
Test name
Test status
Simulation time 43216969570 ps
CPU time 65.43 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:27:20 PM PDT 24
Peak memory 207740 kb
Host smart-78e5d2bc-2735-48de-92ff-deca44151a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73411
231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.73411231
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2576357080
Short name T22
Test name
Test status
Simulation time 971688898 ps
CPU time 23.39 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207728 kb
Host smart-eaf941a2-bc08-49af-abd5-c4b3caa9975c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576357080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2576357080
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1338736986
Short name T1677
Test name
Test status
Simulation time 402721221 ps
CPU time 1.25 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207424 kb
Host smart-2a35f97e-9e33-4ae4-b894-f968afadc90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13387
36986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1338736986
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1179827192
Short name T2956
Test name
Test status
Simulation time 194881789 ps
CPU time 0.84 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207520 kb
Host smart-041d3a75-2cb0-476e-a565-269f9660c3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11798
27192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1179827192
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2457807557
Short name T2525
Test name
Test status
Simulation time 73929034 ps
CPU time 0.75 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207408 kb
Host smart-585d14e8-5524-4afe-be5d-fff97a91f605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
07557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2457807557
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.108623031
Short name T2635
Test name
Test status
Simulation time 727995933 ps
CPU time 2.26 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207676 kb
Host smart-0e451bc1-6bda-46f8-9e99-c98e3bd10f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10862
3031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.108623031
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.2451755203
Short name T498
Test name
Test status
Simulation time 157796269 ps
CPU time 0.89 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207472 kb
Host smart-51c9d821-a8d2-491f-96bf-3b098da17d25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2451755203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.2451755203
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.645414549
Short name T2874
Test name
Test status
Simulation time 189907525 ps
CPU time 1.51 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207672 kb
Host smart-56747a29-90f0-406a-9f0a-f199ee3b6bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64541
4549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.645414549
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.1484891575
Short name T2039
Test name
Test status
Simulation time 110230852842 ps
CPU time 159.26 seconds
Started Aug 09 05:26:17 PM PDT 24
Finished Aug 09 05:28:56 PM PDT 24
Peak memory 207784 kb
Host smart-6c09730a-3fc5-488e-82c6-8c5a58a14953
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1484891575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.1484891575
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2693308795
Short name T3466
Test name
Test status
Simulation time 104070920334 ps
CPU time 176.4 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:29:08 PM PDT 24
Peak memory 207792 kb
Host smart-5006a97d-e079-4f8c-b993-e28745cd48d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693308795 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2693308795
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2836176728
Short name T1351
Test name
Test status
Simulation time 106101322163 ps
CPU time 176.27 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:29:05 PM PDT 24
Peak memory 207804 kb
Host smart-d43e517e-7dca-41e9-8a79-01b5db0fe827
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2836176728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2836176728
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3278949823
Short name T2394
Test name
Test status
Simulation time 80979557463 ps
CPU time 145.72 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207796 kb
Host smart-d440060b-4167-4c82-baf7-700733b7846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278949823 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3278949823
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2380031562
Short name T1909
Test name
Test status
Simulation time 114143237587 ps
CPU time 191.98 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:29:26 PM PDT 24
Peak memory 207708 kb
Host smart-611f6a29-3c39-4e4b-a054-378d9159e156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23800
31562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2380031562
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1674881768
Short name T3371
Test name
Test status
Simulation time 178435109 ps
CPU time 1.01 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 215756 kb
Host smart-85e0eacd-2479-417f-bf9e-9a6c5fea615d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1674881768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1674881768
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3541111178
Short name T2932
Test name
Test status
Simulation time 165830015 ps
CPU time 0.85 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207412 kb
Host smart-a0dd297a-5e6e-4c6c-90db-739869cdb980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35411
11178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3541111178
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1296345577
Short name T595
Test name
Test status
Simulation time 199689082 ps
CPU time 0.93 seconds
Started Aug 09 05:26:06 PM PDT 24
Finished Aug 09 05:26:07 PM PDT 24
Peak memory 207412 kb
Host smart-e383a0bc-5aff-4598-9fdb-8f828d9b0eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12963
45577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1296345577
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3145242417
Short name T1806
Test name
Test status
Simulation time 4173250250 ps
CPU time 31.68 seconds
Started Aug 09 05:26:10 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 217520 kb
Host smart-ec2f2900-42f3-43ae-acde-3ad7e8af9b4e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3145242417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3145242417
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.1695869266
Short name T536
Test name
Test status
Simulation time 7552497505 ps
CPU time 83.38 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207808 kb
Host smart-3ac4f866-314b-40df-9d24-d599e5c621c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1695869266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1695869266
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1663442908
Short name T3190
Test name
Test status
Simulation time 221243984 ps
CPU time 1.01 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207524 kb
Host smart-6ceaa32c-9099-438a-a74f-2e8959f6531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16634
42908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1663442908
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.4146142836
Short name T1168
Test name
Test status
Simulation time 7691466460 ps
CPU time 11.08 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207768 kb
Host smart-a5a38467-3585-44d8-9d8e-b34acdd87a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
42836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.4146142836
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1304676197
Short name T683
Test name
Test status
Simulation time 5985608063 ps
CPU time 8.76 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 207640 kb
Host smart-f2f4b9aa-2d04-4e51-ae81-8d3e90a9063a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
76197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1304676197
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.779141615
Short name T2455
Test name
Test status
Simulation time 3999877091 ps
CPU time 39.48 seconds
Started Aug 09 05:26:07 PM PDT 24
Finished Aug 09 05:26:47 PM PDT 24
Peak memory 216004 kb
Host smart-13fe49b2-fd92-49a8-80df-4f89975fee71
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=779141615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.779141615
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.472981451
Short name T897
Test name
Test status
Simulation time 241690878 ps
CPU time 1.05 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207520 kb
Host smart-501505c3-5361-4ef0-85b7-cd79dbc316b7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=472981451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.472981451
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1271162746
Short name T3253
Test name
Test status
Simulation time 186930541 ps
CPU time 0.96 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:26:09 PM PDT 24
Peak memory 207536 kb
Host smart-3346cc45-d252-4149-98a8-83226625b51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
62746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1271162746
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.2123102098
Short name T833
Test name
Test status
Simulation time 3358560865 ps
CPU time 98.61 seconds
Started Aug 09 05:26:08 PM PDT 24
Finished Aug 09 05:27:47 PM PDT 24
Peak memory 224216 kb
Host smart-33f7ed06-87ad-48d1-8dcd-1052b57c303d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
02098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.2123102098
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3762436325
Short name T2690
Test name
Test status
Simulation time 1893365544 ps
CPU time 13.96 seconds
Started Aug 09 05:26:04 PM PDT 24
Finished Aug 09 05:26:18 PM PDT 24
Peak memory 207676 kb
Host smart-1c575c46-1204-4e8a-8c70-d11ece373412
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3762436325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3762436325
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3500602145
Short name T1621
Test name
Test status
Simulation time 2981336883 ps
CPU time 32.34 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 217732 kb
Host smart-c0b276ab-add4-4782-a16c-0b1ce67c3e0f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3500602145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3500602145
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1289855884
Short name T845
Test name
Test status
Simulation time 191085258 ps
CPU time 0.98 seconds
Started Aug 09 05:26:10 PM PDT 24
Finished Aug 09 05:26:11 PM PDT 24
Peak memory 207480 kb
Host smart-c1c50b2e-ed3f-475c-9458-e4f42c64ce1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1289855884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1289855884
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.71951699
Short name T310
Test name
Test status
Simulation time 164063859 ps
CPU time 0.84 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207484 kb
Host smart-8cb38080-91af-4897-aa3e-02b1f43863dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71951
699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.71951699
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2883377047
Short name T141
Test name
Test status
Simulation time 200231257 ps
CPU time 0.98 seconds
Started Aug 09 05:26:10 PM PDT 24
Finished Aug 09 05:26:11 PM PDT 24
Peak memory 207452 kb
Host smart-c051f2e8-fea4-4b16-bbbf-f6f7ead4df7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
77047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2883377047
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3905857470
Short name T2451
Test name
Test status
Simulation time 148714376 ps
CPU time 0.88 seconds
Started Aug 09 05:26:09 PM PDT 24
Finished Aug 09 05:26:10 PM PDT 24
Peak memory 207560 kb
Host smart-fedc432b-afe6-42c0-a89b-4d11ac275488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
57470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3905857470
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.522112308
Short name T1906
Test name
Test status
Simulation time 158617498 ps
CPU time 0.84 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207472 kb
Host smart-a2d87764-6447-4195-9188-10b3ff0e1363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52211
2308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.522112308
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3357199749
Short name T3554
Test name
Test status
Simulation time 171240801 ps
CPU time 0.89 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207428 kb
Host smart-a9081087-00ac-459f-9bfd-750f60f2a3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571
99749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3357199749
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3785166272
Short name T3260
Test name
Test status
Simulation time 143232771 ps
CPU time 0.84 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207432 kb
Host smart-5e07c6c8-810b-45fa-8ea2-6cc69bf8a0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
66272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3785166272
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.4047135453
Short name T1237
Test name
Test status
Simulation time 223954502 ps
CPU time 1.06 seconds
Started Aug 09 05:26:17 PM PDT 24
Finished Aug 09 05:26:18 PM PDT 24
Peak memory 207460 kb
Host smart-1eb60e5b-3234-4241-bfdc-2c690160f795
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4047135453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.4047135453
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3311288307
Short name T672
Test name
Test status
Simulation time 235038028 ps
CPU time 1.06 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207392 kb
Host smart-325eac23-3d37-4cf8-99fd-3dbd6d809c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33112
88307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3311288307
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2914803414
Short name T831
Test name
Test status
Simulation time 205418571 ps
CPU time 1 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 207452 kb
Host smart-f9bd67fd-9d90-4938-9818-6aa36077a635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
03414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2914803414
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3991707227
Short name T2424
Test name
Test status
Simulation time 59310762 ps
CPU time 0.71 seconds
Started Aug 09 05:26:17 PM PDT 24
Finished Aug 09 05:26:18 PM PDT 24
Peak memory 207404 kb
Host smart-b2964730-2682-4095-b1ed-a241aa523474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39917
07227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3991707227
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1729634417
Short name T264
Test name
Test status
Simulation time 17473047753 ps
CPU time 40.93 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 215916 kb
Host smart-c28b4ab2-d122-4ad0-92ac-f92a860932e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17296
34417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1729634417
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2149297690
Short name T1301
Test name
Test status
Simulation time 143437764 ps
CPU time 0.84 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 207500 kb
Host smart-e9c8fbb9-91f8-4c54-84bb-efabb419e431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21492
97690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2149297690
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3665825737
Short name T3479
Test name
Test status
Simulation time 240398169 ps
CPU time 1.04 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 207540 kb
Host smart-f879bee2-f4f1-4f4b-ac7e-6400581501a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
25737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3665825737
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3865846162
Short name T1722
Test name
Test status
Simulation time 2348290567 ps
CPU time 20.83 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 224224 kb
Host smart-1f508677-3ddc-4ef0-a761-e0458e31b852
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865846162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3865846162
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1478097100
Short name T2030
Test name
Test status
Simulation time 19211033966 ps
CPU time 453.02 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:33:47 PM PDT 24
Peak memory 219652 kb
Host smart-fa9bfc89-7859-4498-9697-43d3e9c1a7c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1478097100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1478097100
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.1162907033
Short name T1273
Test name
Test status
Simulation time 6007772853 ps
CPU time 68.93 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:27:20 PM PDT 24
Peak memory 219184 kb
Host smart-ae90c443-04ed-4e38-ad98-61c6100588f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162907033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1162907033
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3511754193
Short name T3576
Test name
Test status
Simulation time 271324069 ps
CPU time 1.01 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207360 kb
Host smart-3fc19e8f-8d3b-4dab-855d-f0bdab8ffbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35117
54193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3511754193
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3976377217
Short name T2913
Test name
Test status
Simulation time 160535846 ps
CPU time 0.89 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:24 PM PDT 24
Peak memory 207560 kb
Host smart-1510cb58-98a2-4721-a1ac-f5e970dbc49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39763
77217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3976377217
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.3593204387
Short name T3129
Test name
Test status
Simulation time 20163896434 ps
CPU time 26.41 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:49 PM PDT 24
Peak memory 207640 kb
Host smart-6b1198d9-6d2d-495a-9c4e-6f1c65aa9fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932
04387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.3593204387
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2728519395
Short name T1110
Test name
Test status
Simulation time 160739026 ps
CPU time 0.88 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 206488 kb
Host smart-f934ea88-170e-4172-9c10-ada87f04d42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
19395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2728519395
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.2072489804
Short name T1003
Test name
Test status
Simulation time 251360875 ps
CPU time 1.14 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207508 kb
Host smart-0a8309de-b487-4124-b439-93741a6d2a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
89804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.2072489804
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2332868363
Short name T75
Test name
Test status
Simulation time 202931019 ps
CPU time 0.91 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 207504 kb
Host smart-c8b36f56-f085-42ba-b4f9-5869a5cb61fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23328
68363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2332868363
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2820987661
Short name T217
Test name
Test status
Simulation time 1272452553 ps
CPU time 2.2 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 224592 kb
Host smart-9262b96a-8dd8-4abc-85c3-57e6b6600193
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2820987661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2820987661
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.4115388124
Short name T49
Test name
Test status
Simulation time 387594528 ps
CPU time 1.51 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 207472 kb
Host smart-ab49a8e9-25f3-4282-a1d9-29dba2c7d2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
88124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.4115388124
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3672904166
Short name T169
Test name
Test status
Simulation time 208557047 ps
CPU time 1.02 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 207472 kb
Host smart-777f65b0-96c3-429f-9267-6684c7da3f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
04166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3672904166
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1199509074
Short name T1491
Test name
Test status
Simulation time 168631752 ps
CPU time 0.84 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207528 kb
Host smart-9d9ff8d1-2577-44c0-ac6f-81a2370b28ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11995
09074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1199509074
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2798821619
Short name T2977
Test name
Test status
Simulation time 158442113 ps
CPU time 0.85 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207504 kb
Host smart-c16d2df3-0dbc-4ecf-a2c6-c2ac3db84024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
21619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2798821619
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2453413567
Short name T2299
Test name
Test status
Simulation time 258002028 ps
CPU time 1.19 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207396 kb
Host smart-25ad5ba4-a17d-49c3-8af9-6358a7c6e672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24534
13567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2453413567
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1235658344
Short name T2654
Test name
Test status
Simulation time 3176282534 ps
CPU time 94.6 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:27:48 PM PDT 24
Peak memory 224088 kb
Host smart-0275ed65-6a40-4e8a-9292-e76369e3c8d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1235658344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1235658344
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2043420076
Short name T1916
Test name
Test status
Simulation time 167979230 ps
CPU time 0.85 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207552 kb
Host smart-bb6e63ed-ecf5-48b7-bb1f-ae9b5cafdf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20434
20076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2043420076
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.498440066
Short name T3399
Test name
Test status
Simulation time 177396389 ps
CPU time 0.9 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207476 kb
Host smart-2d2cb05b-8dde-4131-9318-981d4e7178e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49844
0066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.498440066
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2314966599
Short name T3222
Test name
Test status
Simulation time 452890456 ps
CPU time 1.54 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207528 kb
Host smart-88e37d3c-5179-4604-89b4-67b3e5517d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
66599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2314966599
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.124401904
Short name T2711
Test name
Test status
Simulation time 3727220359 ps
CPU time 103.99 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 215912 kb
Host smart-90ee04c2-23a5-489f-a633-8d587dee173d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
1904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.124401904
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1623185955
Short name T1002
Test name
Test status
Simulation time 4363235797 ps
CPU time 29.94 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207812 kb
Host smart-6732edd3-3dee-41b5-8f91-2b53d024459f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623185955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.1623185955
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.4205977766
Short name T1111
Test name
Test status
Simulation time 484268210 ps
CPU time 1.46 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207508 kb
Host smart-ce7d307a-eb36-4cff-9c6a-46d18a840ebf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205977766 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.4205977766
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2334214268
Short name T613
Test name
Test status
Simulation time 65560006 ps
CPU time 0.7 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 207668 kb
Host smart-d1adfa39-d14e-4113-b67b-7f07b2055baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2334214268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2334214268
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2547382581
Short name T3558
Test name
Test status
Simulation time 5564058177 ps
CPU time 8.42 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 215996 kb
Host smart-ff65f5a4-f985-4849-9fa3-aafd6ff697ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547382581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.2547382581
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1193549080
Short name T3085
Test name
Test status
Simulation time 15029979118 ps
CPU time 16.42 seconds
Started Aug 09 05:30:09 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 215876 kb
Host smart-ea3a546c-8558-40b5-89ed-465624a0cd0c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193549080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1193549080
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.3967488857
Short name T2758
Test name
Test status
Simulation time 24445740083 ps
CPU time 28.82 seconds
Started Aug 09 05:30:06 PM PDT 24
Finished Aug 09 05:30:35 PM PDT 24
Peak memory 215904 kb
Host smart-193a7c0f-4daf-44c1-b91d-ef78e2fc2ad8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967488857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.3967488857
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3976058050
Short name T1780
Test name
Test status
Simulation time 171788163 ps
CPU time 0.89 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207540 kb
Host smart-d15b48da-3c5b-4c9c-9164-9099cadb7fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
58050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3976058050
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2400406197
Short name T3367
Test name
Test status
Simulation time 145415545 ps
CPU time 0.87 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207496 kb
Host smart-8a283f16-4d93-472e-8f9c-2cc762a259fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24004
06197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2400406197
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2874257686
Short name T1559
Test name
Test status
Simulation time 327168429 ps
CPU time 1.22 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207464 kb
Host smart-bd71d49b-29c8-4279-9da0-f9bb638a1717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
57686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2874257686
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1663863881
Short name T312
Test name
Test status
Simulation time 1007647136 ps
CPU time 2.83 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207720 kb
Host smart-75566039-d8dd-422e-b02b-06da88af33f6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1663863881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1663863881
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1711571865
Short name T350
Test name
Test status
Simulation time 52559498309 ps
CPU time 91.89 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:31:44 PM PDT 24
Peak memory 207740 kb
Host smart-765df47c-365d-441e-8b5b-32612ed5ebbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17115
71865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1711571865
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3501113850
Short name T2737
Test name
Test status
Simulation time 1526433885 ps
CPU time 13.7 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 207940 kb
Host smart-e1002cd8-355c-425d-992d-9d65be682bf1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501113850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3501113850
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3950714229
Short name T2161
Test name
Test status
Simulation time 871401230 ps
CPU time 2.02 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207476 kb
Host smart-c3fafea7-fe26-45a4-8993-f42146b1668f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
14229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3950714229
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3085442994
Short name T2415
Test name
Test status
Simulation time 149227267 ps
CPU time 0.83 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207412 kb
Host smart-2f0a4cb8-ddd4-48e2-a393-bfd841082ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
42994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3085442994
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1547535107
Short name T2579
Test name
Test status
Simulation time 36475815 ps
CPU time 0.72 seconds
Started Aug 09 05:30:18 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207504 kb
Host smart-f26fda2f-fe9e-4c8e-9b07-30327bde7f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
35107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1547535107
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.219923512
Short name T1430
Test name
Test status
Simulation time 972963119 ps
CPU time 2.59 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207724 kb
Host smart-db106382-78ff-45f2-aa4c-0eecd4dc359e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
3512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.219923512
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.511394155
Short name T422
Test name
Test status
Simulation time 463441957 ps
CPU time 1.38 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207356 kb
Host smart-ea09a0b6-dfea-4520-9b94-af3032c6c09f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=511394155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.511394155
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1414634270
Short name T3415
Test name
Test status
Simulation time 354864981 ps
CPU time 2.64 seconds
Started Aug 09 05:30:10 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207708 kb
Host smart-5bc77fc4-624f-4550-8a75-c396c98d97fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14146
34270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1414634270
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1788237904
Short name T2453
Test name
Test status
Simulation time 194908712 ps
CPU time 1.04 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 215852 kb
Host smart-c5344f73-672b-48d6-ba9b-b24d97d94048
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1788237904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1788237904
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1090553596
Short name T1250
Test name
Test status
Simulation time 165394040 ps
CPU time 0.9 seconds
Started Aug 09 05:30:07 PM PDT 24
Finished Aug 09 05:30:08 PM PDT 24
Peak memory 207440 kb
Host smart-6a1769e7-310c-477c-baac-90e2f098f4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
53596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1090553596
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3421555403
Short name T3550
Test name
Test status
Simulation time 200401910 ps
CPU time 0.94 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207496 kb
Host smart-9f7d835b-0ebd-45e9-93ab-41b4bda59c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215
55403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3421555403
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.3685655083
Short name T3039
Test name
Test status
Simulation time 3700177824 ps
CPU time 27.6 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 224256 kb
Host smart-d13e0afc-45d4-4e3e-953f-7656fa286b99
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3685655083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.3685655083
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.82967515
Short name T2230
Test name
Test status
Simulation time 13468632634 ps
CPU time 156.09 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207692 kb
Host smart-c1d51982-148c-40f4-98b2-43fdbea58983
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=82967515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.82967515
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.662908027
Short name T2189
Test name
Test status
Simulation time 174661361 ps
CPU time 0.93 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207408 kb
Host smart-faa8a892-9a87-4e41-9ece-0e9ee630fc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66290
8027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.662908027
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1635259836
Short name T94
Test name
Test status
Simulation time 27211884221 ps
CPU time 39.6 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:56 PM PDT 24
Peak memory 207744 kb
Host smart-88a6c33c-cffd-467f-a629-8ac53d41bd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
59836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1635259836
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1286607553
Short name T2526
Test name
Test status
Simulation time 6053172785 ps
CPU time 7.68 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 216036 kb
Host smart-2c5673fb-bf92-4ac3-b457-976f6e627bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12866
07553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1286607553
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1695062370
Short name T2616
Test name
Test status
Simulation time 3376825032 ps
CPU time 33.56 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 218896 kb
Host smart-add7c6bc-3cd5-444e-a4cb-7f60d719dc95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1695062370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1695062370
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1412184234
Short name T2211
Test name
Test status
Simulation time 3893564579 ps
CPU time 28.74 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 216040 kb
Host smart-f3c12e70-8e70-4ea1-8e61-fea37d4ac5ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1412184234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1412184234
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3592551594
Short name T1890
Test name
Test status
Simulation time 232304104 ps
CPU time 1.02 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207484 kb
Host smart-860a7327-94a3-4c2c-892a-fd7995c18c96
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3592551594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3592551594
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1759657803
Short name T1946
Test name
Test status
Simulation time 238556563 ps
CPU time 1.06 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207436 kb
Host smart-1fc5e6fc-65e6-4b85-8d0a-588c7f6e4551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17596
57803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1759657803
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.704356442
Short name T717
Test name
Test status
Simulation time 2339299745 ps
CPU time 18.6 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:32 PM PDT 24
Peak memory 217816 kb
Host smart-b52e1037-eec6-4f3a-984a-63affe7f5782
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=704356442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.704356442
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3519232244
Short name T2660
Test name
Test status
Simulation time 181392225 ps
CPU time 0.95 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207500 kb
Host smart-91aac1ab-1d48-4ab9-95e1-e5e0313d87ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3519232244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3519232244
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.985087194
Short name T2187
Test name
Test status
Simulation time 152572841 ps
CPU time 0.85 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207508 kb
Host smart-802b57e1-49e9-4fa0-9eaa-de6c6c0e509e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98508
7194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.985087194
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1759998116
Short name T3347
Test name
Test status
Simulation time 211113511 ps
CPU time 0.93 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207440 kb
Host smart-09579cd3-4e3c-4c1c-b223-4eb8e76f0d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17599
98116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1759998116
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.340494074
Short name T3326
Test name
Test status
Simulation time 192399190 ps
CPU time 0.92 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207432 kb
Host smart-679f40d9-b787-4843-a266-f8b2352273b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34049
4074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.340494074
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.829498754
Short name T1963
Test name
Test status
Simulation time 184159154 ps
CPU time 0.89 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207556 kb
Host smart-54bc11d7-4259-4a91-8521-ac868e6d158e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82949
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.829498754
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1673008013
Short name T2157
Test name
Test status
Simulation time 176952010 ps
CPU time 0.9 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207404 kb
Host smart-09c37aa9-f0d2-4ea4-8aac-1c3384a7d3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16730
08013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1673008013
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3295110040
Short name T2305
Test name
Test status
Simulation time 165354409 ps
CPU time 0.88 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207464 kb
Host smart-19b171b7-f77d-48fe-891b-7067e389ddb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32951
10040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3295110040
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1391263058
Short name T2143
Test name
Test status
Simulation time 222840754 ps
CPU time 1.01 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207484 kb
Host smart-0313f358-cbc5-494e-8138-9e4f2dc8a4b3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1391263058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1391263058
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3842118805
Short name T2896
Test name
Test status
Simulation time 156305059 ps
CPU time 0.92 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207520 kb
Host smart-dc9a5a3f-417b-4404-a771-de91752b2d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
18805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3842118805
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1770587645
Short name T293
Test name
Test status
Simulation time 18992373928 ps
CPU time 46.26 seconds
Started Aug 09 05:30:08 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 215972 kb
Host smart-b3d38093-738e-463f-876b-13f619e19a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17705
87645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1770587645
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.928978143
Short name T1948
Test name
Test status
Simulation time 162235920 ps
CPU time 0.88 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 207492 kb
Host smart-dbe935af-eae1-4d3a-9794-c847bd48d1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92897
8143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.928978143
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3966446771
Short name T1741
Test name
Test status
Simulation time 171074948 ps
CPU time 0.91 seconds
Started Aug 09 05:30:18 PM PDT 24
Finished Aug 09 05:30:19 PM PDT 24
Peak memory 207436 kb
Host smart-383b6a8e-40f2-4958-8aac-348fa87690cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
46771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3966446771
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.191085800
Short name T2053
Test name
Test status
Simulation time 201085897 ps
CPU time 0.97 seconds
Started Aug 09 05:30:42 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 207440 kb
Host smart-4feb70a8-8c66-42ad-9537-5eab529409da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
5800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.191085800
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2918365287
Short name T3031
Test name
Test status
Simulation time 188214070 ps
CPU time 0.94 seconds
Started Aug 09 05:30:20 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 207444 kb
Host smart-3065324d-6297-41a4-9841-6eb59976d759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29183
65287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2918365287
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3652185511
Short name T923
Test name
Test status
Simulation time 206863735 ps
CPU time 0.95 seconds
Started Aug 09 05:30:11 PM PDT 24
Finished Aug 09 05:30:12 PM PDT 24
Peak memory 207396 kb
Host smart-27a85c1b-78dc-444e-9b65-407eb4f54873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36521
85511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3652185511
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.1712731376
Short name T2278
Test name
Test status
Simulation time 338659135 ps
CPU time 1.22 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:13 PM PDT 24
Peak memory 207504 kb
Host smart-39bb9596-ffa0-40b2-94a0-f8713a9c60e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127
31376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.1712731376
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2559384069
Short name T160
Test name
Test status
Simulation time 158823298 ps
CPU time 0.85 seconds
Started Aug 09 05:30:24 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207380 kb
Host smart-20737474-8587-485b-bb71-99b9cf8656f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25593
84069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2559384069
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.836761197
Short name T2594
Test name
Test status
Simulation time 143158576 ps
CPU time 0.88 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207504 kb
Host smart-760b4469-f4ce-4a70-b3de-40b3c0ae5ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83676
1197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.836761197
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.479431668
Short name T2783
Test name
Test status
Simulation time 247115720 ps
CPU time 1.02 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207492 kb
Host smart-889f74ea-91ed-4169-a0bb-b62aa4816c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47943
1668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.479431668
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1122063269
Short name T812
Test name
Test status
Simulation time 3364062234 ps
CPU time 33.88 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 224132 kb
Host smart-eee2917e-0cf1-419f-a280-0a4f86970b38
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1122063269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1122063269
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2727717648
Short name T3471
Test name
Test status
Simulation time 243427651 ps
CPU time 0.93 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207384 kb
Host smart-c7310fc7-d4a7-49be-a0d3-f7c870f98929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277
17648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2727717648
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4135149407
Short name T1830
Test name
Test status
Simulation time 196678258 ps
CPU time 0.91 seconds
Started Aug 09 05:30:34 PM PDT 24
Finished Aug 09 05:30:35 PM PDT 24
Peak memory 207484 kb
Host smart-4d6cc951-f2c7-478b-8ad3-fe9ccfb69bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41351
49407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4135149407
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.270948577
Short name T1529
Test name
Test status
Simulation time 1103626650 ps
CPU time 2.56 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207520 kb
Host smart-e35e1d16-ac06-429c-aade-d4b3e869763c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27094
8577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.270948577
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3289852194
Short name T3580
Test name
Test status
Simulation time 1619700520 ps
CPU time 43.98 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 224052 kb
Host smart-f584fee6-370c-41c2-87f4-c1051bcf885d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
52194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3289852194
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.3655041281
Short name T2670
Test name
Test status
Simulation time 2948712712 ps
CPU time 19.09 seconds
Started Aug 09 05:30:12 PM PDT 24
Finished Aug 09 05:30:32 PM PDT 24
Peak memory 207724 kb
Host smart-8068db5a-12d1-4e9b-a357-a7352d8c376f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655041281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.3655041281
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.1520653727
Short name T1083
Test name
Test status
Simulation time 654513593 ps
CPU time 1.77 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207448 kb
Host smart-ac39bc9a-4efd-4bdd-a250-0e35bb6d91b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520653727 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.1520653727
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.4265320419
Short name T1911
Test name
Test status
Simulation time 535153191 ps
CPU time 1.54 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207444 kb
Host smart-1609b945-12b8-4368-a5ee-05ff67c21d00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265320419 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.4265320419
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.3142843293
Short name T2589
Test name
Test status
Simulation time 610107033 ps
CPU time 1.81 seconds
Started Aug 09 05:33:42 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 207500 kb
Host smart-7003a4ee-9ad9-4965-86e1-8a3fb911e94f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142843293 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.3142843293
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.3403566710
Short name T2314
Test name
Test status
Simulation time 575528527 ps
CPU time 1.78 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207484 kb
Host smart-502ca8e8-37dc-4282-8708-3bec9dd40d74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403566710 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.3403566710
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.1246492358
Short name T2319
Test name
Test status
Simulation time 491844032 ps
CPU time 1.48 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 207464 kb
Host smart-80752602-3ae4-4bc2-97d3-13355fd3351f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246492358 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.1246492358
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.2065859227
Short name T3527
Test name
Test status
Simulation time 474716005 ps
CPU time 1.52 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207564 kb
Host smart-9d3d7925-8c99-4c11-86c1-0a2fb031657d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065859227 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.2065859227
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.1111921677
Short name T3378
Test name
Test status
Simulation time 526944738 ps
CPU time 1.56 seconds
Started Aug 09 05:33:51 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207564 kb
Host smart-34c67f09-7cc4-48a4-b132-79a23a8771ef
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111921677 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.1111921677
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.444875933
Short name T1977
Test name
Test status
Simulation time 576704958 ps
CPU time 1.65 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207504 kb
Host smart-b9d11444-9bc4-462c-8386-8b6deb280299
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444875933 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.444875933
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.3145164509
Short name T962
Test name
Test status
Simulation time 443588210 ps
CPU time 1.33 seconds
Started Aug 09 05:33:45 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207464 kb
Host smart-b3cf68de-8e48-456a-9cce-a5c0f6fcdb58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145164509 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.3145164509
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.610442755
Short name T2721
Test name
Test status
Simulation time 387234591 ps
CPU time 1.39 seconds
Started Aug 09 05:33:42 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 207480 kb
Host smart-88448515-2991-4668-a0ec-15b3f4ac5531
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610442755 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.610442755
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.447798893
Short name T2092
Test name
Test status
Simulation time 459868725 ps
CPU time 1.39 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 207492 kb
Host smart-d570f869-f409-4194-8a6c-b6114adf8e05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447798893 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.447798893
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1680070600
Short name T1810
Test name
Test status
Simulation time 63276363 ps
CPU time 0.68 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:22 PM PDT 24
Peak memory 207532 kb
Host smart-9be10af7-1e80-478f-a017-f71b3259c9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1680070600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1680070600
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2697718225
Short name T1451
Test name
Test status
Simulation time 12325724242 ps
CPU time 16.17 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207836 kb
Host smart-a489bb10-0172-45c0-8a1a-976629413704
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697718225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.2697718225
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2177414447
Short name T2615
Test name
Test status
Simulation time 16037275463 ps
CPU time 19.58 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:55 PM PDT 24
Peak memory 215972 kb
Host smart-b40e989b-dc66-48b6-b31b-ef15dbab4c50
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177414447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2177414447
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1423020413
Short name T2541
Test name
Test status
Simulation time 26145631235 ps
CPU time 37.75 seconds
Started Aug 09 05:30:30 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 215960 kb
Host smart-e901f8e7-64d2-44b7-856d-0f34905dfb8d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423020413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.1423020413
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.395207297
Short name T2647
Test name
Test status
Simulation time 153881040 ps
CPU time 0.85 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207392 kb
Host smart-6c089e6e-f55f-46d5-aae3-1fe9cff6847b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39520
7297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.395207297
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1594891796
Short name T3217
Test name
Test status
Simulation time 198065287 ps
CPU time 0.9 seconds
Started Aug 09 05:30:17 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207468 kb
Host smart-1fa66909-69be-4b0a-ac6c-da7b46576f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
91796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1594891796
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.185583190
Short name T3474
Test name
Test status
Simulation time 479688860 ps
CPU time 1.56 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207392 kb
Host smart-37e1e474-5284-461c-ae46-85fbdbb051f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
3190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.185583190
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.575939398
Short name T3166
Test name
Test status
Simulation time 912559343 ps
CPU time 2.54 seconds
Started Aug 09 05:30:18 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 207704 kb
Host smart-2e2a0422-47f9-4a3b-a777-9589b1bb15f9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=575939398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.575939398
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.4151440918
Short name T1384
Test name
Test status
Simulation time 42187643296 ps
CPU time 62.32 seconds
Started Aug 09 05:30:30 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207852 kb
Host smart-63477ed2-77be-4965-b539-6da08b3893eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41514
40918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.4151440918
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.2471821219
Short name T1919
Test name
Test status
Simulation time 4343082989 ps
CPU time 29.03 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 207688 kb
Host smart-bd0c4061-6fde-4a00-928a-0f09e30658a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471821219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.2471821219
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2135935906
Short name T1599
Test name
Test status
Simulation time 950388789 ps
CPU time 2.45 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 207520 kb
Host smart-aa487807-4f98-4e32-b22e-5f7d7433cbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
35906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2135935906
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2952661378
Short name T2544
Test name
Test status
Simulation time 145947326 ps
CPU time 0.83 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:27 PM PDT 24
Peak memory 207424 kb
Host smart-95e5b3fe-564e-417f-8d46-085d0c17b9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29526
61378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2952661378
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1412504856
Short name T2724
Test name
Test status
Simulation time 46695682 ps
CPU time 0.75 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207476 kb
Host smart-e80f809e-ac5c-4742-bce3-664ade4a53a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14125
04856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1412504856
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.4074209121
Short name T2858
Test name
Test status
Simulation time 941773426 ps
CPU time 2.31 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207672 kb
Host smart-2be826a7-b25b-4cef-88db-83b8277c43ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40742
09121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.4074209121
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.2980535044
Short name T482
Test name
Test status
Simulation time 176780916 ps
CPU time 0.93 seconds
Started Aug 09 05:30:30 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 207392 kb
Host smart-2ccff448-2633-41f0-b8e9-81624fd02503
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2980535044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.2980535044
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1255189928
Short name T1709
Test name
Test status
Simulation time 225555918 ps
CPU time 1.38 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207692 kb
Host smart-9cb36004-2c05-414e-a25a-655a9cbd7996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
89928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1255189928
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2058424941
Short name T2879
Test name
Test status
Simulation time 216114010 ps
CPU time 1.01 seconds
Started Aug 09 05:30:17 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207524 kb
Host smart-3a5c78f5-5618-40f4-8d57-bd1db59d8b0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2058424941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2058424941
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.718102432
Short name T561
Test name
Test status
Simulation time 145999764 ps
CPU time 0.83 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 207468 kb
Host smart-b3ab3066-38a3-4a2d-a482-4d36f89a95ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71810
2432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.718102432
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3221092738
Short name T2952
Test name
Test status
Simulation time 215800945 ps
CPU time 1.01 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207440 kb
Host smart-086a5a33-d478-4998-9869-2dbb0545d5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
92738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3221092738
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.3377438513
Short name T3452
Test name
Test status
Simulation time 6296629063 ps
CPU time 60.74 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:31:28 PM PDT 24
Peak memory 217724 kb
Host smart-cf3c02e7-51c6-4af5-abad-5ae709587517
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3377438513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.3377438513
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.3460515881
Short name T2764
Test name
Test status
Simulation time 6196539946 ps
CPU time 78.06 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207720 kb
Host smart-7bd197c2-e688-4265-bf2f-5cdafc733191
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3460515881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.3460515881
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3428141806
Short name T971
Test name
Test status
Simulation time 205167490 ps
CPU time 0.91 seconds
Started Aug 09 05:30:20 PM PDT 24
Finished Aug 09 05:30:21 PM PDT 24
Peak memory 207552 kb
Host smart-b6280b86-5657-4d94-a05b-fbc7f8e41081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
41806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3428141806
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1544962372
Short name T3373
Test name
Test status
Simulation time 34384926868 ps
CPU time 52.1 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207888 kb
Host smart-806994c0-f6b5-4e68-b3bd-ebdc2392e5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
62372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1544962372
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2573915463
Short name T1816
Test name
Test status
Simulation time 10572753021 ps
CPU time 14.22 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207740 kb
Host smart-5b333c90-f819-4e23-9e0d-3cc7d41b1996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
15463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2573915463
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3474989924
Short name T2802
Test name
Test status
Simulation time 4361564755 ps
CPU time 122.01 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:32:23 PM PDT 24
Peak memory 215984 kb
Host smart-a9141647-49eb-4d85-874f-b9157577f75c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3474989924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3474989924
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1719069284
Short name T2469
Test name
Test status
Simulation time 2761918311 ps
CPU time 22.05 seconds
Started Aug 09 05:30:24 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 217744 kb
Host smart-7cbc1dd6-202b-4d2b-b455-eb90fb842d8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1719069284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1719069284
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2678890600
Short name T1464
Test name
Test status
Simulation time 268238515 ps
CPU time 1.07 seconds
Started Aug 09 05:30:29 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 207512 kb
Host smart-9d23ca67-dff8-4894-988a-0974a8572863
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2678890600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2678890600
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3579037717
Short name T1370
Test name
Test status
Simulation time 247812892 ps
CPU time 0.98 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:16 PM PDT 24
Peak memory 207476 kb
Host smart-7e25afee-4e28-4537-b72e-30b1439a016d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
37717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3579037717
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4223042531
Short name T2413
Test name
Test status
Simulation time 2462552626 ps
CPU time 23.19 seconds
Started Aug 09 05:30:34 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 217280 kb
Host smart-22cfee1d-5c1c-4cb2-b2a0-a5b9f5685f62
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4223042531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4223042531
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3015259175
Short name T544
Test name
Test status
Simulation time 164907827 ps
CPU time 0.86 seconds
Started Aug 09 05:30:14 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207388 kb
Host smart-981ee156-53ce-422c-8e2f-31fafeb9e178
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3015259175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3015259175
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3862229289
Short name T2490
Test name
Test status
Simulation time 145923863 ps
CPU time 0.84 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207508 kb
Host smart-33cc8823-6024-4bf8-a070-d5604f3a6366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
29289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3862229289
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2720964181
Short name T1611
Test name
Test status
Simulation time 162275821 ps
CPU time 0.89 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:14 PM PDT 24
Peak memory 207504 kb
Host smart-997fc673-45e0-4e95-9b31-36bbb66845e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27209
64181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2720964181
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.490824868
Short name T2417
Test name
Test status
Simulation time 192027310 ps
CPU time 0.94 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:40 PM PDT 24
Peak memory 207452 kb
Host smart-2e6a0fd8-8d4f-4e88-9d6a-31d8f0f13d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49082
4868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.490824868
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1210750273
Short name T2514
Test name
Test status
Simulation time 158221679 ps
CPU time 0.81 seconds
Started Aug 09 05:30:20 PM PDT 24
Finished Aug 09 05:30:20 PM PDT 24
Peak memory 207500 kb
Host smart-fc581f3e-880f-44e2-8761-09f15eb7054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
50273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1210750273
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1202297858
Short name T2238
Test name
Test status
Simulation time 225764873 ps
CPU time 0.89 seconds
Started Aug 09 05:30:13 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207500 kb
Host smart-0a83a0f3-7291-4e46-b870-575f59206247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
97858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1202297858
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1748179604
Short name T741
Test name
Test status
Simulation time 239381344 ps
CPU time 1.02 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207428 kb
Host smart-cee0d93f-5554-4262-a584-e4b1c0c58399
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1748179604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1748179604
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.75827358
Short name T3494
Test name
Test status
Simulation time 146929495 ps
CPU time 0.82 seconds
Started Aug 09 05:30:15 PM PDT 24
Finished Aug 09 05:30:15 PM PDT 24
Peak memory 207480 kb
Host smart-d7fc67d8-f0e4-42b5-8228-2d0d51c62a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75827
358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.75827358
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2062834735
Short name T26
Test name
Test status
Simulation time 48383357 ps
CPU time 0.7 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:40 PM PDT 24
Peak memory 207444 kb
Host smart-bb0f2692-4531-4c4d-b023-8f581c10ddb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
34735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2062834735
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1117820131
Short name T1684
Test name
Test status
Simulation time 7722712547 ps
CPU time 21.34 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 216240 kb
Host smart-795145d3-034a-40b0-ba5b-33807e7fcf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
20131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1117820131
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.392399171
Short name T1614
Test name
Test status
Simulation time 181913419 ps
CPU time 0.91 seconds
Started Aug 09 05:30:30 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 207496 kb
Host smart-3829ca4f-4b16-4618-82ce-354a4bfcf684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39239
9171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.392399171
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1975535173
Short name T3375
Test name
Test status
Simulation time 260139687 ps
CPU time 1 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207428 kb
Host smart-2c84a906-0fe2-4987-9361-23f325689baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
35173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1975535173
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3802794653
Short name T3327
Test name
Test status
Simulation time 202005600 ps
CPU time 0.95 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 207504 kb
Host smart-98b64e01-b0f4-4916-b3c2-2186d9af4119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38027
94653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3802794653
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3472878902
Short name T2740
Test name
Test status
Simulation time 183449917 ps
CPU time 0.91 seconds
Started Aug 09 05:30:29 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207476 kb
Host smart-59e5f6f3-fa84-468c-9033-488f59f9ea5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
78902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3472878902
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.844808105
Short name T3374
Test name
Test status
Simulation time 171234166 ps
CPU time 0.85 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:22 PM PDT 24
Peak memory 207508 kb
Host smart-23ae6eae-a5db-4f73-828e-b74413d41a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84480
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.844808105
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.1310875422
Short name T2964
Test name
Test status
Simulation time 249162467 ps
CPU time 1.16 seconds
Started Aug 09 05:30:29 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 207492 kb
Host smart-0b5fdd95-c180-49f9-9cb2-7c1ea29c8902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
75422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.1310875422
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1634557875
Short name T3438
Test name
Test status
Simulation time 145100606 ps
CPU time 0.82 seconds
Started Aug 09 05:30:18 PM PDT 24
Finished Aug 09 05:30:18 PM PDT 24
Peak memory 207476 kb
Host smart-19737d4b-76e3-402e-a65e-40190e4fcac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16345
57875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1634557875
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4283698780
Short name T3359
Test name
Test status
Simulation time 167697589 ps
CPU time 0.87 seconds
Started Aug 09 05:30:16 PM PDT 24
Finished Aug 09 05:30:17 PM PDT 24
Peak memory 207552 kb
Host smart-e423d68c-a2eb-4e9e-acdc-cb98005af210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42836
98780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4283698780
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3367744066
Short name T3449
Test name
Test status
Simulation time 248886612 ps
CPU time 1.02 seconds
Started Aug 09 05:30:25 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207436 kb
Host smart-3f4a809b-dbc2-4b07-8ae4-7c79dcc34ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677
44066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3367744066
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.4274450839
Short name T2504
Test name
Test status
Simulation time 3176313732 ps
CPU time 26.27 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 216012 kb
Host smart-ee4b56f3-1fe0-4635-a490-d327a7611c50
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4274450839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.4274450839
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1764655157
Short name T2284
Test name
Test status
Simulation time 214761788 ps
CPU time 0.91 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207524 kb
Host smart-5d52fadc-598e-4004-87b5-604c2324f639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17646
55157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1764655157
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3079328022
Short name T630
Test name
Test status
Simulation time 161370841 ps
CPU time 0.89 seconds
Started Aug 09 05:30:25 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207552 kb
Host smart-a4ce5686-f609-41ac-b964-8663fff67f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
28022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3079328022
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.3871340905
Short name T624
Test name
Test status
Simulation time 368412121 ps
CPU time 1.28 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207380 kb
Host smart-6d881dbd-153f-47f2-8cf5-f30f07282be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713
40905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3871340905
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1400943627
Short name T356
Test name
Test status
Simulation time 3376461463 ps
CPU time 97.61 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 217712 kb
Host smart-817e8080-c45a-4fb9-afc6-5f3c00f97eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14009
43627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1400943627
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.4000406198
Short name T1173
Test name
Test status
Simulation time 550798569 ps
CPU time 11.64 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207628 kb
Host smart-b1198f79-4d5b-4997-af88-162734c6b9d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000406198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.4000406198
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.174106655
Short name T685
Test name
Test status
Simulation time 470321474 ps
CPU time 1.43 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:24 PM PDT 24
Peak memory 207444 kb
Host smart-37205adc-d3c2-4c13-9fd5-e6a49a2e3f43
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174106655 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.174106655
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.582251028
Short name T1482
Test name
Test status
Simulation time 603914256 ps
CPU time 1.55 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207496 kb
Host smart-90e878c0-8a35-41be-a7cf-d66779287bf7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582251028 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.582251028
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.3320984734
Short name T2790
Test name
Test status
Simulation time 478252341 ps
CPU time 1.42 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207540 kb
Host smart-f269c219-bc0f-44b0-b179-a547d343aacc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320984734 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.3320984734
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.517227766
Short name T2984
Test name
Test status
Simulation time 616668248 ps
CPU time 1.63 seconds
Started Aug 09 05:34:10 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 207424 kb
Host smart-07fc3a64-12ef-4068-b8f7-49e332ca8ae2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517227766 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.517227766
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.2016005114
Short name T1875
Test name
Test status
Simulation time 583206511 ps
CPU time 1.52 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207508 kb
Host smart-8dcb8e64-0087-4897-919d-f8d1d6f4616c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016005114 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.2016005114
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.1233771947
Short name T521
Test name
Test status
Simulation time 545131022 ps
CPU time 1.56 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207412 kb
Host smart-9c79ea96-3f49-47dc-931f-5ec639e4eb82
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233771947 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.1233771947
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.4014653335
Short name T2492
Test name
Test status
Simulation time 475127807 ps
CPU time 1.43 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207460 kb
Host smart-3d824361-c8ab-4400-b302-b9dcdbd247d1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014653335 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.4014653335
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.1175096227
Short name T2169
Test name
Test status
Simulation time 512545119 ps
CPU time 1.54 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207464 kb
Host smart-315ae4f5-5446-40c6-bfa5-a860be25a402
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175096227 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.1175096227
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.4087941700
Short name T165
Test name
Test status
Simulation time 453864686 ps
CPU time 1.47 seconds
Started Aug 09 05:33:45 PM PDT 24
Finished Aug 09 05:33:47 PM PDT 24
Peak memory 207472 kb
Host smart-bb70ac97-b1ff-415e-9d44-4005be279765
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087941700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.4087941700
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.2623946048
Short name T1759
Test name
Test status
Simulation time 498127304 ps
CPU time 1.49 seconds
Started Aug 09 05:34:10 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 207428 kb
Host smart-6a162b39-1091-4fc1-8d10-76c519965a0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623946048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.2623946048
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.1061144438
Short name T3610
Test name
Test status
Simulation time 530010999 ps
CPU time 1.82 seconds
Started Aug 09 05:34:03 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 207820 kb
Host smart-8a972721-d9b5-4b01-bc88-49235a99791d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061144438 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.1061144438
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3384438397
Short name T659
Test name
Test status
Simulation time 37077908 ps
CPU time 0.66 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:39 PM PDT 24
Peak memory 207396 kb
Host smart-6b4bb0e3-0edf-4cb4-894a-acffb9cf1c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3384438397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3384438397
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3981799411
Short name T13
Test name
Test status
Simulation time 10800509196 ps
CPU time 13.07 seconds
Started Aug 09 05:30:17 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207828 kb
Host smart-edc42c77-1797-4ee0-a4ae-e8ef7ea39447
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981799411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3981799411
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.4262079627
Short name T2209
Test name
Test status
Simulation time 15366397098 ps
CPU time 16.64 seconds
Started Aug 09 05:30:34 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 215836 kb
Host smart-8a0cf662-b3b5-4397-9ac8-8467d92a06fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262079627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.4262079627
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.527376973
Short name T1171
Test name
Test status
Simulation time 28861412024 ps
CPU time 33.55 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207764 kb
Host smart-9a9d7f62-876e-4329-b67e-114dd826e30d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527376973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_ao
n_wake_resume.527376973
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3935325884
Short name T1486
Test name
Test status
Simulation time 147429677 ps
CPU time 0.84 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:22 PM PDT 24
Peak memory 207528 kb
Host smart-37940d7b-776a-4d8b-9779-2c04748fb281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
25884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3935325884
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3314027209
Short name T1292
Test name
Test status
Simulation time 148271976 ps
CPU time 0.86 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 207644 kb
Host smart-3fe00333-b943-410b-9df6-eb1ad0fc3e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33140
27209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3314027209
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2979653345
Short name T1570
Test name
Test status
Simulation time 398389314 ps
CPU time 1.41 seconds
Started Aug 09 05:30:25 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207380 kb
Host smart-3a72321d-ba88-4ba6-9937-1ed5189e3914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
53345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2979653345
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.197529993
Short name T3547
Test name
Test status
Simulation time 413908940 ps
CPU time 1.35 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:32 PM PDT 24
Peak memory 207804 kb
Host smart-a0aeff64-eff9-4c2f-9ade-74bcf0580665
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=197529993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.197529993
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.114196002
Short name T349
Test name
Test status
Simulation time 15130322086 ps
CPU time 24.97 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 208096 kb
Host smart-06f33d36-bbab-495e-88b4-c7bf456d7613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11419
6002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.114196002
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.2900297353
Short name T565
Test name
Test status
Simulation time 1262707412 ps
CPU time 29.91 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207704 kb
Host smart-1a2f1e89-9432-4e70-b068-a9520e09ec9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900297353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.2900297353
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2588110969
Short name T2007
Test name
Test status
Simulation time 578940705 ps
CPU time 1.59 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207472 kb
Host smart-5555a457-7fa0-474d-b6a8-39632eb6a895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25881
10969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2588110969
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3237267597
Short name T3492
Test name
Test status
Simulation time 147187022 ps
CPU time 0.83 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207424 kb
Host smart-ad0d0fbc-7d2d-4f1c-a983-a9f48e3f9b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32372
67597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3237267597
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.958483973
Short name T1119
Test name
Test status
Simulation time 40210219 ps
CPU time 0.73 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207516 kb
Host smart-74b225c8-8e94-44fb-b220-9fd57ff9f001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95848
3973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.958483973
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.331968849
Short name T1844
Test name
Test status
Simulation time 766463407 ps
CPU time 2.13 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 207568 kb
Host smart-1844f7d4-4710-4f34-bc28-aacb32938cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33196
8849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.331968849
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.2153524237
Short name T858
Test name
Test status
Simulation time 259456054 ps
CPU time 1.08 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207488 kb
Host smart-95b7b458-021d-4596-83b5-eb65707ba8ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2153524237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.2153524237
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.806764806
Short name T607
Test name
Test status
Simulation time 157102598 ps
CPU time 1.37 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207692 kb
Host smart-fc798704-f665-4c48-985f-c5549f8572d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80676
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.806764806
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3345288251
Short name T2063
Test name
Test status
Simulation time 173256658 ps
CPU time 0.94 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 215920 kb
Host smart-01aec768-9b0a-4de4-88e9-9683fe1e3b8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3345288251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3345288251
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3642165006
Short name T2402
Test name
Test status
Simulation time 144336575 ps
CPU time 0.83 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207464 kb
Host smart-4dd74f37-8515-43ab-ac8b-3e6fb4affc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421
65006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3642165006
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2842863279
Short name T608
Test name
Test status
Simulation time 214014294 ps
CPU time 1 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:39 PM PDT 24
Peak memory 207480 kb
Host smart-aa6d4565-483c-4b2a-8281-b2fa0ec3b88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28428
63279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2842863279
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1646299045
Short name T891
Test name
Test status
Simulation time 2548855072 ps
CPU time 23.47 seconds
Started Aug 09 05:30:29 PM PDT 24
Finished Aug 09 05:30:53 PM PDT 24
Peak memory 217544 kb
Host smart-f86f2a12-00ce-4976-bdfb-0771d9496f5b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1646299045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1646299045
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.3541247564
Short name T1230
Test name
Test status
Simulation time 7776869272 ps
CPU time 55.08 seconds
Started Aug 09 05:30:23 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 206788 kb
Host smart-7fe8f85e-affa-436f-87dd-fb05d61d2aed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3541247564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3541247564
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3780478275
Short name T1907
Test name
Test status
Simulation time 210308770 ps
CPU time 0.99 seconds
Started Aug 09 05:30:24 PM PDT 24
Finished Aug 09 05:30:25 PM PDT 24
Peak memory 207440 kb
Host smart-b03de0dd-83cf-4c89-b080-275a544f6dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804
78275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3780478275
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2044804576
Short name T3170
Test name
Test status
Simulation time 7448244359 ps
CPU time 9.88 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 216024 kb
Host smart-a717e3bb-ae31-4134-8e6a-a56406c7eec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
04576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2044804576
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1420810476
Short name T1139
Test name
Test status
Simulation time 11289517934 ps
CPU time 15.41 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 207780 kb
Host smart-aef7b97b-892b-4d1c-89e3-5e99a08488a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
10476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1420810476
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1199983466
Short name T1220
Test name
Test status
Simulation time 4116630124 ps
CPU time 30.56 seconds
Started Aug 09 05:30:46 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 224124 kb
Host smart-4cb04aec-fbb7-4f66-872e-17deabeacd2a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1199983466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1199983466
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2951823753
Short name T1156
Test name
Test status
Simulation time 2225309619 ps
CPU time 63.52 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:31:29 PM PDT 24
Peak memory 224192 kb
Host smart-21969983-295f-45cb-ad48-ff2c8873e374
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2951823753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2951823753
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1392023643
Short name T3138
Test name
Test status
Simulation time 237871547 ps
CPU time 0.96 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207468 kb
Host smart-bf248083-4958-4655-8966-40debafba1e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1392023643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1392023643
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.4028100156
Short name T1502
Test name
Test status
Simulation time 192687105 ps
CPU time 0.92 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207492 kb
Host smart-c18fa0cb-dc12-4d28-807d-8c5283fc03a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40281
00156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.4028100156
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2495288235
Short name T2275
Test name
Test status
Simulation time 3518376612 ps
CPU time 96.32 seconds
Started Aug 09 05:30:24 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 217628 kb
Host smart-202bfe2c-37d8-437a-82d7-7a7d08a00d52
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2495288235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2495288235
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1666542529
Short name T3615
Test name
Test status
Simulation time 164111706 ps
CPU time 0.89 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 207468 kb
Host smart-ea01ce22-274e-431d-90ec-434ad885e4b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1666542529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1666542529
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.202622361
Short name T871
Test name
Test status
Simulation time 139446585 ps
CPU time 0.82 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:35 PM PDT 24
Peak memory 207412 kb
Host smart-ca8cabc3-ddc1-4a1b-8fb3-d7b6e50a8fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
2361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.202622361
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.175768167
Short name T3383
Test name
Test status
Simulation time 163637634 ps
CPU time 0.87 seconds
Started Aug 09 05:30:42 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 207472 kb
Host smart-ea20a702-8273-4c7e-9f59-2794eb3f5b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
8167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.175768167
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.504377390
Short name T1479
Test name
Test status
Simulation time 166775269 ps
CPU time 0.88 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207552 kb
Host smart-a9686d45-a79e-438f-bb5d-ab875a1de43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50437
7390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.504377390
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3528502966
Short name T1296
Test name
Test status
Simulation time 188135608 ps
CPU time 0.87 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:27 PM PDT 24
Peak memory 207508 kb
Host smart-4d772532-613e-4789-b3fc-eef311016e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35285
02966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3528502966
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.67987357
Short name T2447
Test name
Test status
Simulation time 207663708 ps
CPU time 0.95 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207492 kb
Host smart-5cf6d11a-6986-40fb-8217-6a55ac5dd51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67987
357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.67987357
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3304068393
Short name T2534
Test name
Test status
Simulation time 178714317 ps
CPU time 0.88 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207528 kb
Host smart-dc83f832-9c53-4362-8ed9-a1f6d2486095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
68393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3304068393
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2857829518
Short name T191
Test name
Test status
Simulation time 234160341 ps
CPU time 1.13 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207568 kb
Host smart-7880274e-4a4f-4a3e-9b04-423c66f1b0d7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2857829518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2857829518
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3101820381
Short name T1949
Test name
Test status
Simulation time 161346091 ps
CPU time 0.85 seconds
Started Aug 09 05:30:48 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 207384 kb
Host smart-5c66017f-927f-4e97-afe5-f03efde37eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31018
20381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3101820381
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1625956231
Short name T931
Test name
Test status
Simulation time 82822957 ps
CPU time 0.75 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 207328 kb
Host smart-91fb4a70-f048-47ee-8c30-7a1fa4aae94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259
56231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1625956231
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.129091032
Short name T3015
Test name
Test status
Simulation time 16832078999 ps
CPU time 48.04 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 224184 kb
Host smart-ac18a22d-1db3-4045-846e-cd8959a5a95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
1032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.129091032
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3610270312
Short name T335
Test name
Test status
Simulation time 199298344 ps
CPU time 0.91 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:27 PM PDT 24
Peak memory 207508 kb
Host smart-db903f19-e934-4359-8630-89ff56e519d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
70312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3610270312
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3283565056
Short name T3243
Test name
Test status
Simulation time 228535633 ps
CPU time 0.95 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207472 kb
Host smart-c51aa9d8-5038-49e0-b755-57c36d2ac86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32835
65056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3283565056
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.4264517077
Short name T3539
Test name
Test status
Simulation time 195345824 ps
CPU time 0.89 seconds
Started Aug 09 05:30:46 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207444 kb
Host smart-025b3961-a045-4770-bedb-78b1ec61edbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
17077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.4264517077
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2862920713
Short name T1007
Test name
Test status
Simulation time 165893557 ps
CPU time 0.89 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207492 kb
Host smart-c4ef0de9-a020-4605-b33f-c7833ed66218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28629
20713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2862920713
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.867474433
Short name T246
Test name
Test status
Simulation time 140595312 ps
CPU time 0.79 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207376 kb
Host smart-6810bccc-e735-4970-bec5-08c51fecce4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86747
4433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.867474433
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.1749617543
Short name T1134
Test name
Test status
Simulation time 267056400 ps
CPU time 1.15 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:30 PM PDT 24
Peak memory 207500 kb
Host smart-caece601-ec20-4261-b503-c76287ceb4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
17543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.1749617543
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3127732392
Short name T703
Test name
Test status
Simulation time 163884098 ps
CPU time 0.86 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:37 PM PDT 24
Peak memory 207400 kb
Host smart-e7b59494-c2cc-4553-9303-c302d06fb52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
32392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3127732392
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.728392184
Short name T2125
Test name
Test status
Simulation time 155568801 ps
CPU time 0.91 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207548 kb
Host smart-53fce106-d7c1-456c-921c-9614abeec782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72839
2184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.728392184
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3259576471
Short name T1303
Test name
Test status
Simulation time 220455145 ps
CPU time 1.07 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:30:39 PM PDT 24
Peak memory 207412 kb
Host smart-06cba0d4-8f83-496f-9b09-ea66404ab4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32595
76471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3259576471
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1444760428
Short name T2619
Test name
Test status
Simulation time 3108819578 ps
CPU time 86.58 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 223716 kb
Host smart-3bf737ca-4599-49b7-9371-d176e1d9c955
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1444760428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1444760428
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2602518426
Short name T1828
Test name
Test status
Simulation time 163849833 ps
CPU time 0.86 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:27 PM PDT 24
Peak memory 207492 kb
Host smart-58fbb24f-f9df-49db-b88a-322108eec173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26025
18426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2602518426
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.656947689
Short name T874
Test name
Test status
Simulation time 169404523 ps
CPU time 0.85 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:33 PM PDT 24
Peak memory 207556 kb
Host smart-060ee613-bb5d-4f87-b621-318544194789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65694
7689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.656947689
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.4282128582
Short name T1612
Test name
Test status
Simulation time 1224110904 ps
CPU time 2.86 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207504 kb
Host smart-5409f685-ed56-4387-aa36-6fdbb0843d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42821
28582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.4282128582
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2325600480
Short name T3102
Test name
Test status
Simulation time 2162920219 ps
CPU time 61.05 seconds
Started Aug 09 05:30:22 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 217184 kb
Host smart-1099e72e-7c76-4ec7-b531-1b42d162dec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23256
00480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2325600480
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.2018139099
Short name T2280
Test name
Test status
Simulation time 1620320558 ps
CPU time 12.59 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 207656 kb
Host smart-e4b583a0-3a36-443f-94fc-277c6678aa9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018139099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.2018139099
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.3960901809
Short name T2392
Test name
Test status
Simulation time 544182618 ps
CPU time 1.54 seconds
Started Aug 09 05:30:21 PM PDT 24
Finished Aug 09 05:30:23 PM PDT 24
Peak memory 207408 kb
Host smart-a0be25b6-9785-4d07-bc8d-3f729647a93b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960901809 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.3960901809
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.3727314013
Short name T1548
Test name
Test status
Simulation time 599908849 ps
CPU time 1.66 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207512 kb
Host smart-e298fe35-a429-478b-b86e-59e20d0b5053
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727314013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.3727314013
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.3083476915
Short name T1416
Test name
Test status
Simulation time 524376791 ps
CPU time 1.5 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207440 kb
Host smart-d5cea0bc-bce4-4a30-a210-69fe6ae5d4e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083476915 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.3083476915
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.360852607
Short name T2631
Test name
Test status
Simulation time 569532973 ps
CPU time 1.52 seconds
Started Aug 09 05:33:47 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 207380 kb
Host smart-3e107c06-69d5-440e-8538-7a7e5bf9e80c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360852607 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.360852607
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.2041655089
Short name T1892
Test name
Test status
Simulation time 700708115 ps
CPU time 1.8 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207564 kb
Host smart-ad09bb4d-2d75-48b3-82b0-6c0847f980ca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041655089 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.2041655089
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.604315712
Short name T3403
Test name
Test status
Simulation time 684921665 ps
CPU time 1.73 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207440 kb
Host smart-ccfb7650-0b3a-4730-b8f6-8444436d3090
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604315712 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.604315712
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.2286018479
Short name T2411
Test name
Test status
Simulation time 550003896 ps
CPU time 1.63 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207440 kb
Host smart-302b09ca-c2ee-4af8-936c-492e0c68acb6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286018479 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.2286018479
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.1023689021
Short name T1282
Test name
Test status
Simulation time 527368928 ps
CPU time 1.67 seconds
Started Aug 09 05:33:44 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207472 kb
Host smart-93b52d75-957f-44ec-9e18-3063c0c6dc1f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023689021 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.1023689021
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.3635928639
Short name T967
Test name
Test status
Simulation time 524248761 ps
CPU time 1.63 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207564 kb
Host smart-e6cbda79-ba0a-4617-aa6f-dc5a58b819ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635928639 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.3635928639
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.3191207188
Short name T1235
Test name
Test status
Simulation time 415107547 ps
CPU time 1.43 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207504 kb
Host smart-45c470e4-451b-4563-93bf-8e2c77551346
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191207188 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.3191207188
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.2399899839
Short name T2726
Test name
Test status
Simulation time 505871755 ps
CPU time 1.61 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207560 kb
Host smart-ffdd2070-ca24-4965-bd5a-7e917a7fa5a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399899839 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.2399899839
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.1536600520
Short name T223
Test name
Test status
Simulation time 109987399 ps
CPU time 0.71 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207488 kb
Host smart-b5d8f12b-d1c1-44f8-9728-d77433e5c634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1536600520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1536600520
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3684659769
Short name T3281
Test name
Test status
Simulation time 5441423197 ps
CPU time 7.23 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:33 PM PDT 24
Peak memory 215940 kb
Host smart-341a0040-317e-4d22-9245-073f7d5f71db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684659769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.3684659769
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.951782890
Short name T2383
Test name
Test status
Simulation time 15876150172 ps
CPU time 19.34 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 216008 kb
Host smart-6d11cfe2-f53a-4053-bd1c-07df03de7d2a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=951782890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.951782890
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.49130965
Short name T1121
Test name
Test status
Simulation time 29765583666 ps
CPU time 37.39 seconds
Started Aug 09 05:30:42 PM PDT 24
Finished Aug 09 05:31:20 PM PDT 24
Peak memory 207748 kb
Host smart-2f1634b3-7a44-44b2-9ed4-4a03a4255fba
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49130965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon
_wake_resume.49130965
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1949379016
Short name T3111
Test name
Test status
Simulation time 185912465 ps
CPU time 0.94 seconds
Started Aug 09 05:30:31 PM PDT 24
Finished Aug 09 05:30:32 PM PDT 24
Peak memory 207552 kb
Host smart-05a725c4-50f1-4d08-ac30-86ea135d55d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
79016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1949379016
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3053444515
Short name T777
Test name
Test status
Simulation time 163661743 ps
CPU time 0.92 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207400 kb
Host smart-0967c030-df4f-4696-a00e-0a1384575dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
44515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3053444515
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3290581555
Short name T2406
Test name
Test status
Simulation time 144823302 ps
CPU time 0.85 seconds
Started Aug 09 05:30:48 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 207400 kb
Host smart-a5eaa32b-f3f3-4d5e-a0d2-94a16605f4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32905
81555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3290581555
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1989290075
Short name T3226
Test name
Test status
Simulation time 18803916612 ps
CPU time 30.81 seconds
Started Aug 09 05:30:29 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207844 kb
Host smart-d7f19b52-e080-4802-bb2f-526262cae1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
90075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1989290075
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.2610329280
Short name T1177
Test name
Test status
Simulation time 3868397849 ps
CPU time 33.74 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207748 kb
Host smart-b51cc142-ff5c-4563-8003-8180b349e096
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610329280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.2610329280
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.4187453216
Short name T82
Test name
Test status
Simulation time 484338127 ps
CPU time 1.34 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:40 PM PDT 24
Peak memory 207440 kb
Host smart-729f2aaf-5e08-4075-a9bc-567bdc742993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
53216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.4187453216
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2554048865
Short name T3263
Test name
Test status
Simulation time 163290222 ps
CPU time 0.83 seconds
Started Aug 09 05:30:51 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 207400 kb
Host smart-dc782b05-26cd-4daf-b4c8-984b770dda7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25540
48865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2554048865
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3185114958
Short name T2300
Test name
Test status
Simulation time 42342248 ps
CPU time 0.73 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:28 PM PDT 24
Peak memory 207516 kb
Host smart-72d64735-5b28-44b6-8f60-3b949deaa00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31851
14958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3185114958
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3730801604
Short name T3142
Test name
Test status
Simulation time 813452742 ps
CPU time 2.48 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:37 PM PDT 24
Peak memory 207688 kb
Host smart-e52f3d02-83ae-43a2-ba75-93c6914876ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37308
01604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3730801604
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.149961117
Short name T462
Test name
Test status
Simulation time 393780033 ps
CPU time 1.24 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207468 kb
Host smart-eb6cdcf9-a6a6-4817-bd33-882a07d02f5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=149961117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.149961117
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3419621149
Short name T1979
Test name
Test status
Simulation time 216742464 ps
CPU time 2.23 seconds
Started Aug 09 05:30:50 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207624 kb
Host smart-8c9429ec-7822-410f-8793-a58a0bca3ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34196
21149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3419621149
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1346192237
Short name T640
Test name
Test status
Simulation time 178448642 ps
CPU time 0.94 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 215884 kb
Host smart-91e217d3-5bbe-4907-98c9-c26ea1fcd49a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1346192237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1346192237
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2324332737
Short name T1109
Test name
Test status
Simulation time 207627614 ps
CPU time 0.91 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 207400 kb
Host smart-71205e35-049a-4b40-857b-71356845ed77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243
32737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2324332737
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3008548670
Short name T553
Test name
Test status
Simulation time 198014294 ps
CPU time 0.96 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:30:55 PM PDT 24
Peak memory 207496 kb
Host smart-56b173a3-3840-4677-817b-1cdf45f69329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30085
48670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3008548670
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3732763879
Short name T2390
Test name
Test status
Simulation time 5261915529 ps
CPU time 39.06 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 224300 kb
Host smart-50bd5da6-9d8c-4cce-9c45-9e4d60f24837
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3732763879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3732763879
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.371106651
Short name T785
Test name
Test status
Simulation time 8583314933 ps
CPU time 57.24 seconds
Started Aug 09 05:30:27 PM PDT 24
Finished Aug 09 05:31:24 PM PDT 24
Peak memory 207696 kb
Host smart-f3d05748-929c-47c2-a3be-d8ecf7e1d084
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371106651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.371106651
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.4123456347
Short name T1781
Test name
Test status
Simulation time 177187070 ps
CPU time 0.9 seconds
Started Aug 09 05:30:48 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 207408 kb
Host smart-3079eb69-e981-4621-9d87-0338de70a398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41234
56347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.4123456347
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3991005748
Short name T1061
Test name
Test status
Simulation time 30015927369 ps
CPU time 45.14 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207728 kb
Host smart-8fb8b2f0-bed1-45a1-b5a1-bb1f20512bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
05748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3991005748
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3527692130
Short name T2105
Test name
Test status
Simulation time 5123152849 ps
CPU time 7.14 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 216068 kb
Host smart-4da052ab-34c0-4eb7-bce5-0a24d8e4ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
92130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3527692130
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2349277337
Short name T600
Test name
Test status
Simulation time 2414783194 ps
CPU time 17.87 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 218708 kb
Host smart-5c9e5427-06fa-477f-8cb5-835270e0bbba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2349277337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2349277337
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1843191439
Short name T3314
Test name
Test status
Simulation time 3596469174 ps
CPU time 102.91 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 217412 kb
Host smart-59bee257-b5fd-427c-b555-1b6645fdb60c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1843191439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1843191439
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2831285649
Short name T1795
Test name
Test status
Simulation time 310670691 ps
CPU time 1.17 seconds
Started Aug 09 05:30:42 PM PDT 24
Finished Aug 09 05:30:44 PM PDT 24
Peak memory 207404 kb
Host smart-831bf456-267a-485e-9abe-95dbf0077a6a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2831285649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2831285649
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.988536970
Short name T2839
Test name
Test status
Simulation time 209118823 ps
CPU time 0.95 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:37 PM PDT 24
Peak memory 207560 kb
Host smart-9c8985cd-8b4c-4719-a42a-36fc74ed1e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98853
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.988536970
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.4162600731
Short name T1328
Test name
Test status
Simulation time 2949996664 ps
CPU time 85.06 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 217464 kb
Host smart-c87ebcbb-b840-448a-befc-cc236862b9cf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4162600731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.4162600731
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.499635289
Short name T2552
Test name
Test status
Simulation time 183741365 ps
CPU time 0.92 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207396 kb
Host smart-df060576-61a6-404d-8631-9636aa3d1981
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=499635289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.499635289
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1062954299
Short name T1990
Test name
Test status
Simulation time 150390847 ps
CPU time 0.84 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 207428 kb
Host smart-4b036f09-1fa1-4ee6-b25b-56651fc070fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
54299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1062954299
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.650816988
Short name T146
Test name
Test status
Simulation time 193676285 ps
CPU time 0.98 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:42 PM PDT 24
Peak memory 207440 kb
Host smart-a4d78dae-a01d-4ed6-94e5-c807d75838cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65081
6988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.650816988
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2131859551
Short name T2530
Test name
Test status
Simulation time 185771857 ps
CPU time 0.94 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207508 kb
Host smart-74909dea-60fa-4b40-8a4a-f5c6e8752a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21318
59551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2131859551
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1800057628
Short name T929
Test name
Test status
Simulation time 185423171 ps
CPU time 0.87 seconds
Started Aug 09 05:30:32 PM PDT 24
Finished Aug 09 05:30:33 PM PDT 24
Peak memory 207432 kb
Host smart-6f7e2ad9-b0f9-436a-bcd8-b426b5e8f1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18000
57628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1800057628
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.623202960
Short name T1265
Test name
Test status
Simulation time 264625414 ps
CPU time 1.06 seconds
Started Aug 09 05:30:49 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 207476 kb
Host smart-c8156c3b-080f-4ac7-8620-4f2db778a87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62320
2960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.623202960
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2425589675
Short name T1905
Test name
Test status
Simulation time 151219235 ps
CPU time 0.88 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207528 kb
Host smart-76e7b423-4372-4a58-a531-d1ca92c5cef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24255
89675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2425589675
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2906908599
Short name T1908
Test name
Test status
Simulation time 216371835 ps
CPU time 1.03 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:30:37 PM PDT 24
Peak memory 207556 kb
Host smart-78971a8d-faac-4b15-b04f-5c089c171966
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2906908599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2906908599
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3633636102
Short name T2623
Test name
Test status
Simulation time 183040967 ps
CPU time 0.84 seconds
Started Aug 09 05:30:30 PM PDT 24
Finished Aug 09 05:30:31 PM PDT 24
Peak memory 207444 kb
Host smart-e9d8b405-38fe-4d5a-8568-1a3bf456a922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36336
36102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3633636102
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2230366259
Short name T2146
Test name
Test status
Simulation time 44021461 ps
CPU time 0.7 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207552 kb
Host smart-b9527436-f8f9-4f3d-bc62-68da1b92c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
66259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2230366259
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1273841992
Short name T1644
Test name
Test status
Simulation time 18886972316 ps
CPU time 50.9 seconds
Started Aug 09 05:30:42 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 215864 kb
Host smart-1bde4b80-c0b7-4d99-b4c6-bc04c979d619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12738
41992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1273841992
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4047027228
Short name T2719
Test name
Test status
Simulation time 177996594 ps
CPU time 0.92 seconds
Started Aug 09 05:30:49 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 207472 kb
Host smart-2c41ff64-ca10-4d0d-bb51-41f5d4fdf55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
27228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4047027228
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2430606251
Short name T3180
Test name
Test status
Simulation time 232748702 ps
CPU time 0.95 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207468 kb
Host smart-6c8bb0e0-cfbc-4eff-957c-18886503cce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24306
06251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2430606251
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2259257460
Short name T759
Test name
Test status
Simulation time 191135913 ps
CPU time 0.95 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:36 PM PDT 24
Peak memory 207524 kb
Host smart-83e00d46-537a-4283-bda3-080bed625e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22592
57460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2259257460
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2190737671
Short name T2366
Test name
Test status
Simulation time 160590637 ps
CPU time 0.95 seconds
Started Aug 09 05:30:25 PM PDT 24
Finished Aug 09 05:30:26 PM PDT 24
Peak memory 207556 kb
Host smart-89d3fb7e-dd5f-4dbc-a5ea-d14f9adad72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21907
37671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2190737671
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.891038504
Short name T2446
Test name
Test status
Simulation time 223812428 ps
CPU time 0.87 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207532 kb
Host smart-97353f9d-e9ae-4318-8d9d-0fe1bdbb751b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89103
8504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.891038504
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.3895530789
Short name T2673
Test name
Test status
Simulation time 260656893 ps
CPU time 1.08 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:39 PM PDT 24
Peak memory 207472 kb
Host smart-db8f5526-940d-4ace-b22b-6f3686adcbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
30789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.3895530789
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1309174570
Short name T1989
Test name
Test status
Simulation time 144427562 ps
CPU time 0.8 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:27 PM PDT 24
Peak memory 207520 kb
Host smart-9a772d35-a299-4987-a999-ea35d787a209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
74570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1309174570
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1135204107
Short name T1391
Test name
Test status
Simulation time 159580538 ps
CPU time 0.83 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:41 PM PDT 24
Peak memory 207436 kb
Host smart-f9cacb41-755e-402a-bf1f-08e4714ecb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
04107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1135204107
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2681815130
Short name T2015
Test name
Test status
Simulation time 212659435 ps
CPU time 1.03 seconds
Started Aug 09 05:30:37 PM PDT 24
Finished Aug 09 05:30:38 PM PDT 24
Peak memory 207780 kb
Host smart-1b2c000a-16c3-46c9-8fd5-f80c8923787c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818
15130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2681815130
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.823209903
Short name T1414
Test name
Test status
Simulation time 3147259095 ps
CPU time 24.71 seconds
Started Aug 09 05:30:26 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 224144 kb
Host smart-b1e7a6a3-60a1-4976-b2b6-680f88b33414
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=823209903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.823209903
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2737715396
Short name T1440
Test name
Test status
Simulation time 190258657 ps
CPU time 0.93 seconds
Started Aug 09 05:30:28 PM PDT 24
Finished Aug 09 05:30:29 PM PDT 24
Peak memory 207452 kb
Host smart-794f9c1a-961c-4591-bcb7-30870dae84cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
15396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2737715396
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.927681602
Short name T1962
Test name
Test status
Simulation time 190517970 ps
CPU time 0.93 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 207432 kb
Host smart-82fc8df7-e212-41f9-9dd9-70fcf3f8be3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92768
1602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.927681602
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3432624712
Short name T1619
Test name
Test status
Simulation time 675090244 ps
CPU time 1.7 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207396 kb
Host smart-58f7cda8-89b5-4ccb-888d-e6d188892b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326
24712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3432624712
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.131663852
Short name T3626
Test name
Test status
Simulation time 3402863600 ps
CPU time 35.63 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:31:20 PM PDT 24
Peak memory 217620 kb
Host smart-b78555c6-696e-4ddc-ac07-b2262caba809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13166
3852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.131663852
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1724878941
Short name T53
Test name
Test status
Simulation time 898467507 ps
CPU time 18.92 seconds
Started Aug 09 05:30:25 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 207556 kb
Host smart-60e3fe99-d131-4a9d-bf4b-5037030d4121
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724878941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1724878941
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.4246263499
Short name T719
Test name
Test status
Simulation time 601464920 ps
CPU time 1.75 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207568 kb
Host smart-f258213a-c871-4057-90c2-61f1ad3b39fd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246263499 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.4246263499
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.3232211404
Short name T1883
Test name
Test status
Simulation time 509257820 ps
CPU time 1.47 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207360 kb
Host smart-f4915282-9d80-4827-a595-562d1fbfec6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232211404 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.3232211404
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.1504009723
Short name T2094
Test name
Test status
Simulation time 670408584 ps
CPU time 1.9 seconds
Started Aug 09 05:33:44 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207472 kb
Host smart-b2edcd24-3b45-438b-9039-14bba0aa95d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504009723 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.1504009723
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.2120527081
Short name T2887
Test name
Test status
Simulation time 659064911 ps
CPU time 1.77 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207440 kb
Host smart-17746f07-0628-48a2-9e79-50357c48b1b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120527081 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.2120527081
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.4086546631
Short name T641
Test name
Test status
Simulation time 496157914 ps
CPU time 1.51 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207408 kb
Host smart-759daf52-bf97-44fc-ad23-546a3c0f100f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086546631 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.4086546631
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.2782410406
Short name T2650
Test name
Test status
Simulation time 502286906 ps
CPU time 1.6 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207440 kb
Host smart-8d107d7d-bd13-4acd-ad93-9a7cc4700b28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782410406 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.2782410406
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.497975768
Short name T194
Test name
Test status
Simulation time 475240810 ps
CPU time 1.51 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207804 kb
Host smart-a200fd69-1d3b-4bd7-9e1a-bb521b84c882
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497975768 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.497975768
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.2730812133
Short name T2213
Test name
Test status
Simulation time 511940978 ps
CPU time 1.69 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207512 kb
Host smart-e608228e-8ddc-4a64-b29c-552f91058a8a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730812133 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.2730812133
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.3933767080
Short name T111
Test name
Test status
Simulation time 635501833 ps
CPU time 1.79 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207516 kb
Host smart-0bf62e00-0ddd-4ccb-8be5-2e1800f21862
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933767080 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.3933767080
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.3108886322
Short name T2804
Test name
Test status
Simulation time 504004231 ps
CPU time 1.46 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207516 kb
Host smart-e7a24b52-d567-4725-8fe0-31e9f541bb30
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108886322 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.3108886322
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.2827790928
Short name T3046
Test name
Test status
Simulation time 515380315 ps
CPU time 1.58 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207564 kb
Host smart-d885e3d7-52d6-4df5-8e70-e860cecee9a2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827790928 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.2827790928
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3213863252
Short name T3082
Test name
Test status
Simulation time 56894834 ps
CPU time 0.7 seconds
Started Aug 09 05:30:50 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 207604 kb
Host smart-5514ba12-6bab-4120-8891-534afc52a3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3213863252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3213863252
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2699174575
Short name T3368
Test name
Test status
Simulation time 8987412332 ps
CPU time 11.43 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 207652 kb
Host smart-a68f73e6-ac21-4387-b7f9-6d83a8f5d5a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699174575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.2699174575
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1969830866
Short name T2759
Test name
Test status
Simulation time 19024831291 ps
CPU time 23.22 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207204 kb
Host smart-5159ce12-064d-4d35-ad69-4150133b1e1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969830866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1969830866
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.4245980531
Short name T797
Test name
Test status
Simulation time 26425772718 ps
CPU time 33.58 seconds
Started Aug 09 05:30:36 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 216028 kb
Host smart-baa7f338-d940-4a7e-910b-b9899ead6d1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245980531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.4245980531
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.443037562
Short name T2612
Test name
Test status
Simulation time 150802633 ps
CPU time 0.85 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:42 PM PDT 24
Peak memory 207508 kb
Host smart-8b5271fd-5bf9-4ec0-9ef6-270b940e8605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44303
7562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.443037562
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3892493298
Short name T1954
Test name
Test status
Simulation time 141630373 ps
CPU time 0.81 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:30:55 PM PDT 24
Peak memory 207536 kb
Host smart-30fd188d-486a-4fc5-bc94-14f131fd9afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38924
93298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3892493298
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2938366152
Short name T1254
Test name
Test status
Simulation time 421308126 ps
CPU time 1.65 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207540 kb
Host smart-5fa0ce46-55d6-4c54-9b6b-9de7e170f88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2938366152
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3390842966
Short name T2550
Test name
Test status
Simulation time 465353245 ps
CPU time 1.52 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207420 kb
Host smart-9d1ab559-701a-4978-a970-1d5815e708a9
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3390842966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3390842966
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3917415171
Short name T2640
Test name
Test status
Simulation time 29525231335 ps
CPU time 58.07 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207840 kb
Host smart-338db366-a233-4414-95f3-e4bc2c3c95e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
15171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3917415171
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.3048975310
Short name T1314
Test name
Test status
Simulation time 2480260702 ps
CPU time 21.68 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 207780 kb
Host smart-f82b6972-cf43-4967-90b9-a65403ccf4f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048975310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.3048975310
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.285439514
Short name T951
Test name
Test status
Simulation time 542389031 ps
CPU time 1.63 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 207328 kb
Host smart-b203f101-e9a0-4707-a81a-10baf711e738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28543
9514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.285439514
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.970790159
Short name T787
Test name
Test status
Simulation time 143868648 ps
CPU time 0.83 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 207468 kb
Host smart-5085acd1-6b2b-428e-88c6-5b694ef98702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97079
0159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.970790159
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1630864118
Short name T3143
Test name
Test status
Simulation time 42778468 ps
CPU time 0.73 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:44 PM PDT 24
Peak memory 207424 kb
Host smart-0f36f399-3676-49d7-ab82-7cd938e27f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16308
64118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1630864118
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3442267157
Short name T1772
Test name
Test status
Simulation time 835586473 ps
CPU time 2.39 seconds
Started Aug 09 05:30:31 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207720 kb
Host smart-8edcd20e-7060-402b-ae71-e538897257c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
67157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3442267157
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.4179075223
Short name T421
Test name
Test status
Simulation time 492714904 ps
CPU time 1.45 seconds
Started Aug 09 05:30:40 PM PDT 24
Finished Aug 09 05:30:42 PM PDT 24
Peak memory 207488 kb
Host smart-1a0ee736-dce4-4ce1-8a34-bf7b357f5259
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4179075223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.4179075223
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.212415752
Short name T1090
Test name
Test status
Simulation time 170831855 ps
CPU time 2.02 seconds
Started Aug 09 05:30:35 PM PDT 24
Finished Aug 09 05:30:37 PM PDT 24
Peak memory 207700 kb
Host smart-70cf2913-4ab9-4d96-a5cc-8f3141b28338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21241
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.212415752
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1857820957
Short name T809
Test name
Test status
Simulation time 245423021 ps
CPU time 1.1 seconds
Started Aug 09 05:30:50 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 215736 kb
Host smart-f5881184-7d12-4a0e-b97a-34c40cd300bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1857820957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1857820957
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2202362050
Short name T3478
Test name
Test status
Simulation time 174976277 ps
CPU time 0.89 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207404 kb
Host smart-4300dfd1-bb53-44fb-aff7-28578f4a75d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22023
62050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2202362050
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4292072495
Short name T1877
Test name
Test status
Simulation time 188197057 ps
CPU time 0.89 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:30:55 PM PDT 24
Peak memory 207472 kb
Host smart-13f7234d-d450-45b0-9ff2-4c35ddb44899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42920
72495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4292072495
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2953346085
Short name T1665
Test name
Test status
Simulation time 2977834619 ps
CPU time 29.22 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 224208 kb
Host smart-75c2a1b6-072c-482c-b6d3-4f3afd89fd43
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953346085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2953346085
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.1725769270
Short name T1436
Test name
Test status
Simulation time 11935952438 ps
CPU time 91.32 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:32:25 PM PDT 24
Peak memory 207692 kb
Host smart-d1987293-8add-4286-9b3c-212d4a8306dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1725769270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.1725769270
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1077592748
Short name T1727
Test name
Test status
Simulation time 193781564 ps
CPU time 0.92 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 207500 kb
Host smart-a00b5180-9166-4678-8540-d49517e49903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
92748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1077592748
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2233712348
Short name T92
Test name
Test status
Simulation time 26244913647 ps
CPU time 32.46 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:31:27 PM PDT 24
Peak memory 215896 kb
Host smart-ae981eac-0ffe-407b-9ef4-99ee06b72196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
12348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2233712348
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1868716642
Short name T810
Test name
Test status
Simulation time 3920202941 ps
CPU time 5.67 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 216092 kb
Host smart-82d1d57a-aefd-4b2a-b0be-62cfea00e7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
16642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1868716642
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2446767714
Short name T1624
Test name
Test status
Simulation time 4146752191 ps
CPU time 31.4 seconds
Started Aug 09 05:30:55 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 219276 kb
Host smart-4c0c599c-5918-42a7-a4bc-f5c05727b4c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2446767714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2446767714
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2303309603
Short name T2744
Test name
Test status
Simulation time 2187128557 ps
CPU time 22.41 seconds
Started Aug 09 05:30:49 PM PDT 24
Finished Aug 09 05:31:12 PM PDT 24
Peak memory 217248 kb
Host smart-29146278-8637-4e8e-8a23-2a3e2f64c5be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2303309603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2303309603
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1382824745
Short name T2622
Test name
Test status
Simulation time 261170092 ps
CPU time 1.03 seconds
Started Aug 09 05:30:33 PM PDT 24
Finished Aug 09 05:30:34 PM PDT 24
Peak memory 207548 kb
Host smart-2687a26a-8a62-4cc3-b35e-ea9804399cfe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1382824745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1382824745
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1601594636
Short name T3392
Test name
Test status
Simulation time 187808371 ps
CPU time 0.92 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207560 kb
Host smart-da033197-faa5-448b-824b-64ab1155f722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16015
94636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1601594636
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.4177159967
Short name T661
Test name
Test status
Simulation time 1589206683 ps
CPU time 11.58 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 217352 kb
Host smart-b938c704-6d56-4522-9e31-b11c59bd6e5e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4177159967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.4177159967
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.802523696
Short name T1202
Test name
Test status
Simulation time 178564110 ps
CPU time 0.89 seconds
Started Aug 09 05:30:50 PM PDT 24
Finished Aug 09 05:30:51 PM PDT 24
Peak memory 207432 kb
Host smart-07d148bf-a9e4-4617-9f97-86461db6ef0b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=802523696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.802523696
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1507505712
Short name T1164
Test name
Test status
Simulation time 144978544 ps
CPU time 0.85 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 207400 kb
Host smart-e2e25b54-86d4-4692-aeef-bd0f0adb3085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15075
05712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1507505712
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2816066980
Short name T2327
Test name
Test status
Simulation time 209183954 ps
CPU time 0.97 seconds
Started Aug 09 05:30:51 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207444 kb
Host smart-838c9692-adcf-4b7b-ade0-534293185603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28160
66980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2816066980
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1356780741
Short name T2401
Test name
Test status
Simulation time 218013659 ps
CPU time 0.94 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207404 kb
Host smart-0306f32e-456f-4968-8b03-895379e4f10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13567
80741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1356780741
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1535614878
Short name T638
Test name
Test status
Simulation time 167561671 ps
CPU time 0.91 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 207504 kb
Host smart-7e7c79a8-ab05-4c00-8fe0-e29e7233518e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
14878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1535614878
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1415762488
Short name T1776
Test name
Test status
Simulation time 154182488 ps
CPU time 0.83 seconds
Started Aug 09 05:31:12 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207384 kb
Host smart-8c6d8b53-f578-4827-9b32-74913939e2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
62488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1415762488
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.600184422
Short name T1725
Test name
Test status
Simulation time 147239619 ps
CPU time 0.89 seconds
Started Aug 09 05:30:48 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 207512 kb
Host smart-1ae62b7c-09bc-4c05-9710-de7d054e6dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60018
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.600184422
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3896950863
Short name T2048
Test name
Test status
Simulation time 210306642 ps
CPU time 1.01 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207428 kb
Host smart-5951346b-84eb-46c4-b1b1-36277234c8e3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3896950863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3896950863
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.39211436
Short name T1218
Test name
Test status
Simulation time 165102649 ps
CPU time 0.82 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 207480 kb
Host smart-5b9bbe58-03d7-460e-9784-b43399504db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39211
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.39211436
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3256950054
Short name T36
Test name
Test status
Simulation time 45286816 ps
CPU time 0.67 seconds
Started Aug 09 05:30:47 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 207552 kb
Host smart-e385eb34-2741-4698-822c-d574e7fe1161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32569
50054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3256950054
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3948714314
Short name T291
Test name
Test status
Simulation time 13181439972 ps
CPU time 35.96 seconds
Started Aug 09 05:30:47 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 224268 kb
Host smart-0e1b5435-7e00-4f1d-8c67-c5b3f44a9031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
14314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3948714314
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3800278228
Short name T3291
Test name
Test status
Simulation time 168846576 ps
CPU time 0.88 seconds
Started Aug 09 05:30:38 PM PDT 24
Finished Aug 09 05:30:44 PM PDT 24
Peak memory 207380 kb
Host smart-1c04bc8f-fb87-4aaf-961c-601e54a6d19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002
78228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3800278228
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3396920750
Short name T793
Test name
Test status
Simulation time 211399550 ps
CPU time 0.97 seconds
Started Aug 09 05:30:45 PM PDT 24
Finished Aug 09 05:30:46 PM PDT 24
Peak memory 207484 kb
Host smart-0a176071-8e59-43d6-820c-33ea80d302ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33969
20750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3396920750
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1442013381
Short name T219
Test name
Test status
Simulation time 193644849 ps
CPU time 0.93 seconds
Started Aug 09 05:31:00 PM PDT 24
Finished Aug 09 05:31:01 PM PDT 24
Peak memory 207364 kb
Host smart-58e56b66-3057-466b-b4f4-a42b0dfc5f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14420
13381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1442013381
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2103029434
Short name T2557
Test name
Test status
Simulation time 160294916 ps
CPU time 0.95 seconds
Started Aug 09 05:30:41 PM PDT 24
Finished Aug 09 05:30:43 PM PDT 24
Peak memory 207512 kb
Host smart-6d26368d-5d04-415b-a98d-a6eaf47e9647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
29434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2103029434
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1929681847
Short name T2663
Test name
Test status
Simulation time 152519127 ps
CPU time 0.88 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207472 kb
Host smart-2e8f13dd-39e6-4e41-b755-122d238317b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
81847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1929681847
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.3001775614
Short name T2706
Test name
Test status
Simulation time 362946602 ps
CPU time 1.24 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207404 kb
Host smart-90166ea5-c388-4dbf-93f1-db4b1ffa66f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017
75614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.3001775614
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.68753212
Short name T1050
Test name
Test status
Simulation time 146348548 ps
CPU time 0.94 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207524 kb
Host smart-e6333916-0dee-4ed6-8d98-80ac277b1a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68753
212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.68753212
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3343690606
Short name T2029
Test name
Test status
Simulation time 196712399 ps
CPU time 0.89 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 207496 kb
Host smart-738d9a23-a0bc-4d38-b7c6-d7fe7e748530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436
90606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3343690606
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2492985057
Short name T2365
Test name
Test status
Simulation time 186606147 ps
CPU time 0.98 seconds
Started Aug 09 05:30:47 PM PDT 24
Finished Aug 09 05:30:48 PM PDT 24
Peak memory 207548 kb
Host smart-708cd06c-da20-497a-a080-7cbd725c8f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24929
85057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2492985057
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3228257076
Short name T2691
Test name
Test status
Simulation time 3604287856 ps
CPU time 29.27 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 216104 kb
Host smart-b48f5108-c515-4e8c-bfe1-39439de68a68
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3228257076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3228257076
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.66565706
Short name T2339
Test name
Test status
Simulation time 163964056 ps
CPU time 0.84 seconds
Started Aug 09 05:30:51 PM PDT 24
Finished Aug 09 05:30:52 PM PDT 24
Peak memory 207376 kb
Host smart-36014af9-2327-4f0c-9ce4-a2b10b628108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66565
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.66565706
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3043436042
Short name T2302
Test name
Test status
Simulation time 208516117 ps
CPU time 0.92 seconds
Started Aug 09 05:30:49 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 207504 kb
Host smart-573da9bd-f109-461c-af89-c02e1a261560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
36042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3043436042
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.981802264
Short name T1993
Test name
Test status
Simulation time 446285554 ps
CPU time 1.44 seconds
Started Aug 09 05:30:49 PM PDT 24
Finished Aug 09 05:30:50 PM PDT 24
Peak memory 207524 kb
Host smart-4dbe224d-9e0f-4f2a-a964-fccfa26d84c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98180
2264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.981802264
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3243871121
Short name T1545
Test name
Test status
Simulation time 2435523703 ps
CPU time 74.85 seconds
Started Aug 09 05:30:39 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 215988 kb
Host smart-edc35548-452c-497a-a987-cf3ca0823e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
71121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3243871121
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.2605009709
Short name T1779
Test name
Test status
Simulation time 929782975 ps
CPU time 18.79 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:24 PM PDT 24
Peak memory 207604 kb
Host smart-e46f280a-594c-4604-829b-a64e1ced1210
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605009709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.2605009709
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.41249273
Short name T1889
Test name
Test status
Simulation time 486802124 ps
CPU time 1.49 seconds
Started Aug 09 05:30:47 PM PDT 24
Finished Aug 09 05:30:49 PM PDT 24
Peak memory 207536 kb
Host smart-5361c71e-120a-4cbf-9846-226eebf41abf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41249273 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.41249273
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.379768536
Short name T3606
Test name
Test status
Simulation time 577728316 ps
CPU time 1.77 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207528 kb
Host smart-9b910070-b5ae-4e05-848c-6176b5f80f0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379768536 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.379768536
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.3493651063
Short name T3524
Test name
Test status
Simulation time 577429994 ps
CPU time 1.75 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207464 kb
Host smart-9d79a35e-e4f6-4a83-b417-864a49d30462
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493651063 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.3493651063
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.1354849237
Short name T3184
Test name
Test status
Simulation time 619753153 ps
CPU time 1.98 seconds
Started Aug 09 05:33:37 PM PDT 24
Finished Aug 09 05:33:39 PM PDT 24
Peak memory 207432 kb
Host smart-5baa338e-700d-4aa3-94db-c63ef6b6f40a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354849237 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.1354849237
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.3633680994
Short name T606
Test name
Test status
Simulation time 492507454 ps
CPU time 1.5 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207388 kb
Host smart-baac8122-49cd-4047-8947-7d25161e44b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633680994 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.3633680994
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.1771913242
Short name T1300
Test name
Test status
Simulation time 504533054 ps
CPU time 1.45 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207560 kb
Host smart-bf630cce-01c9-44ed-a5eb-f5ac8db08c95
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771913242 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.1771913242
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.706709949
Short name T604
Test name
Test status
Simulation time 650730113 ps
CPU time 1.65 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207516 kb
Host smart-a3ac0956-efa9-4d0c-b11c-eb21d81a52de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706709949 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.706709949
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.2683698295
Short name T2320
Test name
Test status
Simulation time 476611065 ps
CPU time 1.43 seconds
Started Aug 09 05:33:45 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 207356 kb
Host smart-e5650445-57c1-4290-8849-8fff85506424
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683698295 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.2683698295
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.3009749360
Short name T1271
Test name
Test status
Simulation time 505088018 ps
CPU time 1.47 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 207392 kb
Host smart-6c3b3f80-4fb0-493d-bb3c-6e15fcd3d115
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009749360 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.3009749360
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/348.usbdev_tx_rx_disruption.2264460408
Short name T3491
Test name
Test status
Simulation time 550212066 ps
CPU time 1.6 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207444 kb
Host smart-22ec2adc-0215-4099-88de-0884c83f3f13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264460408 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 348.usbdev_tx_rx_disruption.2264460408
Directory /workspace/348.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.1557949941
Short name T3168
Test name
Test status
Simulation time 409825388 ps
CPU time 1.51 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207556 kb
Host smart-28e6ac91-e878-4b5e-bd6a-a74d5b02e25b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557949941 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.1557949941
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1715580647
Short name T2501
Test name
Test status
Simulation time 62542122 ps
CPU time 0.69 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207496 kb
Host smart-d395aadd-b360-4973-9630-5518dfbbde89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1715580647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1715580647
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3682986536
Short name T788
Test name
Test status
Simulation time 10172361825 ps
CPU time 12.83 seconds
Started Aug 09 05:30:55 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207732 kb
Host smart-5b04b525-1cf9-4441-bc3b-d81ecdcb5237
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682986536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3682986536
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.509636742
Short name T2434
Test name
Test status
Simulation time 14292702801 ps
CPU time 19.78 seconds
Started Aug 09 05:30:48 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 215820 kb
Host smart-77a1df59-d1b9-41ae-af2f-6c234b119249
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=509636742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.509636742
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.146796089
Short name T3390
Test name
Test status
Simulation time 28886252239 ps
CPU time 32.36 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207688 kb
Host smart-2865149b-db21-4267-95a4-a4a4c708b033
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146796089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.146796089
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.872023230
Short name T3515
Test name
Test status
Simulation time 150646670 ps
CPU time 0.91 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207436 kb
Host smart-2f5bb2d6-742d-443d-87b5-2fd25579655a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87202
3230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.872023230
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.779319777
Short name T3525
Test name
Test status
Simulation time 150351471 ps
CPU time 0.82 seconds
Started Aug 09 05:30:52 PM PDT 24
Finished Aug 09 05:30:53 PM PDT 24
Peak memory 207528 kb
Host smart-bc8d7cc4-07de-41aa-8c0b-3b1abfe96712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77931
9777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.779319777
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.592567452
Short name T3534
Test name
Test status
Simulation time 569160310 ps
CPU time 1.81 seconds
Started Aug 09 05:30:46 PM PDT 24
Finished Aug 09 05:30:47 PM PDT 24
Peak memory 207396 kb
Host smart-d5318d9d-4e46-4dc8-96f3-779c23cdcbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59256
7452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.592567452
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2779371361
Short name T3304
Test name
Test status
Simulation time 353401688 ps
CPU time 1.14 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207360 kb
Host smart-b112ccc3-1abd-4a00-8050-1e185b0a1ad7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2779371361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2779371361
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.74334698
Short name T2667
Test name
Test status
Simulation time 49432017033 ps
CPU time 74.74 seconds
Started Aug 09 05:30:43 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207852 kb
Host smart-3475ab76-b005-4fd6-8af7-fc858a1808da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74334
698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.74334698
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.3464205633
Short name T941
Test name
Test status
Simulation time 448105913 ps
CPU time 8.24 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 207608 kb
Host smart-d7ba5814-7414-4854-80f7-e97014200e2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464205633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.3464205633
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.832053309
Short name T2224
Test name
Test status
Simulation time 658866580 ps
CPU time 1.69 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207476 kb
Host smart-fdcb6de1-b4aa-4a9c-a471-b893d52165c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83205
3309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.832053309
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3200700620
Short name T3502
Test name
Test status
Simulation time 140758610 ps
CPU time 0.89 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 206864 kb
Host smart-36deac45-eae1-436b-95c2-3d2cbafc5a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
00620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3200700620
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.880251085
Short name T2012
Test name
Test status
Simulation time 49021997 ps
CPU time 0.72 seconds
Started Aug 09 05:30:55 PM PDT 24
Finished Aug 09 05:30:56 PM PDT 24
Peak memory 207444 kb
Host smart-500e0c4f-cc3b-4459-9544-ed38ca240b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88025
1085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.880251085
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3187178014
Short name T1116
Test name
Test status
Simulation time 778898380 ps
CPU time 2.19 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207968 kb
Host smart-1da01dfc-8a75-4712-82a3-b3f28b19f7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871
78014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3187178014
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.1810780164
Short name T2596
Test name
Test status
Simulation time 223985886 ps
CPU time 0.94 seconds
Started Aug 09 05:30:55 PM PDT 24
Finished Aug 09 05:30:56 PM PDT 24
Peak memory 207396 kb
Host smart-326d370a-1290-4813-9142-b684134fa655
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1810780164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.1810780164
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3042164740
Short name T739
Test name
Test status
Simulation time 193492566 ps
CPU time 1.83 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207524 kb
Host smart-15c0ea1a-c9a9-4c8f-b934-ce60b3745bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
64740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3042164740
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2771285736
Short name T1032
Test name
Test status
Simulation time 163226323 ps
CPU time 0.89 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207548 kb
Host smart-3f93269a-55fe-464d-8f94-bf47d66244a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2771285736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2771285736
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2694820268
Short name T2730
Test name
Test status
Simulation time 150663035 ps
CPU time 0.83 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207364 kb
Host smart-98cb9400-476f-4f8a-b6a0-89769d45fdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
20268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2694820268
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.437627497
Short name T1096
Test name
Test status
Simulation time 243850410 ps
CPU time 1.14 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207552 kb
Host smart-bee2c30b-fbd8-4fa1-a4a7-4b786b04f0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43762
7497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.437627497
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1163282707
Short name T1532
Test name
Test status
Simulation time 4112422611 ps
CPU time 40.86 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 217380 kb
Host smart-6568de00-afcd-46a9-8f18-97ab79b4eb3c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1163282707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1163282707
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.4015190190
Short name T2266
Test name
Test status
Simulation time 11958006721 ps
CPU time 91.74 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207812 kb
Host smart-20d7c6f9-d996-415a-9404-0e9142ee586e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4015190190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.4015190190
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3867709193
Short name T2263
Test name
Test status
Simulation time 212237382 ps
CPU time 0.94 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 207424 kb
Host smart-d5b3c4dd-6a18-4e8d-9ab4-e3d6f7d0a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38677
09193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3867709193
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.158083720
Short name T1969
Test name
Test status
Simulation time 13977501893 ps
CPU time 18.19 seconds
Started Aug 09 05:30:54 PM PDT 24
Finished Aug 09 05:31:13 PM PDT 24
Peak memory 207856 kb
Host smart-a30537b8-da7b-4870-bbb1-f71905a297c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
3720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.158083720
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3680345281
Short name T3497
Test name
Test status
Simulation time 8408259884 ps
CPU time 10.78 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207756 kb
Host smart-d5ec8eac-f17d-4389-953b-19c491ec3a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36803
45281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3680345281
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1767695358
Short name T1201
Test name
Test status
Simulation time 3131575445 ps
CPU time 24.53 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 219828 kb
Host smart-ed9e6409-2911-49e7-bd2b-8f5d04a145bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1767695358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1767695358
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3580682049
Short name T667
Test name
Test status
Simulation time 2156674052 ps
CPU time 58.58 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 216068 kb
Host smart-e816375a-a652-4453-b958-6eef3ab3a5f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3580682049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3580682049
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1159197216
Short name T2555
Test name
Test status
Simulation time 289368815 ps
CPU time 1.05 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207516 kb
Host smart-6a87c4fd-aef0-48aa-b6f1-75c51082d9b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1159197216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1159197216
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4130909461
Short name T712
Test name
Test status
Simulation time 200480639 ps
CPU time 0.95 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:30:54 PM PDT 24
Peak memory 207500 kb
Host smart-5f326e3f-9849-4801-9e24-a6f40a468a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41309
09461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4130909461
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3978037463
Short name T1176
Test name
Test status
Simulation time 2737529608 ps
CPU time 27.77 seconds
Started Aug 09 05:30:52 PM PDT 24
Finished Aug 09 05:31:20 PM PDT 24
Peak memory 217268 kb
Host smart-299ced9a-6a6c-497f-8a44-d813f28f6ca1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3978037463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3978037463
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1297462771
Short name T1028
Test name
Test status
Simulation time 219252578 ps
CPU time 0.95 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 207500 kb
Host smart-dc1b7ace-2921-4420-947b-c52db505e807
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1297462771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1297462771
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1539379814
Short name T2866
Test name
Test status
Simulation time 160462634 ps
CPU time 0.88 seconds
Started Aug 09 05:31:00 PM PDT 24
Finished Aug 09 05:31:01 PM PDT 24
Peak memory 207504 kb
Host smart-e79f38e4-cd6f-409b-ada6-f51d1880a78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15393
79814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1539379814
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3270383323
Short name T2813
Test name
Test status
Simulation time 204135110 ps
CPU time 0.93 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207504 kb
Host smart-e3f6b225-af5d-4616-944c-a78aa6dedddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
83323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3270383323
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4167364156
Short name T705
Test name
Test status
Simulation time 165504587 ps
CPU time 0.86 seconds
Started Aug 09 05:30:53 PM PDT 24
Finished Aug 09 05:30:53 PM PDT 24
Peak memory 207512 kb
Host smart-29f5523d-efdf-42c3-ae6d-28c2d2b73ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
64156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4167364156
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3741935254
Short name T2893
Test name
Test status
Simulation time 175917411 ps
CPU time 0.87 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207396 kb
Host smart-e4610b8a-d4cb-46a8-a7da-31d88541f2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
35254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3741935254
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.288691471
Short name T1389
Test name
Test status
Simulation time 262694879 ps
CPU time 1.08 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207504 kb
Host smart-0f6edded-799d-4a74-a83b-80ac1ff3a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
1471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.288691471
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1188799407
Short name T525
Test name
Test status
Simulation time 199671499 ps
CPU time 0.9 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207504 kb
Host smart-8aa739b5-4765-40cd-a0bb-e73b4ddc4da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
99407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1188799407
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2167395862
Short name T1226
Test name
Test status
Simulation time 227133049 ps
CPU time 1.01 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 207468 kb
Host smart-ad7bcc22-a5b1-4c31-bd12-dba15f3991cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2167395862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2167395862
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1168701978
Short name T2236
Test name
Test status
Simulation time 148838504 ps
CPU time 0.84 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207380 kb
Host smart-2f046bf6-528e-4862-b621-0f3b81640159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11687
01978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1168701978
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2383028331
Short name T1203
Test name
Test status
Simulation time 45897732 ps
CPU time 0.72 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207524 kb
Host smart-2ca24ede-570b-49d8-9864-51c9bda795cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830
28331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2383028331
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.4242532753
Short name T3269
Test name
Test status
Simulation time 7509323850 ps
CPU time 17.88 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 216004 kb
Host smart-a89f2e63-a31a-4474-b698-1d6a43b5d563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
32753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.4242532753
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3472191106
Short name T803
Test name
Test status
Simulation time 151805618 ps
CPU time 0.85 seconds
Started Aug 09 05:30:44 PM PDT 24
Finished Aug 09 05:30:45 PM PDT 24
Peak memory 207484 kb
Host smart-57510151-e288-4b66-ac4a-d992ce8e1564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34721
91106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3472191106
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3040809118
Short name T1115
Test name
Test status
Simulation time 233670648 ps
CPU time 0.97 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207480 kb
Host smart-00fb3916-8c58-47ce-aa2a-76d8f4c827fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
09118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3040809118
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.579893271
Short name T3397
Test name
Test status
Simulation time 218380213 ps
CPU time 1 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207552 kb
Host smart-a800f89b-c04b-450d-83f1-635d1362c3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57989
3271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.579893271
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3007504782
Short name T1751
Test name
Test status
Simulation time 147147260 ps
CPU time 0.83 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 207364 kb
Host smart-399b741c-af1d-4ac2-98aa-1d7e53459ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075
04782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3007504782
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.4003091465
Short name T3504
Test name
Test status
Simulation time 138096996 ps
CPU time 0.86 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207440 kb
Host smart-b569d5a5-8afe-47f0-8a48-e53ddbe28fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40030
91465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.4003091465
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.369892884
Short name T301
Test name
Test status
Simulation time 267042473 ps
CPU time 1.15 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 207552 kb
Host smart-02f09880-d392-4d46-b7b8-7c56671afd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
2884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.369892884
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.240768674
Short name T1634
Test name
Test status
Simulation time 156467762 ps
CPU time 0.86 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207476 kb
Host smart-dcb6a479-1b09-4dd1-9750-5cc5c0c4733a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24076
8674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.240768674
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3353464325
Short name T3104
Test name
Test status
Simulation time 153763644 ps
CPU time 0.86 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207552 kb
Host smart-93929fc5-ed24-4c92-8329-5c1e35bc7248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
64325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3353464325
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3052649511
Short name T1331
Test name
Test status
Simulation time 226440798 ps
CPU time 0.96 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207432 kb
Host smart-de217378-a825-4c79-b35b-92061735ddf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
49511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3052649511
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2024710955
Short name T1035
Test name
Test status
Simulation time 3043630565 ps
CPU time 24.79 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 218120 kb
Host smart-a8789936-b885-4a85-b97c-fdb76cd4b850
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2024710955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2024710955
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.672168591
Short name T1815
Test name
Test status
Simulation time 184633376 ps
CPU time 0.86 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207452 kb
Host smart-4569c185-2b70-45e4-beb4-b71d7b46d1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67216
8591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.672168591
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3662918384
Short name T3574
Test name
Test status
Simulation time 188040353 ps
CPU time 0.88 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207380 kb
Host smart-cea4f7ec-cc22-493d-a23a-8893823eb752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36629
18384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3662918384
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.536791603
Short name T2203
Test name
Test status
Simulation time 319419776 ps
CPU time 1.21 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207452 kb
Host smart-1f4bd817-21c5-4d9c-86b6-928a80262b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53679
1603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.536791603
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1986650315
Short name T844
Test name
Test status
Simulation time 3278466335 ps
CPU time 90.82 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 217360 kb
Host smart-a85877a6-b0ab-4a9c-9a8f-86ca27f931bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19866
50315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1986650315
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.1498756090
Short name T3604
Test name
Test status
Simulation time 5617436772 ps
CPU time 38.19 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:39 PM PDT 24
Peak memory 207820 kb
Host smart-d8f2433c-0ade-4ff2-b7d8-720339771287
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498756090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.1498756090
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.3876496321
Short name T2738
Test name
Test status
Simulation time 586302892 ps
CPU time 1.53 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 207400 kb
Host smart-66f172e8-1290-4cb4-8aca-42029004693f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876496321 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.3876496321
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.2248095500
Short name T1858
Test name
Test status
Simulation time 498570505 ps
CPU time 1.43 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 207536 kb
Host smart-26b2518b-f13c-4285-aeb7-f03d93229d14
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248095500 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.2248095500
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.35144416
Short name T3066
Test name
Test status
Simulation time 478485368 ps
CPU time 1.64 seconds
Started Aug 09 05:33:43 PM PDT 24
Finished Aug 09 05:33:45 PM PDT 24
Peak memory 207496 kb
Host smart-8c827039-d671-4fda-b039-c66a0c0b8a35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144416 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.35144416
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.1403170261
Short name T2585
Test name
Test status
Simulation time 487921358 ps
CPU time 1.47 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:47 PM PDT 24
Peak memory 207508 kb
Host smart-2b4bbf00-3c02-4cb9-b401-8d450b106e0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403170261 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.1403170261
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.2707335222
Short name T1549
Test name
Test status
Simulation time 539079245 ps
CPU time 1.64 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207388 kb
Host smart-49556afb-81e0-434a-a48e-eb380cdfb984
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707335222 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.2707335222
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.2501141654
Short name T2769
Test name
Test status
Simulation time 472878211 ps
CPU time 1.5 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207488 kb
Host smart-636f756b-06b6-4872-b439-3b1653427d7b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501141654 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.2501141654
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.405904833
Short name T603
Test name
Test status
Simulation time 517720394 ps
CPU time 1.61 seconds
Started Aug 09 05:33:40 PM PDT 24
Finished Aug 09 05:33:41 PM PDT 24
Peak memory 207432 kb
Host smart-c3f864a9-63c3-46a3-b59d-5490d1be2e21
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405904833 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.405904833
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.2166034746
Short name T2433
Test name
Test status
Simulation time 583276912 ps
CPU time 1.58 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207444 kb
Host smart-feb69af2-74ae-4e39-a3d3-fd4694e5c98b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166034746 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.2166034746
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.1378215115
Short name T2968
Test name
Test status
Simulation time 518326993 ps
CPU time 1.43 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207536 kb
Host smart-386dc439-c482-4ebc-b658-26121fe5c16f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378215115 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.1378215115
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.2400810925
Short name T746
Test name
Test status
Simulation time 561176437 ps
CPU time 1.6 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207440 kb
Host smart-6ac65e67-9a28-4647-8301-ea21d5ea620f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400810925 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.2400810925
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.734443574
Short name T1610
Test name
Test status
Simulation time 465519288 ps
CPU time 1.42 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207464 kb
Host smart-5faf639c-6bd3-4abf-8362-bdb848e67f28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734443574 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.734443574
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2027439757
Short name T198
Test name
Test status
Simulation time 100072146 ps
CPU time 0.72 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207460 kb
Host smart-ab61cee6-e53e-440f-b9e6-1c7aa2f03d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2027439757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2027439757
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4077680297
Short name T1366
Test name
Test status
Simulation time 11692013207 ps
CPU time 14.5 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 207680 kb
Host smart-d93b278c-4a4a-45e0-9bbf-81eccecd471e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077680297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.4077680297
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1013797647
Short name T893
Test name
Test status
Simulation time 15423746555 ps
CPU time 18.29 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:25 PM PDT 24
Peak memory 215856 kb
Host smart-a326c8f0-0b43-4456-afd5-2c0b01cb5f47
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013797647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1013797647
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.4159213396
Short name T1579
Test name
Test status
Simulation time 30299367753 ps
CPU time 37.41 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207828 kb
Host smart-06561267-860e-44d4-ac4e-55a933332942
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159213396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.4159213396
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1351074404
Short name T3508
Test name
Test status
Simulation time 174816402 ps
CPU time 0.93 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207416 kb
Host smart-6677882d-dd26-42dd-b834-8619b9644d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
74404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1351074404
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1781589152
Short name T851
Test name
Test status
Simulation time 165957401 ps
CPU time 0.86 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207408 kb
Host smart-c66b24ca-910e-4f55-87e8-71ea664f3b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17815
89152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1781589152
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.664372862
Short name T2148
Test name
Test status
Simulation time 342925763 ps
CPU time 1.4 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207560 kb
Host smart-29bea31d-f2bc-45ea-95e4-d36432656524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66437
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.664372862
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3887789904
Short name T3512
Test name
Test status
Simulation time 30386606626 ps
CPU time 48.48 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207804 kb
Host smart-db800ec0-22b6-4496-8a70-7ae79d6488f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
89904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3887789904
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.94419845
Short name T2279
Test name
Test status
Simulation time 2525138883 ps
CPU time 21.51 seconds
Started Aug 09 05:31:00 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 207756 kb
Host smart-540d62c4-e56c-4a69-b93f-57f9319d7b49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94419845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.94419845
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.619623751
Short name T887
Test name
Test status
Simulation time 578319700 ps
CPU time 1.56 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:58 PM PDT 24
Peak memory 207424 kb
Host smart-31346288-a614-4f16-9d2b-9f612bb1776d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61962
3751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.619623751
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1603403481
Short name T2077
Test name
Test status
Simulation time 152100988 ps
CPU time 0.87 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 207364 kb
Host smart-1a6af81c-23eb-43ad-99e4-366e5c7ddbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16034
03481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1603403481
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.651405942
Short name T1733
Test name
Test status
Simulation time 43336894 ps
CPU time 0.71 seconds
Started Aug 09 05:31:00 PM PDT 24
Finished Aug 09 05:31:01 PM PDT 24
Peak memory 207404 kb
Host smart-4bbc55f3-0280-4eda-9b55-a40b16031f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65140
5942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.651405942
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2303934766
Short name T822
Test name
Test status
Simulation time 934445236 ps
CPU time 2.25 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:01 PM PDT 24
Peak memory 207656 kb
Host smart-21f5074c-eead-4d4a-b368-b50edece6753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2303934766
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.317912762
Short name T2846
Test name
Test status
Simulation time 477888849 ps
CPU time 1.39 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 207516 kb
Host smart-0c1df91e-3723-4440-b438-84fcec3e3d7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=317912762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.317912762
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.860344201
Short name T3165
Test name
Test status
Simulation time 152421225 ps
CPU time 1.56 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207580 kb
Host smart-14dce9d8-3b62-45b3-bd16-11eace693b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86034
4201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.860344201
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.326421932
Short name T1207
Test name
Test status
Simulation time 179228801 ps
CPU time 0.93 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 207472 kb
Host smart-85531505-3049-4506-af59-6fa79d4b1e36
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=326421932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.326421932
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3043196882
Short name T2943
Test name
Test status
Simulation time 143576018 ps
CPU time 0.8 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207388 kb
Host smart-8c28a1e0-495d-4199-9bf0-5de39f9ec5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30431
96882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3043196882
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2800231972
Short name T1505
Test name
Test status
Simulation time 212133893 ps
CPU time 1.01 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207448 kb
Host smart-7dfdee70-3430-4dc4-883e-203910d98a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28002
31972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2800231972
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2626666281
Short name T1744
Test name
Test status
Simulation time 12296429834 ps
CPU time 89.53 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 207812 kb
Host smart-8c77a5e7-09f7-4d50-ac40-278ec5b8011b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2626666281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2626666281
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2025458691
Short name T1504
Test name
Test status
Simulation time 167162248 ps
CPU time 0.92 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207412 kb
Host smart-11dcb56a-bb81-4774-a51b-3799656f6507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254
58691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2025458691
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1593412615
Short name T1086
Test name
Test status
Simulation time 31808642297 ps
CPU time 53.11 seconds
Started Aug 09 05:31:20 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207796 kb
Host smart-a01c185f-5fb7-4f2a-b82b-e15dc46ae3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15934
12615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1593412615
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1089408222
Short name T2588
Test name
Test status
Simulation time 3880850952 ps
CPU time 5.13 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 215080 kb
Host smart-e31f9dfc-b87b-4770-bd87-4e965e7e5bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
08222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1089408222
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.4278279518
Short name T229
Test name
Test status
Simulation time 3564388225 ps
CPU time 107.82 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 218608 kb
Host smart-45039f21-a4d7-48fe-aeae-e87a185194f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4278279518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.4278279518
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3114692315
Short name T2087
Test name
Test status
Simulation time 1478233550 ps
CPU time 39.43 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 215988 kb
Host smart-5052a4d9-0eff-43f4-9903-1a797fb33ce0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3114692315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3114692315
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1190381579
Short name T1876
Test name
Test status
Simulation time 242354798 ps
CPU time 0.99 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207376 kb
Host smart-c5a7571e-0af5-4873-8adb-f0f60eaa582d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1190381579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1190381579
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.357996219
Short name T1281
Test name
Test status
Simulation time 193000759 ps
CPU time 0.93 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 207508 kb
Host smart-a12489c9-32a6-428c-8edb-304f9804ae9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35799
6219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.357996219
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3687830807
Short name T1721
Test name
Test status
Simulation time 3837965827 ps
CPU time 111.46 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 217476 kb
Host smart-4e205da4-fba1-45e9-8e81-5a7ac553a8ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3687830807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3687830807
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.278242453
Short name T2090
Test name
Test status
Simulation time 147051591 ps
CPU time 0.83 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207476 kb
Host smart-2c4b75ae-7833-48bc-9b43-105ff80fb3d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=278242453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.278242453
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2082456154
Short name T3161
Test name
Test status
Simulation time 181934832 ps
CPU time 0.86 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207472 kb
Host smart-4ac2fc23-56ef-49c9-8747-a64add7ad7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20824
56154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2082456154
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.962170809
Short name T121
Test name
Test status
Simulation time 263246139 ps
CPU time 1.01 seconds
Started Aug 09 05:31:12 PM PDT 24
Finished Aug 09 05:31:13 PM PDT 24
Peak memory 207512 kb
Host smart-fafc3229-2cc2-4658-9414-7d83afa2168b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96217
0809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.962170809
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3585152710
Short name T2405
Test name
Test status
Simulation time 188846030 ps
CPU time 0.99 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:02 PM PDT 24
Peak memory 207528 kb
Host smart-cf585e57-7544-425d-956a-87400a9931f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35851
52710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3585152710
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1856578195
Short name T3364
Test name
Test status
Simulation time 241132914 ps
CPU time 0.93 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207400 kb
Host smart-6dfea6f0-f279-44c3-9c79-63afd19ee30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
78195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1856578195
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3623229290
Short name T1778
Test name
Test status
Simulation time 196703924 ps
CPU time 0.89 seconds
Started Aug 09 05:30:57 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207428 kb
Host smart-7f5044c0-14b6-42fa-9d82-b9c77d66baaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
29290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3623229290
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.639237984
Short name T1380
Test name
Test status
Simulation time 148005302 ps
CPU time 0.83 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:12 PM PDT 24
Peak memory 207392 kb
Host smart-6d487c6a-0914-4b86-8aad-f167057b5cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63923
7984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.639237984
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1400054693
Short name T1794
Test name
Test status
Simulation time 180444418 ps
CPU time 0.97 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207536 kb
Host smart-75144465-ce1b-42d6-979a-6937d14d60fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1400054693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1400054693
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3460954460
Short name T2915
Test name
Test status
Simulation time 146197355 ps
CPU time 0.88 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207352 kb
Host smart-2fb37b34-ff83-41fc-819f-c2fed8228fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34609
54460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3460954460
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2706931495
Short name T939
Test name
Test status
Simulation time 81297232 ps
CPU time 0.75 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207440 kb
Host smart-53c20ffd-7e30-4248-aa8c-07a11603e866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
31495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2706931495
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1681460904
Short name T2766
Test name
Test status
Simulation time 14913592666 ps
CPU time 40.93 seconds
Started Aug 09 05:30:55 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 215968 kb
Host smart-d6fb019d-ee1e-4d76-9261-d1fd493456db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
60904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1681460904
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3121636681
Short name T1252
Test name
Test status
Simulation time 147575600 ps
CPU time 0.82 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207548 kb
Host smart-06a00b1c-6082-40b8-928b-ba4da4ffec99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31216
36681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3121636681
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3525946203
Short name T3414
Test name
Test status
Simulation time 198247849 ps
CPU time 0.97 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207544 kb
Host smart-6aded6bc-07e4-49c3-8372-45cefc43f706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35259
46203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3525946203
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3308683366
Short name T1801
Test name
Test status
Simulation time 205093840 ps
CPU time 0.97 seconds
Started Aug 09 05:30:59 PM PDT 24
Finished Aug 09 05:31:00 PM PDT 24
Peak memory 207448 kb
Host smart-adee692f-7a8a-4859-88a7-8fd96d2b6842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
83366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3308683366
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.412579329
Short name T626
Test name
Test status
Simulation time 177714547 ps
CPU time 0.91 seconds
Started Aug 09 05:30:56 PM PDT 24
Finished Aug 09 05:30:57 PM PDT 24
Peak memory 207784 kb
Host smart-0076a998-0e0d-4100-91bd-82aa7fdbd686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
9329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.412579329
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1913761982
Short name T1957
Test name
Test status
Simulation time 150493096 ps
CPU time 0.84 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207364 kb
Host smart-286b41c9-844f-44bb-864c-3f77a2dbecfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
61982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1913761982
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.3233798532
Short name T303
Test name
Test status
Simulation time 250408617 ps
CPU time 1.11 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207448 kb
Host smart-6eb49bd7-41ef-4512-9a3b-1fa85472f60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
98532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.3233798532
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.977990191
Short name T1729
Test name
Test status
Simulation time 185453746 ps
CPU time 0.85 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207520 kb
Host smart-26223c6f-f9d9-4119-b04a-b4eaa91c5c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97799
0191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.977990191
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.158592628
Short name T2019
Test name
Test status
Simulation time 178912595 ps
CPU time 0.9 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207568 kb
Host smart-55d64554-b501-49c2-aa51-a77d67452a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15859
2628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.158592628
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.393022756
Short name T1981
Test name
Test status
Simulation time 215400174 ps
CPU time 1.02 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207476 kb
Host smart-a189ecc9-9dc6-4ed9-9750-c9e6182f6103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39302
2756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.393022756
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2631465224
Short name T3249
Test name
Test status
Simulation time 2040255080 ps
CPU time 56.3 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 223980 kb
Host smart-476b9906-63cc-4beb-83ad-38b168207030
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2631465224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2631465224
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.347854867
Short name T2844
Test name
Test status
Simulation time 173115841 ps
CPU time 0.89 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207504 kb
Host smart-03fdd6c5-9c7d-4371-8aff-e73052dee80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34785
4867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.347854867
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.326783718
Short name T3096
Test name
Test status
Simulation time 210250206 ps
CPU time 0.92 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207496 kb
Host smart-8a35aa1c-3c82-4a98-8c5e-5175d5ed235e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
3718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.326783718
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2578774242
Short name T2289
Test name
Test status
Simulation time 493082493 ps
CPU time 1.45 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207440 kb
Host smart-2e494caa-e02c-4b9c-966a-d4ea0f00cdc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
74242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2578774242
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3694644297
Short name T1074
Test name
Test status
Simulation time 3994364389 ps
CPU time 32.55 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 216104 kb
Host smart-9c1fd657-da17-4265-b07a-0325ae271385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36946
44297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3694644297
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.4020526250
Short name T1597
Test name
Test status
Simulation time 5731015184 ps
CPU time 36.99 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207776 kb
Host smart-5a44404b-2f9e-4e7e-8cba-10c43016bfbe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020526250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.4020526250
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.1784734310
Short name T185
Test name
Test status
Simulation time 583592858 ps
CPU time 1.65 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207444 kb
Host smart-f84c6e34-2f76-47c9-b9bb-610205e6d4be
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784734310 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.1784734310
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.2800994372
Short name T1079
Test name
Test status
Simulation time 493863201 ps
CPU time 1.45 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207496 kb
Host smart-f173d1e6-fab4-41d2-aeeb-36d918e33a67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800994372 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.2800994372
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.3165026026
Short name T981
Test name
Test status
Simulation time 515131652 ps
CPU time 1.55 seconds
Started Aug 09 05:33:34 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 207472 kb
Host smart-96c8f4ff-2a76-4656-8f9a-1640aa60c453
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165026026 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.3165026026
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.760385833
Short name T2845
Test name
Test status
Simulation time 512097938 ps
CPU time 1.54 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207452 kb
Host smart-0a377884-7607-4d6e-97c5-ae436dfabb26
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760385833 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.760385833
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.685033432
Short name T2430
Test name
Test status
Simulation time 512915855 ps
CPU time 1.68 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207532 kb
Host smart-cfe77ad4-699c-40c0-b00e-7e118e6d8da4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685033432 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.685033432
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.1534201020
Short name T2728
Test name
Test status
Simulation time 549802655 ps
CPU time 1.45 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207512 kb
Host smart-33cd7ecb-42ba-48ee-8c2e-57de98619309
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534201020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.1534201020
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.1988560447
Short name T2750
Test name
Test status
Simulation time 503433396 ps
CPU time 1.5 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207512 kb
Host smart-f56406aa-2c05-4ce5-aecf-24dba0e976ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988560447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.1988560447
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.1762110835
Short name T2749
Test name
Test status
Simulation time 659615375 ps
CPU time 1.65 seconds
Started Aug 09 05:33:47 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 207532 kb
Host smart-1f0db4aa-c58c-41d7-8ccf-9700b5018caf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762110835 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.1762110835
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.1516910287
Short name T763
Test name
Test status
Simulation time 498037148 ps
CPU time 1.39 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207396 kb
Host smart-64828842-e4ab-4cc1-b72d-2e18a1cbd76c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516910287 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.1516910287
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.1365291078
Short name T153
Test name
Test status
Simulation time 639075623 ps
CPU time 1.81 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207404 kb
Host smart-8aff8388-9667-4f03-b3a4-76d581dcf8f3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365291078 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.1365291078
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.4213418385
Short name T2528
Test name
Test status
Simulation time 609017390 ps
CPU time 1.61 seconds
Started Aug 09 05:33:41 PM PDT 24
Finished Aug 09 05:33:43 PM PDT 24
Peak memory 207380 kb
Host smart-3e864d60-96bd-495c-bdc0-0fd459c71321
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213418385 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.4213418385
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3313606593
Short name T1956
Test name
Test status
Simulation time 46214180 ps
CPU time 0.7 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207812 kb
Host smart-3fabe846-99c4-4ffc-8b98-2116a24b34dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3313606593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3313606593
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.172982698
Short name T2851
Test name
Test status
Simulation time 5860612608 ps
CPU time 8.2 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 216028 kb
Host smart-7f95baff-15ef-4f54-bcbf-bf1cf99746b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172982698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_disconnect.172982698
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.180100902
Short name T2060
Test name
Test status
Simulation time 14048253187 ps
CPU time 18.65 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:29 PM PDT 24
Peak memory 215876 kb
Host smart-497a8eb6-ad34-48bf-9e0d-54f025d4bbc9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=180100902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.180100902
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2769785127
Short name T1706
Test name
Test status
Simulation time 30586372281 ps
CPU time 42.91 seconds
Started Aug 09 05:31:00 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207780 kb
Host smart-a80c09ee-efa7-41d6-91f2-b5d78769f842
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769785127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2769785127
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1016439284
Short name T554
Test name
Test status
Simulation time 145103173 ps
CPU time 0.82 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207556 kb
Host smart-f4aa1650-fc67-42d5-b438-8a29a5a51343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
39284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1016439284
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3728873186
Short name T3631
Test name
Test status
Simulation time 162903110 ps
CPU time 0.89 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207472 kb
Host smart-34c4c381-efd3-45d0-aa24-5723aac98d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
73186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3728873186
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2850155945
Short name T2040
Test name
Test status
Simulation time 186138582 ps
CPU time 0.92 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:30:59 PM PDT 24
Peak memory 207476 kb
Host smart-7dfd70d5-78cc-4bce-9f25-5902648cbcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28501
55945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2850155945
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2821712134
Short name T3412
Test name
Test status
Simulation time 401565999 ps
CPU time 1.26 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207356 kb
Host smart-ce57ff2c-3ba1-4f21-975f-3e0d40b36369
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2821712134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2821712134
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.4255832728
Short name T1513
Test name
Test status
Simulation time 24670865433 ps
CPU time 39.38 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207824 kb
Host smart-5adfb0b8-b1e4-4caf-a607-db117803634b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
32728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.4255832728
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.3673679220
Short name T3231
Test name
Test status
Simulation time 1310959569 ps
CPU time 30.08 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207664 kb
Host smart-dae00b01-3950-4a68-ba63-058db82be94e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673679220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.3673679220
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1212735739
Short name T1106
Test name
Test status
Simulation time 508942280 ps
CPU time 1.61 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207476 kb
Host smart-f25387cf-7f90-4284-8172-badbdc71bc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127
35739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1212735739
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_enable.1268679903
Short name T3195
Test name
Test status
Simulation time 65590363 ps
CPU time 0.77 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207436 kb
Host smart-7e1606b9-dfb4-4832-9322-a3c827176cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12686
79903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1268679903
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2184763199
Short name T3093
Test name
Test status
Simulation time 652024165 ps
CPU time 1.88 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 207728 kb
Host smart-48cc4b73-1115-4964-af7a-e15a2a62b265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
63199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2184763199
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.2259001449
Short name T2351
Test name
Test status
Simulation time 418015369 ps
CPU time 1.36 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207488 kb
Host smart-857806fe-3b2d-44bd-a211-a51cc869c6ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2259001449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.2259001449
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1638794735
Short name T625
Test name
Test status
Simulation time 257038960 ps
CPU time 1.82 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207652 kb
Host smart-a95865ff-7148-42a6-9317-bbbb5b2f32f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16387
94735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1638794735
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2263726
Short name T526
Test name
Test status
Simulation time 174814760 ps
CPU time 0.92 seconds
Started Aug 09 05:31:07 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207436 kb
Host smart-e49e4368-d28c-4c03-bc76-96130feef796
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2263726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2263726
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2983808589
Short name T3147
Test name
Test status
Simulation time 161557783 ps
CPU time 0.84 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207524 kb
Host smart-8626ab46-5c2b-4bed-9875-2c05eedda971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
08589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2983808589
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.835530389
Short name T3051
Test name
Test status
Simulation time 218568024 ps
CPU time 1.05 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207516 kb
Host smart-8262aa53-1df1-4e65-807c-1f6a7f5d5e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83553
0389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.835530389
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.597615261
Short name T1933
Test name
Test status
Simulation time 3849817214 ps
CPU time 108.39 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 217588 kb
Host smart-b925b0cf-abff-4372-be88-08e1dd7ca822
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=597615261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.597615261
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.3527364305
Short name T3551
Test name
Test status
Simulation time 8390731740 ps
CPU time 58.89 seconds
Started Aug 09 05:31:01 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207692 kb
Host smart-192af4c7-5e0e-4996-98c5-e146b3f5a615
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3527364305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.3527364305
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.456961238
Short name T2061
Test name
Test status
Simulation time 226925976 ps
CPU time 0.99 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207380 kb
Host smart-2d5ad996-c656-4419-8c90-ecf344919cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45696
1238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.456961238
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1509336516
Short name T980
Test name
Test status
Simulation time 25964012043 ps
CPU time 44.46 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 216068 kb
Host smart-003d07b4-aa32-41d9-9bd9-205062ec7eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
36516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1509336516
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2938814560
Short name T841
Test name
Test status
Simulation time 4437448960 ps
CPU time 6.65 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 216168 kb
Host smart-fd76fe80-41f2-44fd-ba08-0b3044f7951d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
14560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2938814560
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4155277288
Short name T2166
Test name
Test status
Simulation time 3087189833 ps
CPU time 25.59 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 218944 kb
Host smart-45c6bbe2-9abc-4799-9b78-30bfc786ce6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4155277288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4155277288
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.573416374
Short name T1433
Test name
Test status
Simulation time 4100685147 ps
CPU time 32.46 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 216084 kb
Host smart-26c97993-5c6a-494d-a6e6-97f085a272c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=573416374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.573416374
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.886045202
Short name T655
Test name
Test status
Simulation time 250147548 ps
CPU time 1.01 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207460 kb
Host smart-ab0e488b-3c67-474c-9915-e8a0f3db2f92
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=886045202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.886045202
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1680108093
Short name T1888
Test name
Test status
Simulation time 199337766 ps
CPU time 1.01 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207548 kb
Host smart-74b746af-0fad-4380-90ed-8bff1a66e757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
08093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1680108093
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2561602393
Short name T789
Test name
Test status
Simulation time 1715373540 ps
CPU time 47.76 seconds
Started Aug 09 05:30:58 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 223400 kb
Host smart-9780ca72-6fc1-4f65-aa28-ed1d6f760a0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2561602393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2561602393
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3313748310
Short name T3019
Test name
Test status
Simulation time 153531572 ps
CPU time 0.84 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207500 kb
Host smart-6a75b435-f17c-4699-80b2-2cb3b74e9d9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3313748310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3313748310
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1431966219
Short name T2914
Test name
Test status
Simulation time 178452499 ps
CPU time 0.91 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:31:08 PM PDT 24
Peak memory 207432 kb
Host smart-d01b88f9-0b8d-43ce-87c7-2c8f852df900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
66219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1431966219
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2098701061
Short name T3049
Test name
Test status
Simulation time 232536321 ps
CPU time 0.97 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207556 kb
Host smart-5728c9bc-ddc3-41b3-996d-f03c98660c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
01061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2098701061
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1500389919
Short name T1508
Test name
Test status
Simulation time 250739748 ps
CPU time 1.01 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:10 PM PDT 24
Peak memory 207404 kb
Host smart-2321b7f8-f5cb-4584-884c-0c4eca1fce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15003
89919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1500389919
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3499250453
Short name T2067
Test name
Test status
Simulation time 202272633 ps
CPU time 0.95 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207504 kb
Host smart-11df52ba-ff35-4d21-94f2-c426b133eda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992
50453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3499250453
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1752944117
Short name T2337
Test name
Test status
Simulation time 182885182 ps
CPU time 0.94 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207436 kb
Host smart-9b6e47f7-daf7-4d96-aad2-b29dc3cba7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529
44117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1752944117
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3762273677
Short name T1244
Test name
Test status
Simulation time 164621407 ps
CPU time 0.84 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:12 PM PDT 24
Peak memory 207504 kb
Host smart-859f7084-14c2-494f-b10c-f088d3287064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37622
73677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3762273677
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.87993540
Short name T1087
Test name
Test status
Simulation time 233188657 ps
CPU time 0.95 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207476 kb
Host smart-a0b5f715-ed39-40d1-a9b0-00d2d961ac7c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=87993540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.87993540
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2413036023
Short name T2024
Test name
Test status
Simulation time 154170179 ps
CPU time 0.87 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:12 PM PDT 24
Peak memory 207328 kb
Host smart-58e1753e-dcc4-4b9b-99e6-6d514be932d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24130
36023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2413036023
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.749219422
Short name T25
Test name
Test status
Simulation time 48767101 ps
CPU time 0.73 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207372 kb
Host smart-ad71ecce-e991-4156-91b2-fd1854aa64f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74921
9422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.749219422
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3024039986
Short name T3126
Test name
Test status
Simulation time 19294609466 ps
CPU time 50.32 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 216008 kb
Host smart-fe6b31ef-9334-4bd1-a232-2d528f321c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
39986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3024039986
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1631764032
Short name T1100
Test name
Test status
Simulation time 203378658 ps
CPU time 1.02 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207404 kb
Host smart-30d35048-c1fc-412d-b684-80a7e8638784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317
64032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1631764032
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3718414381
Short name T2521
Test name
Test status
Simulation time 227011728 ps
CPU time 0.94 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:09 PM PDT 24
Peak memory 207484 kb
Host smart-c9095a7e-79c2-4b71-8f79-42c67019a635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37184
14381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3718414381
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3937470254
Short name T2524
Test name
Test status
Simulation time 194566782 ps
CPU time 0.91 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207472 kb
Host smart-69096f59-6287-4fe5-9c5e-52455e2a8b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
70254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3937470254
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1728926690
Short name T2432
Test name
Test status
Simulation time 185326966 ps
CPU time 1.05 seconds
Started Aug 09 05:31:04 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207528 kb
Host smart-60aece4e-fccd-4b58-9eed-564bba036845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
26690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1728926690
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1753151775
Short name T2568
Test name
Test status
Simulation time 171011378 ps
CPU time 0.84 seconds
Started Aug 09 05:31:05 PM PDT 24
Finished Aug 09 05:31:06 PM PDT 24
Peak memory 207476 kb
Host smart-0285a823-e501-4efa-a5b6-35e477533170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
51775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1753151775
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.3691968418
Short name T306
Test name
Test status
Simulation time 296358087 ps
CPU time 1.18 seconds
Started Aug 09 05:31:25 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 207404 kb
Host smart-07615114-9742-47a4-8083-a95fd18961a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
68418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3691968418
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.256209575
Short name T1618
Test name
Test status
Simulation time 161663200 ps
CPU time 0.86 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:03 PM PDT 24
Peak memory 207468 kb
Host smart-e537484b-47f3-4988-8691-9fed12d836f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
9575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.256209575
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3864436682
Short name T1842
Test name
Test status
Simulation time 147946292 ps
CPU time 0.84 seconds
Started Aug 09 05:31:21 PM PDT 24
Finished Aug 09 05:31:22 PM PDT 24
Peak memory 207512 kb
Host smart-cc2e9ca2-9264-4254-8485-001d3f0b03a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
36682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3864436682
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.925636291
Short name T1547
Test name
Test status
Simulation time 233588660 ps
CPU time 1.04 seconds
Started Aug 09 05:31:09 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207440 kb
Host smart-d8b6feaa-3701-446b-b433-7a41d699448c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92563
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.925636291
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.961586960
Short name T2803
Test name
Test status
Simulation time 2367455457 ps
CPU time 19.18 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:22 PM PDT 24
Peak memory 217904 kb
Host smart-e11843e0-0bdd-4d84-8970-ddf8fd2f76c7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=961586960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.961586960
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2832743057
Short name T3294
Test name
Test status
Simulation time 191127133 ps
CPU time 0.94 seconds
Started Aug 09 05:31:02 PM PDT 24
Finished Aug 09 05:31:04 PM PDT 24
Peak memory 207508 kb
Host smart-1887014b-f363-4ec2-aff3-37b76251348c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28327
43057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2832743057
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1917621110
Short name T1180
Test name
Test status
Simulation time 198102497 ps
CPU time 0.89 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207472 kb
Host smart-bba8eddd-2899-4fa9-9020-0bd7a3c9a11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176
21110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1917621110
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3180005525
Short name T2912
Test name
Test status
Simulation time 282000923 ps
CPU time 1.1 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207760 kb
Host smart-600f8a8e-04dc-40db-89cd-6dc9b42115e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800
05525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3180005525
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3563858535
Short name T3119
Test name
Test status
Simulation time 2754113007 ps
CPU time 22.59 seconds
Started Aug 09 05:31:27 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 216056 kb
Host smart-b0661291-5129-4c29-921a-cacb8c954838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
58535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3563858535
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.694539675
Short name T750
Test name
Test status
Simulation time 1117041767 ps
CPU time 25.89 seconds
Started Aug 09 05:31:20 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207620 kb
Host smart-f8d4ca58-42f5-43b3-b9c2-f5a190ffe7ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694539675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host
_handshake.694539675
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.1536618665
Short name T2139
Test name
Test status
Simulation time 541587143 ps
CPU time 1.8 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207484 kb
Host smart-bfd9c816-0b4b-46d2-9f1b-f8c724218a2c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536618665 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.1536618665
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.206419695
Short name T2604
Test name
Test status
Simulation time 520056644 ps
CPU time 1.49 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207464 kb
Host smart-e0167762-93fb-4515-812d-931373a3c2e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206419695 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.206419695
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.864641524
Short name T186
Test name
Test status
Simulation time 558322586 ps
CPU time 1.52 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207412 kb
Host smart-923c4b39-adfd-4865-9d2e-a3bc254d6645
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864641524 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.864641524
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.4184580836
Short name T1641
Test name
Test status
Simulation time 462510798 ps
CPU time 1.6 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207516 kb
Host smart-6abf69f4-4b4a-4444-b85b-8718dd90c046
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184580836 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.4184580836
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.161629516
Short name T1337
Test name
Test status
Simulation time 535967607 ps
CPU time 1.73 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207808 kb
Host smart-a57b4634-e1cf-4a3b-8069-e4ffe9ae208d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161629516 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.161629516
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.1716612442
Short name T1861
Test name
Test status
Simulation time 529495672 ps
CPU time 1.64 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207516 kb
Host smart-dfdc6886-95e5-4d4d-bf09-5de498d41a97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716612442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.1716612442
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.3927761150
Short name T2321
Test name
Test status
Simulation time 631291966 ps
CPU time 1.66 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207484 kb
Host smart-87a444ff-0a9a-493a-ae6f-917e9d215c00
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927761150 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.3927761150
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.3985189009
Short name T2859
Test name
Test status
Simulation time 612149057 ps
CPU time 1.62 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207500 kb
Host smart-88a78baf-830b-4511-afb0-3f6954bf3f45
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985189009 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.3985189009
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.3202517986
Short name T3369
Test name
Test status
Simulation time 647071325 ps
CPU time 1.71 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207512 kb
Host smart-a63fd61f-3df1-4921-948e-6a24fe9463cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202517986 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.3202517986
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.664744935
Short name T571
Test name
Test status
Simulation time 524549474 ps
CPU time 1.6 seconds
Started Aug 09 05:33:51 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207400 kb
Host smart-7641653d-871a-4673-b079-ae884c159fc1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664744935 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.664744935
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1962792563
Short name T3089
Test name
Test status
Simulation time 40820370 ps
CPU time 0.72 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207468 kb
Host smart-bd0e14d6-b082-4c33-9af6-f857a09f0464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1962792563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1962792563
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3771790173
Short name T2979
Test name
Test status
Simulation time 9829198910 ps
CPU time 13.22 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:31:19 PM PDT 24
Peak memory 207772 kb
Host smart-6640dcae-c20d-4dc5-8ee6-5281a280aee3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771790173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.3771790173
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1258491035
Short name T2843
Test name
Test status
Simulation time 14789827518 ps
CPU time 20.04 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 215964 kb
Host smart-c0a3c4a5-76b7-4f46-9a21-9b9bfdb7e3c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258491035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1258491035
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.4000824750
Short name T3223
Test name
Test status
Simulation time 24956277369 ps
CPU time 33.74 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 215908 kb
Host smart-997eb48b-10a5-410f-bb47-da9874afcd6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000824750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.4000824750
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.894587031
Short name T2398
Test name
Test status
Simulation time 206777714 ps
CPU time 0.93 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207476 kb
Host smart-6f574ef0-e7ef-47a2-b864-23b7a359748f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89458
7031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.894587031
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3772284585
Short name T1017
Test name
Test status
Simulation time 155466902 ps
CPU time 0.84 seconds
Started Aug 09 05:31:12 PM PDT 24
Finished Aug 09 05:31:13 PM PDT 24
Peak memory 207532 kb
Host smart-916f5970-4da2-45af-82ab-f082b8e3743d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37722
84585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3772284585
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1923212752
Short name T1196
Test name
Test status
Simulation time 281566420 ps
CPU time 1.2 seconds
Started Aug 09 05:31:39 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207440 kb
Host smart-8f95f9f0-ea62-4ffa-a363-5fcf10a282c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19232
12752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1923212752
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3335363022
Short name T320
Test name
Test status
Simulation time 279516894 ps
CPU time 1.07 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207500 kb
Host smart-2f4401de-b0c1-4534-b413-e7ff26f441d2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3335363022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3335363022
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1988583138
Short name T2830
Test name
Test status
Simulation time 50247870051 ps
CPU time 76.81 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 207768 kb
Host smart-8df02028-e43e-45f9-a69b-9e262997220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
83138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1988583138
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2757243103
Short name T2010
Test name
Test status
Simulation time 269383190 ps
CPU time 4.28 seconds
Started Aug 09 05:31:18 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 207692 kb
Host smart-f0be4ffc-ded6-4754-ac95-c6c60cb9713e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757243103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2757243103
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2486023962
Short name T3279
Test name
Test status
Simulation time 630904987 ps
CPU time 1.66 seconds
Started Aug 09 05:31:03 PM PDT 24
Finished Aug 09 05:31:05 PM PDT 24
Peak memory 207516 kb
Host smart-b788e025-af49-4f86-9c19-8233ebf5d883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24860
23962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2486023962
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.504615709
Short name T2496
Test name
Test status
Simulation time 176428124 ps
CPU time 0.91 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 207432 kb
Host smart-6d69ad5b-6b02-4aeb-a5da-d8c6015f90da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50461
5709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.504615709
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.661712861
Short name T3600
Test name
Test status
Simulation time 64090577 ps
CPU time 0.74 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207420 kb
Host smart-ca16051e-13e8-48ef-ab6f-f89eecfc9e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66171
2861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.661712861
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.993154869
Short name T1652
Test name
Test status
Simulation time 1069716806 ps
CPU time 2.49 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207656 kb
Host smart-e580c767-305c-4a44-a02f-63979d2857ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99315
4869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.993154869
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.2400171143
Short name T439
Test name
Test status
Simulation time 404860050 ps
CPU time 1.32 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207464 kb
Host smart-49ffbe01-d0dc-4fd2-bf3e-f3a7c6f5a2fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2400171143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.2400171143
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.359453863
Short name T1084
Test name
Test status
Simulation time 190525905 ps
CPU time 2.14 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207692 kb
Host smart-6b35982d-11a5-4836-965c-631cb8faa3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35945
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.359453863
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3780159600
Short name T1645
Test name
Test status
Simulation time 210241845 ps
CPU time 1.08 seconds
Started Aug 09 05:31:06 PM PDT 24
Finished Aug 09 05:31:07 PM PDT 24
Peak memory 216160 kb
Host smart-a0480c5a-0ca6-4b93-b876-56a4f81bb86d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3780159600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3780159600
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.337679504
Short name T114
Test name
Test status
Simulation time 158951632 ps
CPU time 0.84 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207472 kb
Host smart-28cd3f92-6968-4604-b29a-2227adda3869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33767
9504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.337679504
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1948871457
Short name T3363
Test name
Test status
Simulation time 221774839 ps
CPU time 0.99 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207492 kb
Host smart-c9381413-5cae-4daa-8abe-c3627f0f8ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19488
71457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1948871457
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2647605315
Short name T2780
Test name
Test status
Simulation time 4210969618 ps
CPU time 43.63 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 217224 kb
Host smart-6ce79dc9-06c3-4a45-862d-5918e952f2e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2647605315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2647605315
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1864530365
Short name T1788
Test name
Test status
Simulation time 4810331286 ps
CPU time 29.53 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207812 kb
Host smart-2d8a4cc6-e6d4-46a4-9181-0807fac53448
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1864530365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1864530365
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2879664081
Short name T1484
Test name
Test status
Simulation time 185926816 ps
CPU time 0.91 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207504 kb
Host smart-540a64c3-ceba-4d55-a955-871ee7ffa735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
64081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2879664081
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2401687473
Short name T3020
Test name
Test status
Simulation time 31720298708 ps
CPU time 58.65 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207648 kb
Host smart-a768f889-ce5c-4787-9f6a-1211f020d23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24016
87473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2401687473
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3384092536
Short name T3546
Test name
Test status
Simulation time 4861205193 ps
CPU time 8.05 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 216016 kb
Host smart-3a7fd0d3-4047-42c7-8f27-c7f398cba041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33840
92536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3384092536
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3591832432
Short name T849
Test name
Test status
Simulation time 3354217706 ps
CPU time 95.79 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 218476 kb
Host smart-8d5b927e-19b3-4490-9c66-30c2c4fbd501
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3591832432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3591832432
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2567312063
Short name T2772
Test name
Test status
Simulation time 1985188739 ps
CPU time 19.57 seconds
Started Aug 09 05:31:22 PM PDT 24
Finished Aug 09 05:31:42 PM PDT 24
Peak memory 217248 kb
Host smart-98cb1ff1-6ad5-4338-9c06-a97c09e943b8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2567312063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2567312063
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3531275582
Short name T3174
Test name
Test status
Simulation time 245535255 ps
CPU time 1 seconds
Started Aug 09 05:31:24 PM PDT 24
Finished Aug 09 05:31:25 PM PDT 24
Peak memory 207460 kb
Host smart-8ead7a49-862e-4897-b8d9-9cb5eb8e125e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3531275582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3531275582
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.867401892
Short name T2097
Test name
Test status
Simulation time 185755350 ps
CPU time 0.91 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207504 kb
Host smart-cac778f3-aa8a-4aa5-bdd5-14a6bb786631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86740
1892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.867401892
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1266179942
Short name T2103
Test name
Test status
Simulation time 1676146304 ps
CPU time 16.52 seconds
Started Aug 09 05:31:21 PM PDT 24
Finished Aug 09 05:31:37 PM PDT 24
Peak memory 217452 kb
Host smart-63dc1860-d053-4ee1-9aa4-c4b9fe55853f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1266179942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1266179942
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.880483175
Short name T3128
Test name
Test status
Simulation time 174072832 ps
CPU time 0.94 seconds
Started Aug 09 05:31:22 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 207528 kb
Host smart-400ba3e0-744f-47ff-b408-f4f875683c90
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=880483175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.880483175
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1132197233
Short name T3563
Test name
Test status
Simulation time 164940358 ps
CPU time 0.89 seconds
Started Aug 09 05:31:10 PM PDT 24
Finished Aug 09 05:31:11 PM PDT 24
Peak memory 207532 kb
Host smart-72115a19-2fc8-4161-a38a-ce0ff4e506e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11321
97233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1132197233
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.4264158749
Short name T126
Test name
Test status
Simulation time 208019740 ps
CPU time 0.92 seconds
Started Aug 09 05:31:27 PM PDT 24
Finished Aug 09 05:31:28 PM PDT 24
Peak memory 207436 kb
Host smart-a3c91354-da52-45cc-b411-c277c9df4f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42641
58749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4264158749
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1280169141
Short name T2991
Test name
Test status
Simulation time 183320359 ps
CPU time 0.91 seconds
Started Aug 09 05:31:27 PM PDT 24
Finished Aug 09 05:31:28 PM PDT 24
Peak memory 207556 kb
Host smart-aa2d6ffd-88f1-44c2-96b7-ebb2ea59747b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
69141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1280169141
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1602220390
Short name T689
Test name
Test status
Simulation time 176665095 ps
CPU time 0.89 seconds
Started Aug 09 05:31:28 PM PDT 24
Finished Aug 09 05:31:29 PM PDT 24
Peak memory 207352 kb
Host smart-08a4e135-2a75-4747-a031-2ec1dff11227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
20390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1602220390
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.914549940
Short name T653
Test name
Test status
Simulation time 239135077 ps
CPU time 0.96 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207452 kb
Host smart-98dcf19d-0c0a-41ad-825c-3dd637f3bac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91454
9940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.914549940
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1411281054
Short name T2409
Test name
Test status
Simulation time 155623735 ps
CPU time 0.88 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207436 kb
Host smart-7fc2622f-2274-4e24-9ad6-76e733296dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14112
81054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1411281054
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.481277227
Short name T1538
Test name
Test status
Simulation time 187206788 ps
CPU time 0.93 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:19 PM PDT 24
Peak memory 207428 kb
Host smart-e3a149ce-cae6-45f2-a60d-7f2fb19a541b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=481277227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.481277227
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1958738820
Short name T202
Test name
Test status
Simulation time 175633538 ps
CPU time 0.85 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207436 kb
Host smart-63e15060-8b70-4d5c-8192-de53aaeb6711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
38820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1958738820
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.82947717
Short name T769
Test name
Test status
Simulation time 37453394 ps
CPU time 0.72 seconds
Started Aug 09 05:31:25 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 207756 kb
Host smart-ea30d5d3-c4be-40b2-b027-d4efe5cdf4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82947
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.82947717
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3417212890
Short name T292
Test name
Test status
Simulation time 23234772328 ps
CPU time 60.37 seconds
Started Aug 09 05:31:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 224112 kb
Host smart-a19f5aed-ad94-43b6-950f-07e055f2ced8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
12890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3417212890
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.4176419446
Short name T3074
Test name
Test status
Simulation time 146953877 ps
CPU time 0.82 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:31:38 PM PDT 24
Peak memory 207412 kb
Host smart-186811b5-a027-4911-80be-635a61baf9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
19446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.4176419446
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.127639738
Short name T2852
Test name
Test status
Simulation time 205221463 ps
CPU time 1 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207532 kb
Host smart-a891670f-e455-445d-a6c1-df0f04aa9c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12763
9738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.127639738
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2833923633
Short name T1286
Test name
Test status
Simulation time 239252163 ps
CPU time 0.95 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207492 kb
Host smart-8a3cb19f-21a8-4bd0-b77c-57990a00fddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28339
23633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2833923633
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.2690420117
Short name T2876
Test name
Test status
Simulation time 161297751 ps
CPU time 0.93 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207368 kb
Host smart-7ee9fb6e-48a7-419b-afe4-15125f3fc973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904
20117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.2690420117
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3659864938
Short name T2811
Test name
Test status
Simulation time 141058343 ps
CPU time 0.82 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207520 kb
Host smart-19e7f373-a6ea-4c38-8e1e-9c69274b1e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
64938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3659864938
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.4116794935
Short name T309
Test name
Test status
Simulation time 351741901 ps
CPU time 1.27 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207588 kb
Host smart-4e8770c9-f07b-4ccb-9b33-aa27f039a381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41167
94935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.4116794935
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3217549466
Short name T1685
Test name
Test status
Simulation time 152120285 ps
CPU time 0.85 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207512 kb
Host smart-bcb94821-5f60-4110-bc79-f8f954c5f4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32175
49466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3217549466
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4118171217
Short name T2853
Test name
Test status
Simulation time 155311667 ps
CPU time 0.84 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207452 kb
Host smart-1fa36640-b74a-440f-a7fe-ee1242bbd2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
71217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4118171217
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.948663171
Short name T3062
Test name
Test status
Simulation time 225949386 ps
CPU time 1 seconds
Started Aug 09 05:31:26 PM PDT 24
Finished Aug 09 05:31:27 PM PDT 24
Peak memory 207392 kb
Host smart-a8e9e37f-cc63-437b-b634-bb304e539fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94866
3171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.948663171
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1802478164
Short name T954
Test name
Test status
Simulation time 1859193611 ps
CPU time 15.08 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 224012 kb
Host smart-cef917ac-98ba-40de-a5fb-ce9b335b44f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1802478164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1802478164
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2087622669
Short name T3103
Test name
Test status
Simulation time 196988620 ps
CPU time 0.91 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207432 kb
Host smart-df33e365-7fd4-4e3e-98f2-98f3312215d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20876
22669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2087622669
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1075594495
Short name T757
Test name
Test status
Simulation time 166821950 ps
CPU time 0.87 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:16 PM PDT 24
Peak memory 207496 kb
Host smart-8873bca9-5bc5-4258-8a0e-aa5da71e5cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
94495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1075594495
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1868953699
Short name T3324
Test name
Test status
Simulation time 902504828 ps
CPU time 2.5 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207684 kb
Host smart-e21b8762-9e98-4279-94ca-c1ccc09bfdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
53699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1868953699
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2836246590
Short name T1210
Test name
Test status
Simulation time 2464118035 ps
CPU time 25.8 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:42 PM PDT 24
Peak memory 216952 kb
Host smart-0ae6a22a-b84c-425e-b8a2-0763b96fdc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28362
46590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2836246590
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.3934539818
Short name T2694
Test name
Test status
Simulation time 4246110470 ps
CPU time 28.12 seconds
Started Aug 09 05:31:08 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207792 kb
Host smart-89434e93-cf04-40d2-bfcd-2b4fd226f7b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934539818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.3934539818
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.2642166355
Short name T232
Test name
Test status
Simulation time 526033681 ps
CPU time 1.55 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207532 kb
Host smart-51eccfbd-8b5c-4c43-9aa9-c3ddeffffcea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642166355 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.2642166355
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.3952831437
Short name T779
Test name
Test status
Simulation time 522665214 ps
CPU time 1.54 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207472 kb
Host smart-76321acf-cda7-49b9-8044-d8661b7a6052
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952831437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.3952831437
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.50436887
Short name T896
Test name
Test status
Simulation time 563900104 ps
CPU time 1.74 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207416 kb
Host smart-c39bac5c-b4c0-49c6-9a0c-8268b586c26c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50436887 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.50436887
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.3186429651
Short name T171
Test name
Test status
Simulation time 514863810 ps
CPU time 1.53 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207516 kb
Host smart-5a923402-a7ed-4ca2-9255-e9b54768a7b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186429651 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.3186429651
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.3763112133
Short name T2617
Test name
Test status
Simulation time 633103243 ps
CPU time 1.69 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207496 kb
Host smart-c37058fc-ff40-45db-9949-5cdba1ec73b1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763112133 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.3763112133
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.2469304606
Short name T1466
Test name
Test status
Simulation time 439049057 ps
CPU time 1.33 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 207416 kb
Host smart-fe0ca330-492b-47a6-9ff1-d6e95bd10d35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469304606 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.2469304606
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.1853287987
Short name T2009
Test name
Test status
Simulation time 570597819 ps
CPU time 1.68 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207396 kb
Host smart-3ef12037-8e45-44c5-8880-61730e6a18f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853287987 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.1853287987
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.1966364183
Short name T814
Test name
Test status
Simulation time 564324683 ps
CPU time 1.7 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207468 kb
Host smart-2cbdc8c2-a87a-40d5-960d-0f7431c562a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966364183 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.1966364183
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.163062615
Short name T348
Test name
Test status
Simulation time 572377705 ps
CPU time 1.73 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207504 kb
Host smart-6ce1ce76-acff-444f-b63f-f00f811468cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163062615 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.163062615
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.3581282135
Short name T1514
Test name
Test status
Simulation time 517261426 ps
CPU time 1.62 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207516 kb
Host smart-15e2c8a9-1fc4-45f8-88a7-e729465511f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581282135 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.3581282135
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.2312970340
Short name T1186
Test name
Test status
Simulation time 506602703 ps
CPU time 1.62 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 207512 kb
Host smart-427972db-d0cc-445d-8377-7cfb4949bdab
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312970340 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.2312970340
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1681181521
Short name T2420
Test name
Test status
Simulation time 39980515 ps
CPU time 0.75 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 207808 kb
Host smart-ac4af9a0-ad95-4414-9258-4cac2c2fbb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1681181521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1681181521
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2601095112
Short name T1627
Test name
Test status
Simulation time 6514831711 ps
CPU time 10.35 seconds
Started Aug 09 05:31:28 PM PDT 24
Finished Aug 09 05:31:39 PM PDT 24
Peak memory 215892 kb
Host smart-41ef22c2-6b77-4232-b611-6b550c4b4db0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601095112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.2601095112
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3490490248
Short name T1808
Test name
Test status
Simulation time 18500886471 ps
CPU time 20.33 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207696 kb
Host smart-d7c69c8d-cbba-46fe-8ec4-cd6b1ceffe2d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490490248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3490490248
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2008714597
Short name T2371
Test name
Test status
Simulation time 26123564447 ps
CPU time 35.9 seconds
Started Aug 09 05:31:22 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 215880 kb
Host smart-61a8c0ce-9868-4bb8-b357-ed8163009ff7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008714597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.2008714597
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2863010506
Short name T1668
Test name
Test status
Simulation time 155732253 ps
CPU time 0.86 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207384 kb
Host smart-b073a024-539e-4575-895c-7f4887e51efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
10506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2863010506
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4253005336
Short name T2822
Test name
Test status
Simulation time 155266329 ps
CPU time 0.85 seconds
Started Aug 09 05:31:26 PM PDT 24
Finished Aug 09 05:31:27 PM PDT 24
Peak memory 207504 kb
Host smart-a75c9e69-3d1d-4dfe-99d5-473c2a127191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42530
05336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4253005336
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.4134843700
Short name T2793
Test name
Test status
Simulation time 445816214 ps
CPU time 1.62 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207484 kb
Host smart-8618dba9-a4a9-4b13-83dd-3118af752701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41348
43700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.4134843700
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3159452341
Short name T2466
Test name
Test status
Simulation time 949323456 ps
CPU time 2.4 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207696 kb
Host smart-5ebea832-5f35-4fed-b5fd-f824ddd06e64
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3159452341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3159452341
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3822768535
Short name T3394
Test name
Test status
Simulation time 50379406688 ps
CPU time 78.14 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 207792 kb
Host smart-3fc769e0-1c91-424e-a1ed-cb2684025594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
68535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3822768535
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.2158511067
Short name T670
Test name
Test status
Simulation time 2903861926 ps
CPU time 18.71 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207868 kb
Host smart-ecbd635d-d886-46f7-bf39-5122fdca8d2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158511067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.2158511067
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2904820350
Short name T3024
Test name
Test status
Simulation time 675410090 ps
CPU time 1.84 seconds
Started Aug 09 05:31:18 PM PDT 24
Finished Aug 09 05:31:20 PM PDT 24
Peak memory 207524 kb
Host smart-032bf9a1-e89f-40e4-ac3d-e75fafb59136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29048
20350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2904820350
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1421889364
Short name T1432
Test name
Test status
Simulation time 140628497 ps
CPU time 0.84 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 207360 kb
Host smart-8b38bfd6-4344-4d95-809c-ca5aa7fa177d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
89364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1421889364
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.4066504968
Short name T3601
Test name
Test status
Simulation time 67291204 ps
CPU time 0.78 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207472 kb
Host smart-aef89cf8-f097-45b0-abe9-90be1a561edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40665
04968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4066504968
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.446317947
Short name T2429
Test name
Test status
Simulation time 910187587 ps
CPU time 2.38 seconds
Started Aug 09 05:31:24 PM PDT 24
Finished Aug 09 05:31:27 PM PDT 24
Peak memory 207720 kb
Host smart-38c4c17d-3d94-4853-859d-5888108c13a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44631
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.446317947
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.1473694555
Short name T447
Test name
Test status
Simulation time 470829577 ps
CPU time 1.45 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207488 kb
Host smart-6193f57c-b8c8-4618-a3aa-e827783d1879
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1473694555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.1473694555
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1465267619
Short name T2307
Test name
Test status
Simulation time 177508071 ps
CPU time 1.87 seconds
Started Aug 09 05:31:12 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207696 kb
Host smart-467dd312-07ee-432c-9db1-049f5b0b0ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
67619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1465267619
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.994846829
Short name T829
Test name
Test status
Simulation time 170739082 ps
CPU time 0.91 seconds
Started Aug 09 05:31:11 PM PDT 24
Finished Aug 09 05:31:12 PM PDT 24
Peak memory 207444 kb
Host smart-47f63261-392c-4099-830e-0ab92c94391c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=994846829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.994846829
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2703794953
Short name T3002
Test name
Test status
Simulation time 197714518 ps
CPU time 0.88 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207372 kb
Host smart-cde11e8c-3bdd-4530-b3ab-8bd4f6924184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
94953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2703794953
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.167777336
Short name T713
Test name
Test status
Simulation time 220659783 ps
CPU time 1.04 seconds
Started Aug 09 05:31:21 PM PDT 24
Finished Aug 09 05:31:22 PM PDT 24
Peak memory 207476 kb
Host smart-3cfe638c-1c49-47a3-8b14-4d6feae9b431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
7336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.167777336
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.4101559753
Short name T2903
Test name
Test status
Simulation time 2886602074 ps
CPU time 23.25 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 218276 kb
Host smart-8622d721-debf-4672-a500-dc3625f761fd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4101559753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.4101559753
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2061352576
Short name T3218
Test name
Test status
Simulation time 9388268063 ps
CPU time 67.22 seconds
Started Aug 09 05:31:12 PM PDT 24
Finished Aug 09 05:32:20 PM PDT 24
Peak memory 207804 kb
Host smart-cc8f6b41-26c5-4e58-a00f-43c87b4c8e2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2061352576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2061352576
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1519828145
Short name T817
Test name
Test status
Simulation time 190898249 ps
CPU time 0.9 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207500 kb
Host smart-c65a67d3-1303-4981-9deb-b91e2d059f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
28145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1519828145
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.524644795
Short name T913
Test name
Test status
Simulation time 12531949048 ps
CPU time 16.3 seconds
Started Aug 09 05:31:26 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207760 kb
Host smart-a36c2805-15ef-46a9-848f-e96db5699ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52464
4795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.524644795
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3911470248
Short name T2285
Test name
Test status
Simulation time 9944652593 ps
CPU time 13.58 seconds
Started Aug 09 05:31:15 PM PDT 24
Finished Aug 09 05:31:28 PM PDT 24
Peak memory 207792 kb
Host smart-fb792930-9391-4481-b3d8-5e59ab04c5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
70248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3911470248
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.4031750624
Short name T3032
Test name
Test status
Simulation time 4251779641 ps
CPU time 31.78 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 219728 kb
Host smart-abf33901-ee76-4dbe-a498-15bd5bde6952
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4031750624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.4031750624
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2061974032
Short name T547
Test name
Test status
Simulation time 1535800013 ps
CPU time 42.42 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 224044 kb
Host smart-26e589cc-3910-4147-9632-e0184bc7448d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2061974032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2061974032
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3590625974
Short name T149
Test name
Test status
Simulation time 231340047 ps
CPU time 1.02 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207516 kb
Host smart-570508e6-9b54-4be5-87c0-0c4ccb04aeb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3590625974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3590625974
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4164305873
Short name T708
Test name
Test status
Simulation time 212818455 ps
CPU time 0.99 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:34 PM PDT 24
Peak memory 207480 kb
Host smart-260df103-246f-49ea-a7bb-a49b92815b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
05873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4164305873
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1080355374
Short name T3205
Test name
Test status
Simulation time 4056226903 ps
CPU time 118.09 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 217384 kb
Host smart-73fd180e-05b0-422c-8772-78be11ad6dd0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1080355374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1080355374
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.991039131
Short name T2359
Test name
Test status
Simulation time 195155949 ps
CPU time 0.88 seconds
Started Aug 09 05:31:39 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207444 kb
Host smart-1b8c8be7-e2e0-4cbd-900d-a380bd853466
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=991039131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.991039131
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.4178442800
Short name T3079
Test name
Test status
Simulation time 146134215 ps
CPU time 0.87 seconds
Started Aug 09 05:31:28 PM PDT 24
Finished Aug 09 05:31:29 PM PDT 24
Peak memory 207400 kb
Host smart-a2aa24e6-7f9c-423f-8d9d-22d655a7eabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41784
42800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.4178442800
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1136763561
Short name T2847
Test name
Test status
Simulation time 235240982 ps
CPU time 0.97 seconds
Started Aug 09 05:31:14 PM PDT 24
Finished Aug 09 05:31:15 PM PDT 24
Peak memory 207436 kb
Host smart-3f076438-2e59-4945-bdea-e6561b5fcea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367
63561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1136763561
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.597204283
Short name T1899
Test name
Test status
Simulation time 178356678 ps
CPU time 0.92 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207552 kb
Host smart-1129ea34-51e5-4075-959b-25fdc09fc430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59720
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.597204283
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2040879642
Short name T2775
Test name
Test status
Simulation time 185514290 ps
CPU time 0.88 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:29 PM PDT 24
Peak memory 207420 kb
Host smart-672a9ef4-1e54-4385-8f54-c7a45443f221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20408
79642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2040879642
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1930856247
Short name T1648
Test name
Test status
Simulation time 166530733 ps
CPU time 0.87 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207492 kb
Host smart-b9607c62-033a-4df7-b500-6b64af0cc539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
56247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1930856247
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2876658196
Short name T2175
Test name
Test status
Simulation time 195734409 ps
CPU time 0.93 seconds
Started Aug 09 05:31:18 PM PDT 24
Finished Aug 09 05:31:19 PM PDT 24
Peak memory 207556 kb
Host smart-e4d446c5-f26d-4781-b5bf-9676c484ce58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766
58196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2876658196
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.71438118
Short name T1062
Test name
Test status
Simulation time 287128975 ps
CPU time 1.16 seconds
Started Aug 09 05:31:38 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207380 kb
Host smart-b6f1fd75-93dd-4629-99a2-0badd8b87039
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=71438118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.71438118
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3107620184
Short name T2951
Test name
Test status
Simulation time 164007909 ps
CPU time 0.85 seconds
Started Aug 09 05:31:16 PM PDT 24
Finished Aug 09 05:31:17 PM PDT 24
Peak memory 207524 kb
Host smart-479ef825-5d4d-4296-8821-cfe618229b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
20184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3107620184
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3222329253
Short name T1891
Test name
Test status
Simulation time 39830743 ps
CPU time 0.72 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207420 kb
Host smart-0afb495c-4488-435e-bb5c-ac78489a16a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223
29253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3222329253
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.298379018
Short name T2045
Test name
Test status
Simulation time 23712559186 ps
CPU time 59.04 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 216012 kb
Host smart-706a210a-2918-43e7-8822-79e0a4b0f1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
9018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.298379018
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.786915300
Short name T602
Test name
Test status
Simulation time 202874180 ps
CPU time 0.97 seconds
Started Aug 09 05:31:26 PM PDT 24
Finished Aug 09 05:31:27 PM PDT 24
Peak memory 207500 kb
Host smart-1b4f3457-4e3b-4777-aa4c-a5d8cc6ff81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78691
5300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.786915300
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3473020726
Short name T1655
Test name
Test status
Simulation time 261773052 ps
CPU time 1.01 seconds
Started Aug 09 05:31:20 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 207500 kb
Host smart-31d86a7f-8fb9-418c-8ea1-051a6ab9637d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34730
20726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3473020726
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1209698617
Short name T1038
Test name
Test status
Simulation time 263987015 ps
CPU time 0.96 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207472 kb
Host smart-4ba8ffcd-9bb7-4e6f-8025-0df7ed8fe11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12096
98617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1209698617
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2528986034
Short name T1154
Test name
Test status
Simulation time 242539949 ps
CPU time 0.94 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207488 kb
Host smart-44adfbcd-13f8-4277-a0ef-c9db3ebcef8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
86034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2528986034
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3164009896
Short name T2583
Test name
Test status
Simulation time 183391971 ps
CPU time 0.87 seconds
Started Aug 09 05:31:13 PM PDT 24
Finished Aug 09 05:31:14 PM PDT 24
Peak memory 207552 kb
Host smart-20622d83-952d-4ee5-bf1a-8ea6b61a76dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31640
09896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3164009896
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.1612889620
Short name T2938
Test name
Test status
Simulation time 439322698 ps
CPU time 1.36 seconds
Started Aug 09 05:31:22 PM PDT 24
Finished Aug 09 05:31:23 PM PDT 24
Peak memory 207512 kb
Host smart-64654ea0-80d8-4d17-8464-6cc338dabdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128
89620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.1612889620
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.242168146
Short name T3561
Test name
Test status
Simulation time 158877066 ps
CPU time 0.85 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:31:38 PM PDT 24
Peak memory 207452 kb
Host smart-3ff39b51-44e0-41a9-abfd-8ca3dc23c3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.242168146
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2118496281
Short name T1448
Test name
Test status
Simulation time 218758960 ps
CPU time 0.93 seconds
Started Aug 09 05:31:17 PM PDT 24
Finished Aug 09 05:31:18 PM PDT 24
Peak memory 207348 kb
Host smart-7d626e38-d165-4003-aa62-af020e84b13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21184
96281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2118496281
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1996549480
Short name T1653
Test name
Test status
Simulation time 196514333 ps
CPU time 1.03 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207452 kb
Host smart-96f41f14-a5dc-45eb-8cd0-3623336b1910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19965
49480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1996549480
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1412470961
Short name T1217
Test name
Test status
Simulation time 2296514468 ps
CPU time 22.08 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:53 PM PDT 24
Peak memory 217528 kb
Host smart-d26be1a4-c30c-40fe-b978-92640b593a31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1412470961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1412470961
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.953624560
Short name T2044
Test name
Test status
Simulation time 182563596 ps
CPU time 0.99 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 207436 kb
Host smart-1cc11b2b-f891-41c5-aac7-11abe2bce4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95362
4560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.953624560
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.786363689
Short name T1683
Test name
Test status
Simulation time 206643171 ps
CPU time 0.91 seconds
Started Aug 09 05:31:43 PM PDT 24
Finished Aug 09 05:31:44 PM PDT 24
Peak memory 207552 kb
Host smart-4ffda911-75b3-4922-8fa5-1e23052c5159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78636
3689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.786363689
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.4042282454
Short name T2062
Test name
Test status
Simulation time 575233078 ps
CPU time 1.83 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207396 kb
Host smart-87eae917-b209-453f-bd50-63787feec5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40422
82454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.4042282454
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1460502207
Short name T1527
Test name
Test status
Simulation time 3756945050 ps
CPU time 30.16 seconds
Started Aug 09 05:31:38 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 217732 kb
Host smart-c4c133d3-a3e0-44d2-85bb-262ce6572441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14605
02207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1460502207
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.285483089
Short name T545
Test name
Test status
Simulation time 3345983702 ps
CPU time 29.36 seconds
Started Aug 09 05:31:23 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207652 kb
Host smart-4c10d097-25fc-4878-9c0d-f11eea5f1ae6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285483089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host
_handshake.285483089
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.2669122545
Short name T2857
Test name
Test status
Simulation time 627338363 ps
CPU time 1.54 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:32 PM PDT 24
Peak memory 207496 kb
Host smart-3285c263-a3e5-4707-92da-324f71d7250e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669122545 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2669122545
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.2315338769
Short name T890
Test name
Test status
Simulation time 571727070 ps
CPU time 1.55 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207464 kb
Host smart-17005a67-c33c-4974-ab65-0b3603180808
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315338769 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.2315338769
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.2782550034
Short name T3437
Test name
Test status
Simulation time 418101697 ps
CPU time 1.52 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207392 kb
Host smart-3092b098-8d41-4a12-9541-e3710d76d09c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782550034 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.2782550034
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.2541707125
Short name T632
Test name
Test status
Simulation time 420594682 ps
CPU time 1.39 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207532 kb
Host smart-74f1847d-da46-4125-9793-a843f274c153
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541707125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.2541707125
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.78793243
Short name T2101
Test name
Test status
Simulation time 529917839 ps
CPU time 1.66 seconds
Started Aug 09 05:33:35 PM PDT 24
Finished Aug 09 05:33:37 PM PDT 24
Peak memory 207524 kb
Host smart-86dc3b16-4a1c-4e07-bcaa-b26150c40ddd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78793243 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.78793243
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.1690024658
Short name T1818
Test name
Test status
Simulation time 596865603 ps
CPU time 1.69 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207568 kb
Host smart-f134f6f0-9af4-4193-b7ad-ec4556a4b632
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690024658 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.1690024658
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.1889547654
Short name T2767
Test name
Test status
Simulation time 644103538 ps
CPU time 1.72 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 207496 kb
Host smart-e77760bd-5266-4b2c-93ba-902494ac0f44
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889547654 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.1889547654
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.386984250
Short name T568
Test name
Test status
Simulation time 514303713 ps
CPU time 1.72 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207808 kb
Host smart-2a5cc835-2245-455f-8d2a-a50fd7978e42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386984250 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.386984250
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.4267852875
Short name T176
Test name
Test status
Simulation time 455137375 ps
CPU time 1.52 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207568 kb
Host smart-b3f87116-b1eb-41bd-9f88-21b33c2d5e94
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267852875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.4267852875
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.3742400269
Short name T3033
Test name
Test status
Simulation time 539480479 ps
CPU time 1.49 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207480 kb
Host smart-d5e730b9-7eaa-4fa5-9fe9-4771b8642ce3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742400269 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.3742400269
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.3024042577
Short name T3428
Test name
Test status
Simulation time 437874342 ps
CPU time 1.38 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207404 kb
Host smart-2f5bc525-6c4d-457f-ae33-59279ed6ec65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024042577 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.3024042577
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.878833138
Short name T824
Test name
Test status
Simulation time 43599004 ps
CPU time 0.68 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:27 PM PDT 24
Peak memory 207560 kb
Host smart-2afac227-8a7c-46b9-bb55-bb23166a06e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=878833138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.878833138
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2704305430
Short name T15
Test name
Test status
Simulation time 9785663386 ps
CPU time 13.05 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 208048 kb
Host smart-8adb79f8-58c7-4c66-bae9-a9d4bd4abdce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704305430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.2704305430
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.221980914
Short name T1563
Test name
Test status
Simulation time 16078434942 ps
CPU time 18.48 seconds
Started Aug 09 05:26:29 PM PDT 24
Finished Aug 09 05:26:47 PM PDT 24
Peak memory 216012 kb
Host smart-032d9f28-5270-4f27-aa92-075fd8359ebc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=221980914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.221980914
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.201844247
Short name T3081
Test name
Test status
Simulation time 23804746321 ps
CPU time 29.04 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 215944 kb
Host smart-99ddd011-fdda-4df5-8947-ce434aacf952
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201844247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon
_wake_resume.201844247
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2395522110
Short name T3315
Test name
Test status
Simulation time 201050534 ps
CPU time 0.94 seconds
Started Aug 09 05:26:14 PM PDT 24
Finished Aug 09 05:26:15 PM PDT 24
Peak memory 207504 kb
Host smart-a9b8aa53-3208-4bc2-b900-adf911f316cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
22110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2395522110
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1123034236
Short name T54
Test name
Test status
Simulation time 152537556 ps
CPU time 0.83 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207400 kb
Host smart-3709afdb-76ec-4d8a-8cde-41b1e807a84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230
34236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1123034236
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2581194351
Short name T3335
Test name
Test status
Simulation time 143127366 ps
CPU time 0.84 seconds
Started Aug 09 05:26:15 PM PDT 24
Finished Aug 09 05:26:16 PM PDT 24
Peak memory 207476 kb
Host smart-8493b011-08d0-49d9-8133-781b079618b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
94351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2581194351
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3441128317
Short name T989
Test name
Test status
Simulation time 319563335 ps
CPU time 1.2 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:26:12 PM PDT 24
Peak memory 207424 kb
Host smart-b76eef11-f593-47f2-bdbd-1eace029a680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34411
28317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3441128317
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.584220622
Short name T322
Test name
Test status
Simulation time 994008929 ps
CPU time 2.57 seconds
Started Aug 09 05:26:16 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207680 kb
Host smart-7a0b8869-40ad-4142-925a-5fc1e47aa79c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=584220622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.584220622
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2024412881
Short name T347
Test name
Test status
Simulation time 47683027770 ps
CPU time 92.89 seconds
Started Aug 09 05:26:16 PM PDT 24
Finished Aug 09 05:27:49 PM PDT 24
Peak memory 207808 kb
Host smart-7df515c2-ecd2-4394-b3a3-4ae455ef33a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
12881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2024412881
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.455225801
Short name T1629
Test name
Test status
Simulation time 7037466662 ps
CPU time 46.98 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 207756 kb
Host smart-ed6acdf6-b9a3-4405-b222-40ce7dbc307e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455225801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.455225801
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3488052117
Short name T2041
Test name
Test status
Simulation time 1054269798 ps
CPU time 2.12 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 207376 kb
Host smart-5c3427d8-9791-493f-a452-b2262f6b3adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
52117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3488052117
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.585798837
Short name T2508
Test name
Test status
Simulation time 138146019 ps
CPU time 0.8 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 206452 kb
Host smart-9880f019-1316-49f9-af48-ef4bd3ee0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58579
8837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.585798837
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3194473538
Short name T2826
Test name
Test status
Simulation time 95949610 ps
CPU time 0.81 seconds
Started Aug 09 05:26:13 PM PDT 24
Finished Aug 09 05:26:14 PM PDT 24
Peak memory 207516 kb
Host smart-6037482f-dec8-44d7-bd2c-67075426a58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31944
73538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3194473538
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2174103824
Short name T726
Test name
Test status
Simulation time 1005541159 ps
CPU time 2.54 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:26:24 PM PDT 24
Peak memory 207616 kb
Host smart-e9bc04d5-70c1-48b4-b867-2c9adefb26ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741
03824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2174103824
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.3409086396
Short name T3456
Test name
Test status
Simulation time 481992667 ps
CPU time 1.31 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:26:13 PM PDT 24
Peak memory 207516 kb
Host smart-b04b3ba3-eb90-4808-bf54-7cf11154a99e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3409086396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.3409086396
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2956635695
Short name T2445
Test name
Test status
Simulation time 269304017 ps
CPU time 1.95 seconds
Started Aug 09 05:26:15 PM PDT 24
Finished Aug 09 05:26:17 PM PDT 24
Peak memory 207648 kb
Host smart-77d8dd4f-c055-4e60-9d4f-138700702024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29566
35695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2956635695
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.4086786619
Short name T3493
Test name
Test status
Simulation time 112352002077 ps
CPU time 185.36 seconds
Started Aug 09 05:26:16 PM PDT 24
Finished Aug 09 05:29:22 PM PDT 24
Peak memory 207772 kb
Host smart-c734601a-e67a-4c28-8c70-6e703d24e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086786619 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.4086786619
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1778446697
Short name T2741
Test name
Test status
Simulation time 100131363673 ps
CPU time 144.29 seconds
Started Aug 09 05:26:12 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207728 kb
Host smart-9eb25358-a8fc-4fe4-a15c-153b95792f48
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1778446697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1778446697
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1889255770
Short name T2632
Test name
Test status
Simulation time 118894747732 ps
CPU time 177.49 seconds
Started Aug 09 05:26:15 PM PDT 24
Finished Aug 09 05:29:13 PM PDT 24
Peak memory 207768 kb
Host smart-95ebfefa-10ba-4ec4-a8df-2d1e93decb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889255770 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1889255770
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.1597537598
Short name T2806
Test name
Test status
Simulation time 96178154075 ps
CPU time 145.52 seconds
Started Aug 09 05:26:11 PM PDT 24
Finished Aug 09 05:28:37 PM PDT 24
Peak memory 207816 kb
Host smart-e04596f7-7069-4ba8-9d70-1989c8f1f8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15975
37598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.1597537598
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3848161811
Short name T2924
Test name
Test status
Simulation time 172869575 ps
CPU time 0.92 seconds
Started Aug 09 05:26:16 PM PDT 24
Finished Aug 09 05:26:17 PM PDT 24
Peak memory 215724 kb
Host smart-24c15007-2b02-4c33-ab42-88e0a773553e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3848161811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3848161811
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2588892368
Short name T3451
Test name
Test status
Simulation time 142854268 ps
CPU time 0.85 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:20 PM PDT 24
Peak memory 207460 kb
Host smart-2ee2a64a-0892-4e86-ad6a-27b285886937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888
92368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2588892368
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.915582651
Short name T2695
Test name
Test status
Simulation time 279191526 ps
CPU time 1.09 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207400 kb
Host smart-ab48e178-8547-4ecf-8b2e-e96d0d17721b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91558
2651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.915582651
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.4159015604
Short name T654
Test name
Test status
Simulation time 4013735814 ps
CPU time 30.51 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 218104 kb
Host smart-9526d964-cd63-4abe-8876-86b0e95a2fbc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4159015604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.4159015604
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.728650445
Short name T268
Test name
Test status
Simulation time 4133929338 ps
CPU time 50.99 seconds
Started Aug 09 05:26:17 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207688 kb
Host smart-6d37bee2-1f98-4db4-980f-cf2a78a4dc64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=728650445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.728650445
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.835379498
Short name T1269
Test name
Test status
Simulation time 234666412 ps
CPU time 1.06 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207412 kb
Host smart-73e74b73-1ee0-465f-bb43-f1a71fd94d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83537
9498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.835379498
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1774405126
Short name T96
Test name
Test status
Simulation time 32896426154 ps
CPU time 51.08 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207656 kb
Host smart-8b82a0b0-2f2b-48f8-8b1a-8c3b43dac6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17744
05126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1774405126
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.250427256
Short name T1605
Test name
Test status
Simulation time 6337561209 ps
CPU time 9.72 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:30 PM PDT 24
Peak memory 216024 kb
Host smart-25e31c5b-d9e6-4b43-af38-56ca9a822f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25042
7256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.250427256
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2549882698
Short name T687
Test name
Test status
Simulation time 3938638966 ps
CPU time 109.31 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:28:08 PM PDT 24
Peak memory 224144 kb
Host smart-2b7b209c-98d2-4dfa-8fef-514caac6654a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2549882698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2549882698
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1948930611
Short name T2242
Test name
Test status
Simulation time 3343426430 ps
CPU time 98.46 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 217692 kb
Host smart-92ef57cb-6ad2-4f26-8974-54781135c7d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1948930611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1948930611
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3457456953
Short name T835
Test name
Test status
Simulation time 246545104 ps
CPU time 1 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207464 kb
Host smart-c216a519-da42-4d00-815f-3e0589eeb9f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3457456953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3457456953
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4063603473
Short name T1535
Test name
Test status
Simulation time 203245374 ps
CPU time 0.98 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207512 kb
Host smart-29fbcecd-2279-4428-ab08-6dd2d74c34b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40636
03473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4063603473
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.3559088130
Short name T3241
Test name
Test status
Simulation time 3684167152 ps
CPU time 29.48 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 224216 kb
Host smart-67748ad3-fe65-48f5-9bae-16293bd7f739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35590
88130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.3559088130
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.842349120
Short name T1636
Test name
Test status
Simulation time 2191656981 ps
CPU time 64.46 seconds
Started Aug 09 05:26:24 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 224196 kb
Host smart-605c7df1-dc8e-4941-9fb2-92ef7fc13662
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=842349120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.842349120
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.513506002
Short name T1270
Test name
Test status
Simulation time 2488597780 ps
CPU time 18.57 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:37 PM PDT 24
Peak memory 215932 kb
Host smart-525c3316-4b9b-4e6c-af59-2665696c71db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=513506002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.513506002
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3142082261
Short name T3395
Test name
Test status
Simulation time 147816104 ps
CPU time 0.88 seconds
Started Aug 09 05:26:25 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 207428 kb
Host smart-db95ecfc-a8f0-4093-b8c1-6764d7e08c91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3142082261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3142082261
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2211685134
Short name T3408
Test name
Test status
Simulation time 145170414 ps
CPU time 0.86 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 207476 kb
Host smart-e88767ff-33cf-414e-98f6-b6d964b5b815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22116
85134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2211685134
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3300962833
Short name T130
Test name
Test status
Simulation time 243285940 ps
CPU time 1.02 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:20 PM PDT 24
Peak memory 207592 kb
Host smart-3a404875-5ca5-4ea4-a354-9ef4bb43417b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
62833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3300962833
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3575644963
Short name T537
Test name
Test status
Simulation time 184823499 ps
CPU time 0.97 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207476 kb
Host smart-5c7991b9-c4be-44d3-926f-f147d8407858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
44963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3575644963
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.136449276
Short name T2581
Test name
Test status
Simulation time 175223590 ps
CPU time 0.91 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207476 kb
Host smart-976453a6-4d95-46c1-8b6c-bff73d6354b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
9276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.136449276
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3829766734
Short name T1293
Test name
Test status
Simulation time 161669868 ps
CPU time 0.95 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:20 PM PDT 24
Peak memory 207456 kb
Host smart-bbb6cc67-a4de-45fd-bac4-7b73dbcb85cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38297
66734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3829766734
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.596592625
Short name T1469
Test name
Test status
Simulation time 147898887 ps
CPU time 0.9 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207500 kb
Host smart-ac0c86f0-8cfa-460f-a1e7-3811633d0c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59659
2625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.596592625
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1106507092
Short name T2507
Test name
Test status
Simulation time 236896771 ps
CPU time 1.08 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:24 PM PDT 24
Peak memory 207428 kb
Host smart-d5aff6cd-3be9-4f6b-a418-8c26caf6eeda
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1106507092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1106507092
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2163992065
Short name T1205
Test name
Test status
Simulation time 212933479 ps
CPU time 1 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:26:23 PM PDT 24
Peak memory 207504 kb
Host smart-ce52e4c6-9b47-4055-8238-501d5b2221e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21639
92065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2163992065
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2415874776
Short name T843
Test name
Test status
Simulation time 167396582 ps
CPU time 0.83 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:20 PM PDT 24
Peak memory 207288 kb
Host smart-251b55fe-af88-4436-a34e-540ffefd7d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
74776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2415874776
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3587086425
Short name T1617
Test name
Test status
Simulation time 36330639 ps
CPU time 0.68 seconds
Started Aug 09 05:26:24 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207452 kb
Host smart-e8ce71d6-4466-49d9-a402-864ac1a35778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35870
86425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3587086425
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.275900019
Short name T3288
Test name
Test status
Simulation time 18895278843 ps
CPU time 51.38 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 220372 kb
Host smart-850ef1ee-fabf-45ed-8b96-44e8240aec62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27590
0019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.275900019
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.600200781
Short name T2227
Test name
Test status
Simulation time 183510087 ps
CPU time 0.95 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207432 kb
Host smart-85451ef6-a68d-4772-b628-df7b16bdbca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60020
0781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.600200781
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.934641875
Short name T2050
Test name
Test status
Simulation time 221021501 ps
CPU time 1.03 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207372 kb
Host smart-6fca70ad-27ae-43a7-aed4-6d0a99df808f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93464
1875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.934641875
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2628204555
Short name T2611
Test name
Test status
Simulation time 9457523931 ps
CPU time 161.43 seconds
Started Aug 09 05:26:22 PM PDT 24
Finished Aug 09 05:29:04 PM PDT 24
Peak memory 216096 kb
Host smart-79049c74-43d5-4287-a5f1-21732da3c819
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628204555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2628204555
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2693856077
Short name T2470
Test name
Test status
Simulation time 6446726963 ps
CPU time 26.09 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:26:47 PM PDT 24
Peak memory 224100 kb
Host smart-fd04c0fa-5286-42ef-8cdb-ee6883a5a85c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693856077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2693856077
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3640693741
Short name T2643
Test name
Test status
Simulation time 9249601473 ps
CPU time 170.59 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:29:11 PM PDT 24
Peak memory 218348 kb
Host smart-8b5efce2-9233-43d9-8ff4-e2a5f4925384
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640693741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3640693741
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1041175712
Short name T2163
Test name
Test status
Simulation time 221116771 ps
CPU time 1.04 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:21 PM PDT 24
Peak memory 207788 kb
Host smart-e7863202-cd74-47ac-8044-d2d9f914fe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10411
75712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1041175712
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.492786304
Short name T3257
Test name
Test status
Simulation time 192442756 ps
CPU time 0.98 seconds
Started Aug 09 05:26:24 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207496 kb
Host smart-bc49aaab-48ee-4910-b56a-556ba8862db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49278
6304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.492786304
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.1374156250
Short name T1688
Test name
Test status
Simulation time 20164257408 ps
CPU time 24.51 seconds
Started Aug 09 05:26:20 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 207580 kb
Host smart-aa06ed5e-2b4b-425d-9b3b-e452b15ad81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13741
56250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.1374156250
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1863449634
Short name T3189
Test name
Test status
Simulation time 156210997 ps
CPU time 0.9 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207352 kb
Host smart-9a682f93-bdce-408e-8ef1-9447a2b2293d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
49634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1863449634
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.1571875108
Short name T3398
Test name
Test status
Simulation time 273694953 ps
CPU time 1.15 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:26:22 PM PDT 24
Peak memory 207508 kb
Host smart-2e057818-fd92-4686-a3b5-b419b35f0233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
75108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.1571875108
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4227186652
Short name T3264
Test name
Test status
Simulation time 178611588 ps
CPU time 0.88 seconds
Started Aug 09 05:26:24 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207480 kb
Host smart-eb08975b-9427-4eb4-8367-f49578cef45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
86652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4227186652
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.190800460
Short name T213
Test name
Test status
Simulation time 437712694 ps
CPU time 1.22 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:27 PM PDT 24
Peak memory 223516 kb
Host smart-7f9ac953-eda5-4c36-8938-a6d31f8409ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=190800460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.190800460
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3689168275
Short name T50
Test name
Test status
Simulation time 478881900 ps
CPU time 1.54 seconds
Started Aug 09 05:26:23 PM PDT 24
Finished Aug 09 05:26:25 PM PDT 24
Peak memory 207388 kb
Host smart-7efd00b0-4f18-4c76-803a-02c51ac3428e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36891
68275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3689168275
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1248158251
Short name T1358
Test name
Test status
Simulation time 206835846 ps
CPU time 1.04 seconds
Started Aug 09 05:26:18 PM PDT 24
Finished Aug 09 05:26:19 PM PDT 24
Peak memory 207432 kb
Host smart-09982a37-c085-4245-ad57-0157ccb71c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
58251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1248158251
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2875181880
Short name T3387
Test name
Test status
Simulation time 168089742 ps
CPU time 0.9 seconds
Started Aug 09 05:26:19 PM PDT 24
Finished Aug 09 05:26:20 PM PDT 24
Peak memory 207432 kb
Host smart-3f7da596-d23b-4069-8116-87f918062235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
81880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2875181880
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1441907180
Short name T1967
Test name
Test status
Simulation time 150728844 ps
CPU time 0.87 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207396 kb
Host smart-d575ec7a-7199-46dc-a9a2-54d4e0dc6c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419
07180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1441907180
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2281166292
Short name T2295
Test name
Test status
Simulation time 200237069 ps
CPU time 0.97 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207500 kb
Host smart-235f015d-3182-46a2-aad7-8233479caa73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
66292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2281166292
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1905667690
Short name T3500
Test name
Test status
Simulation time 3043241532 ps
CPU time 89.75 seconds
Started Aug 09 05:26:29 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 217744 kb
Host smart-d3eb7fbb-33c3-46b1-bafa-a5ef36ba3717
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1905667690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1905667690
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2714418865
Short name T575
Test name
Test status
Simulation time 172715971 ps
CPU time 0.86 seconds
Started Aug 09 05:26:25 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 207476 kb
Host smart-e0c3d98e-011c-4e7b-9114-62755b5b22da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27144
18865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2714418865
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.292978086
Short name T771
Test name
Test status
Simulation time 245040371 ps
CPU time 0.94 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207504 kb
Host smart-e0227423-d91b-46ec-b2d9-e293725df52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
8086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.292978086
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1380540092
Short name T767
Test name
Test status
Simulation time 1074358350 ps
CPU time 2.75 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207636 kb
Host smart-72139b3e-c980-42a4-8e57-239de6ee25c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
40092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1380540092
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1551769107
Short name T3132
Test name
Test status
Simulation time 3286244529 ps
CPU time 33.61 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 216108 kb
Host smart-5557a9a8-c4a1-4d05-a357-7c84f5ba7ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
69107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1551769107
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3954885350
Short name T3343
Test name
Test status
Simulation time 4366844777 ps
CPU time 36.26 seconds
Started Aug 09 05:26:21 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207696 kb
Host smart-ed43a45f-2ca2-41b5-a42c-d6862ef9df3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954885350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3954885350
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.1580454106
Short name T2190
Test name
Test status
Simulation time 512832536 ps
CPU time 1.7 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207500 kb
Host smart-47714070-e607-41dd-b243-ef4d4b9c2451
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580454106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.1580454106
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3306994686
Short name T3400
Test name
Test status
Simulation time 73329655 ps
CPU time 0.69 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 207492 kb
Host smart-eebac5e1-f79f-401b-8266-a31d7bdcd8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3306994686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3306994686
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2585812412
Short name T2688
Test name
Test status
Simulation time 6174210200 ps
CPU time 8.21 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 216248 kb
Host smart-2369cf89-c9e1-4f96-a401-70b5b3bbc99a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585812412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.2585812412
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.637525634
Short name T2712
Test name
Test status
Simulation time 19594892765 ps
CPU time 23.71 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 207748 kb
Host smart-5f8d85ba-5bd3-45e3-abf1-2770001bffd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=637525634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.637525634
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1742741077
Short name T2710
Test name
Test status
Simulation time 25536254566 ps
CPU time 32.08 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:32:12 PM PDT 24
Peak memory 215920 kb
Host smart-068efcd2-da8c-41b9-8601-494f08ca497c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742741077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.1742741077
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2593179386
Short name T2875
Test name
Test status
Simulation time 167809004 ps
CPU time 0.89 seconds
Started Aug 09 05:31:27 PM PDT 24
Finished Aug 09 05:31:28 PM PDT 24
Peak memory 207556 kb
Host smart-d25e2054-722c-4101-9093-9879d7859c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931
79386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2593179386
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.424629850
Short name T1355
Test name
Test status
Simulation time 154123778 ps
CPU time 0.85 seconds
Started Aug 09 05:31:20 PM PDT 24
Finished Aug 09 05:31:21 PM PDT 24
Peak memory 207512 kb
Host smart-f8ba47ee-3c9b-47a7-ac9d-ebfec318125f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
9850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.424629850
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1174965855
Short name T2791
Test name
Test status
Simulation time 324414549 ps
CPU time 1.24 seconds
Started Aug 09 05:31:45 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207412 kb
Host smart-c119cefb-3b74-4a75-8bfb-94c0a96c78ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749
65855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1174965855
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.850786055
Short name T1902
Test name
Test status
Simulation time 384168748 ps
CPU time 1.38 seconds
Started Aug 09 05:31:24 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 207500 kb
Host smart-2a808c70-d9a5-4d3c-87c3-758d054c6e62
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=850786055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.850786055
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2357769408
Short name T3038
Test name
Test status
Simulation time 31354963634 ps
CPU time 49.7 seconds
Started Aug 09 05:31:18 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207892 kb
Host smart-35587724-2d1a-4385-92f9-d4f852e31ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23577
69408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2357769408
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.510698166
Short name T1197
Test name
Test status
Simulation time 161023931 ps
CPU time 0.87 seconds
Started Aug 09 05:31:43 PM PDT 24
Finished Aug 09 05:31:44 PM PDT 24
Peak memory 207380 kb
Host smart-b666a392-2105-4ef3-ad0b-23af581c1c19
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510698166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.510698166
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.180785288
Short name T1398
Test name
Test status
Simulation time 779764204 ps
CPU time 1.94 seconds
Started Aug 09 05:31:23 PM PDT 24
Finished Aug 09 05:31:25 PM PDT 24
Peak memory 207472 kb
Host smart-8102a18b-b7b7-4d2f-8e8e-bcb892e2f1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
5288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.180785288
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2620658750
Short name T1357
Test name
Test status
Simulation time 149348299 ps
CPU time 0.82 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207328 kb
Host smart-b5667490-d15f-4e42-aa96-184eac4b8942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26206
58750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2620658750
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2736615742
Short name T2167
Test name
Test status
Simulation time 46818978 ps
CPU time 0.71 seconds
Started Aug 09 05:31:19 PM PDT 24
Finished Aug 09 05:31:19 PM PDT 24
Peak memory 207392 kb
Host smart-dab26f57-13a3-4f53-8746-96acd16fc4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
15742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2736615742
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2557345171
Short name T2755
Test name
Test status
Simulation time 856702721 ps
CPU time 2.16 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207600 kb
Host smart-e1384f28-f821-4640-a3be-42cf201fbf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25573
45171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2557345171
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.2027535607
Short name T412
Test name
Test status
Simulation time 519710181 ps
CPU time 1.42 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207468 kb
Host smart-fe0276d5-f7f0-4195-b24f-122d30bd30bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2027535607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.2027535607
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3989163058
Short name T3464
Test name
Test status
Simulation time 294665628 ps
CPU time 2.11 seconds
Started Aug 09 05:31:43 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207636 kb
Host smart-3eb86ca8-d430-4537-8938-b9baca7cf4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891
63058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3989163058
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1136825494
Short name T2821
Test name
Test status
Simulation time 213676114 ps
CPU time 1.08 seconds
Started Aug 09 05:31:18 PM PDT 24
Finished Aug 09 05:31:19 PM PDT 24
Peak memory 215928 kb
Host smart-324e3749-dffb-46e7-97f0-24ad0757e1fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1136825494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1136825494
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4104343320
Short name T524
Test name
Test status
Simulation time 210177189 ps
CPU time 0.92 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:34 PM PDT 24
Peak memory 207476 kb
Host smart-fd244bc9-b332-4122-ad2d-daf05798e894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41043
43320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4104343320
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2074432377
Short name T516
Test name
Test status
Simulation time 237938457 ps
CPU time 0.99 seconds
Started Aug 09 05:31:24 PM PDT 24
Finished Aug 09 05:31:26 PM PDT 24
Peak memory 207524 kb
Host smart-59686663-3849-431c-ac31-96f94dc508a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20744
32377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2074432377
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.4139213987
Short name T808
Test name
Test status
Simulation time 4190616097 ps
CPU time 115.99 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:33:26 PM PDT 24
Peak memory 216072 kb
Host smart-7738ce63-dea3-45eb-bb99-11ce7ce67992
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4139213987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.4139213987
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2564899324
Short name T2533
Test name
Test status
Simulation time 8204533501 ps
CPU time 55.59 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207780 kb
Host smart-f6d13853-5513-4462-a2a0-79d9985f41db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2564899324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2564899324
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1401434675
Short name T620
Test name
Test status
Simulation time 184583658 ps
CPU time 0.86 seconds
Started Aug 09 05:31:46 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207472 kb
Host smart-bc7ca36e-8567-40a8-818f-23ee025a286a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14014
34675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1401434675
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.721810643
Short name T3467
Test name
Test status
Simulation time 26131558374 ps
CPU time 50.72 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207824 kb
Host smart-fbe0e231-e9fb-4101-9530-24c3d87a7bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72181
0643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.721810643
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1008237117
Short name T1056
Test name
Test status
Simulation time 8628764712 ps
CPU time 12.05 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207728 kb
Host smart-8b03142d-5c8a-4139-879e-184c58b94917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
37117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1008237117
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3915594833
Short name T2258
Test name
Test status
Simulation time 3308150808 ps
CPU time 94.85 seconds
Started Aug 09 05:31:35 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 218440 kb
Host smart-4c8d7622-41ef-4b76-ab90-e450e0aa5630
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3915594833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3915594833
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.587414161
Short name T2861
Test name
Test status
Simulation time 3547429774 ps
CPU time 100.34 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:33:15 PM PDT 24
Peak memory 216056 kb
Host smart-8dfcdb64-6043-4e3a-8b6f-8a1fbb0aecc3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587414161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.587414161
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2050273310
Short name T1052
Test name
Test status
Simulation time 240432454 ps
CPU time 0.98 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207548 kb
Host smart-2cf79f93-382d-4790-a5a7-ff3763ee154f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2050273310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2050273310
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2127356617
Short name T921
Test name
Test status
Simulation time 195110913 ps
CPU time 0.99 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 207432 kb
Host smart-e5b6e98b-cfb5-4d76-94b3-88eb7984445a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21273
56617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2127356617
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.4231967236
Short name T1248
Test name
Test status
Simulation time 4142959412 ps
CPU time 31.32 seconds
Started Aug 09 05:31:38 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 216044 kb
Host smart-7bf6e86a-b296-43ce-8c3d-457d6b30b8a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4231967236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.4231967236
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3321473508
Short name T2902
Test name
Test status
Simulation time 184230177 ps
CPU time 0.88 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207456 kb
Host smart-0478ebf6-e7f3-45a6-87eb-f7d7c1c3e3c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3321473508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3321473508
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3995776269
Short name T1185
Test name
Test status
Simulation time 147433325 ps
CPU time 0.88 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 207484 kb
Host smart-33a3b3c1-f793-4128-87c6-1eb6fa773fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
76269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3995776269
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2848245239
Short name T117
Test name
Test status
Simulation time 244678889 ps
CPU time 0.97 seconds
Started Aug 09 05:31:54 PM PDT 24
Finished Aug 09 05:31:55 PM PDT 24
Peak memory 207404 kb
Host smart-78678c01-0058-44c5-8bea-2d2f0901db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
45239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2848245239
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2109216227
Short name T1996
Test name
Test status
Simulation time 152881818 ps
CPU time 0.91 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:34 PM PDT 24
Peak memory 207384 kb
Host smart-e7d430c8-13e7-4eef-bc0d-72037413be21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
16227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2109216227
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2849718939
Short name T19
Test name
Test status
Simulation time 239209280 ps
CPU time 0.98 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207424 kb
Host smart-8c7c63d3-6ee1-4b83-b782-6fbba5e5a9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28497
18939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2849718939
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2587928025
Short name T1766
Test name
Test status
Simulation time 161395818 ps
CPU time 0.86 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:31:38 PM PDT 24
Peak memory 207396 kb
Host smart-eddcbc24-15f4-4705-9791-17ae1647258e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
28025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2587928025
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1954464782
Short name T2607
Test name
Test status
Simulation time 168975507 ps
CPU time 0.88 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 207472 kb
Host smart-9f9f7d59-68b5-40bc-bd54-01318b5c059c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544
64782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1954464782
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.575753358
Short name T1213
Test name
Test status
Simulation time 222334108 ps
CPU time 1 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207424 kb
Host smart-44b1bb2d-ebd8-49c4-9aef-c058bd7afbca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=575753358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.575753358
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3409762151
Short name T731
Test name
Test status
Simulation time 148500814 ps
CPU time 0.84 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 207496 kb
Host smart-5e1fc15f-ceb7-49ea-90f4-29695bcae505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
62151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3409762151
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3227852773
Short name T1450
Test name
Test status
Simulation time 60397448 ps
CPU time 0.69 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:34 PM PDT 24
Peak memory 207476 kb
Host smart-051872fc-e522-4444-979d-538f0709cff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278
52773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3227852773
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.188448144
Short name T2313
Test name
Test status
Simulation time 17447908415 ps
CPU time 49.82 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 215984 kb
Host smart-e36c49aa-56bc-45cb-bcf1-031e823cb963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
8144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.188448144
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.524235158
Short name T2003
Test name
Test status
Simulation time 147273315 ps
CPU time 0.88 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207504 kb
Host smart-5cfe9499-9ef1-4db2-9d60-4b2502bafee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52423
5158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.524235158
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.398842075
Short name T2628
Test name
Test status
Simulation time 249565807 ps
CPU time 0.99 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 207444 kb
Host smart-76fc0594-07ed-4fb7-84ad-0cf36b4e68c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39884
2075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.398842075
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1833261355
Short name T1150
Test name
Test status
Simulation time 183589028 ps
CPU time 0.92 seconds
Started Aug 09 05:31:35 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207396 kb
Host smart-d3fac7ca-9610-49cb-ad66-07266b58d786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
61355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1833261355
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2569567534
Short name T3268
Test name
Test status
Simulation time 161864579 ps
CPU time 0.93 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:31:53 PM PDT 24
Peak memory 207528 kb
Host smart-a5ad5fca-267e-408a-aab1-41391163c517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
67534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2569567534
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2690315598
Short name T1054
Test name
Test status
Simulation time 183266802 ps
CPU time 0.89 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207384 kb
Host smart-d2f7a14a-eaf1-4178-abcb-2b64bf04b24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
15598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2690315598
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.1456564667
Short name T3239
Test name
Test status
Simulation time 428294475 ps
CPU time 1.31 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207488 kb
Host smart-9d13288e-38ce-4500-a746-1c0e057ec2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
64667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.1456564667
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2789691529
Short name T2931
Test name
Test status
Simulation time 184676755 ps
CPU time 0.89 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207476 kb
Host smart-34e8e311-eb39-414f-a888-35ae9404c248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27896
91529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2789691529
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.859998031
Short name T1311
Test name
Test status
Simulation time 149435953 ps
CPU time 0.84 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207528 kb
Host smart-a0105ffa-9e8a-46bd-8e2f-ec1efc1800fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85999
8031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.859998031
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.668653135
Short name T627
Test name
Test status
Simulation time 183503655 ps
CPU time 0.95 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207476 kb
Host smart-3e81cbd1-2b48-47f6-860b-5c847b93fe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66865
3135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.668653135
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.4132626326
Short name T1976
Test name
Test status
Simulation time 2515938718 ps
CPU time 72.47 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:32:48 PM PDT 24
Peak memory 224228 kb
Host smart-a4c19f0e-76b5-46c4-8e8f-252ffdf1b9a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4132626326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.4132626326
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.4054287091
Short name T945
Test name
Test status
Simulation time 180292570 ps
CPU time 0.88 seconds
Started Aug 09 05:31:46 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207380 kb
Host smart-60ffe812-0c72-4702-8426-52afbca2adeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
87091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.4054287091
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3063709991
Short name T1104
Test name
Test status
Simulation time 151640678 ps
CPU time 0.81 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207448 kb
Host smart-c3056138-0143-4644-8719-11262810cb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30637
09991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3063709991
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.996944407
Short name T970
Test name
Test status
Simulation time 1203649085 ps
CPU time 2.7 seconds
Started Aug 09 05:31:42 PM PDT 24
Finished Aug 09 05:31:44 PM PDT 24
Peak memory 207688 kb
Host smart-92c5efef-4d3c-46cc-b91c-a554fea7d6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99694
4407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.996944407
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3778239871
Short name T1785
Test name
Test status
Simulation time 2069729653 ps
CPU time 20.79 seconds
Started Aug 09 05:31:41 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 216516 kb
Host smart-f1088b20-e350-47e9-bfa6-fa719403878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782
39871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3778239871
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.3659956164
Short name T3590
Test name
Test status
Simulation time 650009938 ps
CPU time 11.37 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:44 PM PDT 24
Peak memory 207584 kb
Host smart-565b0339-5dd1-4382-bc13-96728ad79075
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659956164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.3659956164
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.365246771
Short name T1637
Test name
Test status
Simulation time 448993310 ps
CPU time 1.47 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207564 kb
Host smart-83bbadcb-200f-40fb-9c35-78fcc379269a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365246771 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.365246771
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.3150734961
Short name T3183
Test name
Test status
Simulation time 546152036 ps
CPU time 1.6 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207568 kb
Host smart-f283cd88-4a3f-480f-82f0-6d9282860e0a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150734961 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.3150734961
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.3199262529
Short name T3549
Test name
Test status
Simulation time 487153274 ps
CPU time 1.44 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207568 kb
Host smart-56d4b769-4ffb-42de-b160-e96685e3752f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199262529 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.3199262529
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.539350426
Short name T2288
Test name
Test status
Simulation time 585466968 ps
CPU time 1.81 seconds
Started Aug 09 05:33:46 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207416 kb
Host smart-c91422d9-ad65-41bb-aaae-8f914facce6a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539350426 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.539350426
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.2047090358
Short name T1222
Test name
Test status
Simulation time 440868492 ps
CPU time 1.36 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207596 kb
Host smart-20cf8b46-7d06-45bf-9410-b7dc8a0b34f2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047090358 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.2047090358
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.4246983334
Short name T3030
Test name
Test status
Simulation time 649414748 ps
CPU time 1.67 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207464 kb
Host smart-18f7911a-0e8d-40aa-9bef-011f8d009b2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246983334 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.4246983334
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.3984981182
Short name T804
Test name
Test status
Simulation time 656576540 ps
CPU time 1.71 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207404 kb
Host smart-24b0adba-5c6c-4740-a8f1-c1e055369df3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984981182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.3984981182
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.1132581466
Short name T2311
Test name
Test status
Simulation time 488567809 ps
CPU time 1.51 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207560 kb
Host smart-80ec2686-9cc0-4495-b5e1-5962b8d0cbbb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132581466 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.1132581466
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.2606916684
Short name T3407
Test name
Test status
Simulation time 693212070 ps
CPU time 1.78 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207464 kb
Host smart-4c1c4aaf-36ce-48fc-9215-c606a45e7212
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606916684 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.2606916684
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.912256641
Short name T1552
Test name
Test status
Simulation time 486798573 ps
CPU time 1.71 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 207532 kb
Host smart-adeb5c81-a580-4780-aa6e-06d7015ddccc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912256641 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.912256641
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.749141232
Short name T1276
Test name
Test status
Simulation time 504730201 ps
CPU time 1.42 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207528 kb
Host smart-c650b2ef-ac71-428e-870a-039ac7bc8b13
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749141232 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.749141232
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.2629118400
Short name T1412
Test name
Test status
Simulation time 80582135 ps
CPU time 0.73 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 207532 kb
Host smart-2c9e58d8-cb98-4a91-91a3-a9b270abebd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2629118400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.2629118400
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2505211650
Short name T1277
Test name
Test status
Simulation time 10323791460 ps
CPU time 13.23 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 208084 kb
Host smart-d008dff8-b9f2-45e8-b7a5-68ffda2aa1ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505211650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2505211650
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.651084107
Short name T11
Test name
Test status
Simulation time 15141789315 ps
CPU time 16.77 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 215960 kb
Host smart-215ef876-7bb5-4aeb-941e-49a415af4c8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=651084107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.651084107
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2152516734
Short name T894
Test name
Test status
Simulation time 23460908102 ps
CPU time 28.16 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 215908 kb
Host smart-26422307-f1a2-42db-9853-7868597ff6ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152516734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.2152516734
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1620835172
Short name T2651
Test name
Test status
Simulation time 165541893 ps
CPU time 0.87 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207372 kb
Host smart-060fb10c-bfba-4f5a-8e80-8e2709e49bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
35172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1620835172
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.4237576114
Short name T2718
Test name
Test status
Simulation time 145156979 ps
CPU time 0.85 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207440 kb
Host smart-e314bbb4-9c8f-4b64-a636-a3db1074316c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
76114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.4237576114
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2674408507
Short name T1556
Test name
Test status
Simulation time 334565095 ps
CPU time 1.26 seconds
Started Aug 09 05:31:31 PM PDT 24
Finished Aug 09 05:31:38 PM PDT 24
Peak memory 207496 kb
Host smart-a6f620ed-10bb-45a2-94a5-37be0685fedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
08507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2674408507
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3768986638
Short name T1608
Test name
Test status
Simulation time 1142596834 ps
CPU time 3.11 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 207532 kb
Host smart-9bc29ca4-17e2-45d3-9c0c-32d2aa22e873
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3768986638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3768986638
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.647719928
Short name T2291
Test name
Test status
Simulation time 48194081954 ps
CPU time 69.91 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207736 kb
Host smart-12d907b1-db12-433d-96ed-10f130204e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64771
9928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.647719928
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.1818185478
Short name T2958
Test name
Test status
Simulation time 1111853961 ps
CPU time 26.48 seconds
Started Aug 09 05:31:43 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207628 kb
Host smart-62eebf68-6a62-430a-b7ad-164c1f83eb0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818185478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.1818185478
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.745714324
Short name T2452
Test name
Test status
Simulation time 846776121 ps
CPU time 1.9 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:31:38 PM PDT 24
Peak memory 207472 kb
Host smart-010b5ce3-56a4-4786-9e23-29b469703698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74571
4324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.745714324
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1603392670
Short name T601
Test name
Test status
Simulation time 185547150 ps
CPU time 0.91 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 207516 kb
Host smart-1aed4c4a-3452-4e47-a368-1e662f5f689e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16033
92670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1603392670
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3273928448
Short name T2527
Test name
Test status
Simulation time 42262082 ps
CPU time 0.71 seconds
Started Aug 09 05:31:35 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207520 kb
Host smart-0fe2e6d2-bb60-459b-85ff-a87fd4a46c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
28448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3273928448
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.401386959
Short name T2906
Test name
Test status
Simulation time 1016482546 ps
CPU time 2.45 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207648 kb
Host smart-6643bff6-f403-41f2-9da9-9a74a363b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40138
6959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.401386959
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.761635077
Short name T406
Test name
Test status
Simulation time 280028298 ps
CPU time 1.07 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207344 kb
Host smart-00e3fb3e-6b37-4985-b75b-79a792725e73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=761635077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.761635077
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3020420456
Short name T1717
Test name
Test status
Simulation time 186431246 ps
CPU time 1.3 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207692 kb
Host smart-9a78e1f7-c451-41cd-8a00-0d1751bd5b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30204
20456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3020420456
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3301695790
Short name T1251
Test name
Test status
Simulation time 175648458 ps
CPU time 0.92 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 207364 kb
Host smart-b570e13d-1124-4801-86ae-c99343bb2274
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3301695790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3301695790
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.249951685
Short name T2255
Test name
Test status
Simulation time 139409172 ps
CPU time 0.81 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:30 PM PDT 24
Peak memory 207476 kb
Host smart-631858bb-faef-4bf4-8de2-e682619c08ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
1685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.249951685
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2009761240
Short name T538
Test name
Test status
Simulation time 316522775 ps
CPU time 1.17 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207380 kb
Host smart-1646cff2-a0ff-4011-8a04-38a3a2396eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
61240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2009761240
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1573678874
Short name T2542
Test name
Test status
Simulation time 2953053052 ps
CPU time 84.55 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 216032 kb
Host smart-cc61a097-c1d4-493d-93aa-68061402e0c7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1573678874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1573678874
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2010450666
Short name T88
Test name
Test status
Simulation time 5453875308 ps
CPU time 35.5 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207808 kb
Host smart-22c178fc-7eba-4eeb-94c6-40442f208f13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2010450666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2010450666
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1873983806
Short name T760
Test name
Test status
Simulation time 202511913 ps
CPU time 0.94 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:34 PM PDT 24
Peak memory 207560 kb
Host smart-32564ceb-570f-4801-93c5-f6dfd003eed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18739
83806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1873983806
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3418731888
Short name T1501
Test name
Test status
Simulation time 5333688361 ps
CPU time 8.12 seconds
Started Aug 09 05:31:35 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 215856 kb
Host smart-2babea50-66a6-4a81-8c4b-28577ef6bac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
31888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3418731888
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.19715103
Short name T1676
Test name
Test status
Simulation time 9904865047 ps
CPU time 12.02 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207808 kb
Host smart-a6d6cab9-da3e-42e4-8353-983759918470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.19715103
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2575541524
Short name T2352
Test name
Test status
Simulation time 2832665579 ps
CPU time 83.13 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 216116 kb
Host smart-f85b39f0-aa71-4eb9-a338-5bf5798dd468
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2575541524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2575541524
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3553577633
Short name T1055
Test name
Test status
Simulation time 2583538780 ps
CPU time 25.73 seconds
Started Aug 09 05:31:33 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 217648 kb
Host smart-afeabc2f-5d8c-46ea-9841-1f804fa2c71e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3553577633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3553577633
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.505228855
Short name T1030
Test name
Test status
Simulation time 300927313 ps
CPU time 1.02 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207376 kb
Host smart-bc4a1b92-53e1-44cc-838b-1d8cdab7f8da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=505228855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.505228855
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.242753851
Short name T3295
Test name
Test status
Simulation time 189444939 ps
CPU time 1 seconds
Started Aug 09 05:31:46 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207524 kb
Host smart-ffd3d555-06ec-4e78-a017-2e21434a92d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.242753851
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1516576492
Short name T2301
Test name
Test status
Simulation time 3451206523 ps
CPU time 25.88 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:32:15 PM PDT 24
Peak memory 215976 kb
Host smart-61c4cd40-dc73-45d3-9b37-0c3a5c66ee71
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1516576492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1516576492
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.888945636
Short name T2207
Test name
Test status
Simulation time 156549346 ps
CPU time 0.84 seconds
Started Aug 09 05:31:46 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207492 kb
Host smart-afeb5b68-fa85-4bb4-bdd7-7e249fa346a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=888945636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.888945636
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.947921981
Short name T2840
Test name
Test status
Simulation time 152794250 ps
CPU time 0.89 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 207592 kb
Host smart-f5de9cae-cf2a-46d0-a540-a38ce7b4da66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94792
1981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.947921981
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1410142789
Short name T3087
Test name
Test status
Simulation time 212089736 ps
CPU time 0.96 seconds
Started Aug 09 05:31:38 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207436 kb
Host smart-e926417f-5ae2-4ae1-a781-6c168f4d208f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14101
42789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1410142789
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3144064819
Short name T2761
Test name
Test status
Simulation time 188529728 ps
CPU time 0.95 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207548 kb
Host smart-d116b3e6-395f-4e03-b573-4070758e02f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
64819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3144064819
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3675691693
Short name T2486
Test name
Test status
Simulation time 185093252 ps
CPU time 0.88 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:53 PM PDT 24
Peak memory 207476 kb
Host smart-1b9671fb-33e3-4543-b5a4-2f5a0b1f489f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36756
91693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3675691693
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1660871510
Short name T1537
Test name
Test status
Simulation time 185372395 ps
CPU time 0.94 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 207476 kb
Host smart-5462464e-7608-4788-8a93-12864799a20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16608
71510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1660871510
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4138851271
Short name T3232
Test name
Test status
Simulation time 154241700 ps
CPU time 0.85 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207444 kb
Host smart-2deb9918-959b-41aa-969d-74d82faf45ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
51271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4138851271
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.120832738
Short name T1870
Test name
Test status
Simulation time 217872930 ps
CPU time 0.95 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207400 kb
Host smart-92fabfe4-32c5-470d-aa99-4dedf7d9a976
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=120832738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.120832738
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1190170400
Short name T1236
Test name
Test status
Simulation time 160321881 ps
CPU time 0.81 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:31:37 PM PDT 24
Peak memory 207400 kb
Host smart-e89264e5-3c66-4514-83d4-dd95efc34340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
70400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1190170400
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2212947686
Short name T702
Test name
Test status
Simulation time 30132282 ps
CPU time 0.66 seconds
Started Aug 09 05:31:34 PM PDT 24
Finished Aug 09 05:31:35 PM PDT 24
Peak memory 207356 kb
Host smart-674ea82a-8bf1-4d25-a160-11840415a974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22129
47686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2212947686
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.52584720
Short name T840
Test name
Test status
Simulation time 11456830878 ps
CPU time 29.25 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 215996 kb
Host smart-21ca0696-2739-41c8-bcff-5b97f275271c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52584
720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.52584720
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2863425545
Short name T2652
Test name
Test status
Simulation time 145540154 ps
CPU time 0.9 seconds
Started Aug 09 05:31:42 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207556 kb
Host smart-fd26fc02-2b87-478f-9a05-2185037efcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28634
25545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2863425545
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1541638912
Short name T972
Test name
Test status
Simulation time 221510484 ps
CPU time 0.98 seconds
Started Aug 09 05:31:42 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207368 kb
Host smart-e0f8aea9-c67b-4d73-8037-07cef7c3a2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
38912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1541638912
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1774287576
Short name T2776
Test name
Test status
Simulation time 222350779 ps
CPU time 1.04 seconds
Started Aug 09 05:31:32 PM PDT 24
Finished Aug 09 05:31:33 PM PDT 24
Peak memory 207416 kb
Host smart-3517e112-9247-4ed4-9aae-aa74b1b84c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17742
87576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1774287576
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2276465070
Short name T520
Test name
Test status
Simulation time 186081350 ps
CPU time 0.89 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207476 kb
Host smart-e6f28473-00d5-4275-ad86-e7cb1cf56e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22764
65070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2276465070
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1108757109
Short name T1747
Test name
Test status
Simulation time 147001743 ps
CPU time 0.86 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207452 kb
Host smart-da1b5800-a5ff-45b1-8f18-729afad4e7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
57109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1108757109
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.2433447577
Short name T559
Test name
Test status
Simulation time 352834430 ps
CPU time 1.34 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207548 kb
Host smart-dde0f7bb-f647-48bd-a46b-8f40f0601a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
47577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.2433447577
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.881825108
Short name T2054
Test name
Test status
Simulation time 172641073 ps
CPU time 0.86 seconds
Started Aug 09 05:31:39 PM PDT 24
Finished Aug 09 05:31:40 PM PDT 24
Peak memory 207448 kb
Host smart-19b07662-f0ba-4bf5-896f-9b94d2a105dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88182
5108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.881825108
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2756357804
Short name T225
Test name
Test status
Simulation time 176007053 ps
CPU time 0.89 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207364 kb
Host smart-c1637208-8743-404f-9ced-145ca1aa99ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
57804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2756357804
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3256580736
Short name T2051
Test name
Test status
Simulation time 200040513 ps
CPU time 1.01 seconds
Started Aug 09 05:31:35 PM PDT 24
Finished Aug 09 05:31:36 PM PDT 24
Peak memory 207524 kb
Host smart-2b172bab-25c3-44eb-9051-310be8656fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565
80736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3256580736
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3377285165
Short name T2545
Test name
Test status
Simulation time 2471211889 ps
CPU time 20.48 seconds
Started Aug 09 05:31:45 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 217904 kb
Host smart-5cca8e0d-10a1-437e-9b43-1e5b151e030e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3377285165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3377285165
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.294035847
Short name T2400
Test name
Test status
Simulation time 173075253 ps
CPU time 0.9 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:31:37 PM PDT 24
Peak memory 207436 kb
Host smart-3e3b520e-b7e1-4f5e-8fce-ec28b3446339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
5847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.294035847
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2506514281
Short name T1489
Test name
Test status
Simulation time 225771226 ps
CPU time 0.95 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207412 kb
Host smart-c81e4b27-bd02-479e-a173-b253e21dde30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
14281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2506514281
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3512917463
Short name T2837
Test name
Test status
Simulation time 338003155 ps
CPU time 1.22 seconds
Started Aug 09 05:31:30 PM PDT 24
Finished Aug 09 05:31:31 PM PDT 24
Peak memory 207444 kb
Host smart-2b60639f-8890-401c-99ad-f077a0aed22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35129
17463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3512917463
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3791611959
Short name T2441
Test name
Test status
Simulation time 3658577328 ps
CPU time 27.8 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 217724 kb
Host smart-d1f8a958-8054-4e4d-9d4d-6e8dc8386cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
11959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3791611959
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1972252619
Short name T747
Test name
Test status
Simulation time 1485602654 ps
CPU time 34.22 seconds
Started Aug 09 05:31:29 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207628 kb
Host smart-490ec6c1-fda2-41da-8695-f20406131895
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972252619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1972252619
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.4064566920
Short name T1510
Test name
Test status
Simulation time 622746946 ps
CPU time 1.73 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207412 kb
Host smart-87150031-46f6-4375-85fe-f508ff5384bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064566920 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.4064566920
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.2849652602
Short name T2372
Test name
Test status
Simulation time 477045079 ps
CPU time 1.56 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207500 kb
Host smart-6867b97d-19c2-4e6c-a6b9-fe0e52317050
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849652602 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.2849652602
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.1247650467
Short name T2993
Test name
Test status
Simulation time 498935093 ps
CPU time 1.61 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 207512 kb
Host smart-b1eaed4b-e151-4135-83ab-40d5738d0636
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247650467 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.1247650467
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.2139522998
Short name T828
Test name
Test status
Simulation time 545112072 ps
CPU time 1.65 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207396 kb
Host smart-195fec15-1836-4558-b33b-af41094e19b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139522998 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.2139522998
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.2276760676
Short name T1720
Test name
Test status
Simulation time 597503608 ps
CPU time 1.62 seconds
Started Aug 09 05:33:47 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 207444 kb
Host smart-af2af87c-df25-4612-a062-aeb2e1d37d14
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276760676 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.2276760676
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.3385491305
Short name T3179
Test name
Test status
Simulation time 525961693 ps
CPU time 1.6 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207504 kb
Host smart-64c98efc-bb87-420f-91a7-6ec451296935
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385491305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.3385491305
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.2520477024
Short name T345
Test name
Test status
Simulation time 583610276 ps
CPU time 1.49 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207568 kb
Host smart-51190565-67e8-4bdf-87c8-9e3726496a56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520477024 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.2520477024
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.3064476059
Short name T3227
Test name
Test status
Simulation time 450352466 ps
CPU time 1.38 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207416 kb
Host smart-cdd47119-efbc-4c7c-bcb5-2c0a62d5eae7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064476059 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.3064476059
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.333801750
Short name T1187
Test name
Test status
Simulation time 510002536 ps
CPU time 1.66 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207524 kb
Host smart-bd8facf1-c92d-4699-9f20-6c6b38d1708c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333801750 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.333801750
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.2814203971
Short name T3169
Test name
Test status
Simulation time 505181698 ps
CPU time 1.64 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207564 kb
Host smart-6595de4d-834a-41e1-981f-c4a5d614b41e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814203971 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.2814203971
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.3025861323
Short name T919
Test name
Test status
Simulation time 521371083 ps
CPU time 1.57 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207524 kb
Host smart-5bc2db69-8427-4d58-950a-6a1e234f5a86
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025861323 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.3025861323
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2922509384
Short name T2901
Test name
Test status
Simulation time 79152199 ps
CPU time 0.73 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207460 kb
Host smart-b9c1eae0-3ead-4df6-8d2d-7b0719b9f1df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2922509384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2922509384
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4037284098
Short name T2387
Test name
Test status
Simulation time 6108446116 ps
CPU time 8.92 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 215960 kb
Host smart-df3d8d67-ef4f-4e47-a39d-03cb89922316
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037284098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.4037284098
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2766730310
Short name T852
Test name
Test status
Simulation time 15030714382 ps
CPU time 17.13 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 215964 kb
Host smart-beeeda48-22c9-4440-b18e-872273439ec8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766730310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2766730310
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1492192805
Short name T3178
Test name
Test status
Simulation time 30599825531 ps
CPU time 38.13 seconds
Started Aug 09 05:31:54 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207788 kb
Host smart-cd229c7d-3b36-462a-8558-3f590ac5b4f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492192805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1492192805
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3380490653
Short name T3059
Test name
Test status
Simulation time 184095324 ps
CPU time 0.95 seconds
Started Aug 09 05:31:41 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207504 kb
Host smart-63c76d0b-69b1-4714-b329-582973b9fd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
90653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3380490653
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2084615413
Short name T77
Test name
Test status
Simulation time 148589460 ps
CPU time 0.83 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207720 kb
Host smart-65e83380-9509-44c0-8069-935efa5c8760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
15413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2084615413
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2974111601
Short name T906
Test name
Test status
Simulation time 426632617 ps
CPU time 1.5 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:49 PM PDT 24
Peak memory 207496 kb
Host smart-9947cd8f-b3a2-4a33-ba90-9bef65439c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29741
11601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2974111601
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1041390778
Short name T1405
Test name
Test status
Simulation time 289138828 ps
CPU time 1.11 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207448 kb
Host smart-3fafa137-bcef-49f7-ac22-016821ad9517
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1041390778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1041390778
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1226655635
Short name T2610
Test name
Test status
Simulation time 13789766616 ps
CPU time 21.23 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207748 kb
Host smart-4c7c9d1b-4b7d-47cd-bc56-1e6ab6fc3566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12266
55635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1226655635
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.2188403104
Short name T2191
Test name
Test status
Simulation time 193442852 ps
CPU time 0.97 seconds
Started Aug 09 05:31:44 PM PDT 24
Finished Aug 09 05:31:45 PM PDT 24
Peak memory 207448 kb
Host smart-c9c80ce2-b48a-4d86-8384-77f935cf9964
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188403104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.2188403104
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1219308608
Short name T2290
Test name
Test status
Simulation time 469180337 ps
CPU time 1.42 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207380 kb
Host smart-03a1dd35-90ba-4222-87d7-2bea3c2a3376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193
08608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1219308608
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2250539863
Short name T2689
Test name
Test status
Simulation time 140277338 ps
CPU time 0.83 seconds
Started Aug 09 05:31:36 PM PDT 24
Finished Aug 09 05:31:37 PM PDT 24
Peak memory 207528 kb
Host smart-0f49b051-3d96-442b-9342-1af6ae1ed736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
39863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2250539863
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3183503564
Short name T1242
Test name
Test status
Simulation time 44650801 ps
CPU time 0.72 seconds
Started Aug 09 05:31:43 PM PDT 24
Finished Aug 09 05:31:43 PM PDT 24
Peak memory 207440 kb
Host smart-99dd0af7-4f10-4844-9b6e-b97e71e6fa1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31835
03564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3183503564
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3031852416
Short name T3160
Test name
Test status
Simulation time 994467015 ps
CPU time 2.46 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207624 kb
Host smart-612eb5d1-953b-4c08-af0b-cd5b8fd9edbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
52416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3031852416
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.2926747920
Short name T376
Test name
Test status
Simulation time 515221995 ps
CPU time 1.39 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207480 kb
Host smart-1d7027ad-4228-4aa7-868a-4f633d45b478
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2926747920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.2926747920
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3804558103
Short name T2274
Test name
Test status
Simulation time 200654967 ps
CPU time 2.57 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 207652 kb
Host smart-acb9a7a5-df05-468c-be78-7f0170ef5810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38045
58103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3804558103
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2242190744
Short name T904
Test name
Test status
Simulation time 146765410 ps
CPU time 0.83 seconds
Started Aug 09 05:31:41 PM PDT 24
Finished Aug 09 05:31:42 PM PDT 24
Peak memory 207468 kb
Host smart-7eae2862-e104-4ace-9de2-a8fe11fc525a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2242190744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2242190744
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2983366181
Short name T1388
Test name
Test status
Simulation time 150618027 ps
CPU time 0.85 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207376 kb
Host smart-800fde72-9f9d-4ed0-bdaf-fd86386e0713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29833
66181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2983366181
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3280441436
Short name T2975
Test name
Test status
Simulation time 199909893 ps
CPU time 0.99 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 207468 kb
Host smart-211ae834-4c3d-4334-ad46-76a34fd3e608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
41436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3280441436
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1477434037
Short name T1118
Test name
Test status
Simulation time 4793611704 ps
CPU time 137.31 seconds
Started Aug 09 05:31:37 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 224260 kb
Host smart-f7943ea3-625b-4e2b-8454-0bf8f0480310
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1477434037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1477434037
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.862924204
Short name T756
Test name
Test status
Simulation time 13666208470 ps
CPU time 84.78 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:33:17 PM PDT 24
Peak memory 207692 kb
Host smart-8857a407-d8b7-445b-bc52-45c2c4ec021f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=862924204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.862924204
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3798156335
Short name T802
Test name
Test status
Simulation time 177497754 ps
CPU time 0.89 seconds
Started Aug 09 05:31:45 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207488 kb
Host smart-bfeef2e2-58e2-4d17-a1f1-fa7f8608bded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981
56335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3798156335
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1508241874
Short name T3113
Test name
Test status
Simulation time 31776384608 ps
CPU time 43.21 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207728 kb
Host smart-46c2818c-21fb-4011-84b5-3cab1f4c1f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15082
41874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1508241874
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1037347102
Short name T2966
Test name
Test status
Simulation time 10713172691 ps
CPU time 12.37 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207796 kb
Host smart-269da1cc-61d1-42ce-98a2-07c13fe6d8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373
47102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1037347102
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2978040354
Short name T868
Test name
Test status
Simulation time 3896131845 ps
CPU time 110.61 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 217404 kb
Host smart-34c17fa6-602f-4f56-b386-f1f45ee7df7f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2978040354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2978040354
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.51752156
Short name T531
Test name
Test status
Simulation time 256037958 ps
CPU time 1.06 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207500 kb
Host smart-aec17aba-aaf0-4ae2-8dfd-4edd02c51d6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=51752156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.51752156
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.540741682
Short name T1894
Test name
Test status
Simulation time 188659109 ps
CPU time 0.96 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207432 kb
Host smart-896e9668-1e93-44f2-b4d9-be5c255a8a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54074
1682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.540741682
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3110190134
Short name T175
Test name
Test status
Simulation time 2091903583 ps
CPU time 19.16 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 217420 kb
Host smart-184bcb82-471d-4ea5-b5d7-eaafd65d707f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3110190134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3110190134
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.583199321
Short name T1021
Test name
Test status
Simulation time 165292397 ps
CPU time 0.89 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207460 kb
Host smart-d86d2caf-d03f-4a06-955a-546b86739f05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=583199321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.583199321
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3602612011
Short name T3158
Test name
Test status
Simulation time 167914071 ps
CPU time 0.88 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207408 kb
Host smart-27a2df60-e8b2-4b69-95da-9f6a91998a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
12011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3602612011
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2361385623
Short name T3141
Test name
Test status
Simulation time 254708175 ps
CPU time 0.98 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207352 kb
Host smart-4186b89e-71b8-4f87-aece-0262d31d90b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
85623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2361385623
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4182227124
Short name T1673
Test name
Test status
Simulation time 179253271 ps
CPU time 0.92 seconds
Started Aug 09 05:31:45 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207436 kb
Host smart-615afb1e-2787-4bad-a0b0-b6ddb88ec5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822
27124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4182227124
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2347186629
Short name T748
Test name
Test status
Simulation time 203024559 ps
CPU time 1.02 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207472 kb
Host smart-e64c2103-dadf-4949-81d4-bfec3d6eaa44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23471
86629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2347186629
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4294960118
Short name T1341
Test name
Test status
Simulation time 214051272 ps
CPU time 0.99 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207404 kb
Host smart-62a170cb-6a81-455e-b397-6c63afe74dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
60118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4294960118
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3011695296
Short name T1342
Test name
Test status
Simulation time 154057789 ps
CPU time 0.89 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207560 kb
Host smart-753425a4-c75e-4ac3-a881-e063d826471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30116
95296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3011695296
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3875688408
Short name T245
Test name
Test status
Simulation time 234204168 ps
CPU time 1.04 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:56 PM PDT 24
Peak memory 207504 kb
Host smart-ced97f2f-81c9-42c9-b6b1-18293f6f6678
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3875688408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3875688408
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3874158075
Short name T203
Test name
Test status
Simulation time 154793988 ps
CPU time 0.87 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207348 kb
Host smart-6b9e5dfa-5d2e-48c5-8346-c89f4cc574d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741
58075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3874158075
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3567579121
Short name T706
Test name
Test status
Simulation time 42623237 ps
CPU time 0.68 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207472 kb
Host smart-28fed70d-5180-4f71-bbb1-26c12a8eb59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
79121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3567579121
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3084490580
Short name T328
Test name
Test status
Simulation time 20975686379 ps
CPU time 53.28 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 216076 kb
Host smart-cbd3510c-1592-4bbf-a49d-14dabe3fd0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844
90580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3084490580
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2863311719
Short name T527
Test name
Test status
Simulation time 185264091 ps
CPU time 1.03 seconds
Started Aug 09 05:31:40 PM PDT 24
Finished Aug 09 05:31:41 PM PDT 24
Peak memory 207788 kb
Host smart-45e3cd89-6fa2-4c3f-b187-f7bb3c656ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28633
11719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2863311719
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3992215132
Short name T2065
Test name
Test status
Simulation time 271053743 ps
CPU time 1.05 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207548 kb
Host smart-42b13ecf-3cd2-4527-b37d-5cea2ea0ed86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39922
15132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3992215132
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2784565097
Short name T2727
Test name
Test status
Simulation time 199750600 ps
CPU time 0.93 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207408 kb
Host smart-9459c31d-3839-4138-9661-dcd60b865cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27845
65097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2784565097
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1095554110
Short name T3572
Test name
Test status
Simulation time 161990725 ps
CPU time 0.88 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207476 kb
Host smart-64d37e1e-387a-470b-9e89-7702c1dcc14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10955
54110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1095554110
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.4236426170
Short name T2863
Test name
Test status
Simulation time 140378947 ps
CPU time 0.81 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207376 kb
Host smart-c7366121-5869-4c59-a204-ba71cba2c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
26170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.4236426170
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.371094272
Short name T2753
Test name
Test status
Simulation time 253509500 ps
CPU time 1.02 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:31:51 PM PDT 24
Peak memory 207480 kb
Host smart-08fcd042-1803-4bc2-9c67-f906ab58fd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37109
4272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.371094272
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2375317917
Short name T924
Test name
Test status
Simulation time 158481800 ps
CPU time 0.86 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207404 kb
Host smart-8aebb5a8-1abe-4c55-88d1-27d41426fe38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23753
17917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2375317917
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.173651946
Short name T3617
Test name
Test status
Simulation time 150060177 ps
CPU time 0.87 seconds
Started Aug 09 05:31:45 PM PDT 24
Finished Aug 09 05:31:46 PM PDT 24
Peak memory 207456 kb
Host smart-7cd2068a-6382-483a-a2f5-aed9853b464a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17365
1946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.173651946
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1379240614
Short name T1181
Test name
Test status
Simulation time 237270793 ps
CPU time 0.96 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 207456 kb
Host smart-f545c2bb-739f-4189-aa42-25a19011e592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13792
40614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1379240614
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2608072741
Short name T855
Test name
Test status
Simulation time 2354380945 ps
CPU time 22.54 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:32:18 PM PDT 24
Peak memory 217976 kb
Host smart-452e133f-7513-4099-b231-bf1558cd8aba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2608072741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2608072741
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2141432950
Short name T1302
Test name
Test status
Simulation time 179164338 ps
CPU time 0.9 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207528 kb
Host smart-3c003fe8-da87-40c7-989c-80769881cd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21414
32950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2141432950
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3389080049
Short name T3080
Test name
Test status
Simulation time 206599756 ps
CPU time 0.9 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207508 kb
Host smart-09e4cf4a-ad6d-4896-a5b6-a5afeca282ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33890
80049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3389080049
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2920815417
Short name T530
Test name
Test status
Simulation time 252827165 ps
CPU time 1 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207364 kb
Host smart-f38bfbe5-2daf-4ad2-9beb-d1b5293cd119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
15417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2920815417
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2325748455
Short name T875
Test name
Test status
Simulation time 2715935308 ps
CPU time 26.58 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:32:18 PM PDT 24
Peak memory 216944 kb
Host smart-863f9ca9-934a-4050-b6da-2e9225d569a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
48455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2325748455
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2921164571
Short name T2935
Test name
Test status
Simulation time 308224598 ps
CPU time 4.69 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207688 kb
Host smart-009f631c-4195-49d9-870b-d23c5a0c75bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921164571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.2921164571
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.335620024
Short name T2959
Test name
Test status
Simulation time 517211209 ps
CPU time 1.46 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207464 kb
Host smart-ccfaa5da-4f7e-45e5-a18a-ca1fbf3fdff9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335620024 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.335620024
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.2954384243
Short name T1742
Test name
Test status
Simulation time 474446882 ps
CPU time 1.46 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207500 kb
Host smart-3277d219-ffac-439b-9e36-7e73b42c05e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954384243 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.2954384243
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.525911937
Short name T3200
Test name
Test status
Simulation time 644753876 ps
CPU time 1.63 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207392 kb
Host smart-0aac6605-9863-4047-a2ec-14d77abe13d8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525911937 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.525911937
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.1085174648
Short name T1400
Test name
Test status
Simulation time 617138872 ps
CPU time 1.7 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 207512 kb
Host smart-528c4c10-f28e-4ed1-957e-e806c623d897
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085174648 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.1085174648
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.914864838
Short name T3267
Test name
Test status
Simulation time 480379272 ps
CPU time 1.55 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207432 kb
Host smart-e6bed07c-6879-4a60-8630-f1d8bf420832
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914864838 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.914864838
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.2561990160
Short name T193
Test name
Test status
Simulation time 502268655 ps
CPU time 1.52 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207552 kb
Host smart-6f89d221-b832-43a3-9f59-2886579dac10
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561990160 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.2561990160
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.771612175
Short name T244
Test name
Test status
Simulation time 479045567 ps
CPU time 1.45 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:17 PM PDT 24
Peak memory 207564 kb
Host smart-0ebd42d7-d318-4d29-afcd-40ac6c30cf38
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771612175 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.771612175
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.3441916338
Short name T3587
Test name
Test status
Simulation time 469304764 ps
CPU time 1.51 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207444 kb
Host smart-bfbc1ecb-e2ae-49c6-a82d-2411d75a2c2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441916338 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.3441916338
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.3722651955
Short name T2218
Test name
Test status
Simulation time 544219129 ps
CPU time 1.52 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 207556 kb
Host smart-a63873ea-7eee-4ad6-80b0-638801c29a0f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722651955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.3722651955
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.3043953103
Short name T2787
Test name
Test status
Simulation time 665723853 ps
CPU time 1.81 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207396 kb
Host smart-08fb9264-8d3c-4230-8833-d1436bfd71d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043953103 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.3043953103
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.167284902
Short name T1306
Test name
Test status
Simulation time 553903608 ps
CPU time 1.74 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207528 kb
Host smart-07db12ee-f5ed-4f83-9073-a453c38fa41f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167284902 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.167284902
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2006232766
Short name T983
Test name
Test status
Simulation time 46614384 ps
CPU time 0.67 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 206616 kb
Host smart-919fc574-370e-4126-bce9-bec6a06a2761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2006232766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2006232766
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1951057628
Short name T2648
Test name
Test status
Simulation time 4800462738 ps
CPU time 6.54 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 215928 kb
Host smart-7b844363-6d3b-4d66-b276-e97e1b5d63fe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951057628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.1951057628
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.131565535
Short name T3353
Test name
Test status
Simulation time 19694557155 ps
CPU time 26.5 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207768 kb
Host smart-d516a364-d0a8-48c8-8738-4afc23256c91
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=131565535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.131565535
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3392147383
Short name T3544
Test name
Test status
Simulation time 24115145776 ps
CPU time 35.21 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 215976 kb
Host smart-95afeda6-a8ad-4b50-ac29-540ff04e0f2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392147383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3392147383
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2692278406
Short name T3302
Test name
Test status
Simulation time 169860506 ps
CPU time 0.9 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207524 kb
Host smart-b2184ca2-31eb-47a5-8f39-97d68c397311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26922
78406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2692278406
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.944979559
Short name T3229
Test name
Test status
Simulation time 151590849 ps
CPU time 0.88 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207400 kb
Host smart-32d3386b-abf8-4eea-bb68-834a3c02bac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94497
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.944979559
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.4016497634
Short name T1020
Test name
Test status
Simulation time 289487469 ps
CPU time 1.23 seconds
Started Aug 09 05:31:52 PM PDT 24
Finished Aug 09 05:31:53 PM PDT 24
Peak memory 207508 kb
Host smart-ff4b1181-4ae2-4415-8451-93e3911854bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40164
97634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.4016497634
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2056312196
Short name T102
Test name
Test status
Simulation time 1112391402 ps
CPU time 2.81 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207536 kb
Host smart-a8317dd7-1f5f-43b5-870e-3fe779b5f2a8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2056312196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2056312196
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3193727758
Short name T2232
Test name
Test status
Simulation time 16090672942 ps
CPU time 28.03 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 207776 kb
Host smart-37644539-5816-4cf3-948a-2295c721ef6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31937
27758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3193727758
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.133738514
Short name T2771
Test name
Test status
Simulation time 1044996650 ps
CPU time 22.53 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:23 PM PDT 24
Peak memory 207744 kb
Host smart-49e851f3-7a3b-4cf0-8d94-ef8b9e41bebd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133738514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.133738514
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3330739260
Short name T1318
Test name
Test status
Simulation time 373513998 ps
CPU time 1.39 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207384 kb
Host smart-5efbe31d-28e3-4adf-9be6-309773838ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
39260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3330739260
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3281821125
Short name T2974
Test name
Test status
Simulation time 151839762 ps
CPU time 0.84 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207520 kb
Host smart-f362d3c3-acba-46e9-a126-6a5565e3003c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32818
21125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3281821125
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1394203563
Short name T1657
Test name
Test status
Simulation time 35900295 ps
CPU time 0.73 seconds
Started Aug 09 05:31:51 PM PDT 24
Finished Aug 09 05:31:52 PM PDT 24
Peak memory 207380 kb
Host smart-55064cca-3d84-4360-aaf5-2ba0262f5494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13942
03563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1394203563
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3522424237
Short name T3055
Test name
Test status
Simulation time 902907046 ps
CPU time 2.49 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207720 kb
Host smart-6871b092-1fd2-42fa-bf62-2bbecc316a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35224
24237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3522424237
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.1304558921
Short name T461
Test name
Test status
Simulation time 413178970 ps
CPU time 1.35 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207512 kb
Host smart-19e9f894-f4f6-4547-a7fd-4f22968b7dc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1304558921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.1304558921
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3780034864
Short name T880
Test name
Test status
Simulation time 231018077 ps
CPU time 1.38 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:31:54 PM PDT 24
Peak memory 207596 kb
Host smart-ec0bf19d-3554-4f04-a4ef-9ef5d5386506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37800
34864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3780034864
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1617790384
Short name T1738
Test name
Test status
Simulation time 265441261 ps
CPU time 1.26 seconds
Started Aug 09 05:31:47 PM PDT 24
Finished Aug 09 05:31:48 PM PDT 24
Peak memory 215924 kb
Host smart-568e00d1-aa55-418a-be1b-3688d86b12e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1617790384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1617790384
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4172035553
Short name T572
Test name
Test status
Simulation time 141979697 ps
CPU time 0.82 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207524 kb
Host smart-11956454-ffe6-499f-aea5-61ea33aec174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
35553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4172035553
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.383663486
Short name T2443
Test name
Test status
Simulation time 259207350 ps
CPU time 0.97 seconds
Started Aug 09 05:32:21 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207428 kb
Host smart-7cff1821-7f2d-4c66-a3f0-5b5850d21d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
3486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.383663486
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3744036421
Short name T776
Test name
Test status
Simulation time 2889252087 ps
CPU time 26.84 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 217568 kb
Host smart-75a4d8c8-f044-4ef7-967e-eddbef0f8072
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3744036421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3744036421
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3196563654
Short name T1631
Test name
Test status
Simulation time 12906452531 ps
CPU time 84.32 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:33:27 PM PDT 24
Peak memory 207668 kb
Host smart-3acabbfb-595b-4945-a932-54b92db37f75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3196563654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3196563654
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3647406336
Short name T2905
Test name
Test status
Simulation time 246051979 ps
CPU time 1.05 seconds
Started Aug 09 05:32:08 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207552 kb
Host smart-4ce201f6-133b-40f8-a8be-fdfae486c712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36474
06336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3647406336
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.712990381
Short name T633
Test name
Test status
Simulation time 24617639075 ps
CPU time 40.2 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 216792 kb
Host smart-ac9b2732-32a3-48b4-9142-51047ef6e31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71299
0381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.712990381
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3140965792
Short name T2996
Test name
Test status
Simulation time 10077717267 ps
CPU time 12.35 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207740 kb
Host smart-1414a5f6-2054-4d6c-86de-157bebeb9bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
65792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3140965792
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1228300128
Short name T3078
Test name
Test status
Simulation time 3533557156 ps
CPU time 108.29 seconds
Started Aug 09 05:31:48 PM PDT 24
Finished Aug 09 05:33:36 PM PDT 24
Peak memory 218432 kb
Host smart-b5fddab2-18a7-4370-92c5-0d04e9c4da3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1228300128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1228300128
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.901200931
Short name T2820
Test name
Test status
Simulation time 2714816794 ps
CPU time 20.04 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 207856 kb
Host smart-3513991d-dbc2-4872-9770-eb23f0a2d8f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=901200931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.901200931
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.4268029089
Short name T2086
Test name
Test status
Simulation time 239891690 ps
CPU time 0.95 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207588 kb
Host smart-8840b33b-7550-4ad0-b2cb-e085c0a48789
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4268029089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.4268029089
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3667113714
Short name T991
Test name
Test status
Simulation time 189434807 ps
CPU time 0.91 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:15 PM PDT 24
Peak memory 207460 kb
Host smart-505ce055-4fc8-4094-8ee2-665515cb6651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36671
13714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3667113714
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1855419719
Short name T3048
Test name
Test status
Simulation time 2769282968 ps
CPU time 80.4 seconds
Started Aug 09 05:31:53 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 224120 kb
Host smart-582cc3b4-af08-4968-9129-3c895f8a64b5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1855419719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1855419719
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1572961068
Short name T918
Test name
Test status
Simulation time 180929113 ps
CPU time 0.88 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207376 kb
Host smart-39837f95-4063-4252-a3f9-4306dba496fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1572961068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1572961068
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2097373154
Short name T1216
Test name
Test status
Simulation time 151713808 ps
CPU time 0.89 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207548 kb
Host smart-b17fdb7d-4827-43c4-b338-b57a0a56e227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20973
73154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2097373154
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3069102710
Short name T139
Test name
Test status
Simulation time 196824251 ps
CPU time 0.98 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207556 kb
Host smart-ff87878d-a348-4083-8601-a738ba0e7dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30691
02710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3069102710
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2504145142
Short name T1734
Test name
Test status
Simulation time 174868512 ps
CPU time 0.88 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207472 kb
Host smart-70ab7e7b-011a-49b9-9ddd-12951ab18b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25041
45142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2504145142
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.922929061
Short name T995
Test name
Test status
Simulation time 175200912 ps
CPU time 0.89 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207508 kb
Host smart-8e2bf155-62df-4a7c-8692-b0feee03cc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92292
9061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.922929061
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2166352950
Short name T2659
Test name
Test status
Simulation time 168240390 ps
CPU time 0.91 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207504 kb
Host smart-9c347e65-8c6a-4c93-b198-a2b1e1724b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
52950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2166352950
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.25203376
Short name T1584
Test name
Test status
Simulation time 155412666 ps
CPU time 0.93 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207528 kb
Host smart-7402f1a0-831e-42e5-a66f-b62d3bb24419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25203
376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.25203376
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3431757362
Short name T2310
Test name
Test status
Simulation time 233529048 ps
CPU time 1.04 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207540 kb
Host smart-fd957c60-7858-412a-9b97-29d7199535ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3431757362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3431757362
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3174546534
Short name T2459
Test name
Test status
Simulation time 169301701 ps
CPU time 0.84 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207328 kb
Host smart-5756d3b4-7b9f-4c8c-ac24-1e80f98b6a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
46534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3174546534
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1428789583
Short name T1417
Test name
Test status
Simulation time 86737881 ps
CPU time 0.76 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207516 kb
Host smart-b4486388-d4b7-47ea-8cf4-4b9b46607cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287
89583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1428789583
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3994847238
Short name T3557
Test name
Test status
Simulation time 17922393733 ps
CPU time 42.8 seconds
Started Aug 09 05:31:54 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 214996 kb
Host smart-dc4fc918-3ba3-43da-af28-c6c763d826be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
47238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3994847238
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1958427654
Short name T2100
Test name
Test status
Simulation time 184834944 ps
CPU time 0.91 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207476 kb
Host smart-d2b68721-777a-42ad-80fe-87ef36083d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19584
27654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1958427654
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2128296491
Short name T2925
Test name
Test status
Simulation time 227590232 ps
CPU time 0.96 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207528 kb
Host smart-29c9263f-c06c-4ca5-b4c4-3690bf386a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21282
96491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2128296491
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.16622256
Short name T866
Test name
Test status
Simulation time 161258865 ps
CPU time 0.92 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207520 kb
Host smart-7651304d-5c13-407d-b0ca-198ec9b4073f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16622
256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.16622256
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2986281317
Short name T1757
Test name
Test status
Simulation time 182664049 ps
CPU time 0.94 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207524 kb
Host smart-ad03d41d-d2b9-41dc-adee-d626dcc57137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29862
81317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2986281317
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.709343964
Short name T2473
Test name
Test status
Simulation time 159360249 ps
CPU time 0.83 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207424 kb
Host smart-aebbe716-5a25-4b47-86c6-7c84856aa268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70934
3964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.709343964
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.2969800813
Short name T1492
Test name
Test status
Simulation time 333922387 ps
CPU time 1.25 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207388 kb
Host smart-0e9bdeb8-9c10-4124-b264-6ab3017b968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
00813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.2969800813
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.630026154
Short name T161
Test name
Test status
Simulation time 176739155 ps
CPU time 0.83 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 207424 kb
Host smart-b213d134-e0d2-4b8d-9346-1849fc3f46da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63002
6154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.630026154
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.206687584
Short name T2210
Test name
Test status
Simulation time 212073401 ps
CPU time 0.92 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207440 kb
Host smart-5839585c-1f4e-48b4-a4ac-7283d5ae9876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
7584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.206687584
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3645037208
Short name T1463
Test name
Test status
Simulation time 228698068 ps
CPU time 1.06 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207476 kb
Host smart-40cad92b-91a9-48ad-a3cb-799d3af01820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450
37208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3645037208
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.855175997
Short name T2001
Test name
Test status
Simulation time 3524429813 ps
CPU time 104.96 seconds
Started Aug 09 05:32:01 PM PDT 24
Finished Aug 09 05:33:46 PM PDT 24
Peak memory 216048 kb
Host smart-5c6ae4e8-8efe-4dcb-a2fa-f9cf3129ee63
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=855175997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.855175997
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3750101087
Short name T2732
Test name
Test status
Simulation time 194184152 ps
CPU time 0.96 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207380 kb
Host smart-2212aba4-470f-4df4-ab14-e68912698d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37501
01087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3750101087
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3796195856
Short name T1063
Test name
Test status
Simulation time 214091521 ps
CPU time 0.95 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207528 kb
Host smart-ed69cd91-bd74-4a9d-81de-fe4999b4e5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37961
95856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3796195856
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2594280905
Short name T682
Test name
Test status
Simulation time 858551777 ps
CPU time 2.08 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207504 kb
Host smart-3671f517-efda-46be-a374-23408c035d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25942
80905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2594280905
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.4166233944
Short name T221
Test name
Test status
Simulation time 2387042716 ps
CPU time 17.42 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207812 kb
Host smart-5ef8a477-646d-4cee-845f-c461f6f93e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41662
33944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.4166233944
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.3573365763
Short name T1672
Test name
Test status
Simulation time 198359578 ps
CPU time 0.89 seconds
Started Aug 09 05:31:49 PM PDT 24
Finished Aug 09 05:31:50 PM PDT 24
Peak memory 207480 kb
Host smart-dc0af5b9-83d4-4d16-8061-f0833f24565f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573365763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.3573365763
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.4252836203
Short name T3377
Test name
Test status
Simulation time 468984213 ps
CPU time 1.49 seconds
Started Aug 09 05:31:46 PM PDT 24
Finished Aug 09 05:31:47 PM PDT 24
Peak memory 207452 kb
Host smart-a200082f-228a-47c8-bd39-d9b39ec54308
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252836203 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.4252836203
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.896284759
Short name T3393
Test name
Test status
Simulation time 489441847 ps
CPU time 1.51 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207448 kb
Host smart-7dc5aeb9-4e0f-4781-9725-876e5ffd701d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896284759 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.896284759
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.210952374
Short name T3355
Test name
Test status
Simulation time 584514895 ps
CPU time 1.58 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:17 PM PDT 24
Peak memory 207504 kb
Host smart-877c5e33-5ab2-4c73-b5c2-32a7cfee69e6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210952374 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.210952374
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.4257284353
Short name T155
Test name
Test status
Simulation time 563522494 ps
CPU time 1.61 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207516 kb
Host smart-b892edc5-37b1-439f-b4c8-809ddc2945dc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257284353 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.4257284353
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.2564397626
Short name T2627
Test name
Test status
Simulation time 531273804 ps
CPU time 1.58 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207552 kb
Host smart-a3704a64-3c11-420b-9e6c-a8b4717c762a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564397626 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.2564397626
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.1897639864
Short name T3122
Test name
Test status
Simulation time 549936366 ps
CPU time 1.62 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207412 kb
Host smart-87a72d8d-f438-4279-a9f2-7d1293482011
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897639864 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.1897639864
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.857951548
Short name T753
Test name
Test status
Simulation time 558658705 ps
CPU time 1.65 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207464 kb
Host smart-5f27c5c9-085b-4296-8fde-11b5e06610d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857951548 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.857951548
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.395933453
Short name T1071
Test name
Test status
Simulation time 548423603 ps
CPU time 1.65 seconds
Started Aug 09 05:33:50 PM PDT 24
Finished Aug 09 05:33:52 PM PDT 24
Peak memory 207560 kb
Host smart-54fb921f-f290-4696-86c3-588a4a5b41bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395933453 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.395933453
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.2352700138
Short name T1018
Test name
Test status
Simulation time 456447892 ps
CPU time 1.38 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207380 kb
Host smart-89586556-7b49-4647-8e56-4fd464d98c3c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352700138 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.2352700138
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.1006539400
Short name T2283
Test name
Test status
Simulation time 486295932 ps
CPU time 1.47 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 207440 kb
Host smart-fc1aaa10-c9ad-4d6b-a1e8-f7f48947b399
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006539400 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.1006539400
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.4015623106
Short name T2894
Test name
Test status
Simulation time 570416236 ps
CPU time 1.56 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207416 kb
Host smart-3a068d4e-2b89-4b25-b387-facb3c203868
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015623106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.4015623106
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.559484026
Short name T1553
Test name
Test status
Simulation time 90756306 ps
CPU time 0.72 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207556 kb
Host smart-6fa51241-2648-4650-9386-055dde20a5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=559484026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.559484026
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3135907518
Short name T2347
Test name
Test status
Simulation time 9567134004 ps
CPU time 14.42 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:14 PM PDT 24
Peak memory 208060 kb
Host smart-8a75e493-8fa3-44fd-8063-6b2df175f505
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135907518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.3135907518
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3578212997
Short name T2539
Test name
Test status
Simulation time 15827098497 ps
CPU time 19.04 seconds
Started Aug 09 05:31:50 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 216016 kb
Host smart-90ddcf09-75a8-4178-a369-46103a9ba40d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578212997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3578212997
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3611150262
Short name T7
Test name
Test status
Simulation time 28833856264 ps
CPU time 35.15 seconds
Started Aug 09 05:32:17 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207756 kb
Host smart-55f7d6e5-2d2c-41ea-a98d-969ec2d06199
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611150262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.3611150262
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4262910631
Short name T1395
Test name
Test status
Simulation time 181243746 ps
CPU time 0.94 seconds
Started Aug 09 05:32:00 PM PDT 24
Finished Aug 09 05:32:01 PM PDT 24
Peak memory 207772 kb
Host smart-dc1145d9-157c-4b85-bd98-fd8fb6d77357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
10631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4262910631
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1608324062
Short name T2016
Test name
Test status
Simulation time 146317552 ps
CPU time 0.82 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207444 kb
Host smart-50f0d2e8-1163-4c55-b278-b81dcc262463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
24062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1608324062
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2719353070
Short name T1767
Test name
Test status
Simulation time 288557056 ps
CPU time 1.23 seconds
Started Aug 09 05:32:01 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 207500 kb
Host smart-073e8443-a538-4f0f-98cc-014b3f644b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
53070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2719353070
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.346653923
Short name T311
Test name
Test status
Simulation time 1022965669 ps
CPU time 2.57 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:59 PM PDT 24
Peak memory 207568 kb
Host smart-ebf18e40-0c88-4c6e-aa9a-491fae79f856
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=346653923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.346653923
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.642060394
Short name T420
Test name
Test status
Simulation time 24883639838 ps
CPU time 37.61 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207724 kb
Host smart-fbe58de1-8fb8-432e-94ed-634851f4f9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64206
0394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.642060394
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.1786801560
Short name T969
Test name
Test status
Simulation time 5665984552 ps
CPU time 35.85 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207776 kb
Host smart-2baf4d78-fe72-438d-bf57-fb2538522a6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786801560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1786801560
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.1610613986
Short name T2412
Test name
Test status
Simulation time 789272549 ps
CPU time 1.82 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207376 kb
Host smart-63d9154a-d36f-4fc1-9cf2-252d5b948011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16106
13986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1610613986
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3861206100
Short name T1886
Test name
Test status
Simulation time 142647367 ps
CPU time 0.84 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207452 kb
Host smart-5b9d229f-e650-4a6b-993d-e5322377ad48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
06100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3861206100
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3463774328
Short name T2814
Test name
Test status
Simulation time 41307632 ps
CPU time 0.72 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207440 kb
Host smart-50b61fc1-56bf-4a0c-8cd6-98a6fb7b6954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
74328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3463774328
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2472202455
Short name T754
Test name
Test status
Simulation time 956028675 ps
CPU time 2.53 seconds
Started Aug 09 05:31:54 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207660 kb
Host smart-ff73ab87-5451-4ed6-b4cc-89ab54ecbc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
02455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2472202455
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.977279580
Short name T457
Test name
Test status
Simulation time 702295206 ps
CPU time 1.65 seconds
Started Aug 09 05:31:55 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207436 kb
Host smart-7f156499-3f2a-4d50-a724-99b653d8f495
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=977279580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.977279580
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3267236370
Short name T1239
Test name
Test status
Simulation time 200931298 ps
CPU time 2.02 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 207620 kb
Host smart-c052a1bb-ad2d-4be4-a9a3-163edd4e2a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672
36370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3267236370
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3667246379
Short name T1082
Test name
Test status
Simulation time 181995819 ps
CPU time 1.02 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:31:58 PM PDT 24
Peak memory 215880 kb
Host smart-d26bf866-4252-4124-ada7-3708113941a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3667246379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3667246379
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3767318857
Short name T2222
Test name
Test status
Simulation time 141935500 ps
CPU time 0.89 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207468 kb
Host smart-cbb9877b-ed47-49d1-a2a5-c2422ce2e794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
18857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3767318857
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.543357260
Short name T1952
Test name
Test status
Simulation time 160978454 ps
CPU time 0.92 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207552 kb
Host smart-fa085a74-1fc6-4f44-8c10-0c2503d68c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54335
7260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.543357260
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3166444666
Short name T1496
Test name
Test status
Simulation time 5340719173 ps
CPU time 158.88 seconds
Started Aug 09 05:31:57 PM PDT 24
Finished Aug 09 05:34:36 PM PDT 24
Peak memory 218384 kb
Host smart-2918cd09-b49c-44c1-b876-238bf55f29de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3166444666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3166444666
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1467848712
Short name T1004
Test name
Test status
Simulation time 13626572978 ps
CPU time 88.37 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:33:34 PM PDT 24
Peak memory 207756 kb
Host smart-b8ddb2e2-ae37-460d-9c76-6f6f2d9b8949
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1467848712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1467848712
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3918903372
Short name T1067
Test name
Test status
Simulation time 191067002 ps
CPU time 0.9 seconds
Started Aug 09 05:31:58 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207376 kb
Host smart-aaffdc06-d468-4b18-9d60-fcc6ba7ba500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39189
03372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3918903372
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2032676237
Short name T1530
Test name
Test status
Simulation time 29400574037 ps
CPU time 45.24 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 216084 kb
Host smart-4ee876a7-9a2e-4237-a313-4fc4506dd817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
76237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2032676237
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.4222598355
Short name T786
Test name
Test status
Simulation time 4509430052 ps
CPU time 6.15 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 216124 kb
Host smart-1bd98985-f50f-4371-ad11-4b2ae6a3c9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42225
98355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4222598355
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2370139877
Short name T727
Test name
Test status
Simulation time 4597563866 ps
CPU time 34.04 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 219504 kb
Host smart-b7ee800e-a6cd-4111-93f1-0f0ea7d6ed37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2370139877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2370139877
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1505489624
Short name T882
Test name
Test status
Simulation time 2436774749 ps
CPU time 20.33 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 224260 kb
Host smart-b32baa68-344e-49c1-93de-f65c3e80247b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1505489624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1505489624
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.337482200
Short name T257
Test name
Test status
Simulation time 238840682 ps
CPU time 1.01 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207460 kb
Host smart-83d5478d-4a0f-436d-b374-14b1de46ebd5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=337482200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.337482200
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3887462403
Short name T1065
Test name
Test status
Simulation time 189888985 ps
CPU time 0.91 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:32:21 PM PDT 24
Peak memory 207472 kb
Host smart-4c5cfc6f-653b-4c08-9d2d-30cf0702b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
62403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3887462403
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.614389027
Short name T2988
Test name
Test status
Simulation time 1955381913 ps
CPU time 52.71 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 223940 kb
Host smart-4ebfb967-b37e-405f-9270-60aead796da3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=614389027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.614389027
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2103231507
Short name T3083
Test name
Test status
Simulation time 155219333 ps
CPU time 0.83 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207504 kb
Host smart-97534c29-b3cc-461f-9134-f3c9f70c7296
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2103231507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2103231507
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.412464436
Short name T1313
Test name
Test status
Simulation time 174015369 ps
CPU time 0.89 seconds
Started Aug 09 05:32:01 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 207556 kb
Host smart-7d6119d3-28a1-4b26-86ed-6ac162718efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41246
4436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.412464436
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2318936330
Short name T140
Test name
Test status
Simulation time 207035172 ps
CPU time 0.99 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 206612 kb
Host smart-145b5dde-56f4-4096-aa1e-d21b38737697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23189
36330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2318936330
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1612670937
Short name T3520
Test name
Test status
Simulation time 186831539 ps
CPU time 0.89 seconds
Started Aug 09 05:32:01 PM PDT 24
Finished Aug 09 05:32:02 PM PDT 24
Peak memory 207552 kb
Host smart-fb2d73a0-7e8c-4602-a6b3-bdc1c5423f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
70937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1612670937
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2686330426
Short name T1868
Test name
Test status
Simulation time 159040591 ps
CPU time 0.85 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207432 kb
Host smart-c8f37c59-b5a2-46fe-8910-ff38164c1775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863
30426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2686330426
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3584968963
Short name T847
Test name
Test status
Simulation time 192114417 ps
CPU time 0.87 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207436 kb
Host smart-56d55ece-70f8-4df2-9217-0eaee59a2b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35849
68963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3584968963
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1295092682
Short name T2885
Test name
Test status
Simulation time 154338819 ps
CPU time 0.85 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207504 kb
Host smart-2cb3b1c0-2fdd-4303-bdf4-efb6466f1823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
92682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1295092682
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.828588052
Short name T605
Test name
Test status
Simulation time 232140585 ps
CPU time 0.97 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207428 kb
Host smart-b321c264-68d9-405b-8154-2d3b7127f2d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=828588052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.828588052
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3766461268
Short name T3553
Test name
Test status
Simulation time 193623676 ps
CPU time 0.89 seconds
Started Aug 09 05:31:59 PM PDT 24
Finished Aug 09 05:32:00 PM PDT 24
Peak memory 207376 kb
Host smart-f7b4569b-5c51-4b21-9fb5-16c49cda34b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37664
61268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3766461268
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.981956540
Short name T2649
Test name
Test status
Simulation time 44360704 ps
CPU time 0.72 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207476 kb
Host smart-1cf93d82-2816-4eb2-92ae-80579f445f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98195
6540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.981956540
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2255060158
Short name T2503
Test name
Test status
Simulation time 15990688119 ps
CPU time 44.68 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 216044 kb
Host smart-060801a1-6551-42dc-9fdd-31d75f05cb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
60158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2255060158
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1297147778
Short name T84
Test name
Test status
Simulation time 188338465 ps
CPU time 0.91 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207512 kb
Host smart-72ad2aa0-32db-4a33-bffa-e80fab408037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
47778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1297147778
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.429724147
Short name T3271
Test name
Test status
Simulation time 246205585 ps
CPU time 0.99 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207500 kb
Host smart-2b15cc87-fea2-4488-a90d-2a53853819ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42972
4147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.429724147
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.124646057
Short name T323
Test name
Test status
Simulation time 224347315 ps
CPU time 1.04 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207508 kb
Host smart-47028b24-967c-43e8-8e03-ea679fdd7d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
6057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.124646057
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.48176091
Short name T2487
Test name
Test status
Simulation time 187853351 ps
CPU time 0.98 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207496 kb
Host smart-59c2242c-970b-45df-ac2d-0558bde7d161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48176
091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.48176091
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.125160057
Short name T2020
Test name
Test status
Simulation time 185171142 ps
CPU time 0.88 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207560 kb
Host smart-19dab381-f009-4bca-bc14-456505a50664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12516
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.125160057
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.1270144289
Short name T861
Test name
Test status
Simulation time 391763525 ps
CPU time 1.36 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:03 PM PDT 24
Peak memory 207784 kb
Host smart-c911e81b-ca4a-4905-8b10-d86ac51c8261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
44289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.1270144289
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2263609114
Short name T745
Test name
Test status
Simulation time 154164493 ps
CPU time 0.87 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207360 kb
Host smart-7f940402-4f6a-4f86-8fb9-3a7ef9434653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
09114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2263609114
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.563949863
Short name T2871
Test name
Test status
Simulation time 151698736 ps
CPU time 0.93 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207504 kb
Host smart-5dff0fe0-90ab-4e59-978e-54e02dd6bb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56394
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.563949863
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3915399210
Short name T567
Test name
Test status
Simulation time 226813799 ps
CPU time 1.06 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207492 kb
Host smart-f2108582-408e-4268-87ce-5a399ba14080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39153
99210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3915399210
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3599118436
Short name T3489
Test name
Test status
Simulation time 1622414422 ps
CPU time 44.35 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 217348 kb
Host smart-a224be64-9c1b-4ec3-b6f9-ef20a52a5b6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3599118436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3599118436
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1335132137
Short name T1873
Test name
Test status
Simulation time 180504629 ps
CPU time 0.88 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207548 kb
Host smart-4df8a2dd-9e59-4883-9210-531ca0068166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
32137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1335132137
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3472786195
Short name T1622
Test name
Test status
Simulation time 173903692 ps
CPU time 0.9 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207432 kb
Host smart-992054d1-ba1e-4e3b-8f9e-01848abf6036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34727
86195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3472786195
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2362547097
Short name T1305
Test name
Test status
Simulation time 833860344 ps
CPU time 2.2 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207520 kb
Host smart-19f32a59-973c-44c5-9074-5182f8c25327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
47097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2362547097
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.29805019
Short name T909
Test name
Test status
Simulation time 2493736828 ps
CPU time 72.49 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:33:20 PM PDT 24
Peak memory 217580 kb
Host smart-a38d89a0-cac7-484c-8226-84680e584e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29805
019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.29805019
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.30883500
Short name T2774
Test name
Test status
Simulation time 1559954548 ps
CPU time 13.23 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207588 kb
Host smart-b9333310-37e4-4543-881f-6ad980e8aa67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30883500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host_
handshake.30883500
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.3439983268
Short name T2603
Test name
Test status
Simulation time 521592786 ps
CPU time 1.67 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207508 kb
Host smart-bb720ca1-8d17-44ae-b00c-9b5e56aeabce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439983268 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.3439983268
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.1772849403
Short name T192
Test name
Test status
Simulation time 539878868 ps
CPU time 1.59 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207440 kb
Host smart-5181c8c0-df0d-4b73-9bfa-3aebab9e3c64
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772849403 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.1772849403
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.308440688
Short name T1411
Test name
Test status
Simulation time 611713656 ps
CPU time 1.62 seconds
Started Aug 09 05:33:51 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 207500 kb
Host smart-32e661b8-079a-426b-bba9-f2b141d79418
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308440688 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.308440688
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.3674768314
Short name T27
Test name
Test status
Simulation time 629129685 ps
CPU time 1.94 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207444 kb
Host smart-045a55e9-8022-4fa4-a7d5-60778e38d1f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674768314 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.3674768314
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.2960791102
Short name T2382
Test name
Test status
Simulation time 517043466 ps
CPU time 1.54 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 207464 kb
Host smart-d7b766b3-b118-484d-a18e-1420e70f2fd2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960791102 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.2960791102
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.998267586
Short name T1921
Test name
Test status
Simulation time 459361292 ps
CPU time 1.51 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 207492 kb
Host smart-a3ef8285-66bd-490d-8eab-845af01d0a48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998267586 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.998267586
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.653735602
Short name T2936
Test name
Test status
Simulation time 550352901 ps
CPU time 1.52 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 207536 kb
Host smart-eb7b2c47-4cc8-4cb5-a6fb-f41ce3f785b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653735602 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.653735602
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.714622645
Short name T3060
Test name
Test status
Simulation time 530974223 ps
CPU time 1.61 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 207452 kb
Host smart-6615a604-a69e-4a09-b2cb-c6739149a14f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714622645 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.714622645
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.1293730343
Short name T3121
Test name
Test status
Simulation time 529370265 ps
CPU time 1.77 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207440 kb
Host smart-25ef2672-2250-4c29-89dc-c98935e825c3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293730343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.1293730343
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.3737561376
Short name T725
Test name
Test status
Simulation time 582390203 ps
CPU time 1.7 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 207496 kb
Host smart-047ffc7d-da9d-4c3a-9c21-da5884cbc7b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737561376 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.3737561376
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.443348563
Short name T1208
Test name
Test status
Simulation time 640026640 ps
CPU time 1.6 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207480 kb
Host smart-6a8e5eff-26b9-4208-9c00-92620032e724
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443348563 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.443348563
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.512298637
Short name T1880
Test name
Test status
Simulation time 95397424 ps
CPU time 0.73 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207524 kb
Host smart-06408735-25e6-4c38-85e8-39fcc89dfd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=512298637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.512298637
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.172959139
Short name T1264
Test name
Test status
Simulation time 21426515958 ps
CPU time 25.19 seconds
Started Aug 09 05:32:02 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207732 kb
Host smart-a9d906e1-a86e-4c63-8d31-6002c9aab360
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=172959139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.172959139
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1975150048
Short name T3567
Test name
Test status
Simulation time 23899125344 ps
CPU time 31.41 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 215952 kb
Host smart-5c674337-6184-42d6-87ce-7c9e00939488
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975150048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1975150048
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.291754430
Short name T3107
Test name
Test status
Simulation time 205160695 ps
CPU time 0.97 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207532 kb
Host smart-dc137bb6-e920-4509-a4dc-1bbf54195a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
4430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.291754430
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.463544677
Short name T2676
Test name
Test status
Simulation time 157869857 ps
CPU time 0.87 seconds
Started Aug 09 05:31:56 PM PDT 24
Finished Aug 09 05:31:57 PM PDT 24
Peak memory 207368 kb
Host smart-d5504724-f06d-4b57-9c93-83bc4c34ca46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46354
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.463544677
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3161491513
Short name T1457
Test name
Test status
Simulation time 554921551 ps
CPU time 1.76 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207556 kb
Host smart-624865a9-9c7b-4827-9a11-b9c73685da5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
91513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3161491513
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2863125689
Short name T3293
Test name
Test status
Simulation time 320927527 ps
CPU time 1.12 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207504 kb
Host smart-b6a00652-e3eb-4252-8dc1-de435d386728
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2863125689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2863125689
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.265410828
Short name T1590
Test name
Test status
Simulation time 29182837868 ps
CPU time 46.82 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207736 kb
Host smart-9ee16033-91b5-4ffd-baf7-c5600ed09a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26541
0828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.265410828
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.3000233406
Short name T1073
Test name
Test status
Simulation time 620939652 ps
CPU time 11.22 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:20 PM PDT 24
Peak memory 207608 kb
Host smart-35bf6176-7c1e-4e67-ab0f-2f58db21360d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000233406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3000233406
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2633232527
Short name T1307
Test name
Test status
Simulation time 947754750 ps
CPU time 2.4 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207380 kb
Host smart-3ee2ecac-5a31-4a3a-9433-72302aec1385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
32527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2633232527
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2745758829
Short name T1049
Test name
Test status
Simulation time 145739774 ps
CPU time 0.84 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207556 kb
Host smart-ae727cd2-363a-45cd-ac41-ba287fa32639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
58829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2745758829
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2518538773
Short name T3530
Test name
Test status
Simulation time 38345477 ps
CPU time 0.68 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207528 kb
Host smart-5d6e035b-2768-4fef-9298-310828963a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
38773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2518538773
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2660474540
Short name T2796
Test name
Test status
Simulation time 997668067 ps
CPU time 2.5 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207968 kb
Host smart-6628b123-8e03-48db-aa94-2a5c42f5e9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
74540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2660474540
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2458831302
Short name T1316
Test name
Test status
Simulation time 184673590 ps
CPU time 2.14 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207676 kb
Host smart-0a36eec3-0d61-4fb2-bf7e-a1e8bca4fd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
31302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2458831302
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3110240690
Short name T1279
Test name
Test status
Simulation time 164551152 ps
CPU time 0.91 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207524 kb
Host smart-129d5336-d95e-480a-8431-1ad64b32fc9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3110240690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3110240690
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1627159005
Short name T3611
Test name
Test status
Simulation time 141763648 ps
CPU time 0.86 seconds
Started Aug 09 05:32:04 PM PDT 24
Finished Aug 09 05:32:05 PM PDT 24
Peak memory 207440 kb
Host smart-2bf6e6b9-a449-43f8-8843-7977eed8963c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
59005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1627159005
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1876654839
Short name T3430
Test name
Test status
Simulation time 174165443 ps
CPU time 0.97 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207556 kb
Host smart-2d93b132-0887-4f14-9f53-e1d393ceac45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
54839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1876654839
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.2604131974
Short name T1434
Test name
Test status
Simulation time 3950907321 ps
CPU time 36.78 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 218064 kb
Host smart-788eea10-43da-4c8d-a40d-3563a970d472
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2604131974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2604131974
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.465800091
Short name T2066
Test name
Test status
Simulation time 9877556403 ps
CPU time 122.6 seconds
Started Aug 09 05:32:19 PM PDT 24
Finished Aug 09 05:34:22 PM PDT 24
Peak memory 207752 kb
Host smart-501d3e84-9295-4af9-9ac5-b65697718e6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=465800091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.465800091
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2804779461
Short name T1865
Test name
Test status
Simulation time 196956565 ps
CPU time 0.96 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207444 kb
Host smart-b69a7ab6-fe42-4c4d-a27d-9cbc022f1299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28047
79461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2804779461
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.4153005388
Short name T1658
Test name
Test status
Simulation time 31388603485 ps
CPU time 51.09 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207848 kb
Host smart-3fd64796-6a9d-4c11-8c6d-cbb9995377c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
05388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.4153005388
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2152429539
Short name T1923
Test name
Test status
Simulation time 10620477982 ps
CPU time 12.73 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:20 PM PDT 24
Peak memory 207792 kb
Host smart-a86f2048-a8c5-4779-ad24-cf10eae84b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21524
29539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2152429539
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.565733996
Short name T1258
Test name
Test status
Simulation time 3782105009 ps
CPU time 38.77 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 218824 kb
Host smart-6bf003b7-b84b-49d0-b9cf-a4edc9ac9e73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=565733996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.565733996
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.564404121
Short name T546
Test name
Test status
Simulation time 2870431468 ps
CPU time 22.63 seconds
Started Aug 09 05:32:13 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 216084 kb
Host smart-5482d840-5625-49cc-9c9e-7d6ba0fb5ac7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=564404121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.564404121
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2649512006
Short name T2937
Test name
Test status
Simulation time 244961982 ps
CPU time 0.99 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:08 PM PDT 24
Peak memory 207496 kb
Host smart-d948f5c7-d45d-403d-9cf6-f0c3bc4a269e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2649512006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2649512006
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3624508950
Short name T3311
Test name
Test status
Simulation time 195425700 ps
CPU time 0.92 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207508 kb
Host smart-cd8a0a5b-295c-4f1a-ad62-c4764d846934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
08950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3624508950
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1768257272
Short name T556
Test name
Test status
Simulation time 3949032397 ps
CPU time 112.24 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 217484 kb
Host smart-db640e6b-91aa-4492-aecd-410da029505d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1768257272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1768257272
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3495282479
Short name T942
Test name
Test status
Simulation time 168201627 ps
CPU time 0.97 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207468 kb
Host smart-f42c647f-8b8a-4c0a-aae7-e413384f90c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3495282479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3495282479
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3352801470
Short name T610
Test name
Test status
Simulation time 160594553 ps
CPU time 0.88 seconds
Started Aug 09 05:32:05 PM PDT 24
Finished Aug 09 05:32:06 PM PDT 24
Peak memory 207504 kb
Host smart-d1b5e55f-ab6d-447f-a553-ec0b6d7466dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
01470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3352801470
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1787552375
Short name T122
Test name
Test status
Simulation time 229833718 ps
CPU time 0.94 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207384 kb
Host smart-5fe2c84a-1f2b-42b4-9033-3d26b60c7d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
52375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1787552375
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.11243379
Short name T3382
Test name
Test status
Simulation time 163519665 ps
CPU time 0.83 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:12 PM PDT 24
Peak memory 207436 kb
Host smart-b30ef8c6-b712-4605-a024-83e93739ea51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11243
379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.11243379
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1821748199
Short name T492
Test name
Test status
Simulation time 194296306 ps
CPU time 0.89 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207428 kb
Host smart-7e79a226-4ad2-4df6-8d80-feaf8894728c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
48199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1821748199
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3094491701
Short name T1373
Test name
Test status
Simulation time 202702484 ps
CPU time 0.96 seconds
Started Aug 09 05:32:08 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207508 kb
Host smart-1f8ffc74-3ff2-4c8e-abb8-f2f9205cea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
91701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3094491701
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2364160577
Short name T2909
Test name
Test status
Simulation time 164708090 ps
CPU time 0.89 seconds
Started Aug 09 05:32:08 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207428 kb
Host smart-63323e76-0f10-4a4b-a4aa-e2d445021086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23641
60577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2364160577
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.977428788
Short name T2145
Test name
Test status
Simulation time 221311222 ps
CPU time 1.02 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:23 PM PDT 24
Peak memory 207568 kb
Host smart-736937bd-3d37-4cf6-a5b3-7ef1755cdce9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=977428788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.977428788
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2357306398
Short name T3496
Test name
Test status
Simulation time 158491621 ps
CPU time 0.83 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207484 kb
Host smart-38d20b8d-3869-40e2-b1cf-5ab6f5969521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23573
06398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2357306398
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3009250363
Short name T1997
Test name
Test status
Simulation time 42583313 ps
CPU time 0.72 seconds
Started Aug 09 05:32:21 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207756 kb
Host smart-c8fd15cb-b459-4896-a2ec-40ec9fb8e436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30092
50363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3009250363
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2500058242
Short name T2147
Test name
Test status
Simulation time 9446509094 ps
CPU time 25.68 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 216080 kb
Host smart-802b3c77-566e-4afb-85f7-dad88fe0e4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
58242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2500058242
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2758682458
Short name T2882
Test name
Test status
Simulation time 183536871 ps
CPU time 0.95 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:12 PM PDT 24
Peak memory 207384 kb
Host smart-1f85c94a-639e-47a8-a79e-0a8c7ba0e46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27586
82458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2758682458
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1464361576
Short name T2785
Test name
Test status
Simulation time 184174568 ps
CPU time 0.89 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207500 kb
Host smart-d594fbed-6a80-4d79-b9f6-fb5321dff212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
61576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1464361576
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.186631568
Short name T542
Test name
Test status
Simulation time 160347298 ps
CPU time 0.95 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:07 PM PDT 24
Peak memory 207556 kb
Host smart-1d812416-34df-4f0d-b688-1d7cd4a11041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18663
1568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.186631568
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2928784867
Short name T1443
Test name
Test status
Simulation time 220532327 ps
CPU time 0.99 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207512 kb
Host smart-82803cd0-c8af-400f-86ed-bde59b5e7016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29287
84867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2928784867
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3913044430
Short name T2683
Test name
Test status
Simulation time 172455974 ps
CPU time 0.85 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207380 kb
Host smart-0fe6330b-551a-4b32-8d1d-79e7690f7252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
44430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3913044430
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.3259751233
Short name T2702
Test name
Test status
Simulation time 387266150 ps
CPU time 1.32 seconds
Started Aug 09 05:32:18 PM PDT 24
Finished Aug 09 05:32:19 PM PDT 24
Peak memory 207428 kb
Host smart-dc8a4287-c17d-497e-a5e2-7ceebe5a3ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
51233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.3259751233
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.615694431
Short name T3573
Test name
Test status
Simulation time 164043637 ps
CPU time 0.82 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207472 kb
Host smart-bc036038-056b-4587-9e65-30d246fa3c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61569
4431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.615694431
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2829745153
Short name T2336
Test name
Test status
Simulation time 154845758 ps
CPU time 0.87 seconds
Started Aug 09 05:32:03 PM PDT 24
Finished Aug 09 05:32:04 PM PDT 24
Peak memory 207456 kb
Host smart-f951d7ab-ef16-4ea4-8267-122c5dd3fdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
45153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2829745153
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.4001244135
Short name T3312
Test name
Test status
Simulation time 216157031 ps
CPU time 1.09 seconds
Started Aug 09 05:32:17 PM PDT 24
Finished Aug 09 05:32:18 PM PDT 24
Peak memory 207512 kb
Host smart-5b4cfec5-6b5f-4834-a61d-45856035807b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40012
44135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.4001244135
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3294247771
Short name T635
Test name
Test status
Simulation time 2390584898 ps
CPU time 22.87 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 215916 kb
Host smart-176ab948-cdaa-4655-92a8-c525586305c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3294247771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3294247771
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3909876521
Short name T3468
Test name
Test status
Simulation time 163675413 ps
CPU time 0.82 seconds
Started Aug 09 05:32:19 PM PDT 24
Finished Aug 09 05:32:20 PM PDT 24
Peak memory 207472 kb
Host smart-9dcb96e4-1d0e-42c7-beb5-11b76cb77b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
76521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3909876521
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4201548909
Short name T892
Test name
Test status
Simulation time 176351663 ps
CPU time 0.87 seconds
Started Aug 09 05:32:10 PM PDT 24
Finished Aug 09 05:32:11 PM PDT 24
Peak memory 207440 kb
Host smart-451ee866-53d2-4d0d-8108-55d96e0b43f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
48909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4201548909
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.782683260
Short name T2071
Test name
Test status
Simulation time 1106955644 ps
CPU time 2.83 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207684 kb
Host smart-0a42d245-3cc7-495f-9e77-097b3d92a71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78268
3260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.782683260
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.115950647
Short name T2244
Test name
Test status
Simulation time 1684929501 ps
CPU time 47.19 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 217444 kb
Host smart-c500a55a-6b05-4c37-b125-517234b30fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595
0647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.115950647
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.1861812178
Short name T711
Test name
Test status
Simulation time 1271556991 ps
CPU time 30.62 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207984 kb
Host smart-5b47174d-2327-4f72-9c23-97abb7019182
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861812178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.1861812178
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.1719051397
Short name T2360
Test name
Test status
Simulation time 598625493 ps
CPU time 1.67 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 207556 kb
Host smart-9a4a610b-a9b4-481b-a5b0-f288b686ed96
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719051397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.1719051397
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.660787921
Short name T1799
Test name
Test status
Simulation time 592408360 ps
CPU time 1.54 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207428 kb
Host smart-0e53abd4-2fde-4d14-87ad-3d7f8b0a2df6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660787921 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.660787921
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.1215576806
Short name T2949
Test name
Test status
Simulation time 485429646 ps
CPU time 1.46 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 207564 kb
Host smart-143f3fff-0e5f-4fb8-a9cd-a69503507ff6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215576806 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.1215576806
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.1271501182
Short name T3485
Test name
Test status
Simulation time 508801249 ps
CPU time 1.6 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207432 kb
Host smart-7431873f-0eaf-47ee-a72d-cff7776a291b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271501182 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.1271501182
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.4147120931
Short name T1170
Test name
Test status
Simulation time 586977637 ps
CPU time 1.68 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:51 PM PDT 24
Peak memory 207484 kb
Host smart-85581965-edf8-4b0f-98e4-1262e03f5b48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147120931 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.4147120931
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.2600123884
Short name T2330
Test name
Test status
Simulation time 450950644 ps
CPU time 1.41 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207476 kb
Host smart-952500d5-687c-4db9-9e81-4754515ae3b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600123884 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.2600123884
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.3045847248
Short name T2036
Test name
Test status
Simulation time 517188541 ps
CPU time 1.55 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207412 kb
Host smart-cddfb0b2-42e6-4a87-ad1f-83afe5267efb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045847248 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.3045847248
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.3706904269
Short name T3602
Test name
Test status
Simulation time 504964270 ps
CPU time 1.46 seconds
Started Aug 09 05:33:49 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207436 kb
Host smart-0e2476f0-0065-49dd-90ee-44a3d9bab787
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706904269 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.3706904269
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.2673234496
Short name T2618
Test name
Test status
Simulation time 597174224 ps
CPU time 1.58 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207552 kb
Host smart-ab6b5d6e-f07d-4bea-aa08-1fc50d0732f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673234496 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.2673234496
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.678666303
Short name T709
Test name
Test status
Simulation time 462437439 ps
CPU time 1.32 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207380 kb
Host smart-a9cb7910-112d-4eac-9889-48d3cabdbbb8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678666303 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.678666303
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.3983361535
Short name T564
Test name
Test status
Simulation time 585240581 ps
CPU time 1.55 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207364 kb
Host smart-efc5d97c-92ea-4079-a928-eed2120627c0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983361535 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.3983361535
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1688285681
Short name T1410
Test name
Test status
Simulation time 111856839 ps
CPU time 0.71 seconds
Started Aug 09 05:32:19 PM PDT 24
Finished Aug 09 05:32:20 PM PDT 24
Peak memory 207516 kb
Host smart-fa88d7e3-0074-43d8-8de3-67c1345f8a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1688285681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1688285681
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.181098074
Short name T744
Test name
Test status
Simulation time 11682543827 ps
CPU time 14.32 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207688 kb
Host smart-4fffcaf6-fca2-4cdc-83c0-f49d8a989cd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181098074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_disconnect.181098074
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3931324157
Short name T1068
Test name
Test status
Simulation time 14686795503 ps
CPU time 17.77 seconds
Started Aug 09 05:32:24 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 215852 kb
Host smart-935cf43f-7331-4634-b665-2a251c951f6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931324157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3931324157
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.4060257225
Short name T2046
Test name
Test status
Simulation time 24032789268 ps
CPU time 35.76 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 215976 kb
Host smart-62ca4836-2dee-4c54-be38-b3eed7c81e4a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060257225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.4060257225
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3096876721
Short name T31
Test name
Test status
Simulation time 188035616 ps
CPU time 0.95 seconds
Started Aug 09 05:32:18 PM PDT 24
Finished Aug 09 05:32:19 PM PDT 24
Peak memory 207476 kb
Host smart-3fa60132-78f7-4759-8208-24cdc8229959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968
76721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3096876721
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.863672355
Short name T2944
Test name
Test status
Simulation time 180595759 ps
CPU time 0.88 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207472 kb
Host smart-a7f1432e-a170-41c4-bb01-58848a24c001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86367
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.863672355
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1359588574
Short name T1144
Test name
Test status
Simulation time 365263502 ps
CPU time 1.39 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207580 kb
Host smart-a8abf6a4-c0d6-4f9f-beed-fc4aad414157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
88574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1359588574
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3171423212
Short name T321
Test name
Test status
Simulation time 578433654 ps
CPU time 1.76 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207440 kb
Host smart-5e402127-1945-4439-9cc4-07c0a4039fc8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3171423212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3171423212
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2532186657
Short name T327
Test name
Test status
Simulation time 25015322094 ps
CPU time 44.45 seconds
Started Aug 09 05:32:19 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207772 kb
Host smart-605331e1-8e13-4dc5-b1b6-071ba1ec3548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
86657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2532186657
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.2596436475
Short name T716
Test name
Test status
Simulation time 2077946763 ps
CPU time 18.05 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:25 PM PDT 24
Peak memory 207664 kb
Host smart-68824625-a845-45c8-b4ad-6ca7e6ba0281
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596436475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.2596436475
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.120730970
Short name T976
Test name
Test status
Simulation time 616042971 ps
CPU time 1.88 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 207476 kb
Host smart-36c160a5-5fe7-4cd0-891d-3020b2a92a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
0970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.120730970
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2317180841
Short name T764
Test name
Test status
Simulation time 167416870 ps
CPU time 0.88 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207468 kb
Host smart-bdb0ee75-27ed-43ba-a360-c9933d6f6d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23171
80841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2317180841
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3856573001
Short name T2133
Test name
Test status
Simulation time 75958367 ps
CPU time 0.73 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207456 kb
Host smart-f53cc0b2-5835-4ff1-aff0-327b3ba49a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565
73001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3856573001
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1844407210
Short name T2972
Test name
Test status
Simulation time 976915531 ps
CPU time 2.7 seconds
Started Aug 09 05:32:14 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207692 kb
Host smart-d5009445-060a-4f4e-881d-655eb6aa19b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
07210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1844407210
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.3492310503
Short name T3432
Test name
Test status
Simulation time 164579643 ps
CPU time 0.88 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207400 kb
Host smart-277ba95e-47b9-4bd7-822b-e56b40ad6b04
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3492310503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.3492310503
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1384950943
Short name T830
Test name
Test status
Simulation time 285469297 ps
CPU time 1.89 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 207672 kb
Host smart-95212d48-998a-4610-a27a-2d82ce6fe8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13849
50943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1384950943
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.801940004
Short name T3519
Test name
Test status
Simulation time 241096771 ps
CPU time 1.26 seconds
Started Aug 09 05:32:08 PM PDT 24
Finished Aug 09 05:32:09 PM PDT 24
Peak memory 215876 kb
Host smart-d4f4f599-e5ab-4d8b-a422-05029122858c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=801940004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.801940004
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3767199815
Short name T2873
Test name
Test status
Simulation time 178898084 ps
CPU time 0.87 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 207376 kb
Host smart-262f5c10-5a1d-434a-aa7d-1253647ef7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
99815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3767199815
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.571868608
Short name T517
Test name
Test status
Simulation time 255625194 ps
CPU time 1.06 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:23 PM PDT 24
Peak memory 207364 kb
Host smart-ba34e46f-19f7-40ac-8c04-f3680f7ae45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57186
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.571868608
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.2665161170
Short name T1561
Test name
Test status
Simulation time 3895849644 ps
CPU time 29.11 seconds
Started Aug 09 05:32:07 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 218136 kb
Host smart-e94d9eec-79ad-498b-8032-44cb1b5ee772
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2665161170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2665161170
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.571080519
Short name T3625
Test name
Test status
Simulation time 10003000761 ps
CPU time 71.66 seconds
Started Aug 09 05:32:06 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 207812 kb
Host smart-40bf7638-2ee1-4e2b-846d-6614ee9b3b21
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=571080519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.571080519
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1828419582
Short name T3344
Test name
Test status
Simulation time 235377653 ps
CPU time 0.98 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:10 PM PDT 24
Peak memory 207436 kb
Host smart-959649da-1fce-4287-bc27-e82692599409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
19582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1828419582
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.4219015228
Short name T2042
Test name
Test status
Simulation time 25942667596 ps
CPU time 42.65 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 216076 kb
Host smart-3ee5e5a6-712f-4140-8515-f4a01ef27fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190
15228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.4219015228
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2272169441
Short name T3095
Test name
Test status
Simulation time 3376684509 ps
CPU time 5.12 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 216164 kb
Host smart-ceca7c65-dbee-4856-862e-9a03bb1a42da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
69441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2272169441
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2648622528
Short name T637
Test name
Test status
Simulation time 2581344002 ps
CPU time 73.71 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 218740 kb
Host smart-ce41f9d8-019e-4b8a-afa0-0d341618e1ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2648622528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2648622528
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1669375439
Short name T2597
Test name
Test status
Simulation time 2691953397 ps
CPU time 19.5 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 216012 kb
Host smart-9b377dcd-8331-46b8-8ffe-55d1cb29d06a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1669375439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1669375439
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3432951282
Short name T579
Test name
Test status
Simulation time 241145607 ps
CPU time 0.99 seconds
Started Aug 09 05:32:21 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207496 kb
Host smart-85bfe2b6-b2e3-463c-b8dc-035ea8d14eb1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3432951282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3432951282
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.779049155
Short name T1846
Test name
Test status
Simulation time 223910102 ps
CPU time 1 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207488 kb
Host smart-c67059c9-00d6-473a-bc6e-90146c689149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77904
9155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.779049155
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1469474018
Short name T1833
Test name
Test status
Simulation time 3624758648 ps
CPU time 26.88 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 217564 kb
Host smart-e290c8c7-140a-4109-a5c4-fc6d6de01b2a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1469474018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1469474018
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1831008643
Short name T2204
Test name
Test status
Simulation time 209012979 ps
CPU time 0.93 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207484 kb
Host smart-4e1289b5-a0a2-487d-9256-0c67e6ee84b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1831008643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1831008643
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2074382800
Short name T1813
Test name
Test status
Simulation time 149825678 ps
CPU time 0.85 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207488 kb
Host smart-75d94413-abed-4718-bff5-6bf594e4bb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20743
82800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2074382800
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2081711081
Short name T1326
Test name
Test status
Simulation time 196928494 ps
CPU time 0.95 seconds
Started Aug 09 05:32:13 PM PDT 24
Finished Aug 09 05:32:14 PM PDT 24
Peak memory 207508 kb
Host smart-b6d141f3-26fa-413d-b080-4f548be2c804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817
11081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2081711081
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2974021315
Short name T997
Test name
Test status
Simulation time 174964432 ps
CPU time 0.93 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207588 kb
Host smart-9193ca69-5d71-4b8d-bd44-2042617489e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29740
21315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2974021315
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1762414022
Short name T3016
Test name
Test status
Simulation time 167180925 ps
CPU time 0.85 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207512 kb
Host smart-ab0aa4c2-45fc-49d0-ba92-1a695b9fed2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
14022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1762414022
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.705885466
Short name T2362
Test name
Test status
Simulation time 181072522 ps
CPU time 0.88 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:32:21 PM PDT 24
Peak memory 207556 kb
Host smart-ce05c1b4-77ab-4ea3-811b-17eff6d866e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70588
5466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.705885466
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2592537545
Short name T723
Test name
Test status
Simulation time 256047949 ps
CPU time 1.09 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207532 kb
Host smart-4d2c5342-775e-4f95-b946-8fee956464de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2592537545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2592537545
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.680136874
Short name T1802
Test name
Test status
Simulation time 143120444 ps
CPU time 0.84 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:12 PM PDT 24
Peak memory 207448 kb
Host smart-ed7f508b-eb74-4b02-af50-371722411820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68013
6874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.680136874
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2875895041
Short name T2373
Test name
Test status
Simulation time 50486524 ps
CPU time 0.71 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207360 kb
Host smart-e7e373b2-a25c-49f2-a9e7-9b5c4a61afdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28758
95041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2875895041
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1558579360
Short name T3041
Test name
Test status
Simulation time 14489260610 ps
CPU time 41.12 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 215928 kb
Host smart-b54b1867-aacc-4cc2-a74e-a87fab791f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
79360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1558579360
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.147865277
Short name T1312
Test name
Test status
Simulation time 158770590 ps
CPU time 0.89 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 207520 kb
Host smart-e2a67938-f894-418a-9a96-46d9c4115dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
5277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.147865277
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2368764764
Short name T2816
Test name
Test status
Simulation time 191900718 ps
CPU time 0.89 seconds
Started Aug 09 05:32:24 PM PDT 24
Finished Aug 09 05:32:25 PM PDT 24
Peak memory 207524 kb
Host smart-316874b6-410a-4705-807c-f458767371b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23687
64764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2368764764
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.919005212
Short name T1938
Test name
Test status
Simulation time 223084063 ps
CPU time 0.99 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207360 kb
Host smart-3ed29c0a-c422-4d94-b8e1-c1e946574afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91900
5212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.919005212
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1517496375
Short name T2438
Test name
Test status
Simulation time 197964688 ps
CPU time 0.91 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:16 PM PDT 24
Peak memory 206480 kb
Host smart-8876c521-6187-4d8c-85c7-ea94107dffff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15174
96375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1517496375
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2750116227
Short name T326
Test name
Test status
Simulation time 141153659 ps
CPU time 0.86 seconds
Started Aug 09 05:32:13 PM PDT 24
Finished Aug 09 05:32:14 PM PDT 24
Peak memory 207508 kb
Host smart-a5e44d22-5ef3-4e3a-8615-c85d648b48ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27501
16227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2750116227
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.169631451
Short name T3208
Test name
Test status
Simulation time 266643217 ps
CPU time 1.21 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207468 kb
Host smart-fa420ea4-6c09-4ca8-adc2-83cc1204ca7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16963
1451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.169631451
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.4224117005
Short name T3370
Test name
Test status
Simulation time 166521756 ps
CPU time 0.87 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207428 kb
Host smart-4abc3569-1e1d-4cf6-9365-daba060877bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
17005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.4224117005
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3867263182
Short name T3028
Test name
Test status
Simulation time 155855043 ps
CPU time 0.91 seconds
Started Aug 09 05:32:12 PM PDT 24
Finished Aug 09 05:32:13 PM PDT 24
Peak memory 207508 kb
Host smart-702d4f25-2cbc-44f9-9e6a-b0f90d4fa257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38672
63182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3867263182
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1392525797
Short name T581
Test name
Test status
Simulation time 238907708 ps
CPU time 1.02 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:32:21 PM PDT 24
Peak memory 207492 kb
Host smart-b794b9b6-85c3-4cf9-8dd5-9201f4e30d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13925
25797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1392525797
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3235099835
Short name T2265
Test name
Test status
Simulation time 3207560172 ps
CPU time 25.54 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 218068 kb
Host smart-a45e4d43-3db9-4ed6-9b85-2d86f3d8d3e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3235099835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3235099835
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.594746894
Short name T2602
Test name
Test status
Simulation time 155910587 ps
CPU time 0.85 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207448 kb
Host smart-f346588e-b971-47cb-b38c-88bbbdcafe2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59474
6894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.594746894
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1733491580
Short name T1881
Test name
Test status
Simulation time 251187780 ps
CPU time 0.98 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:32:21 PM PDT 24
Peak memory 207408 kb
Host smart-a41efb97-d727-4ee7-80f7-30e34159e2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334
91580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1733491580
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2238545046
Short name T2713
Test name
Test status
Simulation time 433944674 ps
CPU time 1.32 seconds
Started Aug 09 05:32:13 PM PDT 24
Finished Aug 09 05:32:15 PM PDT 24
Peak memory 207512 kb
Host smart-14b14667-aa4b-457a-b773-87c82260328c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
45046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2238545046
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1858985788
Short name T1225
Test name
Test status
Simulation time 3019670482 ps
CPU time 85.32 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:33:40 PM PDT 24
Peak memory 216076 kb
Host smart-e8e08408-115d-4ec5-abf6-f17a7fdba23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18589
85788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1858985788
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.119925259
Short name T3100
Test name
Test status
Simulation time 1145302302 ps
CPU time 26.64 seconds
Started Aug 09 05:32:09 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207736 kb
Host smart-31efafe1-45e1-442f-96f0-8497607bdecf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119925259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host
_handshake.119925259
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.2641797964
Short name T671
Test name
Test status
Simulation time 476710781 ps
CPU time 1.63 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:26 PM PDT 24
Peak memory 207528 kb
Host smart-6ee18868-c01a-4ebd-86ce-3a38109f223a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641797964 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.2641797964
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.2068797553
Short name T3477
Test name
Test status
Simulation time 508808358 ps
CPU time 1.37 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207564 kb
Host smart-f77402e6-8bea-49ee-82f3-a157d652dc1a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068797553 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.2068797553
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.2561224395
Short name T996
Test name
Test status
Simulation time 518305948 ps
CPU time 1.59 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 207444 kb
Host smart-1096519d-1fc2-402e-b36c-78c5f8d707c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561224395 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.2561224395
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.1248895792
Short name T1498
Test name
Test status
Simulation time 461738316 ps
CPU time 1.45 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207516 kb
Host smart-ccb72b10-a0d0-47b0-8b25-38b176839ac6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248895792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.1248895792
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.3919152013
Short name T2093
Test name
Test status
Simulation time 551305358 ps
CPU time 1.65 seconds
Started Aug 09 05:34:09 PM PDT 24
Finished Aug 09 05:34:11 PM PDT 24
Peak memory 207364 kb
Host smart-6d220edd-d3ff-45b9-ba57-27ea424f28a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919152013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.3919152013
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.3865870319
Short name T1573
Test name
Test status
Simulation time 641505761 ps
CPU time 1.71 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207484 kb
Host smart-7ea0f196-a44b-4ef8-8fd5-a0af1de49874
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865870319 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.3865870319
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.4254966804
Short name T2505
Test name
Test status
Simulation time 462812885 ps
CPU time 1.53 seconds
Started Aug 09 05:33:56 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207556 kb
Host smart-086da770-9112-498e-a581-123d611c1a11
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254966804 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.4254966804
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.397768507
Short name T1703
Test name
Test status
Simulation time 473222570 ps
CPU time 1.4 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207440 kb
Host smart-b69793fd-d05d-481e-94b2-26d78a459fe0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397768507 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.397768507
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.3184786696
Short name T1122
Test name
Test status
Simulation time 580828940 ps
CPU time 1.63 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 207544 kb
Host smart-6385512d-85dd-486a-b494-dda33e1e43ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184786696 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.3184786696
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.1940849380
Short name T3433
Test name
Test status
Simulation time 457005817 ps
CPU time 1.42 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 207568 kb
Host smart-9940304c-8c48-4dd9-a648-9960475eb2fb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940849380 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.1940849380
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.1382454751
Short name T2152
Test name
Test status
Simulation time 519565083 ps
CPU time 1.61 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207484 kb
Host smart-9b4cefc5-fa5f-43bf-aa4b-f32766f7535f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382454751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.1382454751
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3779869277
Short name T1533
Test name
Test status
Simulation time 46368035 ps
CPU time 0.7 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207404 kb
Host smart-6a38537e-0a74-4a7c-85b0-cca92c420c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3779869277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3779869277
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.761374628
Short name T1511
Test name
Test status
Simulation time 9575204777 ps
CPU time 12.51 seconds
Started Aug 09 05:32:24 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207820 kb
Host smart-5d6e23cb-f528-47e8-a8b8-f9613f171641
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761374628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.761374628
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2058035828
Short name T2343
Test name
Test status
Simulation time 14926649135 ps
CPU time 17.23 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 215984 kb
Host smart-11430801-7c4b-42f8-bf32-1d438b8bc508
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058035828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2058035828
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.15544578
Short name T2155
Test name
Test status
Simulation time 29118812190 ps
CPU time 34.41 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:33:07 PM PDT 24
Peak memory 207688 kb
Host smart-ab6f8344-c147-48a3-8254-8788b98dd5a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon
_wake_resume.15544578
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2134722414
Short name T569
Test name
Test status
Simulation time 183651220 ps
CPU time 0.88 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207488 kb
Host smart-efaaa901-f8d8-40c2-bc39-727e398ad0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21347
22414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2134722414
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3898878828
Short name T1290
Test name
Test status
Simulation time 220330856 ps
CPU time 0.97 seconds
Started Aug 09 05:32:16 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207384 kb
Host smart-de463cb1-21b3-456d-9317-4f360c531e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
78828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3898878828
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1088350987
Short name T3613
Test name
Test status
Simulation time 379908596 ps
CPU time 1.39 seconds
Started Aug 09 05:32:11 PM PDT 24
Finished Aug 09 05:32:12 PM PDT 24
Peak memory 207528 kb
Host smart-619a6bc2-7a27-499b-bbf7-ec52dc790905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
50987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1088350987
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1547223169
Short name T1985
Test name
Test status
Simulation time 1047322190 ps
CPU time 2.82 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207580 kb
Host smart-0ce9a664-2fe8-4298-86f2-14c92092d107
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1547223169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1547223169
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.144585090
Short name T1934
Test name
Test status
Simulation time 21651752863 ps
CPU time 34.56 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207680 kb
Host smart-d15fc466-8ab0-4693-a719-18c412896457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
5090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.144585090
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.3413300721
Short name T2206
Test name
Test status
Simulation time 1016015087 ps
CPU time 22.99 seconds
Started Aug 09 05:32:17 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207644 kb
Host smart-e5084721-42c2-4ee3-8585-84d43ad43564
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413300721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.3413300721
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1307303349
Short name T1931
Test name
Test status
Simulation time 893117581 ps
CPU time 2.03 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 207496 kb
Host smart-6d789c8b-223f-4d5c-896e-3dcce83d9b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
03349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1307303349
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2877269647
Short name T2131
Test name
Test status
Simulation time 141053714 ps
CPU time 0.81 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 207436 kb
Host smart-cb55ee8c-4dba-4dc4-b91a-97ef1eac9b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28772
69647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2877269647
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.4112742407
Short name T592
Test name
Test status
Simulation time 42267431 ps
CPU time 0.75 seconds
Started Aug 09 05:32:23 PM PDT 24
Finished Aug 09 05:32:24 PM PDT 24
Peak memory 207384 kb
Host smart-a60b32ad-bfb9-475c-93d7-a258b65d2a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
42407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.4112742407
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1781479734
Short name T2089
Test name
Test status
Simulation time 805810624 ps
CPU time 2.25 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207604 kb
Host smart-e55a965c-54f3-4cf0-a5ad-60c1de000197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
79734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1781479734
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.2949709642
Short name T489
Test name
Test status
Simulation time 432377733 ps
CPU time 1.29 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:17 PM PDT 24
Peak memory 207452 kb
Host smart-b612ca69-f861-42bf-9856-08cd8e5c4f85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2949709642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.2949709642
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.375405894
Short name T3310
Test name
Test status
Simulation time 239561900 ps
CPU time 1.95 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:25 PM PDT 24
Peak memory 207540 kb
Host smart-f6c16055-32d4-4e8f-a8e5-9a5946bbb577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37540
5894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.375405894
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1787464047
Short name T1374
Test name
Test status
Simulation time 293323745 ps
CPU time 1.3 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 215876 kb
Host smart-cd4414e8-d859-442a-bd7e-13907f05ad85
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1787464047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1787464047
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3044279534
Short name T1913
Test name
Test status
Simulation time 210411515 ps
CPU time 0.92 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207388 kb
Host smart-b1cc90ed-2577-46d9-9438-51c85c31d508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30442
79534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3044279534
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.662610428
Short name T1234
Test name
Test status
Simulation time 199722703 ps
CPU time 0.94 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207488 kb
Host smart-72113293-58fb-4d29-8524-bdbc1bbe4d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66261
0428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.662610428
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.550377792
Short name T1330
Test name
Test status
Simulation time 3596387140 ps
CPU time 34.71 seconds
Started Aug 09 05:32:22 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 224192 kb
Host smart-cf8eebc0-7047-49cc-b3af-5bfbc142962c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=550377792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.550377792
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1551689951
Short name T2397
Test name
Test status
Simulation time 5334507003 ps
CPU time 33.44 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207756 kb
Host smart-cc35f062-38a3-47eb-853a-10f7336ec5df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1551689951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1551689951
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3073715439
Short name T2435
Test name
Test status
Simulation time 242982722 ps
CPU time 1 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207556 kb
Host smart-ce9d24e7-0224-4ce5-aabb-a0ac1113412d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30737
15439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3073715439
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2520005163
Short name T2731
Test name
Test status
Simulation time 7883414369 ps
CPU time 12.62 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 216116 kb
Host smart-de5e3279-ade5-4af7-bfa9-8304f30a4e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
05163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2520005163
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1626181837
Short name T2511
Test name
Test status
Simulation time 3388734709 ps
CPU time 4.99 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 216004 kb
Host smart-179ef358-9861-4539-ab17-48b1d2a324d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261
81837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1626181837
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3924174160
Short name T2574
Test name
Test status
Simulation time 2833092937 ps
CPU time 21.83 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 219588 kb
Host smart-e12db5fe-4235-465e-a587-b290f6f755b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3924174160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3924174160
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2129951386
Short name T1477
Test name
Test status
Simulation time 3362913258 ps
CPU time 94.32 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 215972 kb
Host smart-1aec2c7a-620d-4ff4-a41a-e669de5bd774
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2129951386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2129951386
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.360501982
Short name T1980
Test name
Test status
Simulation time 248741223 ps
CPU time 1.06 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207448 kb
Host smart-d4c40942-8b0a-4da5-a174-2d704d30cc15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=360501982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.360501982
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1800125987
Short name T651
Test name
Test status
Simulation time 185993076 ps
CPU time 0.94 seconds
Started Aug 09 05:32:40 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 207792 kb
Host smart-ec18a9bf-697e-490a-9e80-b5b1a826f751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18001
25987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1800125987
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3615373325
Short name T2655
Test name
Test status
Simulation time 3139772951 ps
CPU time 33.2 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:33:10 PM PDT 24
Peak memory 217700 kb
Host smart-3ca7b725-53c4-40eb-8cdd-9afac655637a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3615373325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3615373325
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.480325865
Short name T1596
Test name
Test status
Simulation time 156201776 ps
CPU time 0.85 seconds
Started Aug 09 05:32:29 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 207496 kb
Host smart-1cfa8a08-ada3-4e04-b191-b543a8fcf58f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=480325865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.480325865
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.648064293
Short name T900
Test name
Test status
Simulation time 171098159 ps
CPU time 0.88 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207472 kb
Host smart-f40bb852-ece3-43a5-a814-c71b2f8b5a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64806
4293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.648064293
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2797339702
Short name T132
Test name
Test status
Simulation time 208231150 ps
CPU time 1.01 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207396 kb
Host smart-fad0ccc1-89f9-4774-8715-e98c17440482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973
39702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2797339702
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.850493997
Short name T1585
Test name
Test status
Simulation time 191570000 ps
CPU time 0.87 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207528 kb
Host smart-804d0fbc-a648-41d3-b5f4-fb48d9b7939e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85049
3997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.850493997
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3466245492
Short name T570
Test name
Test status
Simulation time 186934257 ps
CPU time 0.89 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207472 kb
Host smart-72036d68-0ff6-4aed-9a52-bcfce8d29a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34662
45492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3466245492
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2816258958
Short name T2639
Test name
Test status
Simulation time 222187345 ps
CPU time 0.94 seconds
Started Aug 09 05:32:21 PM PDT 24
Finished Aug 09 05:32:22 PM PDT 24
Peak memory 207504 kb
Host smart-dcfd3874-9b97-4d96-956f-7029d9a472be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28162
58958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2816258958
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2860595325
Short name T170
Test name
Test status
Simulation time 148646310 ps
CPU time 0.87 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 207480 kb
Host smart-e10ee378-88c0-4add-875c-48b98bde8998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
95325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2860595325
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.874884208
Short name T3012
Test name
Test status
Simulation time 250984509 ps
CPU time 1.03 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207500 kb
Host smart-ecbc141f-16f8-4f9c-8652-c0100aaf565a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=874884208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.874884208
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.748217109
Short name T222
Test name
Test status
Simulation time 142414357 ps
CPU time 0.87 seconds
Started Aug 09 05:32:31 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207768 kb
Host smart-dd450567-c92d-4b53-bd7c-0df5443b0876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74821
7109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.748217109
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3331098646
Short name T1583
Test name
Test status
Simulation time 50373468 ps
CPU time 0.69 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:27 PM PDT 24
Peak memory 207468 kb
Host smart-cd694907-564a-4823-a866-408bbb86eaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
98646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3331098646
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.179174820
Short name T269
Test name
Test status
Simulation time 11826203650 ps
CPU time 28.05 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 216032 kb
Host smart-eeb55dad-2b84-416e-aacb-a2056bd9be90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
4820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.179174820
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.349095937
Short name T1142
Test name
Test status
Simulation time 183139313 ps
CPU time 0.93 seconds
Started Aug 09 05:32:33 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 207436 kb
Host smart-514332ed-2145-426e-932e-cb27a042bd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
5937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.349095937
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3359734650
Short name T3413
Test name
Test status
Simulation time 246795620 ps
CPU time 1.05 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207528 kb
Host smart-173fa7e5-7dd9-49ba-8988-0e580e147288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
34650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3359734650
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1516067465
Short name T1403
Test name
Test status
Simulation time 194500401 ps
CPU time 0.93 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207412 kb
Host smart-43b19153-3a12-4a15-b4cc-b1a213366bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
67465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1516067465
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.262200091
Short name T1048
Test name
Test status
Simulation time 178341098 ps
CPU time 0.87 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207560 kb
Host smart-e6bccf58-7d71-493f-9fdd-57caa2288f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
0091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.262200091
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.301164592
Short name T3592
Test name
Test status
Simulation time 142613920 ps
CPU time 0.83 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207356 kb
Host smart-9b14a497-b915-4f26-aba1-c5e6fa8c2c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30116
4592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.301164592
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.4025467790
Short name T1047
Test name
Test status
Simulation time 381272787 ps
CPU time 1.26 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207384 kb
Host smart-e4a82f74-ffc8-49dd-a0eb-61f9256908b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40254
67790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.4025467790
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3126993124
Short name T3061
Test name
Test status
Simulation time 180174008 ps
CPU time 0.87 seconds
Started Aug 09 05:32:47 PM PDT 24
Finished Aug 09 05:32:48 PM PDT 24
Peak memory 207396 kb
Host smart-497c856b-ba02-46d5-ac36-05155c8aa743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31269
93124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3126993124
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.350470551
Short name T2620
Test name
Test status
Simulation time 144808341 ps
CPU time 0.83 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:32:33 PM PDT 24
Peak memory 207416 kb
Host smart-6bd6a4e4-1b78-4844-954c-dfe7d4165f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35047
0551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.350470551
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3134007477
Short name T1509
Test name
Test status
Simulation time 223827778 ps
CPU time 1.01 seconds
Started Aug 09 05:32:33 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 207428 kb
Host smart-e1215f2d-364e-46c8-ad85-ac7599e9596e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31340
07477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3134007477
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1249839515
Short name T2407
Test name
Test status
Simulation time 2216399106 ps
CPU time 22.75 seconds
Started Aug 09 05:32:15 PM PDT 24
Finished Aug 09 05:32:38 PM PDT 24
Peak memory 224264 kb
Host smart-d7cc565f-35c5-4e32-bde9-7b12d504031b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1249839515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1249839515
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4170749293
Short name T1138
Test name
Test status
Simulation time 150042154 ps
CPU time 0.84 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:36 PM PDT 24
Peak memory 207412 kb
Host smart-20a80319-73ef-4a5c-a10a-24440a800c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41707
49293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4170749293
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.34190669
Short name T2168
Test name
Test status
Simulation time 231995666 ps
CPU time 0.94 seconds
Started Aug 09 05:32:17 PM PDT 24
Finished Aug 09 05:32:18 PM PDT 24
Peak memory 207552 kb
Host smart-6a81b745-a1f6-4620-9229-fdefa3659317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.34190669
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1435863031
Short name T2182
Test name
Test status
Simulation time 200862391 ps
CPU time 0.95 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207448 kb
Host smart-29739669-d90a-41fb-a3be-d7ce105d6bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
63031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1435863031
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2670752648
Short name T1820
Test name
Test status
Simulation time 2991820759 ps
CPU time 88.06 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 217536 kb
Host smart-28f721a4-b942-41c9-92c6-7dcef4ab3736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
52648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2670752648
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.3266785448
Short name T2273
Test name
Test status
Simulation time 3214972130 ps
CPU time 22.06 seconds
Started Aug 09 05:32:29 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207732 kb
Host smart-4357b9e5-b788-4755-8e88-b059bef349a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266785448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.3266785448
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.4292161145
Short name T3054
Test name
Test status
Simulation time 519977516 ps
CPU time 1.71 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 207564 kb
Host smart-09080c1f-f734-4391-9088-32a3b3d31490
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292161145 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.4292161145
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.3841399462
Short name T2548
Test name
Test status
Simulation time 577857863 ps
CPU time 1.5 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 207456 kb
Host smart-c1308d3d-7045-4f07-bd1a-9adc50ad131a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841399462 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.3841399462
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.1951941683
Short name T3443
Test name
Test status
Simulation time 474075817 ps
CPU time 1.5 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 207560 kb
Host smart-bd4494f4-a09c-4734-97ee-5a4e53e5208e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951941683 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.1951941683
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.3244766469
Short name T1193
Test name
Test status
Simulation time 563879138 ps
CPU time 1.53 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207480 kb
Host smart-f7c7ae82-2bad-4121-9886-d76c7f8b327b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244766469 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.3244766469
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.1787750751
Short name T2770
Test name
Test status
Simulation time 400687959 ps
CPU time 1.33 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 207564 kb
Host smart-00f4c4aa-b0b3-49f2-9586-c48cde2d7af8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787750751 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.1787750751
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.3539695448
Short name T3011
Test name
Test status
Simulation time 525236513 ps
CPU time 1.53 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207404 kb
Host smart-47b9cb13-4fb9-46bd-82a8-fd25fbc9f36d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539695448 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.3539695448
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.1614416545
Short name T1927
Test name
Test status
Simulation time 585821538 ps
CPU time 1.48 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207444 kb
Host smart-7da8eb87-2485-4d31-8aea-0981c7ff9d19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614416545 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.1614416545
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.2253192043
Short name T1862
Test name
Test status
Simulation time 457338863 ps
CPU time 1.43 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 207504 kb
Host smart-e5112b44-8ae8-4318-b5c6-dcf7eb32b07d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253192043 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.2253192043
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.395497060
Short name T3540
Test name
Test status
Simulation time 549440553 ps
CPU time 1.75 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207568 kb
Host smart-d7b2f191-fd0a-4849-a6a6-e016d24f97bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395497060 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.395497060
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.2149590340
Short name T2377
Test name
Test status
Simulation time 510921012 ps
CPU time 1.72 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 207552 kb
Host smart-b2a15dd6-fdc6-45a5-a3e9-ad26f2119d2d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149590340 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.2149590340
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.2406673949
Short name T1470
Test name
Test status
Simulation time 479445125 ps
CPU time 1.54 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 207516 kb
Host smart-d3ade567-ceac-4033-98e1-15539460ded4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406673949 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.2406673949
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2961917951
Short name T2497
Test name
Test status
Simulation time 97248803 ps
CPU time 0.73 seconds
Started Aug 09 05:32:40 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 207552 kb
Host smart-d92ce9c1-5781-4b84-b338-d49a0230ed13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2961917951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2961917951
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1962921287
Short name T3025
Test name
Test status
Simulation time 6301213485 ps
CPU time 8.68 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 215968 kb
Host smart-19bebe4d-680e-453c-b62f-5df683e4cbfd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962921287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1962921287
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.4024043721
Short name T2817
Test name
Test status
Simulation time 15972311613 ps
CPU time 17.51 seconds
Started Aug 09 05:32:29 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 215944 kb
Host smart-714e539c-6697-4499-b170-6bf8bda4b9d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024043721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.4024043721
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.968027272
Short name T3072
Test name
Test status
Simulation time 30379072356 ps
CPU time 35.99 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:33:16 PM PDT 24
Peak memory 207720 kb
Host smart-3dfc5ffa-7fe9-411f-883c-4202ec2c5314
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968027272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.968027272
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1914283787
Short name T2864
Test name
Test status
Simulation time 177486671 ps
CPU time 0.88 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207476 kb
Host smart-cd139a83-6e15-4103-9880-a114708a8dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19142
83787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1914283787
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4114615156
Short name T16
Test name
Test status
Simulation time 186148845 ps
CPU time 0.89 seconds
Started Aug 09 05:32:20 PM PDT 24
Finished Aug 09 05:32:21 PM PDT 24
Peak memory 207468 kb
Host smart-37590d9a-7a80-4faf-96a8-e9363a58386d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
15156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4114615156
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2783153750
Short name T2219
Test name
Test status
Simulation time 289177869 ps
CPU time 1.17 seconds
Started Aug 09 05:32:31 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207416 kb
Host smart-199ea4b5-6e5c-4e2f-a50e-116e19c82963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27831
53750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2783153750
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1733982924
Short name T319
Test name
Test status
Simulation time 1051801498 ps
CPU time 2.71 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207640 kb
Host smart-5a168f43-b2d8-4859-917b-a8673fd4170f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1733982924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1733982924
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3866933439
Short name T2331
Test name
Test status
Simulation time 15094524421 ps
CPU time 27.06 seconds
Started Aug 09 05:32:37 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207796 kb
Host smart-c1497f4e-cfc2-4d0b-a92e-d7899ecd9920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
33439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3866933439
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.1104585102
Short name T645
Test name
Test status
Simulation time 1186518649 ps
CPU time 27.2 seconds
Started Aug 09 05:32:33 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207624 kb
Host smart-4b0ff9c7-ceb1-46dc-ade7-54d7a8258583
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104585102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.1104585102
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.4130018009
Short name T3245
Test name
Test status
Simulation time 653087091 ps
CPU time 1.68 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 207472 kb
Host smart-1bc896d1-991d-4be0-9a3e-6c48e0eb40b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41300
18009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.4130018009
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1736825595
Short name T952
Test name
Test status
Simulation time 188517170 ps
CPU time 0.93 seconds
Started Aug 09 05:32:34 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207520 kb
Host smart-25ab713e-916a-4b5e-abec-c7af1e4bcc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17368
25595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1736825595
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2009789708
Short name T2576
Test name
Test status
Simulation time 106213943 ps
CPU time 0.74 seconds
Started Aug 09 05:32:47 PM PDT 24
Finished Aug 09 05:32:48 PM PDT 24
Peak memory 207440 kb
Host smart-69ed063c-fde3-464a-80f8-6b7983623f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
89708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2009789708
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2924744343
Short name T3162
Test name
Test status
Simulation time 864032227 ps
CPU time 2.5 seconds
Started Aug 09 05:32:40 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207692 kb
Host smart-57f54271-08d8-46e1-b2df-add3293e7dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29247
44343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2924744343
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.2496794219
Short name T742
Test name
Test status
Simulation time 152185567 ps
CPU time 0.87 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:35 PM PDT 24
Peak memory 207464 kb
Host smart-f23f32d8-b88d-4304-930d-8a49b47e39ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2496794219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.2496794219
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.9813455
Short name T2408
Test name
Test status
Simulation time 153835332 ps
CPU time 1.46 seconds
Started Aug 09 05:32:26 PM PDT 24
Finished Aug 09 05:32:28 PM PDT 24
Peak memory 207580 kb
Host smart-dee05748-e746-4b99-b465-f3d686931486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98134
55 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.9813455
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.62466052
Short name T1046
Test name
Test status
Simulation time 216953890 ps
CPU time 1.08 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 215852 kb
Host smart-66418116-f84e-4edd-b471-58a8254ac72c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=62466052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.62466052
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.621072765
Short name T3579
Test name
Test status
Simulation time 177790252 ps
CPU time 0.85 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207368 kb
Host smart-7aef7f4c-a112-46a4-8ff1-58e8c99ef271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62107
2765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.621072765
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4119545611
Short name T3627
Test name
Test status
Simulation time 178720839 ps
CPU time 0.91 seconds
Started Aug 09 05:32:30 PM PDT 24
Finished Aug 09 05:32:31 PM PDT 24
Peak memory 207556 kb
Host smart-a942a1cb-2ff1-46c0-a7e9-4d3eb309e9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41195
45611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4119545611
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.1966099844
Short name T2678
Test name
Test status
Simulation time 4595459064 ps
CPU time 32.87 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:33:09 PM PDT 24
Peak memory 218084 kb
Host smart-db378d2f-b1d2-4b0e-bf08-5ef6bb86cbeb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1966099844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.1966099844
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2588657802
Short name T2188
Test name
Test status
Simulation time 6644521055 ps
CPU time 43.55 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:33:24 PM PDT 24
Peak memory 207812 kb
Host smart-bcb78ea1-5d77-4cb4-99fe-1c1bb27be0f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2588657802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2588657802
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1767899949
Short name T1442
Test name
Test status
Simulation time 205238640 ps
CPU time 0.92 seconds
Started Aug 09 05:32:28 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207516 kb
Host smart-59a49dca-7a03-4348-93e8-5d2fb926da2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
99949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1767899949
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3554319212
Short name T2763
Test name
Test status
Simulation time 32594564142 ps
CPU time 59.36 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:33:32 PM PDT 24
Peak memory 207752 kb
Host smart-f8298e27-8735-48be-b1e5-f492bcf47eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35543
19212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3554319212
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3763936168
Short name T2124
Test name
Test status
Simulation time 8343492099 ps
CPU time 12.52 seconds
Started Aug 09 05:32:35 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207764 kb
Host smart-a509dcd9-f64f-4afe-8686-3af496c6b361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
36168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3763936168
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.125786393
Short name T2184
Test name
Test status
Simulation time 4566367465 ps
CPU time 32.84 seconds
Started Aug 09 05:32:31 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 224276 kb
Host smart-220d80c2-4da4-4b5f-8708-076226a07072
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=125786393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.125786393
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1833272458
Short name T1692
Test name
Test status
Simulation time 2862472697 ps
CPU time 28.65 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 224268 kb
Host smart-7af7d6e4-3590-449c-8622-7273cadc7ca1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1833272458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1833272458
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.410915663
Short name T1691
Test name
Test status
Simulation time 247115606 ps
CPU time 1.02 seconds
Started Aug 09 05:32:31 PM PDT 24
Finished Aug 09 05:32:33 PM PDT 24
Peak memory 207504 kb
Host smart-fba5c1a4-067e-47fe-bce0-733f371df17e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=410915663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.410915663
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3639619124
Short name T1130
Test name
Test status
Simulation time 198651327 ps
CPU time 0.98 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207476 kb
Host smart-b581a67f-c108-421e-99d7-6543e707d782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
19124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3639619124
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.116744535
Short name T3159
Test name
Test status
Simulation time 2409700510 ps
CPU time 24.54 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:33:08 PM PDT 24
Peak memory 215992 kb
Host smart-8ede91f3-4289-43bb-ae29-24befba7a0ff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=116744535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.116744535
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2912966623
Short name T1593
Test name
Test status
Simulation time 159353485 ps
CPU time 0.82 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207544 kb
Host smart-63b51a4c-9e88-4800-9bd0-52122fb812a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2912966623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2912966623
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.879928046
Short name T791
Test name
Test status
Simulation time 163183561 ps
CPU time 0.88 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207464 kb
Host smart-5ba3087b-fc37-40b7-a681-a6e9f9929399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87992
8046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.879928046
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3003453205
Short name T128
Test name
Test status
Simulation time 162624381 ps
CPU time 0.9 seconds
Started Aug 09 05:32:24 PM PDT 24
Finished Aug 09 05:32:25 PM PDT 24
Peak memory 207528 kb
Host smart-0b4f72d6-b82c-44ee-8914-fc2541c8ea10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30034
53205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3003453205
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1316952163
Short name T1040
Test name
Test status
Simulation time 172471696 ps
CPU time 0.88 seconds
Started Aug 09 05:32:33 PM PDT 24
Finished Aug 09 05:32:34 PM PDT 24
Peak memory 207436 kb
Host smart-cc13829a-9fe7-4748-9593-75f9d1d00d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169
52163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1316952163
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.115696919
Short name T2553
Test name
Test status
Simulation time 207252146 ps
CPU time 0.94 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207408 kb
Host smart-eb8b890a-d351-449a-bda4-0c2d22a0e406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11569
6919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.115696919
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2372633436
Short name T1623
Test name
Test status
Simulation time 157647228 ps
CPU time 0.89 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207508 kb
Host smart-aed51be0-1c2d-4bb4-b332-0ae816b70fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23726
33436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2372633436
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1850780694
Short name T3278
Test name
Test status
Simulation time 154997771 ps
CPU time 0.87 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207436 kb
Host smart-bcb4d25d-4733-4637-aa2d-60d4e823a4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
80694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1850780694
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3096973470
Short name T1287
Test name
Test status
Simulation time 204493585 ps
CPU time 1.03 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207496 kb
Host smart-74688212-c9b7-40b9-827e-dbd538dd56f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3096973470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3096973470
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4063546009
Short name T3528
Test name
Test status
Simulation time 146501477 ps
CPU time 0.83 seconds
Started Aug 09 05:32:31 PM PDT 24
Finished Aug 09 05:32:32 PM PDT 24
Peak memory 207380 kb
Host smart-5a265af7-4a6a-4a76-aab4-145d52bc8a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635
46009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4063546009
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.895768521
Short name T920
Test name
Test status
Simulation time 40389205 ps
CPU time 0.72 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:37 PM PDT 24
Peak memory 207460 kb
Host smart-661bb6b3-3212-4e5d-a527-ff3a58542c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89576
8521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.895768521
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1701706365
Short name T1953
Test name
Test status
Simulation time 8551874210 ps
CPU time 22.15 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 215876 kb
Host smart-017316cc-1155-4631-8515-1831e53eb289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
06365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1701706365
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1276350486
Short name T3204
Test name
Test status
Simulation time 157254718 ps
CPU time 0.85 seconds
Started Aug 09 05:32:25 PM PDT 24
Finished Aug 09 05:32:26 PM PDT 24
Peak memory 207552 kb
Host smart-d5f36598-aa0f-495d-a7fe-2c30448936ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12763
50486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1276350486
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.624759034
Short name T1525
Test name
Test status
Simulation time 198828276 ps
CPU time 0.9 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207416 kb
Host smart-65d5ff78-db48-45a2-b0da-2e5f1d53eb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62475
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.624759034
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1657926239
Short name T2202
Test name
Test status
Simulation time 195191762 ps
CPU time 0.95 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207380 kb
Host smart-0f229bc9-587c-45e0-b125-068fc7bfac7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16579
26239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1657926239
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3604942068
Short name T535
Test name
Test status
Simulation time 219813682 ps
CPU time 0.94 seconds
Started Aug 09 05:32:27 PM PDT 24
Finished Aug 09 05:32:29 PM PDT 24
Peak memory 207488 kb
Host smart-5a0e1863-5c9d-40c3-8b6c-6715b991cacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049
42068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3604942068
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1858277013
Short name T1984
Test name
Test status
Simulation time 156544173 ps
CPU time 0.81 seconds
Started Aug 09 05:32:29 PM PDT 24
Finished Aug 09 05:32:30 PM PDT 24
Peak memory 207400 kb
Host smart-4c1aa8f9-341a-418a-87fa-45da3e59d4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18582
77013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1858277013
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.2996575784
Short name T305
Test name
Test status
Simulation time 276990260 ps
CPU time 1.09 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207356 kb
Host smart-05dd9027-c131-4611-9128-1db1bb621890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29965
75784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.2996575784
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1799517177
Short name T1012
Test name
Test status
Simulation time 154519811 ps
CPU time 0.9 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207440 kb
Host smart-4bc293ed-4768-4c6f-9ed6-13e8757cca39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
17177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1799517177
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2233773045
Short name T2950
Test name
Test status
Simulation time 143246930 ps
CPU time 0.82 seconds
Started Aug 09 05:32:45 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207520 kb
Host smart-4582690d-19e2-452a-aa87-770ca095380b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
73045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2233773045
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1956621049
Short name T1859
Test name
Test status
Simulation time 187153872 ps
CPU time 0.93 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207476 kb
Host smart-aad150cf-cf94-4690-9428-acbb4cec1ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19566
21049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1956621049
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1073583939
Short name T2136
Test name
Test status
Simulation time 3056099214 ps
CPU time 24.19 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 224264 kb
Host smart-9447aa4e-ecb7-4a2a-986b-ebbc6cf1e8cc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1073583939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1073583939
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.88028722
Short name T2720
Test name
Test status
Simulation time 208800523 ps
CPU time 0.9 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207432 kb
Host smart-897b3060-b9dc-4b68-9d3f-354972674f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88028
722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.88028722
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2557248242
Short name T2540
Test name
Test status
Simulation time 160249202 ps
CPU time 0.84 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 207496 kb
Host smart-5398c391-5247-482b-a343-65f8fd1cc723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25572
48242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2557248242
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3171203423
Short name T1774
Test name
Test status
Simulation time 561408983 ps
CPU time 1.72 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207388 kb
Host smart-8c96a79c-66e3-454d-8aa9-f2f8288f41e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31712
03423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3171203423
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.196254654
Short name T3318
Test name
Test status
Simulation time 3760233620 ps
CPU time 107.63 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:34:38 PM PDT 24
Peak memory 216020 kb
Host smart-d6ec4a0f-0c22-486b-89d1-27b6f2f0302f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625
4654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.196254654
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.2490767955
Short name T3459
Test name
Test status
Simulation time 2446160057 ps
CPU time 21.38 seconds
Started Aug 09 05:32:32 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207800 kb
Host smart-55b871a4-ddf8-4b60-bc89-0820e30acea1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490767955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.2490767955
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.3151378623
Short name T1076
Test name
Test status
Simulation time 586592044 ps
CPU time 1.59 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207496 kb
Host smart-1d51029d-c627-4260-b644-3b67b3462864
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151378623 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.3151378623
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.2339805125
Short name T1221
Test name
Test status
Simulation time 450573502 ps
CPU time 1.43 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207500 kb
Host smart-85521484-0001-4364-9263-137021b61699
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339805125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.2339805125
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.2556032036
Short name T1263
Test name
Test status
Simulation time 465577867 ps
CPU time 1.43 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207504 kb
Host smart-6e732cc9-091f-4291-95c2-63607f1ec48c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556032036 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.2556032036
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.3217946752
Short name T1900
Test name
Test status
Simulation time 599078652 ps
CPU time 1.64 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:56 PM PDT 24
Peak memory 207496 kb
Host smart-93453639-f070-4564-a4bf-ed66db4c0ff7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217946752 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.3217946752
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.3129706020
Short name T3175
Test name
Test status
Simulation time 491551460 ps
CPU time 1.48 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 207568 kb
Host smart-a1239e77-f602-4aff-b6f4-af15fa3c3b35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129706020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.3129706020
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.1813871191
Short name T701
Test name
Test status
Simulation time 523947610 ps
CPU time 1.54 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:50 PM PDT 24
Peak memory 207564 kb
Host smart-c1b32c96-7357-4f3d-a452-cd393c2114b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813871191 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.1813871191
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.3621002086
Short name T1392
Test name
Test status
Simulation time 553910269 ps
CPU time 1.56 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 207444 kb
Host smart-dd892904-8c98-44ae-a3d7-bd5775700c3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621002086 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.3621002086
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.4101015868
Short name T150
Test name
Test status
Simulation time 541088890 ps
CPU time 1.6 seconds
Started Aug 09 05:33:55 PM PDT 24
Finished Aug 09 05:33:57 PM PDT 24
Peak memory 207464 kb
Host smart-5d086924-2e16-440c-b76f-70ed292b8b7f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101015868 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.4101015868
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.3439915017
Short name T3164
Test name
Test status
Simulation time 618276287 ps
CPU time 1.59 seconds
Started Aug 09 05:33:51 PM PDT 24
Finished Aug 09 05:33:53 PM PDT 24
Peak memory 207484 kb
Host smart-daa967c7-a1d3-4e12-84e9-9945f0ec4f2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439915017 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.3439915017
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.535767088
Short name T2239
Test name
Test status
Simulation time 527449878 ps
CPU time 1.56 seconds
Started Aug 09 05:34:21 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 207512 kb
Host smart-1d544b89-0098-40c6-af51-acff2fd49929
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535767088 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.535767088
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.222084751
Short name T2911
Test name
Test status
Simulation time 603438341 ps
CPU time 1.61 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 207460 kb
Host smart-af843411-2631-4fab-9cea-cc2d6870d8fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222084751 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.222084751
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.43968296
Short name T21
Test name
Test status
Simulation time 68199758 ps
CPU time 0.69 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207436 kb
Host smart-cd9bbf55-cf86-4d82-8158-b806e3f3a335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=43968296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.43968296
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2816722333
Short name T2262
Test name
Test status
Simulation time 5617755758 ps
CPU time 7.98 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 215768 kb
Host smart-df139b01-08ee-45b3-bcdc-fde3bdb394ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816722333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.2816722333
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3924358122
Short name T200
Test name
Test status
Simulation time 15700725418 ps
CPU time 18.75 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:21 PM PDT 24
Peak memory 215984 kb
Host smart-fb25f91a-853d-436d-bc79-47fbcc260ae9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924358122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3924358122
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.2806611300
Short name T1243
Test name
Test status
Simulation time 29337558094 ps
CPU time 35.46 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:33:29 PM PDT 24
Peak memory 207820 kb
Host smart-b1830792-065b-4b78-ac7d-64af310b0773
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806611300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.2806611300
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.324966592
Short name T1941
Test name
Test status
Simulation time 170406338 ps
CPU time 0.95 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207504 kb
Host smart-6a36207f-a313-41df-8ddb-47660993eab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32496
6592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.324966592
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2654056750
Short name T1036
Test name
Test status
Simulation time 155690587 ps
CPU time 0.89 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207560 kb
Host smart-5b4c3570-ee09-4f7b-a49e-54de669daf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540
56750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2654056750
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2969323576
Short name T3125
Test name
Test status
Simulation time 518405854 ps
CPU time 1.69 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:40 PM PDT 24
Peak memory 207576 kb
Host smart-a730fd51-d23f-4452-a6f1-23ec3c697805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29693
23576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2969323576
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3841213952
Short name T1452
Test name
Test status
Simulation time 659383410 ps
CPU time 2.04 seconds
Started Aug 09 05:32:45 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207540 kb
Host smart-7fdd06e4-37c0-4d3c-b72a-8b457e491f45
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3841213952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3841213952
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3861789188
Short name T351
Test name
Test status
Simulation time 31359139956 ps
CPU time 48.27 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:48 PM PDT 24
Peak memory 207740 kb
Host smart-383a4e01-ea51-45a8-ac77-434e55c24e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617
89188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3861789188
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2257370606
Short name T2267
Test name
Test status
Simulation time 469164022 ps
CPU time 8.42 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:09 PM PDT 24
Peak memory 207620 kb
Host smart-6724fe72-13df-4c72-9a13-4a3ce16d94ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257370606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2257370606
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1801583267
Short name T1317
Test name
Test status
Simulation time 549296098 ps
CPU time 1.44 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207364 kb
Host smart-d1aae061-c7f6-4e9a-b4e8-c67be4a4e385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18015
83267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1801583267
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1549116609
Short name T2428
Test name
Test status
Simulation time 153398520 ps
CPU time 0.85 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207364 kb
Host smart-9cb94b0e-e9d4-4e12-9ae5-99cb9e6cc50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15491
16609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1549116609
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.129029754
Short name T2698
Test name
Test status
Simulation time 46890312 ps
CPU time 0.71 seconds
Started Aug 09 05:32:47 PM PDT 24
Finished Aug 09 05:32:48 PM PDT 24
Peak memory 207480 kb
Host smart-6a39d98e-2db8-4afa-9e3f-6bd1f2fd39f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
9754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.129029754
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3889768224
Short name T2088
Test name
Test status
Simulation time 792900488 ps
CPU time 2.26 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207692 kb
Host smart-15477366-7f49-4b70-9cd9-d4d5224c012c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
68224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3889768224
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.3144301434
Short name T471
Test name
Test status
Simulation time 418891757 ps
CPU time 1.37 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207368 kb
Host smart-781fca87-fdaf-4185-9192-f2688e925b2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3144301434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.3144301434
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.49978621
Short name T2515
Test name
Test status
Simulation time 240038658 ps
CPU time 1.76 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207556 kb
Host smart-2485ad55-d33a-4144-bc0d-5dd599e3d8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49978
621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.49978621
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.4016852016
Short name T2127
Test name
Test status
Simulation time 240357207 ps
CPU time 1 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207508 kb
Host smart-6c3d9f89-1ee0-48e3-81a9-12bb6859073a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4016852016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.4016852016
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2266605185
Short name T2268
Test name
Test status
Simulation time 144041586 ps
CPU time 0.84 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207524 kb
Host smart-3eaaab82-b6a8-4299-b81a-bc967ff669a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
05185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2266605185
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3463193222
Short name T819
Test name
Test status
Simulation time 251144124 ps
CPU time 1.06 seconds
Started Aug 09 05:32:59 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207508 kb
Host smart-4c7b3944-64e3-4715-af28-250a1cba34c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
93222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3463193222
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1240934295
Short name T1654
Test name
Test status
Simulation time 3897828576 ps
CPU time 37.52 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:33:30 PM PDT 24
Peak memory 224240 kb
Host smart-be1f132f-e119-4b0d-97e1-b231b25908d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1240934295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1240934295
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.738286079
Short name T2794
Test name
Test status
Simulation time 7937597021 ps
CPU time 99.64 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 207652 kb
Host smart-1d064bcc-00a0-4f48-bafa-788866ca367c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=738286079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.738286079
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.210001951
Short name T940
Test name
Test status
Simulation time 195628355 ps
CPU time 0.91 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207448 kb
Host smart-f200d2f4-7650-4fcc-99fd-ed8b8adeed88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000
1951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.210001951
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1442769422
Short name T2558
Test name
Test status
Simulation time 7864028343 ps
CPU time 11.85 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 207760 kb
Host smart-9b3d6214-1736-4a2e-b4ff-5a55f26bb11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
69422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1442769422
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1010426823
Short name T3127
Test name
Test status
Simulation time 8562898685 ps
CPU time 11.46 seconds
Started Aug 09 05:32:37 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207764 kb
Host smart-5dfacc64-c96e-4605-bf75-6fdd3df277f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
26823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1010426823
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.75825146
Short name T1428
Test name
Test status
Simulation time 6100104925 ps
CPU time 51.77 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:33:31 PM PDT 24
Peak memory 219216 kb
Host smart-916c9509-8468-4338-80fd-b32814777cf1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=75825146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.75825146
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1346773204
Short name T2120
Test name
Test status
Simulation time 2837570622 ps
CPU time 80.39 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 215900 kb
Host smart-b815d4f7-6274-4903-a3de-e70e707716b7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1346773204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1346773204
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1609933734
Short name T780
Test name
Test status
Simulation time 242687810 ps
CPU time 0.97 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207396 kb
Host smart-f88b4791-0497-4de7-aa2b-f2357d54d304
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1609933734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1609933734
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3161898934
Short name T699
Test name
Test status
Simulation time 200144160 ps
CPU time 0.97 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207508 kb
Host smart-4c14b0ae-4007-4377-afdb-6574b0e830d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
98934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3161898934
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3816225011
Short name T2404
Test name
Test status
Simulation time 3577763671 ps
CPU time 33.86 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:33:18 PM PDT 24
Peak memory 215992 kb
Host smart-63040261-a6ae-4e2b-91db-4ddca11c1c26
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3816225011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3816225011
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1345872955
Short name T1401
Test name
Test status
Simulation time 165422083 ps
CPU time 0.9 seconds
Started Aug 09 05:32:47 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207796 kb
Host smart-78f1ceb4-81cd-4251-afca-62c20a48e915
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1345872955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1345872955
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.120428060
Short name T1309
Test name
Test status
Simulation time 148839824 ps
CPU time 0.91 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207412 kb
Host smart-f806dd13-50cd-4e6f-bfdf-cd6e4b3c54e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12042
8060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.120428060
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2331750381
Short name T2608
Test name
Test status
Simulation time 192247170 ps
CPU time 0.93 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207384 kb
Host smart-e51251ae-fefa-421b-a2b9-7aaf7544adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317
50381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2331750381
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.483428374
Short name T2074
Test name
Test status
Simulation time 183502090 ps
CPU time 0.92 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207476 kb
Host smart-4f9b3a10-fe71-47ef-b876-77072c816945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48342
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.483428374
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3112659975
Short name T2491
Test name
Test status
Simulation time 185018428 ps
CPU time 0.9 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207456 kb
Host smart-8bb9b31d-4e29-4055-b43c-8709c288cc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31126
59975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3112659975
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2757753200
Short name T1626
Test name
Test status
Simulation time 218015036 ps
CPU time 0.9 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207504 kb
Host smart-f6054862-d800-4889-967a-7917b5013554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27577
53200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2757753200
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2216219008
Short name T156
Test name
Test status
Simulation time 173634853 ps
CPU time 0.93 seconds
Started Aug 09 05:32:37 PM PDT 24
Finished Aug 09 05:32:38 PM PDT 24
Peak memory 207440 kb
Host smart-e28ad163-148c-4fbb-966b-f38c80e4d002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22162
19008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2216219008
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.836383622
Short name T1959
Test name
Test status
Simulation time 255383483 ps
CPU time 1.03 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207452 kb
Host smart-aca5f076-be73-48f0-bb8e-d64d67046432
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=836383622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.836383622
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3426406391
Short name T32
Test name
Test status
Simulation time 152471508 ps
CPU time 0.86 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207420 kb
Host smart-b5113e55-6811-4850-b95f-77b7e03c2884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
06391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3426406391
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2888001474
Short name T24
Test name
Test status
Simulation time 34588701 ps
CPU time 0.7 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207408 kb
Host smart-a863db16-13d3-4650-a987-33f68f9a6339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880
01474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2888001474
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1599273395
Short name T265
Test name
Test status
Simulation time 8296448238 ps
CPU time 20.01 seconds
Started Aug 09 05:32:36 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 215964 kb
Host smart-ac5b1c4c-5f95-4ff9-a2a5-faaa759a0b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
73395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1599273395
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1814377568
Short name T3301
Test name
Test status
Simulation time 209011188 ps
CPU time 0.93 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207380 kb
Host smart-bf1247d1-ce99-4057-9743-0a44eefc809d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
77568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1814377568
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.166280339
Short name T1128
Test name
Test status
Simulation time 178839658 ps
CPU time 0.93 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207488 kb
Host smart-88e78e6b-c0a4-4c23-8162-f98ea3242b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
0339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.166280339
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3476138915
Short name T3444
Test name
Test status
Simulation time 181451774 ps
CPU time 0.9 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207552 kb
Host smart-f4720efa-29cc-4613-83be-83da2ea3294e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34761
38915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3476138915
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.163479036
Short name T81
Test name
Test status
Simulation time 204255231 ps
CPU time 0.98 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207552 kb
Host smart-118c38a6-07c3-4e39-9d33-304b29eb3a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16347
9036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.163479036
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1408787413
Short name T3531
Test name
Test status
Simulation time 142832692 ps
CPU time 0.83 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207432 kb
Host smart-0790dccc-2e34-4a80-98a7-b9cc951a3f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
87413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1408787413
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.3616401196
Short name T1761
Test name
Test status
Simulation time 364684841 ps
CPU time 1.37 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207492 kb
Host smart-0d1c2e6f-b552-4232-a720-c32fe51b495c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
01196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.3616401196
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3145418203
Short name T3235
Test name
Test status
Simulation time 163886517 ps
CPU time 0.85 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207424 kb
Host smart-fe6d4878-f6ce-4f5d-bf93-e0a88044d4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
18203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3145418203
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4277099562
Short name T1494
Test name
Test status
Simulation time 152698738 ps
CPU time 0.84 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207800 kb
Host smart-48a81705-331a-4e96-8576-e747573b6469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
99562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4277099562
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3872901200
Short name T563
Test name
Test status
Simulation time 209560877 ps
CPU time 0.99 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207504 kb
Host smart-a7fc0d8e-97f2-40d2-a784-c71c9e51b100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38729
01200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3872901200
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.833490896
Short name T3150
Test name
Test status
Simulation time 3158817453 ps
CPU time 93.13 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 217748 kb
Host smart-8beca963-3aa7-4ea5-bfdd-90b34b7dd637
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=833490896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.833490896
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2549626989
Short name T2516
Test name
Test status
Simulation time 177791065 ps
CPU time 0.91 seconds
Started Aug 09 05:32:40 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 207552 kb
Host smart-f6c2cb86-aaf9-4926-a40c-01c838ee46be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
26989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2549626989
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.459672037
Short name T2126
Test name
Test status
Simulation time 188856196 ps
CPU time 0.91 seconds
Started Aug 09 05:32:43 PM PDT 24
Finished Aug 09 05:32:44 PM PDT 24
Peak memory 207508 kb
Host smart-01b8e944-c769-4fad-a674-27923cebecec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45967
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.459672037
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1571086612
Short name T3624
Test name
Test status
Simulation time 1065051117 ps
CPU time 2.69 seconds
Started Aug 09 05:32:55 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207576 kb
Host smart-feb71793-5ea1-40e3-973d-e890ef715c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
86612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1571086612
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.911024623
Short name T2225
Test name
Test status
Simulation time 2362745334 ps
CPU time 18.06 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 216012 kb
Host smart-fe5d772d-4f68-48ab-85d0-7ed435b5dbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91102
4623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.911024623
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.2366555509
Short name T2018
Test name
Test status
Simulation time 165859018 ps
CPU time 0.9 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207404 kb
Host smart-565b13a8-cad0-4e35-b6bb-7610d9d9b6fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366555509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.2366555509
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.4015463737
Short name T2985
Test name
Test status
Simulation time 542430764 ps
CPU time 1.64 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 207432 kb
Host smart-6ab09d0d-1dae-4383-9e91-5f80918659fc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015463737 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.4015463737
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.4106951823
Short name T1745
Test name
Test status
Simulation time 486552649 ps
CPU time 1.53 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207412 kb
Host smart-756c52b7-32e8-49cd-9eeb-4fa9ab47ca91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106951823 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.4106951823
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.834241696
Short name T2693
Test name
Test status
Simulation time 500657550 ps
CPU time 1.45 seconds
Started Aug 09 05:33:54 PM PDT 24
Finished Aug 09 05:33:55 PM PDT 24
Peak memory 207520 kb
Host smart-8b66c285-c22f-4185-bd97-4633b2ec23c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834241696 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.834241696
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.3171140945
Short name T108
Test name
Test status
Simulation time 657128948 ps
CPU time 1.71 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 207484 kb
Host smart-e11ce40b-57b3-485e-838d-c9c9b54d652a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171140945 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.3171140945
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.1238020489
Short name T873
Test name
Test status
Simulation time 585994887 ps
CPU time 1.76 seconds
Started Aug 09 05:33:52 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 207480 kb
Host smart-2069ceab-89da-4b86-906d-f2735c499787
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238020489 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.1238020489
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.353406199
Short name T2129
Test name
Test status
Simulation time 656474545 ps
CPU time 1.63 seconds
Started Aug 09 05:34:11 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 207404 kb
Host smart-cf18b421-d909-405e-9ee0-c90fc24cb4af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353406199 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.353406199
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.2524783056
Short name T2286
Test name
Test status
Simulation time 523864623 ps
CPU time 1.7 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:17 PM PDT 24
Peak memory 207504 kb
Host smart-bb0824a8-8d1c-4295-9bbc-b47e4b9f0dcc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524783056 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.2524783056
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.2421472730
Short name T2570
Test name
Test status
Simulation time 634286043 ps
CPU time 1.78 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 207508 kb
Host smart-9e460413-8faa-4715-baf6-0068a16e035f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421472730 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.2421472730
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.2781170108
Short name T1093
Test name
Test status
Simulation time 511284326 ps
CPU time 1.55 seconds
Started Aug 09 05:34:03 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 207516 kb
Host smart-e58f611c-ef4c-4769-b92c-826819a1489d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781170108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.2781170108
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.3998243999
Short name T3137
Test name
Test status
Simulation time 526410493 ps
CPU time 1.51 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:34:09 PM PDT 24
Peak memory 207516 kb
Host smart-b1e8f21b-3486-481d-aad6-c51ace5d462c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998243999 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.3998243999
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.4209091437
Short name T2257
Test name
Test status
Simulation time 586617150 ps
CPU time 1.61 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 207360 kb
Host smart-c46652b3-1ae5-4088-ac9e-95f190c91769
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209091437 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.4209091437
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1932626557
Short name T2304
Test name
Test status
Simulation time 50874006 ps
CPU time 0.69 seconds
Started Aug 09 05:26:32 PM PDT 24
Finished Aug 09 05:26:33 PM PDT 24
Peak memory 207512 kb
Host smart-2827d2a8-5595-42f0-9485-845bf2c8687a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1932626557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1932626557
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1457940506
Short name T1896
Test name
Test status
Simulation time 5118100002 ps
CPU time 7.51 seconds
Started Aug 09 05:26:30 PM PDT 24
Finished Aug 09 05:26:38 PM PDT 24
Peak memory 215904 kb
Host smart-2f6a6d14-6ec1-46e3-bd46-a2b50a0ef7b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457940506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.1457940506
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.795608003
Short name T3582
Test name
Test status
Simulation time 19629544948 ps
CPU time 23.2 seconds
Started Aug 09 05:26:25 PM PDT 24
Finished Aug 09 05:26:48 PM PDT 24
Peak memory 207804 kb
Host smart-d3ef3ddf-315e-46c5-9e0b-a7df5fc5c416
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=795608003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.795608003
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1300568431
Short name T2393
Test name
Test status
Simulation time 26148492765 ps
CPU time 32.15 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 215884 kb
Host smart-f6d44d7b-8799-4576-802a-84032f7c3116
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300568431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.1300568431
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.731641362
Short name T3509
Test name
Test status
Simulation time 190794358 ps
CPU time 0.86 seconds
Started Aug 09 05:26:29 PM PDT 24
Finished Aug 09 05:26:30 PM PDT 24
Peak memory 207388 kb
Host smart-0d2c4c44-d90c-4c7a-947e-e57eab375e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73164
1362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.731641362
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3411800718
Short name T78
Test name
Test status
Simulation time 140807333 ps
CPU time 0.88 seconds
Started Aug 09 05:26:31 PM PDT 24
Finished Aug 09 05:26:32 PM PDT 24
Peak memory 207392 kb
Host smart-40c2fb95-4fad-4ac3-b94b-be77a14ffa7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34118
00718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3411800718
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1805688379
Short name T3588
Test name
Test status
Simulation time 605957778 ps
CPU time 2.07 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:26:40 PM PDT 24
Peak memory 207484 kb
Host smart-09cc27c8-8737-4615-8525-2784540e33d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
88379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1805688379
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2204872476
Short name T2559
Test name
Test status
Simulation time 660676942 ps
CPU time 1.91 seconds
Started Aug 09 05:26:29 PM PDT 24
Finished Aug 09 05:26:32 PM PDT 24
Peak memory 207716 kb
Host smart-440578a2-a49b-4809-aeaf-000a52d02c9f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2204872476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2204872476
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.905478191
Short name T3173
Test name
Test status
Simulation time 24995128558 ps
CPU time 42.37 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207756 kb
Host smart-53ac3404-8c75-4036-a048-8bfa88ecaba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90547
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.905478191
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.3066630290
Short name T2684
Test name
Test status
Simulation time 3497750690 ps
CPU time 28.29 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:54 PM PDT 24
Peak memory 207860 kb
Host smart-d132fdcc-9685-4c2e-83c9-73048f4db804
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066630290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3066630290
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.739300002
Short name T1386
Test name
Test status
Simulation time 548939705 ps
CPU time 1.49 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207324 kb
Host smart-8acc7950-c19b-4504-8db6-3386de097704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73930
0002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.739300002
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3190755487
Short name T18
Test name
Test status
Simulation time 138642586 ps
CPU time 0.86 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207472 kb
Host smart-38585858-cf1d-440c-8e01-79c1b73286a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
55487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3190755487
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1332719533
Short name T901
Test name
Test status
Simulation time 30533975 ps
CPU time 0.68 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207468 kb
Host smart-4e13ab19-3896-4f58-b070-9127d54dba8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13327
19533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1332719533
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.645345220
Short name T2034
Test name
Test status
Simulation time 965442352 ps
CPU time 2.7 seconds
Started Aug 09 05:26:30 PM PDT 24
Finished Aug 09 05:26:33 PM PDT 24
Peak memory 207744 kb
Host smart-836eb611-b8c3-4369-acfa-47a508be8748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64534
5220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.645345220
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.445557621
Short name T3483
Test name
Test status
Simulation time 231668904 ps
CPU time 2.46 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:31 PM PDT 24
Peak memory 207612 kb
Host smart-ea5044ac-659e-4a20-9719-63658d036c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44555
7621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.445557621
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2212304829
Short name T2000
Test name
Test status
Simulation time 209706555 ps
CPU time 1.08 seconds
Started Aug 09 05:26:34 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 215772 kb
Host smart-32ff548d-9761-45c7-8442-9d2bb769be5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2212304829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2212304829
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.897380455
Short name T1153
Test name
Test status
Simulation time 138157726 ps
CPU time 0.82 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207504 kb
Host smart-71f33e61-0e71-40f1-8360-67def26044c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89738
0455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.897380455
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.332525599
Short name T823
Test name
Test status
Simulation time 241508709 ps
CPU time 1.05 seconds
Started Aug 09 05:26:31 PM PDT 24
Finished Aug 09 05:26:32 PM PDT 24
Peak memory 207432 kb
Host smart-b5398ad8-ce50-4485-8f50-ad9beb92398f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33252
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.332525599
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.2524999182
Short name T3187
Test name
Test status
Simulation time 4781693839 ps
CPU time 139.98 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:28:47 PM PDT 24
Peak memory 218440 kb
Host smart-d8ab78a8-6bce-474e-875d-b6850bf1327d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2524999182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.2524999182
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3687047973
Short name T551
Test name
Test status
Simulation time 10091342968 ps
CPU time 71.14 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 207744 kb
Host smart-329e0173-6729-4280-9255-8d09b7da2e6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3687047973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3687047973
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.147162184
Short name T1674
Test name
Test status
Simulation time 156102124 ps
CPU time 0.87 seconds
Started Aug 09 05:26:25 PM PDT 24
Finished Aug 09 05:26:26 PM PDT 24
Peak memory 207484 kb
Host smart-c076d530-9a2c-4e42-9a50-9e85bcfa531e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14716
2184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.147162184
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3985570584
Short name T3345
Test name
Test status
Simulation time 10707178449 ps
CPU time 17.51 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:26:55 PM PDT 24
Peak memory 216040 kb
Host smart-e7898766-5a62-42ae-bd01-f7b7de13ae21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855
70584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3985570584
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3498086697
Short name T680
Test name
Test status
Simulation time 4149835645 ps
CPU time 6.77 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207768 kb
Host smart-819dee16-f729-49ec-a946-ec735ee3795f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
86697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3498086697
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3983637630
Short name T3120
Test name
Test status
Simulation time 3394655769 ps
CPU time 27.42 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 218576 kb
Host smart-b9a6f7e0-c341-4e5b-9a02-c17a4dbf70f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3983637630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3983637630
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3953855947
Short name T694
Test name
Test status
Simulation time 2232582279 ps
CPU time 60.42 seconds
Started Aug 09 05:26:29 PM PDT 24
Finished Aug 09 05:27:29 PM PDT 24
Peak memory 217428 kb
Host smart-7606872d-58ab-49e3-b1e3-2cba2e8d2284
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3953855947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3953855947
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2749241404
Short name T1855
Test name
Test status
Simulation time 240653694 ps
CPU time 1.01 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:29 PM PDT 24
Peak memory 207492 kb
Host smart-03fd0b88-9981-4383-9903-14673847c53c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2749241404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2749241404
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3826033190
Short name T1069
Test name
Test status
Simulation time 199764966 ps
CPU time 0.96 seconds
Started Aug 09 05:26:31 PM PDT 24
Finished Aug 09 05:26:32 PM PDT 24
Peak memory 207480 kb
Host smart-dc05b9dd-d870-4b38-9edb-9190fc83d579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38260
33190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3826033190
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.1535290531
Short name T968
Test name
Test status
Simulation time 2797721384 ps
CPU time 23.09 seconds
Started Aug 09 05:26:28 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 216068 kb
Host smart-f5a1ada7-1b94-426d-adc1-007977fc0482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15352
90531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.1535290531
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.629806160
Short name T3402
Test name
Test status
Simulation time 2567590656 ps
CPU time 22.65 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 218716 kb
Host smart-48930dec-d48c-40bb-b2de-95264eeb4265
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=629806160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.629806160
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2361484378
Short name T3346
Test name
Test status
Simulation time 2305374347 ps
CPU time 22.81 seconds
Started Aug 09 05:26:31 PM PDT 24
Finished Aug 09 05:26:54 PM PDT 24
Peak memory 216100 kb
Host smart-aa307413-eccc-40b8-8666-ba93ea6b593d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2361484378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2361484378
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2542944434
Short name T3481
Test name
Test status
Simulation time 170945366 ps
CPU time 1.01 seconds
Started Aug 09 05:26:34 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207388 kb
Host smart-861070aa-7b27-4692-990a-aaebd815916d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2542944434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2542944434
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1925469101
Short name T2073
Test name
Test status
Simulation time 159145183 ps
CPU time 0.88 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:27 PM PDT 24
Peak memory 207480 kb
Host smart-995af878-d70a-469d-980f-a00a85f8cd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19254
69101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1925469101
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1923832640
Short name T138
Test name
Test status
Simulation time 207740498 ps
CPU time 0.95 seconds
Started Aug 09 05:26:26 PM PDT 24
Finished Aug 09 05:26:27 PM PDT 24
Peak memory 207508 kb
Host smart-08a4e0b1-a09a-4f48-ba33-5753c873f0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19238
32640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1923832640
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1877727836
Short name T2440
Test name
Test status
Simulation time 198890741 ps
CPU time 0.97 seconds
Started Aug 09 05:26:27 PM PDT 24
Finished Aug 09 05:26:28 PM PDT 24
Peak memory 207552 kb
Host smart-e28c3a0a-4a2f-4239-a2df-bcfa67df7837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
27836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1877727836
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3626338099
Short name T3457
Test name
Test status
Simulation time 162806408 ps
CPU time 0.85 seconds
Started Aug 09 05:26:34 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207436 kb
Host smart-ef657ee9-37ff-45ee-a1e7-52107315a85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36263
38099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3626338099
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.823873108
Short name T1578
Test name
Test status
Simulation time 176557444 ps
CPU time 0.9 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207504 kb
Host smart-a11e8c29-f6eb-4ed3-9807-8ae4a2efdfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82387
3108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.823873108
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.393019244
Short name T2560
Test name
Test status
Simulation time 146965399 ps
CPU time 0.87 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207508 kb
Host smart-e73928f2-ddf4-4c54-a725-08a8987e8840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.393019244
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1249672140
Short name T2807
Test name
Test status
Simulation time 179334855 ps
CPU time 0.99 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207520 kb
Host smart-8512fe3e-e903-400d-aac6-ade2fb9ce20a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1249672140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1249672140
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2555947888
Short name T800
Test name
Test status
Simulation time 146061836 ps
CPU time 0.84 seconds
Started Aug 09 05:26:36 PM PDT 24
Finished Aug 09 05:26:37 PM PDT 24
Peak memory 207556 kb
Host smart-b3a06d31-db60-4a5d-9df1-b36b15c2222e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
47888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2555947888
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2632517084
Short name T1696
Test name
Test status
Simulation time 61180076 ps
CPU time 0.73 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207360 kb
Host smart-91f1b874-d48f-490b-9c07-75844e4b91f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325
17084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2632517084
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2943537373
Short name T2768
Test name
Test status
Simulation time 11976192417 ps
CPU time 28.44 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 216004 kb
Host smart-49596c08-1ba8-4a7b-9a9d-3214f1146a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29435
37373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2943537373
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.579317999
Short name T3536
Test name
Test status
Simulation time 193949658 ps
CPU time 0.94 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207528 kb
Host smart-b47e721a-1536-46ec-a383-007ea60d5f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57931
7999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.579317999
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1291941971
Short name T911
Test name
Test status
Simulation time 233855978 ps
CPU time 0.99 seconds
Started Aug 09 05:26:37 PM PDT 24
Finished Aug 09 05:26:38 PM PDT 24
Peak memory 207484 kb
Host smart-34ac5bdb-886c-4326-b635-0821c09bbe11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
41971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1291941971
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2341664962
Short name T2754
Test name
Test status
Simulation time 3155719093 ps
CPU time 60.75 seconds
Started Aug 09 05:26:40 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 218056 kb
Host smart-70e95566-e317-4f82-8be8-70ae08c5c206
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341664962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2341664962
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.359937538
Short name T773
Test name
Test status
Simulation time 6753460980 ps
CPU time 88.15 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 219728 kb
Host smart-f1bfb32a-b235-4c92-9e72-cd0bab48d7f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359937538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.359937538
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.187871607
Short name T982
Test name
Test status
Simulation time 10230535966 ps
CPU time 74.04 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:27:55 PM PDT 24
Peak memory 218824 kb
Host smart-785c5ab6-7940-4d91-9a0b-1ec8ed351859
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=187871607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.187871607
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.4229675222
Short name T2646
Test name
Test status
Simulation time 224160952 ps
CPU time 0.98 seconds
Started Aug 09 05:26:40 PM PDT 24
Finished Aug 09 05:26:41 PM PDT 24
Peak memory 207472 kb
Host smart-27e9549d-ed5e-4c9d-af86-83b3d8db9b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42296
75222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.4229675222
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.462262849
Short name T856
Test name
Test status
Simulation time 172326024 ps
CPU time 0.88 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:26:39 PM PDT 24
Peak memory 207480 kb
Host smart-f70c645c-f44a-4462-b169-bc918334acc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46226
2849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.462262849
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.1654104941
Short name T3098
Test name
Test status
Simulation time 20153419546 ps
CPU time 27.65 seconds
Started Aug 09 05:26:39 PM PDT 24
Finished Aug 09 05:27:07 PM PDT 24
Peak memory 207480 kb
Host smart-9ef6412f-dc09-4d89-b566-4a2a3e11c8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16541
04941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.1654104941
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2713930929
Short name T1267
Test name
Test status
Simulation time 140029891 ps
CPU time 0.83 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:26:39 PM PDT 24
Peak memory 207480 kb
Host smart-559d865a-2c8e-4c51-b38d-471e4b9daafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27139
30929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2713930929
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.3537486332
Short name T307
Test name
Test status
Simulation time 252477164 ps
CPU time 1.07 seconds
Started Aug 09 05:26:34 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207552 kb
Host smart-b8089de2-d9b8-4822-b762-67e84ab2b8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35374
86332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.3537486332
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1626061081
Short name T3216
Test name
Test status
Simulation time 144583395 ps
CPU time 0.85 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:26:36 PM PDT 24
Peak memory 207476 kb
Host smart-898f73cd-ce89-4a17-a4ce-c91d3b0cfe95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16260
61081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1626061081
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.674987201
Short name T1349
Test name
Test status
Simulation time 217364009 ps
CPU time 1.03 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207460 kb
Host smart-341121d3-bbf6-4f20-8e08-c5abfcf75927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67498
7201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.674987201
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1197749256
Short name T2298
Test name
Test status
Simulation time 307802908 ps
CPU time 1.09 seconds
Started Aug 09 05:26:36 PM PDT 24
Finished Aug 09 05:26:37 PM PDT 24
Peak memory 207428 kb
Host smart-1cb3e0b9-9453-4dbf-8ff0-64e4ab369f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11977
49256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1197749256
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2917712779
Short name T888
Test name
Test status
Simulation time 3206329965 ps
CPU time 97.45 seconds
Started Aug 09 05:26:33 PM PDT 24
Finished Aug 09 05:28:11 PM PDT 24
Peak memory 217976 kb
Host smart-e94c3720-67d1-449b-ba6d-30fc247df745
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2917712779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2917712779
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.891359135
Short name T3305
Test name
Test status
Simulation time 171741126 ps
CPU time 0.84 seconds
Started Aug 09 05:26:40 PM PDT 24
Finished Aug 09 05:26:41 PM PDT 24
Peak memory 207496 kb
Host smart-5dcac202-195f-4334-9e51-ca0152f34abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89135
9135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.891359135
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1039529345
Short name T1869
Test name
Test status
Simulation time 159965593 ps
CPU time 0.85 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:26:39 PM PDT 24
Peak memory 207408 kb
Host smart-81b386e7-62d5-4fb7-b3bf-23997aa47177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
29345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1039529345
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2286269861
Short name T2674
Test name
Test status
Simulation time 269593359 ps
CPU time 1.06 seconds
Started Aug 09 05:26:33 PM PDT 24
Finished Aug 09 05:26:35 PM PDT 24
Peak memory 207348 kb
Host smart-7abb022e-484f-43e7-84c7-bbe004698239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
69861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2286269861
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2796471570
Short name T2008
Test name
Test status
Simulation time 2765398813 ps
CPU time 83.69 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 217484 kb
Host smart-f972f5f0-07e7-4f64-b3f4-6773506d7912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27964
71570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2796471570
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.3630860176
Short name T2212
Test name
Test status
Simulation time 6387613801 ps
CPU time 45.77 seconds
Started Aug 09 05:26:34 PM PDT 24
Finished Aug 09 05:27:20 PM PDT 24
Peak memory 207672 kb
Host smart-fea8d89d-4c1f-4ca5-93cf-17ff255aa164
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630860176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.3630860176
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.51297046
Short name T2580
Test name
Test status
Simulation time 584901816 ps
CPU time 1.6 seconds
Started Aug 09 05:26:37 PM PDT 24
Finished Aug 09 05:26:39 PM PDT 24
Peak memory 207568 kb
Host smart-a4ee0ac6-061d-44bd-9453-f19f127e1d97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51297046 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.51297046
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.2814107358
Short name T440
Test name
Test status
Simulation time 539948825 ps
CPU time 1.4 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207340 kb
Host smart-e92e5a6e-f931-40be-a84f-1638b3b9857a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2814107358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.2814107358
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.2737389095
Short name T1708
Test name
Test status
Simulation time 481399775 ps
CPU time 1.49 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207432 kb
Host smart-e5067c27-43ef-4c00-9920-b7e2deeb2baa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737389095 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.2737389095
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.1237653772
Short name T392
Test name
Test status
Simulation time 330668590 ps
CPU time 1.26 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 207468 kb
Host smart-d16cee5a-6077-4c9a-9f61-19e32f4a7da9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1237653772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.1237653772
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.2553566299
Short name T3566
Test name
Test status
Simulation time 507918137 ps
CPU time 1.46 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207456 kb
Host smart-17cf0c46-3bc2-4c37-a110-5a090aac25f2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553566299 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.2553566299
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.2037941349
Short name T3361
Test name
Test status
Simulation time 214848768 ps
CPU time 0.98 seconds
Started Aug 09 05:33:08 PM PDT 24
Finished Aug 09 05:33:09 PM PDT 24
Peak memory 207512 kb
Host smart-f779eaa1-03e8-405d-b4e4-30c8ce7e4815
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2037941349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.2037941349
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.1856373442
Short name T1354
Test name
Test status
Simulation time 540111853 ps
CPU time 1.47 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207556 kb
Host smart-972c5473-22f0-49bb-a176-5f9f1acf15bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856373442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.1856373442
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.3824643490
Short name T452
Test name
Test status
Simulation time 359547681 ps
CPU time 1.24 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 207388 kb
Host smart-bcbeeab1-1016-427b-b759-132edc03cf6a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3824643490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3824643490
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.1857645168
Short name T2854
Test name
Test status
Simulation time 683863541 ps
CPU time 1.78 seconds
Started Aug 09 05:32:41 PM PDT 24
Finished Aug 09 05:32:42 PM PDT 24
Peak memory 207468 kb
Host smart-7f1b4e78-362b-40f5-b1d1-b25657740b0b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857645168 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.1857645168
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.1480229164
Short name T418
Test name
Test status
Simulation time 334785813 ps
CPU time 1.13 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207456 kb
Host smart-ceb05abc-ae59-4b84-a0b5-3dd421b5b5cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1480229164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.1480229164
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.2752750728
Short name T2645
Test name
Test status
Simulation time 474981650 ps
CPU time 1.47 seconds
Started Aug 09 05:32:39 PM PDT 24
Finished Aug 09 05:32:41 PM PDT 24
Peak memory 207528 kb
Host smart-b6bf9192-4127-4a23-99ee-fa63ae09e1df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752750728 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.2752750728
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.2506594372
Short name T1558
Test name
Test status
Simulation time 158689401 ps
CPU time 0.83 seconds
Started Aug 09 05:32:38 PM PDT 24
Finished Aug 09 05:32:39 PM PDT 24
Peak memory 207472 kb
Host smart-27c907b4-6bf1-4489-8b49-297355dcf1d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2506594372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.2506594372
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.4190502507
Short name T2621
Test name
Test status
Simulation time 515898960 ps
CPU time 1.66 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207400 kb
Host smart-ddbeed2f-6d3f-45b4-a1c1-c6587e6fd664
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190502507 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.4190502507
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.242029609
Short name T2342
Test name
Test status
Simulation time 277966455 ps
CPU time 1.01 seconds
Started Aug 09 05:32:45 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207492 kb
Host smart-b0a18619-3065-47d7-8f66-ea576251697e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=242029609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.242029609
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.2270932781
Short name T3329
Test name
Test status
Simulation time 578795004 ps
CPU time 1.48 seconds
Started Aug 09 05:32:45 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207428 kb
Host smart-ea29cdac-87dd-463d-b690-fe816d911e2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270932781 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.2270932781
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.1741480386
Short name T380
Test name
Test status
Simulation time 382359548 ps
CPU time 1.2 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207488 kb
Host smart-2d72b697-0e0e-46b5-94b7-6a0c293ed320
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1741480386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.1741480386
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.1766093690
Short name T1327
Test name
Test status
Simulation time 507627532 ps
CPU time 1.55 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207436 kb
Host smart-0b22bbb4-4621-4e56-b369-6e5d75549299
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766093690 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.1766093690
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.1592575905
Short name T500
Test name
Test status
Simulation time 526707457 ps
CPU time 1.57 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207468 kb
Host smart-9e72ec3c-d55d-4232-abd9-da94ce2194e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1592575905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.1592575905
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.3428556795
Short name T922
Test name
Test status
Simulation time 226866426 ps
CPU time 0.97 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207436 kb
Host smart-4a45acb6-b9d5-4830-b73b-c81028ba6d7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3428556795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.3428556795
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.2811121752
Short name T629
Test name
Test status
Simulation time 502802605 ps
CPU time 1.56 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207408 kb
Host smart-8e7b26e0-b864-4dbb-a073-2373f8e8d7ed
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811121752 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.2811121752
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.2256893794
Short name T978
Test name
Test status
Simulation time 93291420 ps
CPU time 0.72 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 207520 kb
Host smart-4cd9f794-c9d1-4e89-a4b4-1e1c24786086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2256893794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2256893794
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3199674198
Short name T1289
Test name
Test status
Simulation time 9150158655 ps
CPU time 12.07 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207740 kb
Host smart-bc428b2b-531d-48f9-b0d8-29d386d0592a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199674198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.3199674198
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2732193645
Short name T2624
Test name
Test status
Simulation time 21087414615 ps
CPU time 23.48 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:27:01 PM PDT 24
Peak memory 207832 kb
Host smart-1decc443-9733-432b-87ac-6d1e2f160470
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732193645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2732193645
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3305532844
Short name T1145
Test name
Test status
Simulation time 28973349941 ps
CPU time 34.71 seconds
Started Aug 09 05:26:38 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207764 kb
Host smart-229ceacf-5fa0-4855-8e56-de4b04126eb0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305532844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3305532844
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4189023727
Short name T960
Test name
Test status
Simulation time 156491010 ps
CPU time 0.85 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 207784 kb
Host smart-2517133f-d109-45ca-9e35-b16d60344e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41890
23727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4189023727
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1906469618
Short name T1474
Test name
Test status
Simulation time 150382043 ps
CPU time 0.88 seconds
Started Aug 09 05:26:44 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 207504 kb
Host smart-3eb14ab8-0717-4dcb-aed9-e66748308d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19064
69618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1906469618
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1356225666
Short name T775
Test name
Test status
Simulation time 210546790 ps
CPU time 1.01 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207484 kb
Host smart-5e713f3f-bead-4e7a-8321-f303ed387a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13562
25666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1356225666
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1686405188
Short name T3503
Test name
Test status
Simulation time 464747665 ps
CPU time 1.54 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207384 kb
Host smart-cd0cb547-579a-4225-8c6b-6d4b1ae85a98
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1686405188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1686405188
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.125803372
Short name T3348
Test name
Test status
Simulation time 22114208552 ps
CPU time 37.08 seconds
Started Aug 09 05:26:44 PM PDT 24
Finished Aug 09 05:27:21 PM PDT 24
Peak memory 207672 kb
Host smart-6250a953-eaa4-4987-8dd4-341591dea2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12580
3372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.125803372
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.2314010744
Short name T3006
Test name
Test status
Simulation time 4319462759 ps
CPU time 38.98 seconds
Started Aug 09 05:26:37 PM PDT 24
Finished Aug 09 05:27:16 PM PDT 24
Peak memory 207776 kb
Host smart-6656dc65-468c-4fd1-946f-0cf08f0f3d42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314010744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2314010744
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3558995538
Short name T2243
Test name
Test status
Simulation time 591457367 ps
CPU time 1.58 seconds
Started Aug 09 05:26:37 PM PDT 24
Finished Aug 09 05:26:39 PM PDT 24
Peak memory 207476 kb
Host smart-413bcdbb-c436-44b5-beb2-364ea6d1a071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
95538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3558995538
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3437813868
Short name T1321
Test name
Test status
Simulation time 170152174 ps
CPU time 0.87 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:26:48 PM PDT 24
Peak memory 207380 kb
Host smart-d53d11e5-ab53-4044-81c5-cc5f1cb195ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34378
13868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3437813868
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1152463642
Short name T1789
Test name
Test status
Simulation time 33762049 ps
CPU time 0.7 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207520 kb
Host smart-48e55e5d-9107-43fc-a767-c0328522121a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
63642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1152463642
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3472560068
Short name T3236
Test name
Test status
Simulation time 846849144 ps
CPU time 2.22 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:26:47 PM PDT 24
Peak memory 207636 kb
Host smart-e3d5b8c0-1460-4f32-bb03-e0332adbffac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725
60068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3472560068
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.3263190971
Short name T388
Test name
Test status
Simulation time 572248730 ps
CPU time 1.43 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 207464 kb
Host smart-7434a337-5b56-48af-a7e3-4a2f80695778
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3263190971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.3263190971
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2229032829
Short name T1760
Test name
Test status
Simulation time 345698899 ps
CPU time 2.37 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 207616 kb
Host smart-f6b04e95-3101-4b66-9395-aac45c08d818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
32829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2229032829
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2409714961
Short name T1091
Test name
Test status
Simulation time 233125869 ps
CPU time 1.14 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 215928 kb
Host smart-b2d7c48a-d4ca-4886-b3ba-db2af1361b11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2409714961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2409714961
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.10969022
Short name T2810
Test name
Test status
Simulation time 146387082 ps
CPU time 0.81 seconds
Started Aug 09 05:26:40 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207480 kb
Host smart-9c760d42-5045-45f4-9daf-4c4bf93751fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10969
022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.10969022
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.57542204
Short name T2606
Test name
Test status
Simulation time 230623648 ps
CPU time 1.01 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207508 kb
Host smart-e5c405ee-bafe-42fe-8365-292e35d427f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57542
204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.57542204
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.267371464
Short name T662
Test name
Test status
Simulation time 4362603563 ps
CPU time 134.81 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:28:57 PM PDT 24
Peak memory 218424 kb
Host smart-0d2c54a3-3afd-4f71-8997-7d2c1af54267
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=267371464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.267371464
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.1885190133
Short name T1454
Test name
Test status
Simulation time 7427233141 ps
CPU time 96.24 seconds
Started Aug 09 05:26:44 PM PDT 24
Finished Aug 09 05:28:20 PM PDT 24
Peak memory 207692 kb
Host smart-8970e19d-70c4-49d3-bcf4-f47fd2e1bd28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1885190133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1885190133
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3173789977
Short name T3201
Test name
Test status
Simulation time 212815816 ps
CPU time 0.92 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207428 kb
Host smart-27c304b1-5382-4493-af41-1bb055340d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
89977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3173789977
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1386588655
Short name T2838
Test name
Test status
Simulation time 9916329350 ps
CPU time 14.56 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207820 kb
Host smart-285ac35c-3d20-4e64-b7c8-41770379034b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13865
88655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1386588655
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1190242699
Short name T964
Test name
Test status
Simulation time 4353582507 ps
CPU time 6.28 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:26:48 PM PDT 24
Peak memory 216084 kb
Host smart-d1ddfbf8-bccf-4a32-984f-58694ae2b9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11902
42699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1190242699
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2764455228
Short name T2079
Test name
Test status
Simulation time 5237799287 ps
CPU time 41.41 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 219324 kb
Host smart-975086db-8a3c-4b82-9600-78db6f7a1904
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2764455228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2764455228
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3540828120
Short name T1231
Test name
Test status
Simulation time 2609222025 ps
CPU time 74.58 seconds
Started Aug 09 05:26:46 PM PDT 24
Finished Aug 09 05:28:01 PM PDT 24
Peak memory 216068 kb
Host smart-ef5ed08c-2c66-4674-83b4-294f4d7ce13e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3540828120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3540828120
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.307364534
Short name T1970
Test name
Test status
Simulation time 239450836 ps
CPU time 1 seconds
Started Aug 09 05:26:46 PM PDT 24
Finished Aug 09 05:26:47 PM PDT 24
Peak memory 207504 kb
Host smart-38cc4f31-f721-4e01-a3e4-54b692fd1687
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=307364534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.307364534
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3749625009
Short name T1947
Test name
Test status
Simulation time 199888631 ps
CPU time 0.92 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:26:49 PM PDT 24
Peak memory 207452 kb
Host smart-2a205fa2-cda1-4e2d-becb-dd6d0dcd9001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37496
25009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3749625009
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.23593497
Short name T1343
Test name
Test status
Simulation time 3079249505 ps
CPU time 86.5 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:28:09 PM PDT 24
Peak memory 217708 kb
Host smart-6f16a275-c031-4bfd-9c3f-23abd8820120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23593
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.23593497
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2925239143
Short name T162
Test name
Test status
Simulation time 3233889057 ps
CPU time 27.7 seconds
Started Aug 09 05:26:40 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 224256 kb
Host smart-49b511d5-8832-4cb2-9903-a56f24fdc15c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2925239143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2925239143
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.856949757
Short name T180
Test name
Test status
Simulation time 3427984272 ps
CPU time 34.18 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:27:16 PM PDT 24
Peak memory 216028 kb
Host smart-17c63527-4e45-4907-bc83-2da10f7b654a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=856949757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.856949757
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1961882809
Short name T1345
Test name
Test status
Simulation time 199747136 ps
CPU time 0.97 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207496 kb
Host smart-85d5808f-b3f0-465d-9315-8262da6bf643
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1961882809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1961882809
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2492438152
Short name T3144
Test name
Test status
Simulation time 151316557 ps
CPU time 0.92 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207556 kb
Host smart-bde5d84f-c57c-49cd-a8d2-d1f9826ee2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24924
38152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2492438152
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2993363748
Short name T3628
Test name
Test status
Simulation time 223525811 ps
CPU time 1.01 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 207384 kb
Host smart-8ad6260a-f98c-41e5-aa68-49c1f6884678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
63748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2993363748
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1100337680
Short name T1898
Test name
Test status
Simulation time 179025581 ps
CPU time 0.97 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:26:43 PM PDT 24
Peak memory 207552 kb
Host smart-c3dafb37-b8cb-436b-b388-50ea178db0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11003
37680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1100337680
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2439596943
Short name T2677
Test name
Test status
Simulation time 182776644 ps
CPU time 0.91 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:26:46 PM PDT 24
Peak memory 207432 kb
Host smart-4659d9d3-a9b6-420c-ae9c-1dc801531378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
96943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2439596943
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.703042408
Short name T1399
Test name
Test status
Simulation time 160070792 ps
CPU time 0.87 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207752 kb
Host smart-570b9aa5-2812-4e40-8bc4-f658c5f57eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70304
2408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.703042408
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3998948569
Short name T1340
Test name
Test status
Simulation time 201616872 ps
CPU time 0.91 seconds
Started Aug 09 05:26:44 PM PDT 24
Finished Aug 09 05:26:46 PM PDT 24
Peak memory 207436 kb
Host smart-faaa50bc-3e76-465b-a8d7-145d39296d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39989
48569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3998948569
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.163656047
Short name T3069
Test name
Test status
Simulation time 236118296 ps
CPU time 1.01 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:26:46 PM PDT 24
Peak memory 207516 kb
Host smart-5af56038-2fa7-4a38-bab9-55791e8bca9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=163656047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.163656047
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.379879989
Short name T1229
Test name
Test status
Simulation time 153616018 ps
CPU time 0.88 seconds
Started Aug 09 05:26:41 PM PDT 24
Finished Aug 09 05:26:42 PM PDT 24
Peak memory 207428 kb
Host smart-5efb083a-be2e-4121-95a9-c5b62e0d4247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
9989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.379879989
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1073464180
Short name T611
Test name
Test status
Simulation time 38627583 ps
CPU time 0.7 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 207400 kb
Host smart-2fb01678-2bbb-4451-8df4-98a0815d90a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10734
64180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1073464180
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3880188952
Short name T87
Test name
Test status
Simulation time 21279340132 ps
CPU time 54 seconds
Started Aug 09 05:26:42 PM PDT 24
Finished Aug 09 05:27:36 PM PDT 24
Peak memory 215920 kb
Host smart-c1083b6e-5479-43c2-a0fe-6cef474da48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
88952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3880188952
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1599239282
Short name T2582
Test name
Test status
Simulation time 166381248 ps
CPU time 0.93 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:26:46 PM PDT 24
Peak memory 207452 kb
Host smart-3a519c74-471c-4c4b-b12b-43c7dfc46d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
39282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1599239282
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1715894324
Short name T986
Test name
Test status
Simulation time 167568379 ps
CPU time 0.9 seconds
Started Aug 09 05:26:44 PM PDT 24
Finished Aug 09 05:26:45 PM PDT 24
Peak memory 207472 kb
Host smart-ec07e7b8-a9a9-4034-b0c5-7a80bbda7a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
94324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1715894324
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3424950265
Short name T2867
Test name
Test status
Simulation time 7001924270 ps
CPU time 51.17 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 218416 kb
Host smart-c6ec20bf-da01-4779-91a8-1e664ca6652d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424950265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3424950265
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3273385651
Short name T1266
Test name
Test status
Simulation time 5826931753 ps
CPU time 18.57 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 224216 kb
Host smart-404f7b80-b06d-4527-847b-7b04b0de3a97
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3273385651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3273385651
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.520692380
Short name T2757
Test name
Test status
Simulation time 10010318905 ps
CPU time 50.29 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 224220 kb
Host smart-39409ae6-13a3-444a-8870-68a056de40e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=520692380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.520692380
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.153860840
Short name T3242
Test name
Test status
Simulation time 215152147 ps
CPU time 0.93 seconds
Started Aug 09 05:26:45 PM PDT 24
Finished Aug 09 05:26:46 PM PDT 24
Peak memory 207356 kb
Host smart-6ca50743-e68d-48ed-a9e4-35f0ba42638b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15386
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.153860840
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1351330130
Short name T1901
Test name
Test status
Simulation time 217929623 ps
CPU time 1.04 seconds
Started Aug 09 05:26:43 PM PDT 24
Finished Aug 09 05:26:44 PM PDT 24
Peak memory 207544 kb
Host smart-5b321ef1-c8ee-45ac-9876-f9968da75bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513
30130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1351330130
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.634017738
Short name T1609
Test name
Test status
Simulation time 20169747920 ps
CPU time 26.76 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:27:15 PM PDT 24
Peak memory 207516 kb
Host smart-24f5d8a8-d61a-44b3-8006-81a9dcf7fa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63401
7738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.634017738
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3085720259
Short name T1066
Test name
Test status
Simulation time 184169204 ps
CPU time 0.91 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207384 kb
Host smart-632ada41-8159-4a58-a9b5-bf8d3cae3efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
20259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3085720259
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.1897094256
Short name T2778
Test name
Test status
Simulation time 381060226 ps
CPU time 1.28 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207516 kb
Host smart-f1196881-6e99-4d0f-a143-50d03056d4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18970
94256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1897094256
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4108348328
Short name T907
Test name
Test status
Simulation time 151649024 ps
CPU time 0.85 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:26:49 PM PDT 24
Peak memory 207472 kb
Host smart-33722126-3041-4be0-a0df-8b381c90a61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
48328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4108348328
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2696705458
Short name T3154
Test name
Test status
Simulation time 153591837 ps
CPU time 0.82 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:26:49 PM PDT 24
Peak memory 207504 kb
Host smart-7c029398-7e0d-432b-a4b7-541040d872de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26967
05458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2696705458
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3809237846
Short name T85
Test name
Test status
Simulation time 232863598 ps
CPU time 1.06 seconds
Started Aug 09 05:26:51 PM PDT 24
Finished Aug 09 05:26:53 PM PDT 24
Peak memory 207464 kb
Host smart-d7aa3252-5b71-4f8e-aa02-f689230955b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
37846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3809237846
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2549288843
Short name T1512
Test name
Test status
Simulation time 2674371151 ps
CPU time 28.23 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:27:17 PM PDT 24
Peak memory 217888 kb
Host smart-44190b47-7a48-40cf-9c5d-f7280073946e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2549288843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2549288843
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2534358858
Short name T2444
Test name
Test status
Simulation time 241510497 ps
CPU time 0.94 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207504 kb
Host smart-463fd05c-76fd-4e00-8a83-ff3700d241b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25343
58858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2534358858
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3877755855
Short name T2107
Test name
Test status
Simulation time 156925523 ps
CPU time 0.86 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207792 kb
Host smart-e131e3e1-b749-49c6-9ef7-7c9462b1adff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38777
55855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3877755855
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.2376933670
Short name T1595
Test name
Test status
Simulation time 1185952646 ps
CPU time 2.92 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:26:54 PM PDT 24
Peak memory 207680 kb
Host smart-d591447b-af36-4411-b294-2e68374916e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23769
33670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2376933670
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2209555656
Short name T3290
Test name
Test status
Simulation time 3667758427 ps
CPU time 106.95 seconds
Started Aug 09 05:26:52 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 217520 kb
Host smart-8fdcb60b-61cf-4fba-b8e6-72c4fa9eb40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095
55656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2209555656
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.4008254890
Short name T593
Test name
Test status
Simulation time 2237567920 ps
CPU time 13.3 seconds
Started Aug 09 05:26:35 PM PDT 24
Finished Aug 09 05:26:48 PM PDT 24
Peak memory 207836 kb
Host smart-10a4a474-54a1-4319-a5ce-b84e60aa4b7c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008254890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.4008254890
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.2890105013
Short name T1480
Test name
Test status
Simulation time 643869522 ps
CPU time 1.73 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207552 kb
Host smart-7a49d17c-4c57-47a9-a91f-42d4b4ab4a9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890105013 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.2890105013
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.4007457967
Short name T403
Test name
Test status
Simulation time 421868920 ps
CPU time 1.33 seconds
Started Aug 09 05:32:47 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207376 kb
Host smart-a8e0d3e3-3d84-4e34-a717-12a7a2b635a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4007457967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.4007457967
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.776044506
Short name T1646
Test name
Test status
Simulation time 475256794 ps
CPU time 1.49 seconds
Started Aug 09 05:32:55 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 207456 kb
Host smart-e5fc028d-7aa4-4b2e-ae42-facfc389af9b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776044506 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.776044506
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.2899332674
Short name T3188
Test name
Test status
Simulation time 175299201 ps
CPU time 0.91 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207392 kb
Host smart-174508b3-60ce-4d20-a77b-d10b913e8c27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2899332674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.2899332674
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.2286158523
Short name T782
Test name
Test status
Simulation time 487449482 ps
CPU time 1.51 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207512 kb
Host smart-d3750620-af38-4b5c-8c7d-982d3c642e2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286158523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.2286158523
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.3317187677
Short name T1199
Test name
Test status
Simulation time 235990116 ps
CPU time 1.07 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207488 kb
Host smart-5d42e742-3de0-47e8-807c-ca0789d23b7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3317187677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.3317187677
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.1859954409
Short name T1841
Test name
Test status
Simulation time 502418280 ps
CPU time 1.52 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 207460 kb
Host smart-366aaf2e-985f-416d-a359-f0348412c4d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859954409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.1859954409
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.3557242415
Short name T401
Test name
Test status
Simulation time 653776385 ps
CPU time 1.64 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207556 kb
Host smart-11e88dc2-252d-4eba-939f-a63c7e6debaf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3557242415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.3557242415
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.39469389
Short name T2765
Test name
Test status
Simulation time 459769980 ps
CPU time 1.4 seconds
Started Aug 09 05:32:45 PM PDT 24
Finished Aug 09 05:32:46 PM PDT 24
Peak memory 207532 kb
Host smart-dcc997d8-c3aa-4624-a4aa-d19c3842bc1a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39469389 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.39469389
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.106600312
Short name T3362
Test name
Test status
Simulation time 169480501 ps
CPU time 0.93 seconds
Started Aug 09 05:32:42 PM PDT 24
Finished Aug 09 05:32:43 PM PDT 24
Peak memory 207528 kb
Host smart-1095bade-2a8c-4e47-9490-6686d3123e0e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=106600312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.106600312
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.1049621061
Short name T614
Test name
Test status
Simulation time 594096692 ps
CPU time 1.62 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207476 kb
Host smart-33aa5c92-1356-439d-b382-77cf82578a94
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049621061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.1049621061
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.1724504349
Short name T2376
Test name
Test status
Simulation time 511288847 ps
CPU time 1.53 seconds
Started Aug 09 05:33:07 PM PDT 24
Finished Aug 09 05:33:09 PM PDT 24
Peak memory 207808 kb
Host smart-1dfde63a-6497-4e87-b331-ffda9ae05441
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724504349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.1724504349
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.1301942370
Short name T428
Test name
Test status
Simulation time 573167442 ps
CPU time 1.49 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207344 kb
Host smart-be8ecc41-4ffa-420d-9283-f7ca58afff1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1301942370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.1301942370
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.993509182
Short name T2888
Test name
Test status
Simulation time 520997457 ps
CPU time 1.64 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:56 PM PDT 24
Peak memory 207432 kb
Host smart-c2132959-6732-4e74-93df-ba702c6f3766
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993509182 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.993509182
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.1359114703
Short name T464
Test name
Test status
Simulation time 282233985 ps
CPU time 1.14 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207368 kb
Host smart-4ed6c379-cf73-4d17-9cf5-7dd723809869
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1359114703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.1359114703
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.2841381841
Short name T2883
Test name
Test status
Simulation time 561044986 ps
CPU time 1.65 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207412 kb
Host smart-ac7a1de5-c689-4ce5-a3e3-8329713a2b67
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841381841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.2841381841
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.4022417561
Short name T1481
Test name
Test status
Simulation time 502020354 ps
CPU time 1.44 seconds
Started Aug 09 05:32:57 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207512 kb
Host smart-58e2e728-b555-4c57-8a7d-ac6d06ef30a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022417561 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.4022417561
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.3520248626
Short name T442
Test name
Test status
Simulation time 513754081 ps
CPU time 1.37 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207460 kb
Host smart-555244ae-e88e-441a-a615-94629c824eee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3520248626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.3520248626
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.1715202914
Short name T597
Test name
Test status
Simulation time 496907948 ps
CPU time 1.42 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207416 kb
Host smart-d62ea0eb-f321-4d72-aa80-724c873a37dc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715202914 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.1715202914
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2197696159
Short name T1542
Test name
Test status
Simulation time 53880527 ps
CPU time 0.78 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:26:59 PM PDT 24
Peak memory 207560 kb
Host smart-7f128620-7aa4-4475-9e51-d0eb326b566d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2197696159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2197696159
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2912051778
Short name T3280
Test name
Test status
Simulation time 4278187215 ps
CPU time 6.74 seconds
Started Aug 09 05:26:53 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 215988 kb
Host smart-b900028b-291c-4395-b594-bee1fbb08f0a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912051778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.2912051778
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1046110577
Short name T14
Test name
Test status
Simulation time 19991628841 ps
CPU time 24.79 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:27:16 PM PDT 24
Peak memory 207640 kb
Host smart-ff5b5279-d681-4406-a161-c39d7c150754
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046110577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1046110577
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.443119170
Short name T1581
Test name
Test status
Simulation time 30190412752 ps
CPU time 34.42 seconds
Started Aug 09 05:26:47 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207732 kb
Host smart-1a95eaaa-63e9-4dd8-9cfc-fb7305191d25
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443119170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_resume.443119170
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2107726629
Short name T2513
Test name
Test status
Simulation time 201271480 ps
CPU time 0.96 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207544 kb
Host smart-143f8000-e848-4486-a446-d80295556f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21077
26629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2107726629
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1395606227
Short name T735
Test name
Test status
Simulation time 140092159 ps
CPU time 0.8 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207496 kb
Host smart-da0defac-111f-4f68-9492-53b0b55c06eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13956
06227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1395606227
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2709241351
Short name T766
Test name
Test status
Simulation time 341129749 ps
CPU time 1.38 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:26:59 PM PDT 24
Peak memory 207444 kb
Host smart-e1abc2c4-61da-48dc-b1a1-35dc98ec31df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
41351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2709241351
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1616401183
Short name T1146
Test name
Test status
Simulation time 467694727 ps
CPU time 1.72 seconds
Started Aug 09 05:26:55 PM PDT 24
Finished Aug 09 05:26:56 PM PDT 24
Peak memory 207456 kb
Host smart-1f0d22f6-d49c-485e-af7a-05b9973a95e7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1616401183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1616401183
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2277539663
Short name T2494
Test name
Test status
Simulation time 1501507575 ps
CPU time 9.9 seconds
Started Aug 09 05:26:52 PM PDT 24
Finished Aug 09 05:27:02 PM PDT 24
Peak memory 207580 kb
Host smart-2515458c-ff9f-43f8-afb9-a6f68f4f1dd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277539663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2277539663
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1595551182
Short name T354
Test name
Test status
Simulation time 767015135 ps
CPU time 1.73 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207464 kb
Host smart-a409f8b8-91e6-4857-82da-152ee69f655d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955
51182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1595551182
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3386998757
Short name T2345
Test name
Test status
Simulation time 156062262 ps
CPU time 0.85 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207384 kb
Host smart-c176899e-cff5-47fc-ba63-18756e256169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33869
98757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3386998757
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.1606964734
Short name T2715
Test name
Test status
Simulation time 67350482 ps
CPU time 0.73 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207464 kb
Host smart-32601069-696b-4334-b866-071013d04fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16069
64734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1606964734
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1690334917
Short name T3577
Test name
Test status
Simulation time 1043473326 ps
CPU time 2.61 seconds
Started Aug 09 05:26:54 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207588 kb
Host smart-136cb01a-2610-46ca-9147-bc5ca3d3a70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16903
34917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1690334917
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.2834467850
Short name T429
Test name
Test status
Simulation time 619651943 ps
CPU time 1.63 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:26:51 PM PDT 24
Peak memory 207468 kb
Host smart-bece6fa6-f8b9-4ce9-b1d7-d5de60a7c752
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2834467850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.2834467850
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1963281186
Short name T3040
Test name
Test status
Simulation time 228454138 ps
CPU time 2.52 seconds
Started Aug 09 05:26:47 PM PDT 24
Finished Aug 09 05:26:49 PM PDT 24
Peak memory 207672 kb
Host smart-9003baef-6b42-4b34-9e33-59a9ce419df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19632
81186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1963281186
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3715458745
Short name T1564
Test name
Test status
Simulation time 228593263 ps
CPU time 1.2 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 216164 kb
Host smart-a0e0a75c-fc20-4b2f-847f-4c97337efa05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3715458745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3715458745
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1662819098
Short name T3357
Test name
Test status
Simulation time 155964747 ps
CPU time 0.84 seconds
Started Aug 09 05:26:54 PM PDT 24
Finished Aug 09 05:26:54 PM PDT 24
Peak memory 207392 kb
Host smart-12da47e2-8350-47e2-b655-82aab143b8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
19098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1662819098
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3166065695
Short name T540
Test name
Test status
Simulation time 224868493 ps
CPU time 1.05 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:26:50 PM PDT 24
Peak memory 207504 kb
Host smart-86683864-d129-4ebf-9173-cef904edd671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
65695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3166065695
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1749137646
Short name T2870
Test name
Test status
Simulation time 4985913072 ps
CPU time 148.95 seconds
Started Aug 09 05:26:54 PM PDT 24
Finished Aug 09 05:29:23 PM PDT 24
Peak memory 224252 kb
Host smart-34a5984d-9ab7-44d6-8bd4-00c56d874057
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1749137646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1749137646
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3320291868
Short name T1588
Test name
Test status
Simulation time 10905254836 ps
CPU time 69.57 seconds
Started Aug 09 05:26:48 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 207764 kb
Host smart-2fdc93b3-2d8c-48b7-98f8-bac310477b13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3320291868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3320291868
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2884131215
Short name T2363
Test name
Test status
Simulation time 182539470 ps
CPU time 0.87 seconds
Started Aug 09 05:26:51 PM PDT 24
Finished Aug 09 05:26:52 PM PDT 24
Peak memory 207428 kb
Host smart-245ffced-98df-4a38-8d24-f23bc1fee7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28841
31215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2884131215
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.4070907387
Short name T2260
Test name
Test status
Simulation time 26208555610 ps
CPU time 33.83 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:37 PM PDT 24
Peak memory 215924 kb
Host smart-aa88f7f6-91f0-4eb1-9b1b-c8ef86a636e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709
07387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.4070907387
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1516340409
Short name T2464
Test name
Test status
Simulation time 9042324290 ps
CPU time 11.44 seconds
Started Aug 09 05:26:53 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207776 kb
Host smart-bdcd1793-6d84-4056-a68e-84d6168089cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
40409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1516340409
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1565746490
Short name T181
Test name
Test status
Simulation time 4028059618 ps
CPU time 30.97 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 224192 kb
Host smart-f200437d-62c6-4d9f-98fe-d40789f9fe49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1565746490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1565746490
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.155812966
Short name T1324
Test name
Test status
Simulation time 1761115997 ps
CPU time 17.28 seconds
Started Aug 09 05:26:49 PM PDT 24
Finished Aug 09 05:27:07 PM PDT 24
Peak memory 215952 kb
Host smart-f91e38c1-4cc6-4659-9963-0ddc1f0ab758
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=155812966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.155812966
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3861919029
Short name T2252
Test name
Test status
Simulation time 242500535 ps
CPU time 1.02 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207552 kb
Host smart-b9a126ab-6aa1-43df-93ee-e3b5a4b9791b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3861919029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3861919029
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.307809344
Short name T3583
Test name
Test status
Simulation time 254203112 ps
CPU time 1 seconds
Started Aug 09 05:26:53 PM PDT 24
Finished Aug 09 05:26:54 PM PDT 24
Peak memory 207520 kb
Host smart-fbd851de-4b62-4a31-9557-6069181bd76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780
9344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.307809344
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3032553508
Short name T2488
Test name
Test status
Simulation time 2424662903 ps
CPU time 26.32 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:27:17 PM PDT 24
Peak memory 217212 kb
Host smart-75e1ee4e-1815-4b3e-bdf1-1e25313c826a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30325
53508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3032553508
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2834074480
Short name T2176
Test name
Test status
Simulation time 2539220624 ps
CPU time 27.22 seconds
Started Aug 09 05:26:50 PM PDT 24
Finished Aug 09 05:27:18 PM PDT 24
Peak memory 223988 kb
Host smart-a9bda4e5-75be-4b6f-ab8c-48dafd680402
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2834074480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2834074480
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3007702202
Short name T5
Test name
Test status
Simulation time 2191375224 ps
CPU time 61.52 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:28:04 PM PDT 24
Peak memory 216000 kb
Host smart-4c72b1c6-e063-4b14-96c1-f8f4f2b85740
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3007702202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3007702202
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.911111476
Short name T1926
Test name
Test status
Simulation time 159964366 ps
CPU time 0.87 seconds
Started Aug 09 05:27:01 PM PDT 24
Finished Aug 09 05:27:01 PM PDT 24
Peak memory 207448 kb
Host smart-9c1fdea1-3818-406b-8637-bb16135dcc85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=911111476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.911111476
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3892558166
Short name T3076
Test name
Test status
Simulation time 152588876 ps
CPU time 0.85 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207440 kb
Host smart-40fcf9fd-8b63-4086-add3-a6bc347e921c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
58166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3892558166
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3067863659
Short name T144
Test name
Test status
Simulation time 225297947 ps
CPU time 1.05 seconds
Started Aug 09 05:27:01 PM PDT 24
Finished Aug 09 05:27:02 PM PDT 24
Peak memory 207412 kb
Host smart-2e73f7e9-1407-47fd-83ac-eca1c312d046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
63659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3067863659
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1466804803
Short name T993
Test name
Test status
Simulation time 154548646 ps
CPU time 0.88 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 207424 kb
Host smart-92fe90e1-043a-4158-9bb3-ebdd2352c0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14668
04803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1466804803
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3451643741
Short name T1019
Test name
Test status
Simulation time 201814070 ps
CPU time 0.91 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207456 kb
Host smart-ba36cdb0-4db6-4200-9fb6-e8147155f774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
43741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3451643741
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2413875653
Short name T3202
Test name
Test status
Simulation time 164955284 ps
CPU time 0.89 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207556 kb
Host smart-e5f6bb34-11d1-4484-8aa8-7bb40df4b1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
75653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2413875653
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.142788478
Short name T179
Test name
Test status
Simulation time 150812967 ps
CPU time 0.89 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207432 kb
Host smart-6bd228c3-639c-40b5-a815-2826eaeb05a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14278
8478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.142788478
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1015327395
Short name T580
Test name
Test status
Simulation time 230599155 ps
CPU time 1.01 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207460 kb
Host smart-1fed5a60-77bf-4e41-9706-9cccde7926f3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1015327395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1015327395
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3950949719
Short name T507
Test name
Test status
Simulation time 167921780 ps
CPU time 0.82 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207480 kb
Host smart-4fba5b5f-d099-4f15-85be-0dae0066bc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
49719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3950949719
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1133243705
Short name T663
Test name
Test status
Simulation time 59517076 ps
CPU time 0.77 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207460 kb
Host smart-8ed72760-1b1a-48df-977b-c9d01a065e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
43705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1133243705
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2981963935
Short name T3284
Test name
Test status
Simulation time 23243456985 ps
CPU time 62.65 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:28:02 PM PDT 24
Peak memory 215980 kb
Host smart-a6177dfa-776a-4638-9bf4-54740307ac2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819
63935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2981963935
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1208173353
Short name T573
Test name
Test status
Simulation time 190764165 ps
CPU time 0.94 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207500 kb
Host smart-827d974d-b5a2-4e97-8561-7ed49fdad200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081
73353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1208173353
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4056105434
Short name T1113
Test name
Test status
Simulation time 201339487 ps
CPU time 0.93 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207476 kb
Host smart-c1164b0a-53df-4dc1-a276-4ed8e15d50c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40561
05434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4056105434
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.6168880
Short name T933
Test name
Test status
Simulation time 6696148719 ps
CPU time 182.92 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:30:01 PM PDT 24
Peak memory 218304 kb
Host smart-ed80c74c-bb13-4e29-9beb-354992cb6e4d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=6168880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.6168880
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1496829850
Short name T1446
Test name
Test status
Simulation time 5577451254 ps
CPU time 26.95 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:29 PM PDT 24
Peak memory 219508 kb
Host smart-cf8cd8ba-9fc9-40c3-8f17-d50398695d48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1496829850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1496829850
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1434514062
Short name T2174
Test name
Test status
Simulation time 5511720179 ps
CPU time 20.17 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:17 PM PDT 24
Peak memory 224272 kb
Host smart-1b3cfeb7-9025-44bd-9819-a96642d947d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434514062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1434514062
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.752813379
Short name T665
Test name
Test status
Simulation time 209803427 ps
CPU time 0.93 seconds
Started Aug 09 05:26:54 PM PDT 24
Finished Aug 09 05:26:55 PM PDT 24
Peak memory 207480 kb
Host smart-18f9b0d2-a920-4019-a7cd-6c0ab6f1432b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75281
3379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.752813379
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3294211334
Short name T3434
Test name
Test status
Simulation time 167242379 ps
CPU time 0.95 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207504 kb
Host smart-aa9c217a-ed98-422a-bb9b-788c25b8212d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
11334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3294211334
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.2299031976
Short name T1754
Test name
Test status
Simulation time 20157704100 ps
CPU time 25.82 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 207636 kb
Host smart-75ba971a-be9f-4b84-a485-89aed221cec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990
31976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.2299031976
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3641302021
Short name T664
Test name
Test status
Simulation time 160496276 ps
CPU time 0.87 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207472 kb
Host smart-02bfa704-9cac-4d92-8355-af84deee8b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36413
02021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3641302021
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.3064034104
Short name T1924
Test name
Test status
Simulation time 324342396 ps
CPU time 1.22 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207472 kb
Host smart-2a303deb-06e4-477d-ba56-8f3c2b8644c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30640
34104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.3064034104
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.4127190396
Short name T2848
Test name
Test status
Simulation time 156421223 ps
CPU time 0.89 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:26:59 PM PDT 24
Peak memory 207476 kb
Host smart-e3e9ae64-47c4-42df-87ac-e89aa079cbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41271
90396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4127190396
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4269546352
Short name T2954
Test name
Test status
Simulation time 156391913 ps
CPU time 0.9 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207504 kb
Host smart-602c12aa-0550-40cc-a505-49f7ac83b2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
46352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4269546352
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2265013597
Short name T1249
Test name
Test status
Simulation time 214493216 ps
CPU time 1.04 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 207484 kb
Host smart-6f0fb242-98f9-49d8-b387-036836cdfbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22650
13597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2265013597
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2930688357
Short name T1155
Test name
Test status
Simulation time 2282318790 ps
CPU time 63 seconds
Started Aug 09 05:27:00 PM PDT 24
Finished Aug 09 05:28:03 PM PDT 24
Peak memory 224088 kb
Host smart-56781c8d-ab16-4a9d-8239-5ec320ad2b71
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2930688357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2930688357
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3459334945
Short name T2881
Test name
Test status
Simulation time 186481829 ps
CPU time 0.96 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207532 kb
Host smart-5c433767-243f-45fe-9d03-9b967647956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
34945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3459334945
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3571173875
Short name T884
Test name
Test status
Simulation time 218173227 ps
CPU time 0.93 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207460 kb
Host smart-31c507c6-9bee-4201-96cc-cc4fca39f217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35711
73875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3571173875
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.847973322
Short name T2416
Test name
Test status
Simulation time 1139672657 ps
CPU time 2.65 seconds
Started Aug 09 05:26:55 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207720 kb
Host smart-75a0265c-dd79-4f94-81dd-8c10d6a4509d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84797
3322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.847973322
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3949119013
Short name T1159
Test name
Test status
Simulation time 2963614744 ps
CPU time 81.37 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:28:19 PM PDT 24
Peak memory 217400 kb
Host smart-81ee67ab-faf5-48a6-8ea9-f834a37b0995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491
19013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3949119013
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.92806524
Short name T3501
Test name
Test status
Simulation time 615934228 ps
CPU time 5.31 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:27:02 PM PDT 24
Peak memory 207644 kb
Host smart-33f7f856-76ea-4985-aa49-50cf86e39fda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92806524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_h
andshake.92806524
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.381927857
Short name T848
Test name
Test status
Simulation time 613152405 ps
CPU time 1.65 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:26:59 PM PDT 24
Peak memory 207356 kb
Host smart-8aa07be2-065b-42d7-995e-c555338a8744
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381927857 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.381927857
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.3855264831
Short name T497
Test name
Test status
Simulation time 228432902 ps
CPU time 1.02 seconds
Started Aug 09 05:32:57 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207492 kb
Host smart-b819094a-40a2-47c5-b16e-df53cd2fa330
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3855264831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.3855264831
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.573651475
Short name T2999
Test name
Test status
Simulation time 475512901 ps
CPU time 1.33 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207460 kb
Host smart-667b12a8-1b52-44cb-acd2-cebf0cba138c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=573651475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.573651475
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.742080238
Short name T3265
Test name
Test status
Simulation time 560644530 ps
CPU time 1.72 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 207564 kb
Host smart-7b39bc94-377d-44cf-a8fa-a4b059eb16ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742080238 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.742080238
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.3711508218
Short name T415
Test name
Test status
Simulation time 594014339 ps
CPU time 1.46 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207416 kb
Host smart-a6c8ae47-1f8d-47f5-bcad-42806fe2df94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3711508218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.3711508218
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.2725495309
Short name T1161
Test name
Test status
Simulation time 661601480 ps
CPU time 1.72 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:47 PM PDT 24
Peak memory 207504 kb
Host smart-d092631b-1997-42c5-a028-0d8d3bf3704c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725495309 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.2725495309
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.1808110769
Short name T371
Test name
Test status
Simulation time 546484006 ps
CPU time 1.6 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207468 kb
Host smart-077e4edf-8f69-4dda-9e4f-daf40ae0c3f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1808110769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.1808110769
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.872834540
Short name T1257
Test name
Test status
Simulation time 515171615 ps
CPU time 1.53 seconds
Started Aug 09 05:32:55 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207376 kb
Host smart-2dc77702-25b5-42ec-91e9-e6aa5294e7a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872834540 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.872834540
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.4265805573
Short name T378
Test name
Test status
Simulation time 376252542 ps
CPU time 1.21 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207464 kb
Host smart-76b27948-031d-4901-9f05-f1b4291436c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4265805573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.4265805573
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.1352205127
Short name T2705
Test name
Test status
Simulation time 618219869 ps
CPU time 1.62 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:52 PM PDT 24
Peak memory 207460 kb
Host smart-bc52229b-f7cd-4918-9f1f-92111b881191
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352205127 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.1352205127
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.3749223176
Short name T414
Test name
Test status
Simulation time 401683066 ps
CPU time 1.21 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207260 kb
Host smart-605b1241-890d-4164-9253-13da19f97b5c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3749223176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.3749223176
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.3883275420
Short name T1206
Test name
Test status
Simulation time 483460948 ps
CPU time 1.56 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207520 kb
Host smart-db1d8e79-2c51-4291-80ff-5059e23936e0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883275420 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.3883275420
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.580884296
Short name T3052
Test name
Test status
Simulation time 198185348 ps
CPU time 0.94 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207516 kb
Host smart-22ff4895-47b3-4822-a84d-e9a11231bccd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=580884296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.580884296
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.2957355930
Short name T2941
Test name
Test status
Simulation time 594876463 ps
CPU time 1.62 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207400 kb
Host smart-50207b5b-3749-4a03-b33e-4d5fc3b61abd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957355930 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.2957355930
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.1299146249
Short name T2637
Test name
Test status
Simulation time 248779711 ps
CPU time 0.95 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 207416 kb
Host smart-0a35c051-fc82-492f-a01d-7e53918214e1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1299146249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.1299146249
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.4222155409
Short name T2756
Test name
Test status
Simulation time 651134049 ps
CPU time 1.67 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207556 kb
Host smart-2915a265-9288-42a1-9a94-cf846e0b5f7a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222155409 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.4222155409
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.2270302757
Short name T435
Test name
Test status
Simulation time 610621415 ps
CPU time 1.53 seconds
Started Aug 09 05:32:50 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207772 kb
Host smart-a8114ec9-8a3b-4f33-a055-8c74411cbe7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2270302757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.2270302757
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.3896627343
Short name T2536
Test name
Test status
Simulation time 530261933 ps
CPU time 1.6 seconds
Started Aug 09 05:32:46 PM PDT 24
Finished Aug 09 05:32:48 PM PDT 24
Peak memory 207460 kb
Host smart-10a4d616-764f-42a2-835a-4886a1629076
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896627343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.3896627343
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.3283034847
Short name T479
Test name
Test status
Simulation time 422547333 ps
CPU time 1.33 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207396 kb
Host smart-b75ecb5d-0d4a-4d38-85a3-36e9be6a500d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3283034847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.3283034847
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.4290967008
Short name T3219
Test name
Test status
Simulation time 418475309 ps
CPU time 1.33 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207520 kb
Host smart-30339ae4-b75d-4a26-a35d-11ab6febcd90
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290967008 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.4290967008
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1631600009
Short name T199
Test name
Test status
Simulation time 44479524 ps
CPU time 0.69 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207484 kb
Host smart-a51148bb-97c2-4121-86d2-0109acebc5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1631600009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1631600009
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3290354189
Short name T3214
Test name
Test status
Simulation time 6802828011 ps
CPU time 10.05 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 215960 kb
Host smart-fa910c2b-4700-4b9f-ad39-7f8465f8db04
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290354189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3290354189
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2134676324
Short name T1375
Test name
Test status
Simulation time 14285434229 ps
CPU time 18.58 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:15 PM PDT 24
Peak memory 216008 kb
Host smart-e154b314-dd3b-4315-8c8b-c7dd844acd17
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134676324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2134676324
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1623072654
Short name T953
Test name
Test status
Simulation time 26271876067 ps
CPU time 37.36 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 215836 kb
Host smart-459d5b0d-5853-475f-827f-e03135ec5066
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623072654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.1623072654
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2457886867
Short name T2841
Test name
Test status
Simulation time 191313360 ps
CPU time 1.04 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207508 kb
Host smart-63090cab-2ec4-4754-b108-a2c239eaafad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
86867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2457886867
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3961636230
Short name T1441
Test name
Test status
Simulation time 135532968 ps
CPU time 0.85 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 207480 kb
Host smart-76168e62-1d3d-4020-b08f-c3a4c4eeb7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
36230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3961636230
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.103192371
Short name T3203
Test name
Test status
Simulation time 293758466 ps
CPU time 1.14 seconds
Started Aug 09 05:27:01 PM PDT 24
Finished Aug 09 05:27:02 PM PDT 24
Peak memory 207500 kb
Host smart-7cb09d45-72c3-4a6a-8406-a80c18cd18ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10319
2371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.103192371
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1799700292
Short name T3321
Test name
Test status
Simulation time 404476142 ps
CPU time 1.34 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:26:57 PM PDT 24
Peak memory 207520 kb
Host smart-65bf9ad5-4473-4bac-bd2e-fff5c4a29c90
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1799700292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1799700292
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1721093934
Short name T3450
Test name
Test status
Simulation time 21703938418 ps
CPU time 32.95 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:30 PM PDT 24
Peak memory 207804 kb
Host smart-116770a1-c5f4-4d19-878f-6f3fbe06197f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17210
93934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1721093934
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.3247194448
Short name T1594
Test name
Test status
Simulation time 1104424175 ps
CPU time 8.72 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207628 kb
Host smart-f04d5f6f-a09f-4306-8bd9-ecd52ae19346
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247194448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.3247194448
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3806242400
Short name T3518
Test name
Test status
Simulation time 807218111 ps
CPU time 1.81 seconds
Started Aug 09 05:27:06 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207396 kb
Host smart-9d79a111-8b33-42c1-87bf-fb5eb328e080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38062
42400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3806242400
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2341233402
Short name T1350
Test name
Test status
Simulation time 137479011 ps
CPU time 0.84 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207464 kb
Host smart-c8360341-94ab-4343-9008-98b78da0f813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
33402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2341233402
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2831187494
Short name T3136
Test name
Test status
Simulation time 38575926 ps
CPU time 0.74 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207400 kb
Host smart-e5bbefcf-4c75-4cfb-ae0c-786f5d3d9b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28311
87494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2831187494
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3845284679
Short name T1163
Test name
Test status
Simulation time 844244261 ps
CPU time 2.32 seconds
Started Aug 09 05:26:55 PM PDT 24
Finished Aug 09 05:26:58 PM PDT 24
Peak memory 207684 kb
Host smart-48b9c30f-0224-416a-9f3d-15984dd4985c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
84679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3845284679
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.3008731377
Short name T2495
Test name
Test status
Simulation time 314309309 ps
CPU time 1.11 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207464 kb
Host smart-4161b765-ebe1-43ea-9083-a18fdfff7025
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3008731377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.3008731377
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1868335150
Short name T2522
Test name
Test status
Simulation time 327696314 ps
CPU time 2.05 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 207616 kb
Host smart-9919b4f2-124c-4e14-9783-39d1cb5964d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
35150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1868335150
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3651415314
Short name T1394
Test name
Test status
Simulation time 248763194 ps
CPU time 1.25 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 215772 kb
Host smart-508b84ab-1845-44f9-8a9d-79c7985ad48e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3651415314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3651415314
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.193506147
Short name T528
Test name
Test status
Simulation time 153680140 ps
CPU time 0.83 seconds
Started Aug 09 05:26:59 PM PDT 24
Finished Aug 09 05:27:00 PM PDT 24
Peak memory 207524 kb
Host smart-11966db0-c9bb-4c04-b3b9-35d8ec7f72cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19350
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.193506147
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.956784180
Short name T1010
Test name
Test status
Simulation time 170909363 ps
CPU time 0.88 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207476 kb
Host smart-7fba7a0e-1bed-48cf-9308-a41e41b17ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95678
4180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.956784180
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.1060636639
Short name T915
Test name
Test status
Simulation time 3581251635 ps
CPU time 103.08 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:28:55 PM PDT 24
Peak memory 218432 kb
Host smart-3287a7ed-e81d-4892-a5d2-3e0d072b918d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1060636639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1060636639
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.32088407
Short name T1569
Test name
Test status
Simulation time 9146585768 ps
CPU time 118.73 seconds
Started Aug 09 05:26:56 PM PDT 24
Finished Aug 09 05:28:55 PM PDT 24
Peak memory 207760 kb
Host smart-59acadc3-f19a-4ea5-bd03-a8822eb41775
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=32088407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.32088407
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.384658128
Short name T3556
Test name
Test status
Simulation time 222572304 ps
CPU time 0.97 seconds
Started Aug 09 05:26:58 PM PDT 24
Finished Aug 09 05:26:59 PM PDT 24
Peak memory 207476 kb
Host smart-096c5fed-bfef-4a95-808e-3ef4d86c3bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
8128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.384658128
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1164105142
Short name T3384
Test name
Test status
Simulation time 11933084666 ps
CPU time 17.29 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207736 kb
Host smart-600512f0-8136-4cf8-9b2e-d49d886c2f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
05142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1164105142
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1664599581
Short name T2812
Test name
Test status
Simulation time 4925022272 ps
CPU time 7.71 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 215876 kb
Host smart-dfd71662-2a8e-4790-baa0-a11a2116bd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16645
99581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1664599581
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3076279712
Short name T3197
Test name
Test status
Simulation time 2728405923 ps
CPU time 27.03 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 224260 kb
Host smart-6c7bead6-ab5e-4d20-bf1a-2609353b2098
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3076279712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3076279712
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.775237161
Short name T1852
Test name
Test status
Simulation time 2161354346 ps
CPU time 16.05 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 224136 kb
Host smart-f73c65cc-e8ac-46cc-bec0-6970f25ebea5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=775237161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.775237161
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.256569819
Short name T2361
Test name
Test status
Simulation time 257132902 ps
CPU time 1.07 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207548 kb
Host smart-9f37f1fe-3660-4727-b621-200d83b7a536
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=256569819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.256569819
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.661077411
Short name T523
Test name
Test status
Simulation time 259599803 ps
CPU time 1.04 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:06 PM PDT 24
Peak memory 207440 kb
Host smart-900e62b8-1700-4619-bd86-9d702d65c6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66107
7411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.661077411
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.219612361
Short name T2679
Test name
Test status
Simulation time 2843967307 ps
CPU time 28.39 seconds
Started Aug 09 05:27:06 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 224128 kb
Host smart-041b6ec8-b5fb-4804-8d2a-53e287a2d815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
2361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.219612361
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.234436136
Short name T1836
Test name
Test status
Simulation time 3017257233 ps
CPU time 33.59 seconds
Started Aug 09 05:27:05 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 217544 kb
Host smart-3b09eb6c-2d47-420b-900a-6123b6771ca3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=234436136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.234436136
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2614465625
Short name T1253
Test name
Test status
Simulation time 3947825968 ps
CPU time 113.3 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:29:01 PM PDT 24
Peak memory 217712 kb
Host smart-211947c5-5aca-4cbe-8816-db4d8e3552bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2614465625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2614465625
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1395535042
Short name T2483
Test name
Test status
Simulation time 175172043 ps
CPU time 0.98 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207796 kb
Host smart-fe282516-a559-4d9b-9a40-9d96aef3bf32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1395535042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1395535042
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1905817362
Short name T3416
Test name
Test status
Simulation time 158798853 ps
CPU time 0.87 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207556 kb
Host smart-84585e5e-ef3c-42d3-a721-be49369083c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19058
17362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1905817362
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.840969980
Short name T131
Test name
Test status
Simulation time 226802146 ps
CPU time 0.98 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207440 kb
Host smart-f5ce1928-4a11-4de7-9d89-0ba72adc4139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84096
9980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.840969980
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.746813454
Short name T2329
Test name
Test status
Simulation time 196766798 ps
CPU time 0.94 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207560 kb
Host smart-47dcaaf6-7a35-47c5-b7ff-b34142d3e377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74681
3454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.746813454
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.999321960
Short name T1710
Test name
Test status
Simulation time 198314634 ps
CPU time 1.01 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207504 kb
Host smart-449a496b-e43b-44c9-a5c6-5225a3c9b5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99932
1960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.999321960
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.216404881
Short name T836
Test name
Test status
Simulation time 142957377 ps
CPU time 0.83 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207504 kb
Host smart-d8ece76a-d9eb-4d8f-8819-adf0f260eac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21640
4881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.216404881
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.4092072947
Short name T1863
Test name
Test status
Simulation time 148363326 ps
CPU time 0.82 seconds
Started Aug 09 05:27:07 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207448 kb
Host smart-ca2ab6a7-b261-4baf-bf3f-79070fd15684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
72947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4092072947
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2724705184
Short name T1878
Test name
Test status
Simulation time 226260286 ps
CPU time 1 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207588 kb
Host smart-5c53df8e-59ef-4d25-a11b-b92b177481a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2724705184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2724705184
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.263972985
Short name T2324
Test name
Test status
Simulation time 157021210 ps
CPU time 0.86 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207520 kb
Host smart-d6586494-4f88-44fe-be72-93e51c02655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26397
2985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.263972985
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2619549165
Short name T1152
Test name
Test status
Simulation time 45114697 ps
CPU time 0.75 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207512 kb
Host smart-701b4e6b-8425-4160-8863-e323cbf4761b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26195
49165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2619549165
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3750187255
Short name T2692
Test name
Test status
Simulation time 19539121512 ps
CPU time 51.49 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 220492 kb
Host smart-5b5ae07f-2f80-458c-afba-67116edd3bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37501
87255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3750187255
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.475401300
Short name T1660
Test name
Test status
Simulation time 201236489 ps
CPU time 0.94 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207532 kb
Host smart-0c923960-9e5d-462e-8611-ce70299c4ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47540
1300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.475401300
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1757247219
Short name T3376
Test name
Test status
Simulation time 177345517 ps
CPU time 0.98 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207456 kb
Host smart-2dd32182-2ce8-459d-b600-3d698bae5195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17572
47219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1757247219
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4204349723
Short name T3207
Test name
Test status
Simulation time 5590609812 ps
CPU time 56.28 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:28:06 PM PDT 24
Peak memory 219268 kb
Host smart-d649e63f-6d81-428d-9ba1-2c7b85cfb7a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204349723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4204349723
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3314567330
Short name T2587
Test name
Test status
Simulation time 10670233379 ps
CPU time 56.73 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:28:05 PM PDT 24
Peak memory 219616 kb
Host smart-b8dc1d3b-1e8c-4aba-902c-21e1832dc96a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3314567330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3314567330
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3534770396
Short name T1419
Test name
Test status
Simulation time 6471611258 ps
CPU time 69.56 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:28:23 PM PDT 24
Peak memory 224088 kb
Host smart-872586d2-f791-46e5-b91a-900891847523
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534770396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3534770396
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2575841395
Short name T3156
Test name
Test status
Simulation time 191829936 ps
CPU time 0.93 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207548 kb
Host smart-fe6050ed-36d3-40ec-bbf6-b61645c6b74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758
41395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2575841395
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2959732620
Short name T642
Test name
Test status
Simulation time 162084338 ps
CPU time 0.89 seconds
Started Aug 09 05:27:06 PM PDT 24
Finished Aug 09 05:27:07 PM PDT 24
Peak memory 207500 kb
Host smart-a9691d52-24ef-4358-b3f2-2534d95780e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597
32620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2959732620
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.1947246575
Short name T3425
Test name
Test status
Simulation time 20204058041 ps
CPU time 25.9 seconds
Started Aug 09 05:27:06 PM PDT 24
Finished Aug 09 05:27:32 PM PDT 24
Peak memory 207580 kb
Host smart-bfcdaad9-8fc2-45a8-be52-9f83d7fc4fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
46575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.1947246575
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3904565413
Short name T2226
Test name
Test status
Simulation time 139351249 ps
CPU time 0.88 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207396 kb
Host smart-849fbbbe-a9c1-4e7d-ad65-47bc1da1e154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39045
65413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3904565413
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.3254463314
Short name T1739
Test name
Test status
Simulation time 392408987 ps
CPU time 1.26 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207480 kb
Host smart-4e8f3fc1-e034-4d96-80af-6bd69a80a040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32544
63314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.3254463314
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3630459691
Short name T2634
Test name
Test status
Simulation time 183155716 ps
CPU time 0.9 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207488 kb
Host smart-5e653ce7-04fe-4c07-8d8a-cd3766440ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
59691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3630459691
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.841617138
Short name T686
Test name
Test status
Simulation time 155580893 ps
CPU time 0.87 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207556 kb
Host smart-b28b795a-a4bd-450e-a989-380f4dddbbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84161
7138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.841617138
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2528970978
Short name T3308
Test name
Test status
Simulation time 261947972 ps
CPU time 1.1 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207556 kb
Host smart-03284349-c949-4abd-9fba-5a22a720dc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
70978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2528970978
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.694404556
Short name T325
Test name
Test status
Simulation time 3266368629 ps
CPU time 35.09 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:44 PM PDT 24
Peak memory 224236 kb
Host smart-2bb2aa33-161c-4400-b07e-fb99b2ff74d6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=694404556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.694404556
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4004452914
Short name T2326
Test name
Test status
Simulation time 205080332 ps
CPU time 0.99 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207528 kb
Host smart-0a23dc89-ccde-40a3-8477-305b3242d877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40044
52914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4004452914
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2230552901
Short name T1406
Test name
Test status
Simulation time 172659996 ps
CPU time 0.88 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207412 kb
Host smart-11f9d33f-e637-4702-9787-59627dfc5d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
52901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2230552901
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.153473872
Short name T1059
Test name
Test status
Simulation time 658761152 ps
CPU time 1.84 seconds
Started Aug 09 05:27:04 PM PDT 24
Finished Aug 09 05:27:06 PM PDT 24
Peak memory 207396 kb
Host smart-f3b70cb6-f2be-41d0-a35c-9f420e7ba7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
3872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.153473872
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.52446252
Short name T1487
Test name
Test status
Simulation time 1957303190 ps
CPU time 21.37 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 217472 kb
Host smart-60d01448-6318-4de2-a2f9-ee984b6b68e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52446
252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.52446252
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.4068796368
Short name T3548
Test name
Test status
Simulation time 923633943 ps
CPU time 19.57 seconds
Started Aug 09 05:26:57 PM PDT 24
Finished Aug 09 05:27:16 PM PDT 24
Peak memory 207716 kb
Host smart-52c6091e-d569-4ad1-9ff6-5bc63e345d96
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068796368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.4068796368
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.2846729217
Short name T955
Test name
Test status
Simulation time 445036162 ps
CPU time 1.42 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207476 kb
Host smart-486a99c4-c282-49b4-963e-c71c8da6ac23
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846729217 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.2846729217
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.1623874179
Short name T467
Test name
Test status
Simulation time 600908917 ps
CPU time 1.72 seconds
Started Aug 09 05:33:15 PM PDT 24
Finished Aug 09 05:33:16 PM PDT 24
Peak memory 207396 kb
Host smart-bb655fef-05e8-4815-9bb2-a712e9ff61de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1623874179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.1623874179
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.2690391140
Short name T794
Test name
Test status
Simulation time 614216256 ps
CPU time 1.68 seconds
Started Aug 09 05:32:53 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 207504 kb
Host smart-160ecdc2-fc40-4cf1-9736-b0acb9078312
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690391140 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.2690391140
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.738879275
Short name T468
Test name
Test status
Simulation time 472359784 ps
CPU time 1.46 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207508 kb
Host smart-a703b9aa-7a21-4f80-9169-c22b4cb85aa1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=738879275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.738879275
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.2546915576
Short name T2934
Test name
Test status
Simulation time 547495103 ps
CPU time 1.74 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207460 kb
Host smart-d1664731-550e-4453-9186-579ea540c480
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546915576 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.2546915576
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.2865688478
Short name T436
Test name
Test status
Simulation time 440804218 ps
CPU time 1.22 seconds
Started Aug 09 05:33:18 PM PDT 24
Finished Aug 09 05:33:19 PM PDT 24
Peak memory 207424 kb
Host smart-9efac680-837b-4bc4-98d4-28c54d821dd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2865688478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.2865688478
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.1193068075
Short name T2910
Test name
Test status
Simulation time 617241784 ps
CPU time 1.69 seconds
Started Aug 09 05:32:49 PM PDT 24
Finished Aug 09 05:32:51 PM PDT 24
Peak memory 207460 kb
Host smart-2f51cf0e-ad5b-4393-b729-aaf958bc9ee3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193068075 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.1193068075
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.2227887388
Short name T501
Test name
Test status
Simulation time 343674740 ps
CPU time 1.14 seconds
Started Aug 09 05:32:54 PM PDT 24
Finished Aug 09 05:32:55 PM PDT 24
Peak memory 207392 kb
Host smart-e36da306-2af3-46d1-a325-3ccff0569fde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2227887388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2227887388
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.3113747571
Short name T679
Test name
Test status
Simulation time 493883364 ps
CPU time 1.71 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207436 kb
Host smart-f049216a-9fec-4e1b-b0ba-37a01607464d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113747571 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.3113747571
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.4100145585
Short name T346
Test name
Test status
Simulation time 410594849 ps
CPU time 1.4 seconds
Started Aug 09 05:33:11 PM PDT 24
Finished Aug 09 05:33:13 PM PDT 24
Peak memory 207344 kb
Host smart-a6e358b3-9277-4f1d-9f03-af49c143bd6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4100145585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.4100145585
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.974213940
Short name T529
Test name
Test status
Simulation time 456443746 ps
CPU time 1.61 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:49 PM PDT 24
Peak memory 207464 kb
Host smart-56714ae0-e5ad-4132-80c8-fe4296194f79
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974213940 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.974213940
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.1512336014
Short name T456
Test name
Test status
Simulation time 615294385 ps
CPU time 1.48 seconds
Started Aug 09 05:32:57 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207436 kb
Host smart-c0fd3af1-99c2-46da-9d61-4d786074fa7c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1512336014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.1512336014
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.622462610
Short name T2014
Test name
Test status
Simulation time 528474255 ps
CPU time 1.54 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207424 kb
Host smart-4a61b544-ce0d-46e9-99a0-0780c50d1dd3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622462610 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.622462610
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.301371555
Short name T234
Test name
Test status
Simulation time 430049956 ps
CPU time 1.26 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207480 kb
Host smart-1775b10d-cf40-4e3b-ad3a-05dfe3bfc4d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=301371555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.301371555
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.218195932
Short name T3109
Test name
Test status
Simulation time 492481157 ps
CPU time 1.5 seconds
Started Aug 09 05:33:09 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207400 kb
Host smart-dfb002db-d4e7-400f-92c2-bf1a9d809bb0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218195932 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.218195932
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.425018253
Short name T450
Test name
Test status
Simulation time 263993922 ps
CPU time 1.06 seconds
Started Aug 09 05:32:59 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207468 kb
Host smart-f1d5fc35-ecff-433c-a034-1f1278ba8771
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=425018253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.425018253
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.1325728050
Short name T1108
Test name
Test status
Simulation time 448235312 ps
CPU time 1.42 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207512 kb
Host smart-a09ce9c4-7b74-48a2-b9d7-052479b16c70
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325728050 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.1325728050
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.836255821
Short name T426
Test name
Test status
Simulation time 498509014 ps
CPU time 1.51 seconds
Started Aug 09 05:32:48 PM PDT 24
Finished Aug 09 05:32:50 PM PDT 24
Peak memory 207392 kb
Host smart-96c8b6a7-7101-4613-9b4b-953a6aa5c2d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=836255821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.836255821
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.1659466828
Short name T2196
Test name
Test status
Simulation time 482491600 ps
CPU time 1.54 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207384 kb
Host smart-0925a308-2f69-48ad-8572-d258c6ca79fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659466828 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.1659466828
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.2605313656
Short name T2762
Test name
Test status
Simulation time 411506604 ps
CPU time 1.29 seconds
Started Aug 09 05:32:44 PM PDT 24
Finished Aug 09 05:32:45 PM PDT 24
Peak memory 207516 kb
Host smart-64de2dc7-73c0-4dc8-9dec-6d299c5fbf45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2605313656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.2605313656
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.2814140625
Short name T1845
Test name
Test status
Simulation time 545934352 ps
CPU time 1.68 seconds
Started Aug 09 05:32:56 PM PDT 24
Finished Aug 09 05:32:57 PM PDT 24
Peak memory 207560 kb
Host smart-eb02a911-fd4e-4d38-a631-f677a3c5dcff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814140625 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.2814140625
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1258565464
Short name T959
Test name
Test status
Simulation time 66257200 ps
CPU time 0.7 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:21 PM PDT 24
Peak memory 207460 kb
Host smart-279f1aec-ae87-4236-8d5b-59eeec4ba6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1258565464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1258565464
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1131508328
Short name T1826
Test name
Test status
Simulation time 9822407947 ps
CPU time 12.65 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207020 kb
Host smart-bafa56f3-bbe6-4540-914b-48e53279cdca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131508328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1131508328
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.841236429
Short name T1101
Test name
Test status
Simulation time 14272639710 ps
CPU time 18.34 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:28 PM PDT 24
Peak memory 215280 kb
Host smart-8794c1b6-079e-4c72-9b86-55111821f642
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=841236429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.841236429
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1165181917
Short name T790
Test name
Test status
Simulation time 29594802354 ps
CPU time 43.15 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:51 PM PDT 24
Peak memory 207828 kb
Host smart-d2a1f3ae-d8e5-4daa-b145-5c8838bd51f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165181917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1165181917
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2541507184
Short name T1755
Test name
Test status
Simulation time 179478539 ps
CPU time 0.92 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207408 kb
Host smart-fb3207b3-1c5d-47e3-bcf4-99f7a1e7e969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25415
07184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2541507184
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2729279052
Short name T774
Test name
Test status
Simulation time 154006021 ps
CPU time 0.91 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 207472 kb
Host smart-0900dc8b-1f83-42be-818b-635ed0782af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
79052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2729279052
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3997219204
Short name T1136
Test name
Test status
Simulation time 417263039 ps
CPU time 1.44 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:05 PM PDT 24
Peak memory 207392 kb
Host smart-4b39dbcd-ce14-4b60-90ac-c805c246eb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39972
19204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3997219204
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2516366738
Short name T2256
Test name
Test status
Simulation time 420951120 ps
CPU time 1.3 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:27:16 PM PDT 24
Peak memory 207468 kb
Host smart-56b8a04f-6212-4d62-a88e-5154a8746bf0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2516366738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2516366738
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1597898075
Short name T106
Test name
Test status
Simulation time 31940095312 ps
CPU time 47.85 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 207856 kb
Host smart-1f65aeca-8600-4ed8-8bda-e7423f7310d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15978
98075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1597898075
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.3132066066
Short name T1325
Test name
Test status
Simulation time 6312913745 ps
CPU time 43.08 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:53 PM PDT 24
Peak memory 207812 kb
Host smart-4f513105-428e-401d-9bd0-e88f0987cb76
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132066066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.3132066066
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3572429218
Short name T2800
Test name
Test status
Simulation time 698772354 ps
CPU time 1.65 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:10 PM PDT 24
Peak memory 207368 kb
Host smart-1df8269a-96dd-4fe0-a574-3664556a6363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35724
29218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3572429218
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.4247294625
Short name T1112
Test name
Test status
Simulation time 145095184 ps
CPU time 0.85 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:09 PM PDT 24
Peak memory 207528 kb
Host smart-544dece2-5f89-45e7-ab07-df0a9154cae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42472
94625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4247294625
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.249666666
Short name T669
Test name
Test status
Simulation time 82061154 ps
CPU time 0.74 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:08 PM PDT 24
Peak memory 207396 kb
Host smart-6fb0b84b-4a66-4691-969e-5ca1a117f179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24966
6666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.249666666
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.862614653
Short name T2828
Test name
Test status
Simulation time 941825331 ps
CPU time 2.55 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207652 kb
Host smart-9a6334b1-8f1f-4ddb-b601-cf86ec4b82a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86261
4653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.862614653
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.1126572491
Short name T444
Test name
Test status
Simulation time 657724034 ps
CPU time 1.91 seconds
Started Aug 09 05:27:09 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207520 kb
Host smart-72a30436-b510-466d-878a-4d220b6e7d59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1126572491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.1126572491
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2161105146
Short name T2953
Test name
Test status
Simulation time 304777859 ps
CPU time 1.77 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207648 kb
Host smart-7968a3a9-7b37-4a1e-8a58-1dcbb0d7cb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
05146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2161105146
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2082467794
Short name T3303
Test name
Test status
Simulation time 183424988 ps
CPU time 0.97 seconds
Started Aug 09 05:27:02 PM PDT 24
Finished Aug 09 05:27:03 PM PDT 24
Peak memory 207412 kb
Host smart-64226420-fde4-4087-9472-e6db6070cef1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2082467794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2082467794
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1913587296
Short name T1602
Test name
Test status
Simulation time 167652483 ps
CPU time 0.86 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:04 PM PDT 24
Peak memory 207480 kb
Host smart-39a63d7c-4b65-4e88-9f10-8b26960db096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
87296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1913587296
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4238564975
Short name T3000
Test name
Test status
Simulation time 315909343 ps
CPU time 1.04 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207500 kb
Host smart-5bf0fb31-699f-466c-bdc0-193db4f26886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42385
64975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4238564975
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.1376679382
Short name T1125
Test name
Test status
Simulation time 4346756796 ps
CPU time 31.15 seconds
Started Aug 09 05:27:03 PM PDT 24
Finished Aug 09 05:27:34 PM PDT 24
Peak memory 224228 kb
Host smart-ecb25ca2-a21f-4631-8015-5ed1f04ab457
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1376679382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.1376679382
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1888325624
Short name T2353
Test name
Test status
Simulation time 9260928866 ps
CPU time 62.59 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:28:17 PM PDT 24
Peak memory 207852 kb
Host smart-82ecbacf-e384-475f-8d77-5678baece53b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1888325624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1888325624
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2217687908
Short name T3460
Test name
Test status
Simulation time 222570910 ps
CPU time 0.97 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207384 kb
Host smart-c14e3d6f-4099-442e-8cc6-d00d4720d01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
87908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2217687908
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.30576275
Short name T987
Test name
Test status
Simulation time 8142928818 ps
CPU time 12.14 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:25 PM PDT 24
Peak memory 207632 kb
Host smart-58ea81f9-bb23-4b78-af7b-b1525212e77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30576
275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.30576275
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2873523240
Short name T576
Test name
Test status
Simulation time 10117418772 ps
CPU time 12.72 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:26 PM PDT 24
Peak memory 207824 kb
Host smart-9730dba5-91dc-4091-9dba-df47ed45dfba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28735
23240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2873523240
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3823302057
Short name T3339
Test name
Test status
Simulation time 4320134551 ps
CPU time 47.2 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:59 PM PDT 24
Peak memory 218184 kb
Host smart-52081cde-4e31-44b3-b8a4-58e72c46138d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3823302057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3823302057
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3310157561
Short name T1915
Test name
Test status
Simulation time 3813832328 ps
CPU time 39.67 seconds
Started Aug 09 05:27:17 PM PDT 24
Finished Aug 09 05:27:57 PM PDT 24
Peak memory 217556 kb
Host smart-17eab78b-50c9-42ca-a10a-52c30c7f7aeb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3310157561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3310157561
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3710806376
Short name T2106
Test name
Test status
Simulation time 250559062 ps
CPU time 1.09 seconds
Started Aug 09 05:27:10 PM PDT 24
Finished Aug 09 05:27:11 PM PDT 24
Peak memory 207564 kb
Host smart-22a67d74-638d-40d3-b62c-191524189217
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3710806376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3710806376
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.303338851
Short name T650
Test name
Test status
Simulation time 197025057 ps
CPU time 0.92 seconds
Started Aug 09 05:27:26 PM PDT 24
Finished Aug 09 05:27:27 PM PDT 24
Peak memory 207440 kb
Host smart-43913d3a-d851-4c86-923a-7fdf6992fb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30333
8851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.303338851
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.2899527495
Short name T1456
Test name
Test status
Simulation time 2878072397 ps
CPU time 81.5 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:28:39 PM PDT 24
Peak memory 224104 kb
Host smart-b9c33917-3a24-4461-bb19-c5cf8aee613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
27495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.2899527495
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1055191688
Short name T1930
Test name
Test status
Simulation time 1594349448 ps
CPU time 16.5 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:27:31 PM PDT 24
Peak memory 215948 kb
Host smart-b300198a-01c9-4a00-8328-0f74a0f0982f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1055191688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1055191688
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2502420893
Short name T3331
Test name
Test status
Simulation time 3504921039 ps
CPU time 26.64 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:38 PM PDT 24
Peak memory 217576 kb
Host smart-7e5298ae-b593-4317-a552-fac27132a39c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2502420893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2502420893
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2094393761
Short name T2160
Test name
Test status
Simulation time 169409945 ps
CPU time 0.87 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:27:15 PM PDT 24
Peak memory 207492 kb
Host smart-0f226047-694b-44d7-8e59-00f98482a855
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2094393761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2094393761
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3207234093
Short name T1743
Test name
Test status
Simulation time 161210597 ps
CPU time 0.86 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207556 kb
Host smart-932c45f6-e6e6-42f7-b6d1-8aff12620417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
34093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3207234093
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.329077285
Short name T2338
Test name
Test status
Simulation time 186617186 ps
CPU time 0.94 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207556 kb
Host smart-dcf3d3c6-3ece-49c0-aefb-724baaa6e96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32907
7285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.329077285
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3226388076
Short name T3130
Test name
Test status
Simulation time 163665537 ps
CPU time 1.01 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207424 kb
Host smart-79450146-e590-4ad6-971f-7387b89a90e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32263
88076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3226388076
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3947209264
Short name T2498
Test name
Test status
Simulation time 193493703 ps
CPU time 0.94 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207456 kb
Host smart-c1671a67-3b58-490d-93a2-238b0152c533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
09264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3947209264
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3937204789
Short name T2114
Test name
Test status
Simulation time 187921754 ps
CPU time 0.88 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207412 kb
Host smart-2ed534ed-25d3-4ea6-9e86-be4449f6388b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39372
04789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3937204789
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3624609582
Short name T1786
Test name
Test status
Simulation time 149495997 ps
CPU time 0.83 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207436 kb
Host smart-71919894-70bd-4c3f-9a44-064ff19c27a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36246
09582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3624609582
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.725622074
Short name T3307
Test name
Test status
Simulation time 242657287 ps
CPU time 1.04 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207504 kb
Host smart-24a53195-c712-4f4e-bfd2-30081d351116
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=725622074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.725622074
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1765738648
Short name T1925
Test name
Test status
Simulation time 140594610 ps
CPU time 0.87 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207432 kb
Host smart-5f6061bd-8ba8-4cb4-9c38-442dff8fdf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17657
38648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1765738648
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3602411039
Short name T35
Test name
Test status
Simulation time 94499527 ps
CPU time 0.79 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207468 kb
Host smart-d6312e08-8d02-478e-8fcb-0d0e8e09b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
11039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3602411039
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.837346358
Short name T266
Test name
Test status
Simulation time 19433700462 ps
CPU time 45.93 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:58 PM PDT 24
Peak memory 220452 kb
Host smart-25ad39c4-768d-4277-82f6-e4e09311de62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83734
6358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.837346358
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3351698738
Short name T1334
Test name
Test status
Simulation time 217126093 ps
CPU time 0.91 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207472 kb
Host smart-9c4791ca-cb4d-4ed3-9129-b87aa60f3670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33516
98738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3351698738
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.871551750
Short name T2220
Test name
Test status
Simulation time 235483678 ps
CPU time 1.06 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207472 kb
Host smart-e0ee7372-0ecf-4776-9d2e-5ffa9a601432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87155
1750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.871551750
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.510630593
Short name T2543
Test name
Test status
Simulation time 3342621950 ps
CPU time 27.89 seconds
Started Aug 09 05:27:18 PM PDT 24
Finished Aug 09 05:27:46 PM PDT 24
Peak memory 224100 kb
Host smart-f5861d3a-eb0d-4a0c-9cad-3ef6c44dbb2d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=510630593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.510630593
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.416828855
Short name T2043
Test name
Test status
Simulation time 9313324276 ps
CPU time 48.43 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:28:02 PM PDT 24
Peak memory 218696 kb
Host smart-b5a6d81b-0740-42c8-86f8-841e145d75e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=416828855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.416828855
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.128562742
Short name T1811
Test name
Test status
Simulation time 204303480 ps
CPU time 0.88 seconds
Started Aug 09 05:27:12 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207504 kb
Host smart-5e018f31-2ae5-4d61-8509-8ed8af16edc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
2742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.128562742
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1065568738
Short name T3196
Test name
Test status
Simulation time 184345752 ps
CPU time 0.87 seconds
Started Aug 09 05:27:13 PM PDT 24
Finished Aug 09 05:27:14 PM PDT 24
Peak memory 207452 kb
Host smart-059635b1-5b13-4975-966a-4563b4c0b3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10655
68738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1065568738
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.355320104
Short name T97
Test name
Test status
Simulation time 20197302086 ps
CPU time 24.12 seconds
Started Aug 09 05:27:15 PM PDT 24
Finished Aug 09 05:27:40 PM PDT 24
Peak memory 207492 kb
Host smart-55e2fcf8-094b-4b97-a8b9-9366c8878fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
0104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.355320104
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1712397073
Short name T3465
Test name
Test status
Simulation time 174548834 ps
CPU time 0.89 seconds
Started Aug 09 05:27:14 PM PDT 24
Finished Aug 09 05:27:15 PM PDT 24
Peak memory 207588 kb
Host smart-2edde937-a2f9-4478-a145-970a0768286c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123
97073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1712397073
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.111013775
Short name T44
Test name
Test status
Simulation time 245665043 ps
CPU time 1.05 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207432 kb
Host smart-e4057182-1a56-450a-b6d2-d22af6900504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
3775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.111013775
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1518310142
Short name T698
Test name
Test status
Simulation time 151684902 ps
CPU time 0.82 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207400 kb
Host smart-87beb6f8-3195-4f2b-8a6e-85550e79bdf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15183
10142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1518310142
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2229438167
Short name T2827
Test name
Test status
Simulation time 150392932 ps
CPU time 0.84 seconds
Started Aug 09 05:27:11 PM PDT 24
Finished Aug 09 05:27:12 PM PDT 24
Peak memory 207500 kb
Host smart-e84eb05b-2788-4478-adba-c92f2b11503a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22294
38167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2229438167
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2747089158
Short name T2877
Test name
Test status
Simulation time 207823374 ps
CPU time 1.02 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207508 kb
Host smart-2942bdf9-37ef-489b-9114-b9d4503447de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
89158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2747089158
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.3691666480
Short name T2669
Test name
Test status
Simulation time 2003789247 ps
CPU time 19.24 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:39 PM PDT 24
Peak memory 217548 kb
Host smart-252e67f1-f4d4-4adc-9d43-74eee8489901
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3691666480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.3691666480
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1800609275
Short name T3565
Test name
Test status
Simulation time 248646718 ps
CPU time 0.99 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:21 PM PDT 24
Peak memory 207464 kb
Host smart-d593cf2b-7fde-45a0-9ee7-dccd1526403e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
09275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1800609275
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2587205735
Short name T3250
Test name
Test status
Simulation time 172121454 ps
CPU time 0.92 seconds
Started Aug 09 05:27:20 PM PDT 24
Finished Aug 09 05:27:21 PM PDT 24
Peak memory 207740 kb
Host smart-e8156332-e5a4-4553-978c-e81f67ba7f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25872
05735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2587205735
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.672922954
Short name T974
Test name
Test status
Simulation time 1358561430 ps
CPU time 3.55 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:24 PM PDT 24
Peak memory 207652 kb
Host smart-bc39f9c8-2262-49e1-aa9c-457eb37caf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67292
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.672922954
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1554177230
Short name T2159
Test name
Test status
Simulation time 2019350954 ps
CPU time 16.46 seconds
Started Aug 09 05:27:29 PM PDT 24
Finished Aug 09 05:27:46 PM PDT 24
Peak memory 217240 kb
Host smart-4c595451-d852-4cab-aa57-6ee36108052c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
77230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1554177230
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.4138071046
Short name T1840
Test name
Test status
Simulation time 610649779 ps
CPU time 5.11 seconds
Started Aug 09 05:27:08 PM PDT 24
Finished Aug 09 05:27:13 PM PDT 24
Peak memory 207628 kb
Host smart-28ce1b60-282a-4e1f-8677-bed249960033
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138071046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.4138071046
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.59090579
Short name T1982
Test name
Test status
Simulation time 609365904 ps
CPU time 1.55 seconds
Started Aug 09 05:27:21 PM PDT 24
Finished Aug 09 05:27:22 PM PDT 24
Peak memory 207480 kb
Host smart-23b1c214-4349-4420-84f4-5620607cc5c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59090579 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.59090579
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.4058452290
Short name T448
Test name
Test status
Simulation time 429808153 ps
CPU time 1.44 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207392 kb
Host smart-de1da1cd-2fef-4d4a-83c7-36068bd375bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4058452290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.4058452290
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.3260315738
Short name T3330
Test name
Test status
Simulation time 436749635 ps
CPU time 1.39 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:33:00 PM PDT 24
Peak memory 207532 kb
Host smart-fc75191b-56c6-4cd4-9e6e-acd22b1a1ad0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260315738 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.3260315738
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.2470086163
Short name T235
Test name
Test status
Simulation time 158706606 ps
CPU time 0.87 seconds
Started Aug 09 05:33:04 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207512 kb
Host smart-ab340e86-ae22-441c-8e19-460383e9bc77
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2470086163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.2470086163
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.1630989240
Short name T2895
Test name
Test status
Simulation time 606753815 ps
CPU time 1.6 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207464 kb
Host smart-6cfe293b-3e40-4b95-8e40-fb2f74b37139
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630989240 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.1630989240
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.1371674231
Short name T3562
Test name
Test status
Simulation time 166475654 ps
CPU time 0.88 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207460 kb
Host smart-85f506d9-ac3b-4a33-b145-8ecd66dc5ee1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1371674231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.1371674231
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.1426695582
Short name T1666
Test name
Test status
Simulation time 603552205 ps
CPU time 1.64 seconds
Started Aug 09 05:32:58 PM PDT 24
Finished Aug 09 05:32:59 PM PDT 24
Peak memory 207596 kb
Host smart-939b52f7-9587-45a2-ad3a-71dca2e4fd42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426695582 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.1426695582
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.1855381174
Short name T859
Test name
Test status
Simulation time 423490244 ps
CPU time 1.54 seconds
Started Aug 09 05:32:51 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207532 kb
Host smart-4cb25bc1-a302-408c-a98e-01d0fe3953a8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855381174 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.1855381174
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.1296257124
Short name T460
Test name
Test status
Simulation time 240483151 ps
CPU time 1.06 seconds
Started Aug 09 05:33:10 PM PDT 24
Finished Aug 09 05:33:11 PM PDT 24
Peak memory 207464 kb
Host smart-6f585fb6-09d0-49ae-ba20-0af474286fd8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1296257124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.1296257124
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.2387978996
Short name T1114
Test name
Test status
Simulation time 544816534 ps
CPU time 1.67 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:05 PM PDT 24
Peak memory 207464 kb
Host smart-4b16c5ed-c0ab-4e6d-a7f9-4f7314bcce38
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387978996 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.2387978996
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.140589007
Short name T443
Test name
Test status
Simulation time 491388419 ps
CPU time 1.32 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207364 kb
Host smart-3a22ca5f-a08f-4e56-b967-1a7caf1e8bec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=140589007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.140589007
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.1538749932
Short name T3210
Test name
Test status
Simulation time 536718096 ps
CPU time 1.57 seconds
Started Aug 09 05:33:01 PM PDT 24
Finished Aug 09 05:33:03 PM PDT 24
Peak memory 207532 kb
Host smart-701dc898-8fe1-44ab-aec4-39a36e507373
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538749932 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.1538749932
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.2598171986
Short name T469
Test name
Test status
Simulation time 292721355 ps
CPU time 1.17 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:53 PM PDT 24
Peak memory 207436 kb
Host smart-78def997-08be-444e-afd1-ebf3767fc672
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2598171986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.2598171986
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.1671524825
Short name T1072
Test name
Test status
Simulation time 497182234 ps
CPU time 1.46 seconds
Started Aug 09 05:33:03 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207504 kb
Host smart-e3992cce-e132-41eb-b688-ea39e2af4ace
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671524825 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.1671524825
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.1067863625
Short name T3058
Test name
Test status
Simulation time 371733235 ps
CPU time 1.21 seconds
Started Aug 09 05:32:57 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207488 kb
Host smart-1979f4ac-12f7-4e29-aacb-1606892b025e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1067863625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.1067863625
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.3975833343
Short name T1972
Test name
Test status
Simulation time 541091190 ps
CPU time 1.64 seconds
Started Aug 09 05:33:02 PM PDT 24
Finished Aug 09 05:33:04 PM PDT 24
Peak memory 207376 kb
Host smart-d4d8fe99-82c6-4999-b5c6-25008a1bdfc9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975833343 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.3975833343
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.2194299898
Short name T409
Test name
Test status
Simulation time 388908982 ps
CPU time 1.23 seconds
Started Aug 09 05:32:57 PM PDT 24
Finished Aug 09 05:32:58 PM PDT 24
Peak memory 207492 kb
Host smart-f68d12cb-eb33-4281-9743-8a7b85e31cde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2194299898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.2194299898
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.2091699806
Short name T163
Test name
Test status
Simulation time 580163538 ps
CPU time 1.5 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:01 PM PDT 24
Peak memory 207440 kb
Host smart-4498075c-8a2e-4721-9ef8-1a8b3cd112d9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091699806 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.2091699806
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.2247754692
Short name T486
Test name
Test status
Simulation time 248968739 ps
CPU time 1.05 seconds
Started Aug 09 05:32:52 PM PDT 24
Finished Aug 09 05:32:54 PM PDT 24
Peak memory 207508 kb
Host smart-1f6d9973-e2cd-4b6f-9c97-dd6d0fdb2329
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2247754692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.2247754692
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.4268335592
Short name T3396
Test name
Test status
Simulation time 455552085 ps
CPU time 1.49 seconds
Started Aug 09 05:33:00 PM PDT 24
Finished Aug 09 05:33:02 PM PDT 24
Peak memory 207480 kb
Host smart-96638d3f-2805-4611-bcf8-7b23694d7016
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268335592 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.4268335592
Directory /workspace/99.usbdev_tx_rx_disruption/latest
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