Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171438	1			T1	2		T2	2		T3	3
all_values[1]	171438	1			T1	2		T2	2		T3	3
all_values[2]	171438	1			T1	2		T2	2		T3	3
all_values[3]	171438	1			T1	2		T2	2		T3	3
all_values[4]	171438	1			T1	2		T2	2		T3	3
all_values[5]	171438	1			T1	2		T2	2		T3	3
all_values[6]	171438	1			T1	2		T2	2		T3	3
all_values[7]	171438	1			T1	2		T2	2		T3	3
all_values[8]	171438	1			T1	2		T2	2		T3	3
all_values[9]	171438	1			T1	2		T2	2		T3	3
all_values[10]	171438	1			T1	2		T2	2		T3	3
all_values[11]	171438	1			T1	2		T2	2		T3	3
all_values[12]	171438	1			T1	2		T2	2		T3	3
all_values[13]	171438	1			T1	2		T2	2		T3	3
all_values[14]	171438	1			T1	2		T2	2		T3	3
all_values[15]	171438	1			T1	2		T2	2		T3	3
all_values[16]	171438	1			T1	2		T2	2		T3	3
all_values[17]	171438	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5476087

1

T1

64

T2

64

T3

96

auto[1]

9929

1

T37

3

T31

3

T34

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701843

1

T1

62

T2

58

T3

78

auto[1]

784173

1

T1

2

T2

6

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142984	1			T1	2		T2	2		T4	2
all_values[0]	auto[0]	auto[1]	25118	1			T3	3		T27	3		T29	1
all_values[0]	auto[1]	auto[0]	3215	1			T37	3		T31	3		T35	5
all_values[0]	auto[1]	auto[1]	121	1			T287	1		T375	1		T376	1
all_values[1]	auto[0]	auto[0]	166893	1			T1	2		T2	2		T27	2
all_values[1]	auto[0]	auto[1]	3085	1			T3	3		T27	1		T30	2
all_values[1]	auto[1]	auto[0]	564	1			T34	1		T36	2		T23	2
all_values[1]	auto[1]	auto[1]	896	1			T34	1		T36	12		T23	12
all_values[2]	auto[0]	auto[0]	4251	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	166936	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	133	1			T17	1		T44	1		T66	1
all_values[2]	auto[1]	auto[1]	118	1			T17	1		T44	1		T66	1
all_values[3]	auto[0]	auto[0]	169487	1			T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	287	1			T30	1		T67	1		T68	1
all_values[3]	auto[1]	auto[0]	1601	1			T69	1484		T248	1		T249	2
all_values[3]	auto[1]	auto[1]	63	1			T69	1		T249	5		T250	2
all_values[4]	auto[0]	auto[0]	4226	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	167045	1			T1	1		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	88	1			T70	1		T248	3		T250	4
all_values[4]	auto[1]	auto[1]	79	1			T70	1		T249	1		T250	1
all_values[5]	auto[0]	auto[0]	170925	1			T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	347	1			T59	1		T34	1		T7	1
all_values[5]	auto[1]	auto[0]	98	1			T248	4		T249	1		T250	1
all_values[5]	auto[1]	auto[1]	68	1			T249	3		T250	2		T251	1
all_values[6]	auto[0]	auto[0]	170997	1			T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	207	1			T59	1		T34	1		T10	1
all_values[6]	auto[1]	auto[0]	113	1			T248	1		T249	3		T250	2
all_values[6]	auto[1]	auto[1]	121	1			T45	1		T71	1		T72	1
all_values[7]	auto[0]	auto[0]	115060	1			T1	2		T2	2		T4	2
all_values[7]	auto[0]	auto[1]	56173	1			T3	3		T27	3		T29	4
all_values[7]	auto[1]	auto[0]	129	1			T47	1		T48	1		T49	1
all_values[7]	auto[1]	auto[1]	76	1			T47	1		T48	1		T49	1
all_values[8]	auto[0]	auto[0]	170683	1			T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	65	1			T248	2		T250	3		T251	3
all_values[8]	auto[1]	auto[0]	614	1			T20	10		T52	10		T53	10
all_values[8]	auto[1]	auto[1]	76	1			T20	1		T50	1		T51	1
all_values[9]	auto[0]	auto[0]	171165	1			T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	80	1			T249	1		T370	3		T346	3
all_values[9]	auto[1]	auto[0]	95	1			T63	3		T64	3		T65	3
all_values[9]	auto[1]	auto[1]	98	1			T63	2		T64	2		T65	2
all_values[10]	auto[0]	auto[0]	170861	1			T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	405	1			T60	2		T61	1		T62	1
all_values[10]	auto[1]	auto[0]	100	1			T248	4		T249	1		T250	4
all_values[10]	auto[1]	auto[1]	72	1			T248	2		T249	1		T250	3
all_values[11]	auto[0]	auto[0]	170472	1			T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	702	1			T46	3		T76	3		T79	3
all_values[11]	auto[1]	auto[0]	138	1			T22	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	126	1			T22	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	171071	1			T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	183	1			T80	3		T81	3		T82	1
all_values[12]	auto[1]	auto[0]	116	1			T83	2		T84	2		T85	2
all_values[12]	auto[1]	auto[1]	68	1			T83	1		T84	1		T85	1
all_values[13]	auto[0]	auto[0]	171086	1			T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	81	1			T82	1		T89	1		T90	1
all_values[13]	auto[1]	auto[0]	143	1			T86	1		T87	1		T88	1
all_values[13]	auto[1]	auto[1]	128	1			T86	1		T87	1		T88	1
all_values[14]	auto[0]	auto[0]	35343	1			T1	2		T2	1		T3	3
all_values[14]	auto[0]	auto[1]	135964	1			T2	1		T4	1		T30	1
all_values[14]	auto[1]	auto[0]	83	1			T248	1		T250	4		T346	2
all_values[14]	auto[1]	auto[1]	48	1			T248	5		T249	1		T251	1
all_values[15]	auto[0]	auto[0]	4266	1			T1	2		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	167013	1			T2	1		T3	2		T27	2
all_values[15]	auto[1]	auto[0]	95	1			T248	5		T249	2		T250	2
all_values[15]	auto[1]	auto[1]	64	1			T248	1		T249	2		T250	1
all_values[16]	auto[0]	auto[0]	170446	1			T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	782	1			T28	1		T33	1		T19	1
all_values[16]	auto[1]	auto[0]	118	1			T73	4		T74	4		T75	4
all_values[16]	auto[1]	auto[1]	92	1			T73	4		T74	4		T75	4
all_values[17]	auto[0]	auto[0]	113938	1			T1	2		T4	2		T25	2
all_values[17]	auto[0]	auto[1]	57328	1			T2	2		T3	3		T27	3
all_values[17]	auto[1]	auto[0]	114	1			T57	1		T58	1		T248	6
all_values[17]	auto[1]	auto[1]	58	1			T57	1		T58	1		T249	3