Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	977	1			T127	1		T310	10		T68	1
range_16_to_126	152986	1			T3	2		T4	82		T28	2
fifteen	1638	1			T91	1		T114	4		T498	1
range_2_to_14	20903	1			T4	1		T33	1		T92	1
seven	2658	1			T173	1		T113	1		T114	7
one	718	1			T114	7		T527	2		T115	7
zero	1450	1			T27	2		T4	1		T307	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

14425

1

T4

3

T30

11

T31

3

three

15397

1

T4

1

T37

1

T30

33

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	65	1			T114	1		T115	1		T422	1
range_127	three	77	1			T310	10		T114	1		T528	1
range_16_to_126	seven	12870	1			T4	3		T30	11		T31	3
range_16_to_126	three	13444	1			T4	1		T37	1		T30	33
fifteen	seven	107	1			T115	1		T182	2		T443	1
fifteen	three	100	1			T224	1		T182	1		T529	17
range_2_to_14	seven	1288	1			T113	1		T201	8		T530	1
range_2_to_14	three	1597	1			T413	1		T307	1		T114	6
seven	seven	152	1			T114	2		T261	3		T531	1
seven	three	264	1			T50	8		T532	91		T182	2
one	seven	33	1			T114	1		T115	1		T182	1
one	three	108	1			T114	1		T182	2		T533	1
zero	seven	62	1			T510	1		T114	1		T531	39
zero	three	71	1			T115	1		T388	1		T444	1