Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110580

1

T3

1

T27

1

T4

43

auto[1]

45587

1

T3

1

T27

1

T4

33

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29822	1			T3	2		T30	1		T32	1
max_len_m1	776	1			T4	6		T28	1		T30	2
max_len_m2	853	1			T4	2		T30	1		T5	2
max_len_m3	895	1			T4	2		T31	1		T5	4
five	1125	1			T30	4		T23	2		T117	2
four	1179	1			T4	2		T29	1		T30	3
three	767	1			T4	2		T30	3		T76	1
one	866	1			T4	1		T30	3		T21	1
zero	11290	1			T4	2		T30	90		T35	1

---

Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24087	1			T3	1		T30	1		T32	1
max_len	auto[1]	5735	1			T3	1		T5	2		T117	1
max_len_m1	auto[0]	528	1			T4	3		T28	1		T30	2
max_len_m1	auto[1]	248	1			T4	3		T36	1		T6	1
max_len_m2	auto[0]	579	1			T4	1		T30	1		T5	1
max_len_m2	auto[1]	274	1			T4	1		T5	1		T76	1
max_len_m3	auto[0]	601	1			T4	1		T5	2		T9	1
max_len_m3	auto[1]	294	1			T4	1		T31	1		T5	2
five	auto[0]	580	1			T30	2		T23	1		T117	1
five	auto[1]	545	1			T30	2		T23	1		T117	1
four	auto[0]	590	1			T4	1		T29	1		T30	1
four	auto[1]	589	1			T4	1		T30	2		T540	1
three	auto[0]	356	1			T4	2		T30	1		T507	1
three	auto[1]	411	1			T30	2		T76	1		T67	6
one	auto[0]	388	1			T4	1		T30	1		T21	1
one	auto[1]	478	1			T30	2		T99	1		T67	7
zero	auto[0]	516	1			T4	1		T30	2		T23	1
zero	auto[1]	10774	1			T4	1		T30	88		T35	1