Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68691

1

T3

1

T27

1

T4

32

auto[1]

77486

1

T3

2

T4

32

T30

248

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10397	1			T4	48		T30	28		T33	1
endpoints[0x1]	11290	1			T30	34		T36	3		T23	3
endpoints[0x2]	11505	1			T30	38		T36	3		T23	3
endpoints[0x3]	14844	1			T37	1		T30	49		T36	3
endpoints[0x4]	11514	1			T30	15		T36	3		T23	3
endpoints[0x5]	11950	1			T30	36		T32	1		T36	3
endpoints[0x6]	11483	1			T4	16		T30	39		T36	3
endpoints[0x7]	13635	1			T30	16		T31	4		T35	4
endpoints[0x8]	13505	1			T3	3		T27	1		T28	2
endpoints[0x9]	12162	1			T30	34		T36	3		T23	3
endpoints[0xa]	11985	1			T30	29		T36	3		T23	3
endpoints[0xb]	11907	1			T29	1		T30	26		T36	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	171	1			T110	4		T111	5		T112	2
ack	38139	1			T3	1		T4	16		T30	124
data1	50408	1			T4	24		T28	1		T30	125
data0	57396	1			T3	2		T27	1		T4	24

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	13	1			T356	3		T357	1		T358	2
nak	auto[1]	endpoints[0x1]	9	1			T110	1		T357	1		T359	1
nak	auto[1]	endpoints[0x2]	19	1			T111	1		T112	1		T360	2
nak	auto[1]	endpoints[0x3]	11	1			T111	2		T356	2		T361	1
nak	auto[1]	endpoints[0x4]	12	1			T110	1		T356	1		T357	1
nak	auto[1]	endpoints[0x5]	10	1			T356	1		T362	1		T363	1
nak	auto[1]	endpoints[0x6]	18	1			T111	1		T362	1		T364	1
nak	auto[1]	endpoints[0x7]	17	1			T362	1		T357	1		T364	4
nak	auto[1]	endpoints[0x8]	13	1			T112	1		T360	1		T362	1
nak	auto[1]	endpoints[0x9]	18	1			T110	1		T111	1		T360	1
nak	auto[1]	endpoints[0xa]	16	1			T110	1		T360	1		T362	1
nak	auto[1]	endpoints[0xb]	15	1			T360	1		T356	2		T364	1
ack	auto[1]	endpoints[0x0]	3203	1			T4	16		T30	10		T34	1
ack	auto[1]	endpoints[0x1]	3186	1			T30	13		T36	1		T23	1
ack	auto[1]	endpoints[0x2]	2928	1			T30	10		T36	1		T23	1
ack	auto[1]	endpoints[0x3]	3498	1			T30	16		T36	1		T23	1
ack	auto[1]	endpoints[0x4]	3296	1			T30	4		T36	1		T23	1
ack	auto[1]	endpoints[0x5]	3105	1			T30	10		T36	1		T5	60
ack	auto[1]	endpoints[0x6]	2995	1			T30	14		T36	1		T23	1
ack	auto[1]	endpoints[0x7]	3182	1			T30	5		T31	1		T35	1
ack	auto[1]	endpoints[0x8]	3271	1			T3	1		T30	12		T35	2
ack	auto[1]	endpoints[0x9]	3227	1			T30	13		T36	1		T23	1
ack	auto[1]	endpoints[0xa]	3143	1			T30	9		T36	1		T23	1
ack	auto[1]	endpoints[0xb]	3105	1			T30	8		T36	1		T23	1
data1	auto[0]	endpoints[0x0]	1473	1			T4	8		T30	4		T76	1
data1	auto[0]	endpoints[0x1]	2052	1			T30	4		T76	2		T117	2
data1	auto[0]	endpoints[0x2]	2376	1			T30	9		T117	3		T165	2
data1	auto[0]	endpoints[0x3]	3349	1			T30	8		T67	15		T310	5
data1	auto[0]	endpoints[0x4]	1995	1			T30	3		T6	15		T117	3
data1	auto[0]	endpoints[0x5]	2404	1			T30	8		T5	19		T165	2
data1	auto[0]	endpoints[0x6]	2290	1			T4	8		T30	5		T79	1
data1	auto[0]	endpoints[0x7]	3185	1			T30	3		T31	1		T35	1
data1	auto[0]	endpoints[0x8]	3025	1			T28	1		T30	7		T35	2
data1	auto[0]	endpoints[0x9]	2334	1			T30	4		T46	1		T155	1
data1	auto[0]	endpoints[0xa]	2343	1			T30	5		T46	2		T121	1
data1	auto[0]	endpoints[0xb]	2414	1			T30	5		T121	2		T117	3
data1	auto[1]	endpoints[0x0]	1774	1			T4	8		T30	5		T76	1
data1	auto[1]	endpoints[0x1]	1767	1			T30	6		T76	2		T117	4
data1	auto[1]	endpoints[0x2]	1586	1			T30	5		T61	2		T117	3
data1	auto[1]	endpoints[0x3]	1956	1			T30	8		T67	12		T68	5
data1	auto[1]	endpoints[0x4]	1847	1			T30	2		T6	31		T117	3
data1	auto[1]	endpoints[0x5]	1740	1			T30	5		T5	41		T165	2
data1	auto[1]	endpoints[0x6]	1636	1			T30	7		T79	1		T117	4
data1	auto[1]	endpoints[0x7]	1772	1			T30	2		T31	1		T35	1
data1	auto[1]	endpoints[0x8]	1797	1			T30	6		T35	2		T172	1
data1	auto[1]	endpoints[0x9]	1822	1			T30	6		T46	1		T107	1
data1	auto[1]	endpoints[0xa]	1798	1			T30	4		T46	2		T121	1
data1	auto[1]	endpoints[0xb]	1673	1			T30	4		T121	2		T117	3
data0	auto[0]	endpoints[0x0]	2436	1			T4	8		T30	4		T33	1
data0	auto[0]	endpoints[0x1]	2764	1			T30	4		T36	1		T23	1
data0	auto[0]	endpoints[0x2]	3167	1			T30	9		T36	1		T23	1
data0	auto[0]	endpoints[0x3]	4370	1			T37	1		T30	9		T36	1
data0	auto[0]	endpoints[0x4]	2831	1			T30	4		T36	1		T23	1
data0	auto[0]	endpoints[0x5]	3258	1			T30	8		T32	1		T36	1
data0	auto[0]	endpoints[0x6]	3097	1			T4	8		T30	6		T36	1
data0	auto[0]	endpoints[0x7]	4000	1			T30	3		T31	1		T35	1
data0	auto[0]	endpoints[0x8]	3825	1			T3	1		T27	1		T28	1
data0	auto[0]	endpoints[0x9]	3269	1			T30	4		T36	1		T23	1
data0	auto[0]	endpoints[0xa]	3235	1			T30	6		T36	1		T23	1
data0	auto[0]	endpoints[0xb]	3186	1			T29	1		T30	5		T36	1
data0	auto[1]	endpoints[0x0]	1492	1			T4	8		T30	5		T34	1
data0	auto[1]	endpoints[0x1]	1507	1			T30	7		T36	1		T23	1
data0	auto[1]	endpoints[0x2]	1424	1			T30	5		T36	1		T23	1
data0	auto[1]	endpoints[0x3]	1650	1			T30	8		T36	1		T23	1
data0	auto[1]	endpoints[0x4]	1527	1			T30	2		T36	1		T23	1
data0	auto[1]	endpoints[0x5]	1428	1			T30	5		T36	1		T5	19
data0	auto[1]	endpoints[0x6]	1441	1			T30	7		T36	1		T23	1
data0	auto[1]	endpoints[0x7]	1473	1			T30	3		T36	1		T23	1
data0	auto[1]	endpoints[0x8]	1571	1			T3	1		T30	6		T36	1
data0	auto[1]	endpoints[0x9]	1490	1			T30	7		T36	1		T23	1
data0	auto[1]	endpoints[0xa]	1443	1			T30	5		T36	1		T23	1
data0	auto[1]	endpoints[0xb]	1512	1			T30	4		T36	1		T23	1