Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8524

1

T4

5

T92

3

T173

3

auto[1]

53881

1

T3

1

T27

1

T4

36

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54818

1

T3

1

T4

23

T30

124

auto[1]

7587

1

T27

1

T4

18

T92

2

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56301

1

T3

1

T27

1

T4

41

auto[1]

6104

1

T92

2

T113

2

T126

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4547

1

T4

7

T92

1

T113

1

pkt_types[PidTypeInToken]

57858

1

T3

1

T27

1

T4

34

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1352

1

T4

4

T127

1

T114

37

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

750

1

T114

24

T115

52

T383

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

95

1

T4

1

T113

1

T68

2

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

19

1

T116

1

T382

2

T397

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1501

1

T4

2

T68

2

T114

34

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

715

1

T127

1

T308

1

T114

31

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

95

1

T68

2

T186

1

T224

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

20

1

T92

1

T308

1

T387

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3927

1

T92

3

T173

1

T307

2

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2297

1

T113

2

T114

53

T392

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

44

1

T173

2

T410

1

T424

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

40

1

T435

1

T410

1

T491

2

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

42064

1

T3

1

T4

17

T30

124

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2212

1

T126

1

T127

2

T128

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7223

1

T27

1

T4

17

T113

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

51

1

T92

1

T308

1

T381

1