Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171438	1			T1	2		T2	2		T3	3
all_pins[1]	171438	1			T1	2		T2	2		T3	3
all_pins[2]	171438	1			T1	2		T2	2		T3	3
all_pins[3]	171438	1			T1	2		T2	2		T3	3
all_pins[4]	171438	1			T1	2		T2	2		T3	3
all_pins[5]	171438	1			T1	2		T2	2		T3	3
all_pins[6]	171438	1			T1	2		T2	2		T3	3
all_pins[7]	171438	1			T1	2		T2	2		T3	3
all_pins[8]	171438	1			T1	2		T2	2		T3	3
all_pins[9]	171438	1			T1	2		T2	2		T3	3
all_pins[10]	171438	1			T1	2		T2	2		T3	3
all_pins[11]	171438	1			T1	2		T2	2		T3	3
all_pins[12]	171438	1			T1	2		T2	2		T3	3
all_pins[13]	171438	1			T1	2		T2	2		T3	3
all_pins[14]	171438	1			T1	2		T2	2		T3	3
all_pins[15]	171438	1			T1	2		T2	2		T3	3
all_pins[16]	171438	1			T1	2		T2	2		T3	3
all_pins[17]	171438	1			T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5483644	1			T1	64		T2	64		T3	96
values[0x1]	2372	1			T34	1		T36	12		T17	1
transitions[0x0=>0x1]	2100	1			T34	1		T36	12		T17	1
transitions[0x1=>0x0]	2100	1			T34	1		T36	12		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171317	1			T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	121	1			T287	1		T375	1		T376	1
all_pins[0]	transitions[0x0=>0x1]	101	1			T287	1		T375	1		T376	1
all_pins[0]	transitions[0x1=>0x0]	876	1			T34	1		T36	12		T23	12
all_pins[1]	values[0x0]	170542	1			T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	896	1			T34	1		T36	12		T23	12
all_pins[1]	transitions[0x0=>0x1]	887	1			T34	1		T36	12		T23	12
all_pins[1]	transitions[0x1=>0x0]	109	1			T17	1		T44	1		T66	1
all_pins[2]	values[0x0]	171320	1			T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	118	1			T17	1		T44	1		T66	1
all_pins[2]	transitions[0x0=>0x1]	110	1			T17	1		T44	1		T66	1
all_pins[2]	transitions[0x1=>0x0]	55	1			T69	1		T249	5		T250	2
all_pins[3]	values[0x0]	171375	1			T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	63	1			T69	1		T249	5		T250	2
all_pins[3]	transitions[0x0=>0x1]	48	1			T69	1		T249	4		T250	2
all_pins[3]	transitions[0x1=>0x0]	64	1			T70	1		T250	1		T346	2
all_pins[4]	values[0x0]	171359	1			T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	79	1			T70	1		T249	1		T250	1
all_pins[4]	transitions[0x0=>0x1]	63	1			T70	1		T371	1		T374	1
all_pins[4]	transitions[0x1=>0x0]	52	1			T249	2		T250	1		T251	1
all_pins[5]	values[0x0]	171370	1			T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	68	1			T249	3		T250	2		T251	1
all_pins[5]	transitions[0x0=>0x1]	47	1			T249	3		T250	2		T346	4
all_pins[5]	transitions[0x1=>0x0]	100	1			T45	1		T71	1		T72	1
all_pins[6]	values[0x0]	171317	1			T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	121	1			T45	1		T71	1		T72	1
all_pins[6]	transitions[0x0=>0x1]	103	1			T45	1		T71	1		T72	1
all_pins[6]	transitions[0x1=>0x0]	58	1			T47	1		T48	1		T49	1
all_pins[7]	values[0x0]	171362	1			T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	76	1			T47	1		T48	1		T49	1
all_pins[7]	transitions[0x0=>0x1]	61	1			T47	1		T48	1		T49	1
all_pins[7]	transitions[0x1=>0x0]	61	1			T20	1		T50	1		T51	1
all_pins[8]	values[0x0]	171362	1			T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	76	1			T20	1		T50	1		T51	1
all_pins[8]	transitions[0x0=>0x1]	68	1			T20	1		T50	1		T51	1
all_pins[8]	transitions[0x1=>0x0]	90	1			T63	2		T64	2		T65	2
all_pins[9]	values[0x0]	171340	1			T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	98	1			T63	2		T64	2		T65	2
all_pins[9]	transitions[0x0=>0x1]	72	1			T63	2		T64	2		T65	2
all_pins[9]	transitions[0x1=>0x0]	46	1			T370	3		T371	1		T374	1
all_pins[10]	values[0x0]	171366	1			T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	72	1			T248	2		T249	1		T250	3
all_pins[10]	transitions[0x0=>0x1]	54	1			T249	1		T370	3		T371	3
all_pins[10]	transitions[0x1=>0x0]	108	1			T22	1		T77	1		T78	1
all_pins[11]	values[0x0]	171312	1			T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	126	1			T22	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	110	1			T22	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	52	1			T83	1		T84	1		T85	1
all_pins[12]	values[0x0]	171370	1			T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	68	1			T83	1		T84	1		T85	1
all_pins[12]	transitions[0x0=>0x1]	50	1			T83	1		T84	1		T85	1
all_pins[12]	transitions[0x1=>0x0]	110	1			T86	1		T87	1		T88	1
all_pins[13]	values[0x0]	171310	1			T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	128	1			T86	1		T87	1		T88	1
all_pins[13]	transitions[0x0=>0x1]	109	1			T86	1		T87	1		T88	1
all_pins[13]	transitions[0x1=>0x0]	29	1			T248	3		T249	1		T251	1
all_pins[14]	values[0x0]	171390	1			T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	48	1			T248	5		T249	1		T251	1
all_pins[14]	transitions[0x0=>0x1]	35	1			T248	4		T249	1		T251	1
all_pins[14]	transitions[0x1=>0x0]	51	1			T249	2		T250	1		T251	2
all_pins[15]	values[0x0]	171374	1			T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	64	1			T248	1		T249	2		T250	1
all_pins[15]	transitions[0x0=>0x1]	48	1			T249	1		T250	1		T251	2
all_pins[15]	transitions[0x1=>0x0]	76	1			T73	4		T74	4		T75	4
all_pins[16]	values[0x0]	171346	1			T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	92	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	76	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	42	1			T57	1		T58	1		T249	2
all_pins[17]	values[0x0]	171380	1			T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	58	1			T57	1		T58	1		T249	3
all_pins[17]	transitions[0x0=>0x1]	58	1			T57	1		T58	1		T249	3