Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4721	1			T91	1		T92	1		T113	2
invalid_ep[0xd]	4637	1			T92	1		T173	2		T113	1
invalid_ep[0xe]	4639	1			T173	1		T290	2		T219	5
invalid_ep[0xf]	4562	1			T92	2		T173	2		T113	1
endpoints[0x0]	11515	1			T4	35		T30	18		T91	1
endpoints[0x1]	12786	1			T4	1		T30	21		T36	2
endpoints[0x2]	12883	1			T4	2		T30	28		T91	1
endpoints[0x3]	15397	1			T4	1		T37	1		T30	33
endpoints[0x4]	12961	1			T4	1		T30	11		T91	1
endpoints[0x5]	13794	1			T30	26		T32	1		T36	2
endpoints[0x6]	12656	1			T4	34		T30	25		T36	2
endpoints[0x7]	14425	1			T4	3		T30	11		T31	3
endpoints[0x8]	14391	1			T3	2		T27	2		T4	4
endpoints[0x9]	13210	1			T30	21		T91	1		T36	2
endpoints[0xa]	13040	1			T4	2		T30	20		T36	2
endpoints[0xb]	13055	1			T4	1		T29	1		T30	18

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23628	1			T37	1		T31	1		T91	2
pkt_types[PidTypeOutToken]	75350	1			T3	1		T27	1		T4	32
pkt_types[PidTypeInToken]	62085	1			T3	1		T27	1		T4	34

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1023	1			T113	1		T413	1		T290	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1106	1			T173	1		T113	1		T114	32
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	958	1			T290	1		T114	24		T115	14
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1025	1			T173	1		T413	1		T307	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1700	1			T20	8		T76	1		T127	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1597	1			T76	3		T173	1		T113	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1521	1			T91	1		T165	2		T166	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1734	1			T37	1		T173	1		T307	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1731	1			T6	25		T127	1		T169	5
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1642	1			T5	29		T113	1		T307	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1525	1			T79	1		T117	2		T127	2
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1613	1			T31	1		T35	1		T79	3
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1583	1			T35	2		T172	1		T169	4
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1649	1			T91	1		T46	1		T107	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1735	1			T46	2		T121	1		T117	4
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1486	1			T92	1		T121	2		T165	4
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1567	1			T91	1		T226	1		T290	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1532	1			T308	1		T435	1		T219	6
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1563	1			T290	1		T219	5		T194	6
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1506	1			T92	1		T113	1		T219	11
pkt_types[PidTypeOutToken]	endpoints[0x0]	3937	1			T4	16		T30	8		T33	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	4924	1			T30	8		T36	1		T23	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	5824	1			T30	18		T36	1		T23	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	7527	1			T30	17		T36	1		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4761	1			T30	7		T91	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	5835	1			T30	16		T32	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	5533	1			T4	16		T30	11		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	7240	1			T30	6		T31	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	6897	1			T3	1		T27	1		T28	2
pkt_types[PidTypeOutToken]	endpoints[0x9]	5536	1			T30	8		T36	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5483	1			T30	11		T36	1		T23	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	5685	1			T29	1		T30	10		T36	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1067	1			T113	1		T114	33		T115	17
pkt_types[PidTypeInToken]	invalid_ep[0xd]	997	1			T92	1		T173	1		T114	29
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1139	1			T173	1		T114	32		T115	25
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1024	1			T92	1		T173	1		T308	1
pkt_types[PidTypeInToken]	endpoints[0x0]	4803	1			T4	17		T30	10		T34	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5130	1			T30	13		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4386	1			T30	10		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4974	1			T30	16		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0x4]	5315	1			T30	4		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0x5]	5204	1			T30	10		T36	1		T5	61
pkt_types[PidTypeInToken]	endpoints[0x6]	4417	1			T4	17		T30	14		T36	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4404	1			T30	5		T31	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4820	1			T3	1		T27	1		T30	12
pkt_types[PidTypeInToken]	endpoints[0x9]	4885	1			T30	13		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4709	1			T30	9		T36	1		T23	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4811	1			T30	8		T36	1		T23	1