Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1			T248	7		T249	7		T250	7
all_values[1]	296	1			T248	7		T249	7		T250	7
all_values[2]	296	1			T248	7		T249	7		T250	7
all_values[3]	296	1			T248	7		T249	7		T250	7
all_values[4]	296	1			T248	7		T249	7		T250	7
all_values[5]	296	1			T248	7		T249	7		T250	7
all_values[6]	296	1			T248	7		T249	7		T250	7
all_values[7]	296	1			T248	7		T249	7		T250	7
all_values[8]	296	1			T248	7		T249	7		T250	7
all_values[9]	296	1			T248	7		T249	7		T250	7
all_values[10]	296	1			T248	7		T249	7		T250	7
all_values[11]	296	1			T248	7		T249	7		T250	7
all_values[12]	296	1			T248	7		T249	7		T250	7
all_values[13]	296	1			T248	7		T249	7		T250	7
all_values[14]	296	1			T248	7		T249	7		T250	7
all_values[15]	296	1			T248	7		T249	7		T250	7
all_values[16]	296	1			T248	7		T249	7		T250	7
all_values[17]	296	1			T248	7		T249	7		T250	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7092

1

T248

163

T249

160

T250

159

auto[1]

2380

1

T248

61

T249

64

T250

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6434

1

T248

158

T249

149

T250

145

auto[1]

3038

1

T248

66

T249

75

T250

79

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5447

1

T248

135

T249

120

T250

118

auto[1]

4025

1

T248

89

T249

104

T250

106

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	99	1			T248	1		T249	1		T250	2
all_values[0]	auto[0]	auto[1]	auto[0]	71	1			T248	3		T249	2		T250	1
all_values[0]	auto[1]	auto[0]	auto[1]	68	1			T248	1		T249	3		T250	2
all_values[0]	auto[1]	auto[1]	auto[1]	58	1			T248	2		T249	1		T250	2
all_values[1]	auto[0]	auto[0]	auto[0]	90	1			T248	2		T249	3		T251	6
all_values[1]	auto[0]	auto[1]	auto[0]	85	1			T248	3		T249	2		T250	4
all_values[1]	auto[1]	auto[0]	auto[1]	77	1			T248	1		T249	1		T250	2
all_values[1]	auto[1]	auto[1]	auto[1]	44	1			T248	1		T249	1		T250	1
all_values[2]	auto[0]	auto[0]	auto[0]	52	1			T249	2		T370	1		T371	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1			T248	5		T249	1		T250	1
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T249	2		T250	1		T372	2
all_values[2]	auto[0]	auto[1]	auto[1]	33	1			T250	1		T346	1		T373	1
all_values[2]	auto[1]	auto[0]	auto[1]	73	1			T248	1		T249	2		T250	3
all_values[2]	auto[1]	auto[1]	auto[1]	55	1			T248	1		T250	1		T251	3
all_values[3]	auto[0]	auto[0]	auto[0]	72	1			T248	4		T251	1		T346	1
all_values[3]	auto[0]	auto[0]	auto[1]	24	1			T248	1		T250	1		T370	1
all_values[3]	auto[0]	auto[1]	auto[0]	60	1			T250	3		T251	2		T370	1
all_values[3]	auto[0]	auto[1]	auto[1]	27	1			T249	2		T250	1		T346	3
all_values[3]	auto[1]	auto[0]	auto[1]	61	1			T248	2		T249	1		T251	3
all_values[3]	auto[1]	auto[1]	auto[1]	52	1			T249	4		T250	2		T251	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1			T248	2		T249	1		T250	2
all_values[4]	auto[0]	auto[0]	auto[1]	32	1			T248	2		T249	2		T250	1
all_values[4]	auto[0]	auto[1]	auto[0]	40	1			T248	2		T250	1		T251	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1			T250	1		T371	1		T374	2
all_values[4]	auto[1]	auto[0]	auto[1]	63	1			T248	1		T249	2		T250	2
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T249	2		T346	2		T373	2
all_values[5]	auto[0]	auto[0]	auto[0]	81	1			T248	3		T250	3		T251	3
all_values[5]	auto[0]	auto[0]	auto[1]	25	1			T249	1		T372	1		T347	1
all_values[5]	auto[0]	auto[1]	auto[0]	41	1			T248	4		T373	1		T371	2
all_values[5]	auto[0]	auto[1]	auto[1]	35	1			T249	2		T250	2		T251	1
all_values[5]	auto[1]	auto[0]	auto[1]	57	1			T249	2		T251	2		T346	2
all_values[5]	auto[1]	auto[1]	auto[1]	57	1			T249	2		T250	2		T251	1
all_values[6]	auto[0]	auto[0]	auto[0]	58	1			T249	1		T251	1		T346	2
all_values[6]	auto[0]	auto[0]	auto[1]	29	1			T248	1		T249	1		T250	2
all_values[6]	auto[0]	auto[1]	auto[0]	59	1			T248	1		T249	1		T250	1
all_values[6]	auto[0]	auto[1]	auto[1]	35	1			T248	1		T249	1		T250	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1			T248	3		T249	3		T250	3
all_values[6]	auto[1]	auto[1]	auto[1]	45	1			T248	1		T251	1		T370	1
all_values[7]	auto[0]	auto[0]	auto[0]	79	1			T248	2		T250	1		T251	2
all_values[7]	auto[0]	auto[1]	auto[0]	90	1			T248	4		T249	5		T250	2
all_values[7]	auto[1]	auto[0]	auto[1]	73	1			T249	1		T250	3		T251	1
all_values[7]	auto[1]	auto[1]	auto[1]	54	1			T248	1		T249	1		T250	1
all_values[8]	auto[0]	auto[0]	auto[0]	102	1			T249	4		T250	4		T251	2
all_values[8]	auto[0]	auto[1]	auto[0]	79	1			T248	2		T249	1		T251	1
all_values[8]	auto[1]	auto[0]	auto[1]	74	1			T248	2		T250	3		T251	4
all_values[8]	auto[1]	auto[1]	auto[1]	41	1			T248	3		T249	2		T370	1
all_values[9]	auto[0]	auto[0]	auto[0]	54	1			T248	3		T250	2		T251	2
all_values[9]	auto[0]	auto[0]	auto[1]	37	1			T370	1		T346	1		T373	1
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T249	2		T251	2		T372	1
all_values[9]	auto[0]	auto[1]	auto[1]	32	1			T248	2		T249	2		T250	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T248	1		T249	2		T370	2
all_values[9]	auto[1]	auto[1]	auto[1]	69	1			T248	1		T249	1		T250	4
all_values[10]	auto[0]	auto[0]	auto[0]	75	1			T248	2		T249	4		T251	2
all_values[10]	auto[0]	auto[0]	auto[1]	25	1			T249	1		T250	1		T373	1
all_values[10]	auto[0]	auto[1]	auto[0]	49	1			T248	1		T250	1		T251	1
all_values[10]	auto[0]	auto[1]	auto[1]	32	1			T248	1		T250	1		T370	2
all_values[10]	auto[1]	auto[0]	auto[1]	67	1			T249	1		T250	1		T251	3
all_values[10]	auto[1]	auto[1]	auto[1]	48	1			T248	3		T249	1		T250	3
all_values[11]	auto[0]	auto[0]	auto[0]	59	1			T248	3		T251	2		T370	1
all_values[11]	auto[0]	auto[0]	auto[1]	31	1			T250	1		T370	1		T346	3
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T249	1		T370	1		T346	1
all_values[11]	auto[0]	auto[1]	auto[1]	32	1			T248	1		T249	3		T250	1
all_values[11]	auto[1]	auto[0]	auto[1]	62	1			T248	1		T249	1		T250	1
all_values[11]	auto[1]	auto[1]	auto[1]	68	1			T248	2		T249	2		T250	4
all_values[12]	auto[0]	auto[0]	auto[0]	62	1			T248	3		T249	1		T250	1
all_values[12]	auto[0]	auto[0]	auto[1]	29	1			T249	1		T250	3		T251	1
all_values[12]	auto[0]	auto[1]	auto[0]	62	1			T248	2		T249	4		T251	2
all_values[12]	auto[0]	auto[1]	auto[1]	31	1			T251	1		T346	1		T373	1
all_values[12]	auto[1]	auto[0]	auto[1]	72	1			T248	2		T249	1		T250	2
all_values[12]	auto[1]	auto[1]	auto[1]	40	1			T250	1		T370	1		T346	2
all_values[13]	auto[0]	auto[0]	auto[0]	53	1			T248	2		T249	3		T251	3
all_values[13]	auto[0]	auto[0]	auto[1]	30	1			T251	1		T346	2		T371	1
all_values[13]	auto[0]	auto[1]	auto[0]	46	1			T248	1		T251	2		T370	1
all_values[13]	auto[0]	auto[1]	auto[1]	37	1			T248	1		T249	2		T250	2
all_values[13]	auto[1]	auto[0]	auto[1]	72	1			T248	2		T249	2		T250	2
all_values[13]	auto[1]	auto[1]	auto[1]	58	1			T248	1		T250	3		T370	1
all_values[14]	auto[0]	auto[0]	auto[0]	62	1			T250	2		T251	2		T370	1
all_values[14]	auto[0]	auto[0]	auto[1]	39	1			T248	1		T249	2		T250	1
all_values[14]	auto[0]	auto[1]	auto[0]	41	1			T250	3		T346	2		T374	4
all_values[14]	auto[0]	auto[1]	auto[1]	19	1			T248	2		T251	1		T371	1
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T248	2		T249	4		T251	3
all_values[14]	auto[1]	auto[1]	auto[1]	49	1			T248	2		T249	1		T250	1
all_values[15]	auto[0]	auto[0]	auto[0]	58	1			T248	1		T249	1		T250	2
all_values[15]	auto[0]	auto[0]	auto[1]	36	1			T346	2		T371	1		T374	1
all_values[15]	auto[0]	auto[1]	auto[0]	50	1			T248	2		T249	1		T250	2
all_values[15]	auto[0]	auto[1]	auto[1]	22	1			T249	1		T373	1		T371	2
all_values[15]	auto[1]	auto[0]	auto[1]	78	1			T248	3		T249	2		T250	2
all_values[15]	auto[1]	auto[1]	auto[1]	52	1			T248	1		T249	2		T250	1
all_values[16]	auto[0]	auto[0]	auto[0]	55	1			T249	2		T250	1		T370	1
all_values[16]	auto[0]	auto[0]	auto[1]	28	1			T248	1		T251	1		T346	1
all_values[16]	auto[0]	auto[1]	auto[0]	57	1			T249	3		T250	4		T251	1
all_values[16]	auto[0]	auto[1]	auto[1]	31	1			T248	1		T250	1		T251	1
all_values[16]	auto[1]	auto[0]	auto[1]	65	1			T248	2		T251	4		T346	2
all_values[16]	auto[1]	auto[1]	auto[1]	60	1			T248	3		T249	2		T250	1
all_values[17]	auto[0]	auto[0]	auto[0]	94	1			T248	2		T249	2		T250	2
all_values[17]	auto[0]	auto[1]	auto[0]	86	1			T248	5		T249	2		T250	2
all_values[17]	auto[1]	auto[0]	auto[1]	70	1			T250	2		T251	1		T346	2
all_values[17]	auto[1]	auto[1]	auto[1]	46	1			T249	3		T250	1		T251	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal