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LINE 65
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T244,T278,T279 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 77
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T252,T253,T254 |
| 1 | 0 | Covered | T278,T284,T285 |
LINE 84
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T252,T253,T254 |
| 0 | 1 | 0 | Covered | T278,T284,T285 |
| 1 | 0 | 0 | Covered | T252,T253,T254 |
LINE 132
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T28,T29 |
LINE 170
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T278,T284,T285 |
| 0 | 1 | 0 | Covered | T242,T243,T244 |
| 1 | 0 | 0 | Covered | T244,T279,T286 |
LINE 8684
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 8685
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T37,T31,T59 |
LINE 8686
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T28,T117,T45 |
LINE 8687
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T117,T45 |
LINE 8688
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T27 |
LINE 8689
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T27 |
LINE 8690
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T27,T4 |
LINE 8691
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T37,T30 |
LINE 8692
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVOUTBUFFER_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T27 |
LINE 8693
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVSETUPBUFFER_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T31,T91 |
LINE 8694
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T28,T29 |
LINE 8695
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T37,T31 |
LINE 8696
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T27 |
LINE 8697
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T28,T91,T21 |
LINE 8698
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T4,T31 |
LINE 8699
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T31,T91,T33 |
LINE 8700
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
--------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T28,T91,T92 |
LINE 8701
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T34 |
LINE 8702
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8703
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8704
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8705
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8706
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8707
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8708
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T31 |
LINE 8709
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T27,T4 |
LINE 8710
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8711
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8712
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T30,T36 |
LINE 8713
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T91,T5 |
LINE 8714
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T27,T4,T91 |
LINE 8715
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_DATA_TOGGLE_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T117,T45,T129 |
LINE 8716
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_DATA_TOGGLE_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T22,T61,T117 |
LINE 8717
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T25,T23 |
LINE 8718
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T25,T117 |
LINE 8719
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T27 |
LINE 8720
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 8721
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 8722
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_FIFO_CTRL_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T91,T5 |
LINE 8723
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_COUNT_OUT_OFFSET)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T287,T117,T45 |
LINE 8724
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_COUNT_IN_OFFSET)
--------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T36,T117,T45 |
LINE 8725
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_COUNT_NODATA_IN_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T117,T45,T288 |
LINE 8726
EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_COUNT_ERRORS_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T117,T26,T45 |
LINE 8729
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 8729
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 8733
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T242,T243,T244 |
LINE 8733
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T1,T2,T3 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T117,T45,T238 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T117,T45,T288 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T36,T117,T45 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T287,T117,T45 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T117,T45,T288 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T7,T8,T9 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T117,T45,T288 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T36,T117,T45 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T117,T45,T230 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T24,T289,T117 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T22,T61,T117 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T117,T45,T288 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T36,T117,T45 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T117,T45,T230 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T4,T5,T287 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T92,T6,T117 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T4,T5,T6 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T4,T6,T117 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T6,T117,T45 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T4,T36,T117 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T4,T5,T117 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T4,T92,T6 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T23,T113,T6 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T36,T61,T117 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T4,T5,T117 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T4,T6,T117 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T28,T117,T45 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T117,T45,T288 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T27,T4,T31 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T117,T45,T288 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T28,T117,T45 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T117,T45,T230 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T4,T28,T30 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T23,T117,T45 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T36,T117,T45 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T4,T37,T30 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T117,T45,T230 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T117,T45,T230 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T27,T24,T289 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T117,T45,T288 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T28,T117,T45 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T117,T45,T230 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T1,T2,T3 |
LINE 8733
SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 8733
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T37,T31,T59 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T45,T288 |
| 1 | 1 | Covered | T28,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T18,T117,T45 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T27 |
| 1 | 1 | Covered | T27,T24,T289 |
LINE 8733
SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T2,T3,T27 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T3,T27,T4 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T94 |
| 1 | 1 | Covered | T4,T37,T30 |
LINE 8733
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T2,T3,T27 |
| 1 | 1 | Covered | T36,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T4,T31,T91 |
| 1 | 1 | Covered | T23,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T29,T30 |
| 1 | 1 | Covered | T4,T28,T30 |
LINE 8733
SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T4,T37,T31 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T2,T3,T27 |
| 1 | 1 | Covered | T28,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T28,T91,T21 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T27,T4,T31 |
| 1 | 1 | Covered | T27,T4,T31 |
LINE 8733
SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T31,T91,T33 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T91,T92,T173 |
| 1 | 1 | Covered | T28,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T34 |
| 1 | 1 | Covered | T4,T6,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T36,T23 |
| 1 | 1 | Covered | T4,T5,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T36 |
| 1 | 1 | Covered | T36,T61,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T36 |
| 1 | 1 | Covered | T23,T113,T6 |
LINE 8733
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T36,T5 |
| 1 | 1 | Covered | T4,T92,T6 |
LINE 8733
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T36,T5 |
| 1 | 1 | Covered | T4,T5,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T36 |
| 1 | 1 | Covered | T4,T36,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T31 |
| 1 | 1 | Covered | T6,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T27,T30 |
| 1 | 1 | Covered | T4,T6,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T36,T23 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 8733
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T30,T36 |
| 1 | 1 | Covered | T92,T6,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T36,T23 |
| 1 | 1 | Covered | T4,T5,T287 |
LINE 8733
SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T4,T91,T5 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T27,T4,T91 |
| 1 | 1 | Covered | T36,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T45,T129 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T45,T129 |
| 1 | 1 | Covered | T22,T61,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T25,T23 |
| 1 | 1 | Covered | T24,T289,T117 |
LINE 8733
SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T25,T117 |
| 1 | 1 | Covered | T117,T45,T230 |
LINE 8733
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T2,T3,T27 |
| 1 | 1 | Covered | T36,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[37] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T8,T117,T45 |
| 1 | 1 | Covered | T7,T8,T9 |
LINE 8733
SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T27 |
| 1 | 0 | Covered | T4,T91,T5 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T68,T202 |
| 1 | 1 | Covered | T287,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T288,T290 |
| 1 | 1 | Covered | T36,T117,T45 |
LINE 8733
SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T117,T45,T288 |
| 1 | 1 | Covered | T117,T45,T288 |
LINE 8733
SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T26,T68,T202 |
| 1 | 1 | Covered | T117,T45,T238 |
LINE 8780
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T243,T279,T291 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 8807
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T37,T31,T59 |
| 1 | 1 | 0 | Covered | T243,T286,T292 |
| 1 | 1 | 1 | Covered | T37,T31,T59 |
LINE 8844
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T28,T117,T45 |
| 1 | 1 | 0 | Covered | T243,T286,T292 |
| 1 | 1 | 1 | Covered | T248,T249,T250 |
LINE 8881
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T18,T117,T45 |
| 1 | 1 | 0 | Covered | T243,T286,T292 |
| 1 | 1 | 1 | Covered | T18,T232,T233 |
LINE 8884
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T27 |
| 1 | 1 | 0 | Covered | T243,T279,T292 |
| 1 | 1 | 1 | Covered | T2,T3,T27 |
LINE 8891
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T27 |
| 1 | 1 | 0 | Covered | T243,T286,T292 |
| 1 | 1 | 1 | Covered | T2,T3,T27 |
LINE 8916
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T27,T4 |
| 1 | 1 | 0 | Covered | T279,T291,T286 |
| 1 | 1 | 1 | Covered | T3,T27,T4 |
LINE 8941
EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T37,T30 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T4,T37,T30 |
LINE 8942
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T27 |
| 1 | 1 | 0 | Covered | T279,T292,T293 |
| 1 | 1 | 1 | Covered | T2,T3,T27 |
LINE 8945
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T31,T91 |
| 1 | 1 | 0 | Covered | T243,T292,T293 |
| 1 | 1 | 1 | Covered | T4,T31,T91 |
LINE 8948
EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T28,T29 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T4,T28,T29 |
LINE 8949
EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T37,T31 |
| 1 | 1 | 0 | Covered | T243,T279,T286 |
| 1 | 1 | 1 | Covered | T4,T37,T31 |
LINE 8974
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T27 |
| 1 | 1 | 0 | Covered | T286,T292,T293 |
| 1 | 1 | 1 | Covered | T2,T3,T27 |
LINE 8999
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T28,T91,T21 |
| 1 | 1 | 0 | Covered | T279,T286,T292 |
| 1 | 1 | 1 | Covered | T28,T91,T21 |
LINE 9024
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T27,T4,T31 |
| 1 | 1 | 0 | Covered | T243,T279,T294 |
| 1 | 1 | 1 | Covered | T27,T4,T31 |
LINE 9049
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T31,T91,T33 |
| 1 | 1 | 0 | Covered | T242,T243,T279 |
| 1 | 1 | 1 | Covered | T31,T91,T33 |
LINE 9074
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T28,T91,T92 |
| 1 | 1 | 0 | Covered | T279,T286,T292 |
| 1 | 1 | 1 | Covered | T91,T92,T173 |
LINE 9099
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T34 |
| 1 | 1 | 0 | Covered | T279,T292,T293 |
| 1 | 1 | 1 | Covered | T4,T30,T34 |
LINE 9110
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T279,T286,T292 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9121
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T279,T292,T293 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9132
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T293,T295,T296 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9143
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T244,T279,T286 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9154
EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T243,T279,T291 |
| 1 | 1 | 1 | Covered | T30,T36,T5 |
LINE 9165
EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T243,T292,T293 |
| 1 | 1 | 1 | Covered | T4,T30,T36 |
LINE 9176
EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T31 |
| 1 | 1 | 0 | Covered | T279,T286,T293 |
| 1 | 1 | 1 | Covered | T30,T31,T35 |
LINE 9187
EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T27,T4 |
| 1 | 1 | 0 | Covered | T292,T296,T297 |
| 1 | 1 | 1 | Covered | T3,T27,T30 |
LINE 9198
EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T279,T286,T298 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9209
EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T292,T293,T295 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9220
EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T30,T36 |
| 1 | 1 | 0 | Covered | T279,T286,T295 |
| 1 | 1 | 1 | Covered | T30,T36,T23 |
LINE 9231
EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T91,T5 |
| 1 | 1 | 0 | Covered | T279,T286,T292 |
| 1 | 1 | 1 | Covered | T4,T91,T5 |
LINE 9256
EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T27,T4,T91 |
| 1 | 1 | 0 | Covered | T244,T279,T286 |
| 1 | 1 | 1 | Covered | T27,T4,T91 |