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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.56 98.14 95.98 97.44 94.92 98.34 98.17 92.94


Total test records in report: 3738
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T3568 /workspace/coverage/default/2.usbdev_invalid_sync.3154506018 Aug 10 07:00:46 PM PDT 24 Aug 10 07:01:22 PM PDT 24 4006591254 ps
T3569 /workspace/coverage/default/9.usbdev_iso_retraction.3788351017 Aug 10 07:05:27 PM PDT 24 Aug 10 07:06:42 PM PDT 24 10572774784 ps
T3570 /workspace/coverage/default/26.usbdev_low_speed_traffic.1477516745 Aug 10 07:11:29 PM PDT 24 Aug 10 07:12:45 PM PDT 24 2630733855 ps
T3571 /workspace/coverage/default/0.usbdev_min_length_in_transaction.1819029363 Aug 10 06:58:39 PM PDT 24 Aug 10 06:58:40 PM PDT 24 165973322 ps
T3572 /workspace/coverage/default/18.usbdev_out_trans_nak.579786952 Aug 10 07:09:06 PM PDT 24 Aug 10 07:09:07 PM PDT 24 177416174 ps
T3573 /workspace/coverage/default/27.usbdev_aon_wake_reset.1190963716 Aug 10 07:11:36 PM PDT 24 Aug 10 07:12:02 PM PDT 24 21175194185 ps
T3574 /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4114440943 Aug 10 07:03:02 PM PDT 24 Aug 10 07:04:05 PM PDT 24 2108803516 ps
T3575 /workspace/coverage/default/26.usbdev_data_toggle_restore.3742158898 Aug 10 07:11:27 PM PDT 24 Aug 10 07:11:31 PM PDT 24 1120916513 ps
T3576 /workspace/coverage/default/39.usbdev_endpoint_types.2584653269 Aug 10 07:14:26 PM PDT 24 Aug 10 07:14:28 PM PDT 24 471111232 ps
T3577 /workspace/coverage/default/310.usbdev_tx_rx_disruption.1339545826 Aug 10 07:18:11 PM PDT 24 Aug 10 07:18:12 PM PDT 24 472967331 ps
T3578 /workspace/coverage/default/5.usbdev_invalid_sync.3441664417 Aug 10 07:03:17 PM PDT 24 Aug 10 07:03:47 PM PDT 24 4328512401 ps
T3579 /workspace/coverage/default/36.usbdev_rx_crc_err.1501203613 Aug 10 07:13:55 PM PDT 24 Aug 10 07:13:56 PM PDT 24 153322788 ps
T3580 /workspace/coverage/default/6.usbdev_min_length_out_transaction.2130436322 Aug 10 07:04:06 PM PDT 24 Aug 10 07:04:07 PM PDT 24 152540794 ps
T3581 /workspace/coverage/default/1.usbdev_out_stall.3664985749 Aug 10 06:59:58 PM PDT 24 Aug 10 06:59:59 PM PDT 24 196438429 ps
T3582 /workspace/coverage/default/21.usbdev_iso_retraction.857683829 Aug 10 07:09:58 PM PDT 24 Aug 10 07:12:12 PM PDT 24 11410804209 ps
T3583 /workspace/coverage/default/43.usbdev_fifo_rst.3612468214 Aug 10 07:15:19 PM PDT 24 Aug 10 07:15:21 PM PDT 24 226336629 ps
T3584 /workspace/coverage/default/286.usbdev_tx_rx_disruption.427693638 Aug 10 07:18:04 PM PDT 24 Aug 10 07:18:06 PM PDT 24 535093250 ps
T3585 /workspace/coverage/default/24.usbdev_data_toggle_restore.1461302747 Aug 10 07:10:48 PM PDT 24 Aug 10 07:10:50 PM PDT 24 719912173 ps
T3586 /workspace/coverage/default/13.usbdev_out_trans_nak.589169434 Aug 10 07:07:19 PM PDT 24 Aug 10 07:07:20 PM PDT 24 154734828 ps
T3587 /workspace/coverage/default/4.usbdev_setup_priority.2684626029 Aug 10 07:03:00 PM PDT 24 Aug 10 07:03:01 PM PDT 24 337883874 ps
T3588 /workspace/coverage/default/46.usbdev_min_length_in_transaction.457120816 Aug 10 07:15:58 PM PDT 24 Aug 10 07:15:59 PM PDT 24 169873150 ps
T3589 /workspace/coverage/default/49.usbdev_in_iso.1147643557 Aug 10 07:16:46 PM PDT 24 Aug 10 07:16:48 PM PDT 24 218052381 ps
T3590 /workspace/coverage/default/10.usbdev_rx_full.231615633 Aug 10 07:06:13 PM PDT 24 Aug 10 07:06:14 PM PDT 24 326793248 ps
T3591 /workspace/coverage/default/6.usbdev_random_length_in_transaction.2398401844 Aug 10 07:04:13 PM PDT 24 Aug 10 07:04:14 PM PDT 24 164682760 ps
T3592 /workspace/coverage/default/41.usbdev_aon_wake_reset.2611016519 Aug 10 07:14:54 PM PDT 24 Aug 10 07:15:16 PM PDT 24 16057605849 ps
T3593 /workspace/coverage/default/17.usbdev_iso_retraction.1015074017 Aug 10 07:08:44 PM PDT 24 Aug 10 07:10:08 PM PDT 24 6391637392 ps
T3594 /workspace/coverage/default/13.usbdev_link_resume.343957448 Aug 10 07:07:16 PM PDT 24 Aug 10 07:08:05 PM PDT 24 27226336783 ps
T3595 /workspace/coverage/default/3.usbdev_av_overflow.416823736 Aug 10 07:01:25 PM PDT 24 Aug 10 07:01:26 PM PDT 24 138499064 ps
T3596 /workspace/coverage/default/4.usbdev_max_usb_traffic.1666116656 Aug 10 07:02:41 PM PDT 24 Aug 10 07:02:59 PM PDT 24 1754889188 ps
T3597 /workspace/coverage/default/17.usbdev_in_stall.690980384 Aug 10 07:08:44 PM PDT 24 Aug 10 07:08:45 PM PDT 24 145004586 ps
T3598 /workspace/coverage/default/33.usbdev_pkt_buffer.1126396024 Aug 10 07:13:27 PM PDT 24 Aug 10 07:14:08 PM PDT 24 17246458139 ps
T3599 /workspace/coverage/default/23.usbdev_in_iso.3740836887 Aug 10 07:10:32 PM PDT 24 Aug 10 07:10:33 PM PDT 24 219794972 ps
T3600 /workspace/coverage/default/46.usbdev_max_length_out_transaction.830464538 Aug 10 07:15:59 PM PDT 24 Aug 10 07:16:00 PM PDT 24 193037250 ps
T3601 /workspace/coverage/default/11.usbdev_device_timeout.3795569601 Aug 10 07:06:23 PM PDT 24 Aug 10 07:06:51 PM PDT 24 4328642191 ps
T3602 /workspace/coverage/default/48.usbdev_out_iso.2001050662 Aug 10 07:16:27 PM PDT 24 Aug 10 07:16:28 PM PDT 24 184237492 ps
T3603 /workspace/coverage/default/5.usbdev_rand_bus_resets.1866131522 Aug 10 07:03:36 PM PDT 24 Aug 10 07:04:26 PM PDT 24 7434773036 ps
T3604 /workspace/coverage/default/36.usbdev_phy_config_pinflip.3846730727 Aug 10 07:13:49 PM PDT 24 Aug 10 07:13:50 PM PDT 24 236689529 ps
T3605 /workspace/coverage/default/0.usbdev_pkt_received.3708616947 Aug 10 06:58:50 PM PDT 24 Aug 10 06:58:51 PM PDT 24 273259761 ps
T3606 /workspace/coverage/default/409.usbdev_tx_rx_disruption.2202517493 Aug 10 07:18:27 PM PDT 24 Aug 10 07:18:29 PM PDT 24 568633681 ps
T3607 /workspace/coverage/default/17.usbdev_aon_wake_resume.3969851415 Aug 10 07:08:29 PM PDT 24 Aug 10 07:08:58 PM PDT 24 23862906201 ps
T3608 /workspace/coverage/default/2.usbdev_enable.1737778267 Aug 10 07:00:38 PM PDT 24 Aug 10 07:00:39 PM PDT 24 43688446 ps
T3609 /workspace/coverage/default/23.usbdev_random_length_in_transaction.2581021140 Aug 10 07:10:38 PM PDT 24 Aug 10 07:10:39 PM PDT 24 272910381 ps
T3610 /workspace/coverage/default/1.usbdev_data_toggle_restore.3239949860 Aug 10 06:59:23 PM PDT 24 Aug 10 06:59:25 PM PDT 24 819293688 ps
T3611 /workspace/coverage/default/23.usbdev_nak_trans.2076726045 Aug 10 07:10:39 PM PDT 24 Aug 10 07:10:40 PM PDT 24 194039644 ps
T3612 /workspace/coverage/default/46.usbdev_setup_stage.1597406708 Aug 10 07:16:06 PM PDT 24 Aug 10 07:16:07 PM PDT 24 158947062 ps
T3613 /workspace/coverage/default/478.usbdev_tx_rx_disruption.2023518095 Aug 10 07:18:35 PM PDT 24 Aug 10 07:18:37 PM PDT 24 511933190 ps
T3614 /workspace/coverage/default/24.usbdev_tx_rx_disruption.3762598031 Aug 10 07:10:53 PM PDT 24 Aug 10 07:10:54 PM PDT 24 455183101 ps
T3615 /workspace/coverage/default/36.usbdev_alert_test.3980180098 Aug 10 07:14:07 PM PDT 24 Aug 10 07:14:08 PM PDT 24 50049775 ps
T3616 /workspace/coverage/default/9.usbdev_rx_full.2959763807 Aug 10 07:05:43 PM PDT 24 Aug 10 07:05:45 PM PDT 24 257587055 ps
T3617 /workspace/coverage/default/45.usbdev_bitstuff_err.3099855402 Aug 10 07:15:51 PM PDT 24 Aug 10 07:15:52 PM PDT 24 182262557 ps
T3618 /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1442657165 Aug 10 07:13:52 PM PDT 24 Aug 10 07:15:17 PM PDT 24 2960341030 ps
T3619 /workspace/coverage/default/11.usbdev_invalid_sync.1213351917 Aug 10 07:06:23 PM PDT 24 Aug 10 07:07:44 PM PDT 24 2927710113 ps
T3620 /workspace/coverage/default/27.usbdev_tx_rx_disruption.147006242 Aug 10 07:11:48 PM PDT 24 Aug 10 07:11:50 PM PDT 24 547976551 ps
T3621 /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4114358959 Aug 10 07:08:35 PM PDT 24 Aug 10 07:08:52 PM PDT 24 2571929139 ps
T3622 /workspace/coverage/default/15.usbdev_link_resume.3766142405 Aug 10 07:08:00 PM PDT 24 Aug 10 07:08:50 PM PDT 24 33462997628 ps
T3623 /workspace/coverage/default/15.usbdev_alert_test.2228017988 Aug 10 07:08:08 PM PDT 24 Aug 10 07:08:08 PM PDT 24 66093698 ps
T3624 /workspace/coverage/default/9.usbdev_disable_endpoint.428725620 Aug 10 07:05:26 PM PDT 24 Aug 10 07:05:28 PM PDT 24 1022551021 ps
T3625 /workspace/coverage/default/45.usbdev_tx_rx_disruption.2495722890 Aug 10 07:15:58 PM PDT 24 Aug 10 07:16:00 PM PDT 24 516954043 ps
T3626 /workspace/coverage/default/149.usbdev_endpoint_types.415656158 Aug 10 07:17:25 PM PDT 24 Aug 10 07:17:27 PM PDT 24 549423359 ps
T3627 /workspace/coverage/default/7.usbdev_pkt_received.3635384719 Aug 10 07:04:41 PM PDT 24 Aug 10 07:04:42 PM PDT 24 171249098 ps
T3628 /workspace/coverage/default/27.usbdev_pending_in_trans.1069822209 Aug 10 07:11:36 PM PDT 24 Aug 10 07:11:37 PM PDT 24 157833525 ps
T3629 /workspace/coverage/default/17.usbdev_av_buffer.2871006795 Aug 10 07:08:30 PM PDT 24 Aug 10 07:08:31 PM PDT 24 178260723 ps
T3630 /workspace/coverage/default/226.usbdev_tx_rx_disruption.1744058937 Aug 10 07:18:05 PM PDT 24 Aug 10 07:18:07 PM PDT 24 486950154 ps
T248 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2807745922 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 66970431 ps
T242 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3065864975 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:58 PM PDT 24 76272183 ps
T243 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2539105341 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:48 PM PDT 24 148217582 ps
T280 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.896206321 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:48 PM PDT 24 106002636 ps
T249 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1212071777 Aug 10 05:58:05 PM PDT 24 Aug 10 05:58:05 PM PDT 24 93663950 ps
T244 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.171291542 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:46 PM PDT 24 102411306 ps
T301 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3163554188 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:43 PM PDT 24 46613709 ps
T277 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2249958788 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:49 PM PDT 24 89103519 ps
T281 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4158161470 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:55 PM PDT 24 74080394 ps
T278 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3010805245 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:52 PM PDT 24 2054381348 ps
T250 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.985346534 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:46 PM PDT 24 50415777 ps
T279 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3549668494 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:57 PM PDT 24 85956716 ps
T251 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2788334382 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 39688042 ps
T335 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2852262738 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:47 PM PDT 24 72235788 ps
T321 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.504533226 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 112436310 ps
T284 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2838888439 Aug 10 05:57:36 PM PDT 24 Aug 10 05:57:41 PM PDT 24 761487932 ps
T370 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2550450322 Aug 10 05:57:44 PM PDT 24 Aug 10 05:57:45 PM PDT 24 103267452 ps
T342 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2972735429 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:47 PM PDT 24 915484969 ps
T346 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2501312113 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:07 PM PDT 24 46609189 ps
T3631 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1344945960 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 103699953 ps
T373 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3376322357 Aug 10 05:57:49 PM PDT 24 Aug 10 05:57:49 PM PDT 24 33851893 ps
T371 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3469296951 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:54 PM PDT 24 44839107 ps
T322 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.979138927 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:58 PM PDT 24 62745300 ps
T374 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1449874816 Aug 10 05:58:19 PM PDT 24 Aug 10 05:58:19 PM PDT 24 38585557 ps
T336 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1648070764 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 122146022 ps
T299 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1046843225 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:56 PM PDT 24 184709783 ps
T372 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4219948044 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:02 PM PDT 24 48839102 ps
T285 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.912500097 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:57 PM PDT 24 349138192 ps
T291 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.952537735 Aug 10 05:58:00 PM PDT 24 Aug 10 05:58:02 PM PDT 24 82246315 ps
T303 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2337504434 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:57 PM PDT 24 152184689 ps
T347 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.204339858 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:05 PM PDT 24 38738844 ps
T3632 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2292101519 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 55052050 ps
T3633 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.143340343 Aug 10 05:58:12 PM PDT 24 Aug 10 05:58:13 PM PDT 24 54178227 ps
T337 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.488916752 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:57 PM PDT 24 215833830 ps
T323 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3591971386 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:50 PM PDT 24 311224259 ps
T305 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3881545935 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:49 PM PDT 24 997140679 ps
T338 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1489725500 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 99579277 ps
T304 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4209216011 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 106752713 ps
T324 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2545121805 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:48 PM PDT 24 98657952 ps
T306 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2414813610 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:48 PM PDT 24 113643317 ps
T3634 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3231666433 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:45 PM PDT 24 87765512 ps
T519 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.619706473 Aug 10 05:57:57 PM PDT 24 Aug 10 05:58:01 PM PDT 24 493514276 ps
T286 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.508973188 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:49 PM PDT 24 182952619 ps
T3635 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.915935794 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:56 PM PDT 24 85464614 ps
T520 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1066597425 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:58 PM PDT 24 654977649 ps
T292 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3606270822 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:58 PM PDT 24 310934502 ps
T325 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1468040176 Aug 10 05:57:41 PM PDT 24 Aug 10 05:57:42 PM PDT 24 79695934 ps
T3636 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4226515787 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 59409699 ps
T3637 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.404382248 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 69385076 ps
T3638 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.506920687 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:43 PM PDT 24 83550737 ps
T3639 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.569236972 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 43802895 ps
T3640 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.495404318 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:57 PM PDT 24 129091412 ps
T326 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2181524673 Aug 10 05:58:00 PM PDT 24 Aug 10 05:58:01 PM PDT 24 122690629 ps
T3641 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2877304919 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 39638363 ps
T3642 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3283806289 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 40826664 ps
T327 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1227171695 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:48 PM PDT 24 306793581 ps
T328 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.454036578 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:55 PM PDT 24 78342489 ps
T3643 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.627847651 Aug 10 05:57:49 PM PDT 24 Aug 10 05:57:50 PM PDT 24 86128695 ps
T333 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1840994887 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:55 PM PDT 24 50104208 ps
T3644 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2396760908 Aug 10 05:57:50 PM PDT 24 Aug 10 05:57:51 PM PDT 24 106039917 ps
T343 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2868596609 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:57 PM PDT 24 1302400501 ps
T3645 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2656687326 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:47 PM PDT 24 67097284 ps
T3646 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3022497758 Aug 10 05:58:06 PM PDT 24 Aug 10 05:58:07 PM PDT 24 71452750 ps
T3647 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3706996138 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:58 PM PDT 24 50769717 ps
T344 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3244220364 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:43 PM PDT 24 158660010 ps
T3648 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4148758031 Aug 10 05:58:07 PM PDT 24 Aug 10 05:58:08 PM PDT 24 33531723 ps
T294 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1905847872 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:03 PM PDT 24 72525886 ps
T298 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1034452563 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:54 PM PDT 24 121028005 ps
T3649 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4243230629 Aug 10 05:58:09 PM PDT 24 Aug 10 05:58:10 PM PDT 24 57278982 ps
T3650 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2376420124 Aug 10 05:57:35 PM PDT 24 Aug 10 05:57:38 PM PDT 24 272923822 ps
T524 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1991038147 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:56 PM PDT 24 699149327 ps
T3651 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1539257109 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 97018884 ps
T293 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2321124156 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:55 PM PDT 24 129038647 ps
T3652 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.103933247 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:58 PM PDT 24 168294999 ps
T3653 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1210932557 Aug 10 05:58:08 PM PDT 24 Aug 10 05:58:09 PM PDT 24 55004317 ps
T334 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.512834687 Aug 10 05:57:34 PM PDT 24 Aug 10 05:57:35 PM PDT 24 116164311 ps
T300 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4257477506 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:59 PM PDT 24 210040372 ps
T3654 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3069490575 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:58 PM PDT 24 42393643 ps
T3655 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3419613249 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:54 PM PDT 24 50128062 ps
T345 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1857348725 Aug 10 05:57:48 PM PDT 24 Aug 10 05:57:49 PM PDT 24 105735472 ps
T3656 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2519216029 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:02 PM PDT 24 48870374 ps
T3657 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2495104750 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:03 PM PDT 24 63835516 ps
T3658 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3425649561 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:03 PM PDT 24 77692505 ps
T329 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2541160767 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:54 PM PDT 24 170203890 ps
T295 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2629457862 Aug 10 05:57:37 PM PDT 24 Aug 10 05:57:38 PM PDT 24 74269159 ps
T330 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.26821902 Aug 10 05:57:41 PM PDT 24 Aug 10 05:57:46 PM PDT 24 772629911 ps
T3659 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.410189133 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:54 PM PDT 24 53879566 ps
T3660 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3210579145 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 48127878 ps
T296 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1406134484 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:59 PM PDT 24 96086088 ps
T3661 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2350187859 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:54 PM PDT 24 135521994 ps
T3662 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3861322017 Aug 10 05:58:05 PM PDT 24 Aug 10 05:58:07 PM PDT 24 133378385 ps
T522 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2420269961 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:48 PM PDT 24 640045773 ps
T521 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2975756889 Aug 10 05:57:41 PM PDT 24 Aug 10 05:57:45 PM PDT 24 709673168 ps
T331 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4294771217 Aug 10 05:57:41 PM PDT 24 Aug 10 05:57:42 PM PDT 24 231787287 ps
T3663 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3996311413 Aug 10 05:57:50 PM PDT 24 Aug 10 05:57:52 PM PDT 24 196309697 ps
T3664 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.381988898 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:48 PM PDT 24 267791811 ps
T3665 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3492173716 Aug 10 05:58:05 PM PDT 24 Aug 10 05:58:06 PM PDT 24 44340813 ps
T3666 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1205186155 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 86687031 ps
T525 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2748235563 Aug 10 05:57:49 PM PDT 24 Aug 10 05:57:54 PM PDT 24 1270032312 ps
T3667 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2888502820 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:50 PM PDT 24 370137740 ps
T523 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3839744278 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:59 PM PDT 24 1508171872 ps
T3668 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.371521166 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:07 PM PDT 24 406568116 ps
T3669 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1995752504 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:43 PM PDT 24 42566039 ps
T332 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2284235874 Aug 10 05:57:44 PM PDT 24 Aug 10 05:57:48 PM PDT 24 392310265 ps
T526 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1132128399 Aug 10 05:57:56 PM PDT 24 Aug 10 05:58:02 PM PDT 24 2082086642 ps
T3670 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3775502515 Aug 10 05:57:36 PM PDT 24 Aug 10 05:57:38 PM PDT 24 201318260 ps
T3671 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2431265269 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:53 PM PDT 24 46240181 ps
T3672 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.39430534 Aug 10 05:57:40 PM PDT 24 Aug 10 05:57:43 PM PDT 24 182294607 ps
T3673 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2438966767 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:53 PM PDT 24 144625311 ps
T3674 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1420617205 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:02 PM PDT 24 114410212 ps
T3675 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.43058440 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 39856790 ps
T3676 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.814005998 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:47 PM PDT 24 52124213 ps
T3677 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1795421950 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:55 PM PDT 24 78113154 ps
T3678 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3379752862 Aug 10 05:57:59 PM PDT 24 Aug 10 05:58:01 PM PDT 24 161190261 ps
T3679 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.981980145 Aug 10 05:57:35 PM PDT 24 Aug 10 05:57:36 PM PDT 24 33727088 ps
T3680 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3660946742 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:48 PM PDT 24 490015323 ps
T3681 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2699040600 Aug 10 05:57:59 PM PDT 24 Aug 10 05:58:04 PM PDT 24 46110399 ps
T3682 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3137995905 Aug 10 05:57:58 PM PDT 24 Aug 10 05:58:00 PM PDT 24 130460755 ps
T3683 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2129370691 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:52 PM PDT 24 32846132 ps
T3684 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4207013432 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:46 PM PDT 24 318782588 ps
T3685 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.426324564 Aug 10 05:57:48 PM PDT 24 Aug 10 05:57:49 PM PDT 24 114247041 ps
T3686 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4110370857 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:48 PM PDT 24 172229213 ps
T3687 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2541397900 Aug 10 05:57:41 PM PDT 24 Aug 10 05:57:42 PM PDT 24 66812997 ps
T3688 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2930979224 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 106688486 ps
T3689 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3747778364 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:07 PM PDT 24 875637731 ps
T3690 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2310698188 Aug 10 05:57:57 PM PDT 24 Aug 10 05:58:01 PM PDT 24 138043908 ps
T3691 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.626533928 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:47 PM PDT 24 830787043 ps
T3692 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.172878655 Aug 10 05:57:58 PM PDT 24 Aug 10 05:57:59 PM PDT 24 67154691 ps
T3693 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2745625990 Aug 10 05:57:44 PM PDT 24 Aug 10 05:57:46 PM PDT 24 62101657 ps
T3694 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.816513135 Aug 10 05:57:55 PM PDT 24 Aug 10 05:57:56 PM PDT 24 46668106 ps
T3695 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2717710979 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:43 PM PDT 24 56496804 ps
T3696 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.549636933 Aug 10 05:58:17 PM PDT 24 Aug 10 05:58:18 PM PDT 24 36205986 ps
T3697 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1591648457 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:51 PM PDT 24 60267188 ps
T297 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2465888602 Aug 10 05:57:58 PM PDT 24 Aug 10 05:58:00 PM PDT 24 176088104 ps
T3698 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.573064587 Aug 10 05:57:53 PM PDT 24 Aug 10 05:57:53 PM PDT 24 50851461 ps
T3699 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1296080289 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:48 PM PDT 24 207477094 ps
T3700 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3028470191 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:53 PM PDT 24 206097137 ps
T3701 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2861191251 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 72252696 ps
T3702 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2331207658 Aug 10 05:57:43 PM PDT 24 Aug 10 05:57:46 PM PDT 24 274393528 ps
T3703 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.764795527 Aug 10 05:57:57 PM PDT 24 Aug 10 05:57:59 PM PDT 24 90635358 ps
T3704 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3420091450 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:55 PM PDT 24 1754975353 ps
T3705 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1813237160 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:03 PM PDT 24 44642706 ps
T3706 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.339261693 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:48 PM PDT 24 90860227 ps
T3707 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2363183622 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:45 PM PDT 24 109827035 ps
T3708 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2875532398 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:05 PM PDT 24 38904620 ps
T3709 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3411391182 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:06 PM PDT 24 173918114 ps
T3710 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.245672088 Aug 10 05:57:47 PM PDT 24 Aug 10 05:57:48 PM PDT 24 72844242 ps
T3711 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3986916759 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 79043838 ps
T3712 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2196188678 Aug 10 05:58:01 PM PDT 24 Aug 10 05:58:04 PM PDT 24 144995769 ps
T3713 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1498833801 Aug 10 05:57:42 PM PDT 24 Aug 10 05:57:43 PM PDT 24 82741419 ps
T3714 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1847276893 Aug 10 05:57:40 PM PDT 24 Aug 10 05:57:42 PM PDT 24 165437403 ps
T3715 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.687421827 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:05 PM PDT 24 258243113 ps
T3716 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1431830253 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 139034800 ps
T3717 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1177051613 Aug 10 05:57:51 PM PDT 24 Aug 10 05:57:52 PM PDT 24 49232401 ps
T3718 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1940755001 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:49 PM PDT 24 144957649 ps
T3719 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.751763564 Aug 10 05:58:04 PM PDT 24 Aug 10 05:58:05 PM PDT 24 68328706 ps
T3720 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3274219213 Aug 10 05:58:00 PM PDT 24 Aug 10 05:58:04 PM PDT 24 1043696523 ps
T3721 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2965382504 Aug 10 05:58:03 PM PDT 24 Aug 10 05:58:04 PM PDT 24 41123125 ps
T3722 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2053940940 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:57 PM PDT 24 90081203 ps
T3723 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3455736315 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:58 PM PDT 24 117798269 ps
T3724 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.350876272 Aug 10 05:57:45 PM PDT 24 Aug 10 05:57:47 PM PDT 24 303251979 ps
T3725 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2188342157 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:53 PM PDT 24 43843744 ps
T3726 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3456931142 Aug 10 05:57:44 PM PDT 24 Aug 10 05:57:45 PM PDT 24 91511403 ps
T3727 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764909030 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:57 PM PDT 24 196527293 ps
T3728 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1248968432 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:48 PM PDT 24 140180750 ps
T3729 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.770838831 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:47 PM PDT 24 46126564 ps
T3730 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1737972431 Aug 10 05:58:00 PM PDT 24 Aug 10 05:58:02 PM PDT 24 165294346 ps
T3731 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4069600973 Aug 10 05:57:58 PM PDT 24 Aug 10 05:57:59 PM PDT 24 80495142 ps
T3732 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1325727992 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:47 PM PDT 24 79772155 ps
T3733 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3000522042 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:56 PM PDT 24 285259696 ps
T3734 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2209711066 Aug 10 05:57:56 PM PDT 24 Aug 10 05:57:58 PM PDT 24 195983795 ps
T3735 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.996774175 Aug 10 05:58:02 PM PDT 24 Aug 10 05:58:05 PM PDT 24 281415884 ps
T3736 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.741077300 Aug 10 05:57:54 PM PDT 24 Aug 10 05:57:56 PM PDT 24 144535967 ps
T3737 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1733622368 Aug 10 05:57:52 PM PDT 24 Aug 10 05:57:54 PM PDT 24 434972905 ps
T3738 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.733590636 Aug 10 05:57:46 PM PDT 24 Aug 10 05:57:51 PM PDT 24 635489573 ps

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2077657378
Short name T30
Test name
Test status
Simulation time 6122402255 ps
CPU time 16.15 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:40 PM PDT 24
Peak memory 224100 kb
Host smart-93548234-fc35-4ed6-bbc9-ead6c8835b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20776
57378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2077657378
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2362001693
Short name T36
Test name
Test status
Simulation time 974969027 ps
CPU time 2.39 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:16 PM PDT 24
Peak memory 207692 kb
Host smart-cb440afe-9ae1-47ee-8957-161789bc3393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23620
01693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2362001693
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/81.usbdev_endpoint_types.1757398665
Short name T92
Test name
Test status
Simulation time 384507043 ps
CPU time 1.33 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207568 kb
Host smart-37179c45-4644-4203-9e1b-d538d246a828
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1757398665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1757398665
Directory /workspace/81.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3742795414
Short name T9
Test name
Test status
Simulation time 9817546042 ps
CPU time 11.86 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:21 PM PDT 24
Peak memory 207892 kb
Host smart-e65c05a8-4085-4167-9a25-41b942ff7ef0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742795414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.3742795414
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.985346534
Short name T250
Test name
Test status
Simulation time 50415777 ps
CPU time 0.71 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 206644 kb
Host smart-eb977cb0-5d9b-48c4-ac0f-c542a694d5d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=985346534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.985346534
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.4064613224
Short name T68
Test name
Test status
Simulation time 4422200173 ps
CPU time 46.36 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:07:11 PM PDT 24
Peak memory 219092 kb
Host smart-b3cc8270-bd57-4c6b-8fb9-962071d593e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4064613224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.4064613224
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2838888439
Short name T284
Test name
Test status
Simulation time 761487932 ps
CPU time 4.82 seconds
Started Aug 10 05:57:36 PM PDT 24
Finished Aug 10 05:57:41 PM PDT 24
Peak memory 206956 kb
Host smart-298439bb-aea0-47c4-9f6f-026e70beea56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2838888439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2838888439
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.67147122
Short name T71
Test name
Test status
Simulation time 29048949219 ps
CPU time 46.39 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:51 PM PDT 24
Peak memory 207856 kb
Host smart-a2115aed-523d-475c-9015-925c6de54f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67147
122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.67147122
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3795883219
Short name T110
Test name
Test status
Simulation time 1350428355 ps
CPU time 3.48 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:13:00 PM PDT 24
Peak memory 207748 kb
Host smart-3312988f-0130-4f63-85cd-f76b2f678e0d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3795883219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3795883219
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1625325224
Short name T114
Test name
Test status
Simulation time 44617074989 ps
CPU time 70.77 seconds
Started Aug 10 07:12:55 PM PDT 24
Finished Aug 10 07:14:06 PM PDT 24
Peak memory 207776 kb
Host smart-f1e7e800-d91a-4b3a-bd36-d29ea83893ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
25224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1625325224
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2013281761
Short name T97
Test name
Test status
Simulation time 24473917677 ps
CPU time 31.65 seconds
Started Aug 10 07:03:17 PM PDT 24
Finished Aug 10 07:03:49 PM PDT 24
Peak memory 215876 kb
Host smart-043c09ea-7f32-4028-9efe-3b512bee2259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20132
81761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2013281761
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.100761405
Short name T265
Test name
Test status
Simulation time 302471661 ps
CPU time 1.13 seconds
Started Aug 10 06:58:41 PM PDT 24
Finished Aug 10 06:58:42 PM PDT 24
Peak memory 207424 kb
Host smart-0741bb3f-504c-4e32-a961-655470cb8bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10076
1405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.100761405
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1182730191
Short name T25
Test name
Test status
Simulation time 47524726 ps
CPU time 0.7 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207536 kb
Host smart-fa85789a-63e4-4b3b-891f-590c9d5804dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11827
30191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1182730191
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/268.usbdev_tx_rx_disruption.3173763841
Short name T76
Test name
Test status
Simulation time 502919871 ps
CPU time 1.52 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207604 kb
Host smart-913ec464-5031-4688-954f-42710f8daf4c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173763841 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.usbdev_tx_rx_disruption.3173763841
Directory /workspace/268.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_tx_rx_disruption.2975705710
Short name T266
Test name
Test status
Simulation time 616002875 ps
CPU time 1.55 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 207564 kb
Host smart-f7594289-3538-4dfe-b1fe-7f599aa65cc0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975705710 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.usbdev_tx_rx_disruption.2975705710
Directory /workspace/33.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.473564666
Short name T252
Test name
Test status
Simulation time 259653909 ps
CPU time 1.09 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 223492 kb
Host smart-63d9f634-a5cb-4a31-b015-e3ca54d14ab1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=473564666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.473564666
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3469296951
Short name T371
Test name
Test status
Simulation time 44839107 ps
CPU time 0.72 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 206624 kb
Host smart-86cacd2a-6d85-4b21-9c26-cfae3ea12ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3469296951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3469296951
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4208971007
Short name T11
Test name
Test status
Simulation time 20468731076 ps
CPU time 26.31 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207804 kb
Host smart-72d243d1-a2c7-4df2-8bfe-8d7b52cf4acb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208971007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4208971007
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3549668494
Short name T279
Test name
Test status
Simulation time 85956716 ps
CPU time 2.05 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206984 kb
Host smart-f590fab6-6a97-4ebd-9973-f6a3477d3f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3549668494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3549668494
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.243121741
Short name T104
Test name
Test status
Simulation time 15120584352 ps
CPU time 18.22 seconds
Started Aug 10 07:07:27 PM PDT 24
Finished Aug 10 07:07:45 PM PDT 24
Peak memory 215872 kb
Host smart-314bd4d4-0be7-40c2-aae8-c6f64905f102
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=243121741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.243121741
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/113.usbdev_tx_rx_disruption.4130209588
Short name T273
Test name
Test status
Simulation time 576667935 ps
CPU time 1.67 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207600 kb
Host smart-3e247f8d-ceea-4e04-b22e-e4f480a36d65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130209588 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.usbdev_tx_rx_disruption.4130209588
Directory /workspace/113.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_tx_rx_disruption.3124943125
Short name T270
Test name
Test status
Simulation time 557068005 ps
CPU time 1.66 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:10:11 PM PDT 24
Peak memory 207472 kb
Host smart-7a443ac1-f787-4ea9-ae3e-ae9b0783a7f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124943125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.usbdev_tx_rx_disruption.3124943125
Directory /workspace/21.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.979138927
Short name T322
Test name
Test status
Simulation time 62745300 ps
CPU time 0.8 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206688 kb
Host smart-bbdfe51d-614f-4b89-b734-a857977b208b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=979138927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.979138927
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/default/33.usbdev_rx_full.498098154
Short name T20
Test name
Test status
Simulation time 249586076 ps
CPU time 1.06 seconds
Started Aug 10 07:13:27 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207460 kb
Host smart-f0652c43-ed03-4370-b7a2-2c9c94ab44b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49809
8154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.498098154
Directory /workspace/33.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_device_address.283808608
Short name T1051
Test name
Test status
Simulation time 46989693016 ps
CPU time 76.61 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:16:54 PM PDT 24
Peak memory 207964 kb
Host smart-68245343-4593-48cf-bf74-76f72db320ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28380
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.283808608
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/430.usbdev_tx_rx_disruption.4269518682
Short name T239
Test name
Test status
Simulation time 504671036 ps
CPU time 1.63 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207536 kb
Host smart-ae2fd226-c21b-42ae-b9c9-cc395b0f1a9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269518682 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 430.usbdev_tx_rx_disruption.4269518682
Directory /workspace/430.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.4093991959
Short name T721
Test name
Test status
Simulation time 142110871 ps
CPU time 0.84 seconds
Started Aug 10 07:08:55 PM PDT 24
Finished Aug 10 07:08:56 PM PDT 24
Peak memory 207572 kb
Host smart-4befc338-e349-48d7-9cfa-79de6a773a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40939
91959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.4093991959
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_types.3315527301
Short name T307
Test name
Test status
Simulation time 716022016 ps
CPU time 1.68 seconds
Started Aug 10 07:08:36 PM PDT 24
Finished Aug 10 07:08:38 PM PDT 24
Peak memory 207492 kb
Host smart-a339247a-153d-4e28-b817-f0db3df1aab7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3315527301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.3315527301
Directory /workspace/17.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/124.usbdev_endpoint_types.1180175639
Short name T397
Test name
Test status
Simulation time 830743185 ps
CPU time 2.02 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207472 kb
Host smart-5d38786a-0cc6-45ec-91c5-ddec87a36dca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1180175639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.1180175639
Directory /workspace/124.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/160.usbdev_endpoint_types.3682007210
Short name T495
Test name
Test status
Simulation time 473263259 ps
CPU time 1.45 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207384 kb
Host smart-64ddc665-e642-45c2-8e60-95a2a3c9a2ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3682007210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.3682007210
Directory /workspace/160.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.327348926
Short name T22
Test name
Test status
Simulation time 167310153 ps
CPU time 0.82 seconds
Started Aug 10 07:12:13 PM PDT 24
Finished Aug 10 07:12:14 PM PDT 24
Peak memory 207500 kb
Host smart-96c6be9c-6b1b-494a-871a-64d495651fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
8926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.327348926
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1212071777
Short name T249
Test name
Test status
Simulation time 93663950 ps
CPU time 0.78 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206580 kb
Host smart-7fb4c3ed-2aa8-4404-a9de-560fe6694077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1212071777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1212071777
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/151.usbdev_endpoint_types.4108116262
Short name T487
Test name
Test status
Simulation time 529146017 ps
CPU time 1.45 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207572 kb
Host smart-f8c36d1e-2962-4bd0-9b55-ebdbd3fa865f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4108116262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.4108116262
Directory /workspace/151.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3969009125
Short name T698
Test name
Test status
Simulation time 139688999 ps
CPU time 0.84 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 207528 kb
Host smart-94fd0d78-9319-4025-a4ac-c52ac898c4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
09125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3969009125
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/122.usbdev_endpoint_types.2092532734
Short name T378
Test name
Test status
Simulation time 609620555 ps
CPU time 1.56 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:19 PM PDT 24
Peak memory 207572 kb
Host smart-144ab898-f241-49f0-8cde-02870f9bca18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2092532734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.2092532734
Directory /workspace/122.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/71.usbdev_endpoint_types.3950182004
Short name T506
Test name
Test status
Simulation time 588391874 ps
CPU time 1.69 seconds
Started Aug 10 07:16:54 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 207556 kb
Host smart-48171ab0-d3e5-4700-aa12-f14c5a58be13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3950182004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.3950182004
Directory /workspace/71.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.3315160640
Short name T117
Test name
Test status
Simulation time 2920117788 ps
CPU time 27.59 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 217420 kb
Host smart-891b2ff0-d54a-48cb-bbe0-419eb85ff407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
60640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.3315160640
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1756400326
Short name T246
Test name
Test status
Simulation time 25650914281 ps
CPU time 34.57 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:58 PM PDT 24
Peak memory 216060 kb
Host smart-e0b7cabb-3a9f-47f9-88cd-a0609152f791
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756400326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.1756400326
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2591397122
Short name T443
Test name
Test status
Simulation time 35686443847 ps
CPU time 55.32 seconds
Started Aug 10 07:05:25 PM PDT 24
Finished Aug 10 07:06:21 PM PDT 24
Peak memory 207844 kb
Host smart-0685a4b4-120d-4fdb-a9d7-4a969f52fc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
97122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2591397122
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/131.usbdev_endpoint_types.3666475472
Short name T405
Test name
Test status
Simulation time 457685097 ps
CPU time 1.37 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207628 kb
Host smart-99636ef5-3b68-41e9-9dc4-b83003fdee46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3666475472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.3666475472
Directory /workspace/131.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/192.usbdev_endpoint_types.340537490
Short name T408
Test name
Test status
Simulation time 556719290 ps
CPU time 1.46 seconds
Started Aug 10 07:17:50 PM PDT 24
Finished Aug 10 07:17:52 PM PDT 24
Peak memory 207516 kb
Host smart-93ecbe10-bf79-4924-807c-00566de89158
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=340537490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.340537490
Directory /workspace/192.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/69.usbdev_endpoint_types.3731365372
Short name T406
Test name
Test status
Simulation time 553644514 ps
CPU time 1.57 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207492 kb
Host smart-2d326154-25e0-4523-9837-5e6e83d7c468
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3731365372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.3731365372
Directory /workspace/69.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/92.usbdev_endpoint_types.469766034
Short name T467
Test name
Test status
Simulation time 415759864 ps
CPU time 1.38 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207472 kb
Host smart-9964de0d-ee14-4192-9e17-c4c49364bdcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=469766034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.469766034
Directory /workspace/92.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2483541769
Short name T82
Test name
Test status
Simulation time 5780103766 ps
CPU time 52.94 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:01:13 PM PDT 24
Peak memory 218792 kb
Host smart-b65816a3-8363-44e2-b6cb-595ec927f859
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483541769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2483541769
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/139.usbdev_endpoint_types.528183954
Short name T428
Test name
Test status
Simulation time 648909246 ps
CPU time 1.62 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207512 kb
Host smart-ebad6e7a-bc07-46ed-b56e-d9466d74b21d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=528183954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.528183954
Directory /workspace/139.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1856476191
Short name T362
Test name
Test status
Simulation time 1065974345 ps
CPU time 2.69 seconds
Started Aug 10 07:14:30 PM PDT 24
Finished Aug 10 07:14:33 PM PDT 24
Peak memory 207736 kb
Host smart-ffba9018-ffbd-4a6e-a9d4-ee8574da1951
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1856476191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1856476191
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.2089205908
Short name T2728
Test name
Test status
Simulation time 411495977 ps
CPU time 1.37 seconds
Started Aug 10 06:59:07 PM PDT 24
Finished Aug 10 06:59:08 PM PDT 24
Peak memory 207580 kb
Host smart-39db10f1-0c72-4883-8dea-3a10e96da20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20892
05908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2089205908
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.619706473
Short name T519
Test name
Test status
Simulation time 493514276 ps
CPU time 4.01 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:58:01 PM PDT 24
Peak memory 206904 kb
Host smart-a4e0ff8c-2f0d-4ad8-8ec7-75e52e898213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=619706473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.619706473
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/117.usbdev_endpoint_types.413141217
Short name T399
Test name
Test status
Simulation time 598562442 ps
CPU time 1.58 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207488 kb
Host smart-ecfa65cd-d6ce-4278-a7b4-8cc73b20eff5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=413141217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.413141217
Directory /workspace/117.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/119.usbdev_endpoint_types.4281246174
Short name T407
Test name
Test status
Simulation time 521847660 ps
CPU time 1.51 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207572 kb
Host smart-b6f4f17a-eb70-4a0f-8c48-fe6bc38f78a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4281246174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.4281246174
Directory /workspace/119.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/140.usbdev_endpoint_types.3080095998
Short name T417
Test name
Test status
Simulation time 350821681 ps
CPU time 1.25 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207552 kb
Host smart-f037b39d-13c9-4c2a-ac86-2c09529bad2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3080095998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.3080095998
Directory /workspace/140.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/94.usbdev_endpoint_types.4019402151
Short name T437
Test name
Test status
Simulation time 506544707 ps
CPU time 1.65 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207540 kb
Host smart-a3a0fcc1-1bcf-4654-b15e-9a76c6664407
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4019402151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.4019402151
Directory /workspace/94.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1213419893
Short name T748
Test name
Test status
Simulation time 42540535 ps
CPU time 0.66 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207664 kb
Host smart-29786a97-a734-4f32-9389-e80490655c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1213419893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1213419893
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/113.usbdev_endpoint_types.4107384427
Short name T2985
Test name
Test status
Simulation time 516895378 ps
CPU time 1.38 seconds
Started Aug 10 07:17:15 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207476 kb
Host smart-46a06af5-de03-47c7-896f-110ed5eb91be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4107384427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.4107384427
Directory /workspace/113.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/114.usbdev_endpoint_types.4153592647
Short name T290
Test name
Test status
Simulation time 543184621 ps
CPU time 1.47 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207572 kb
Host smart-ef26d043-950c-4aa1-9462-70b39929e80c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4153592647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.4153592647
Directory /workspace/114.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2672751247
Short name T573
Test name
Test status
Simulation time 156892331 ps
CPU time 0.9 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:15 PM PDT 24
Peak memory 207528 kb
Host smart-45b33840-c865-497a-85fd-a3b3659db9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
51247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2672751247
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/138.usbdev_endpoint_types.1899845556
Short name T430
Test name
Test status
Simulation time 655811727 ps
CPU time 1.63 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207472 kb
Host smart-c744f442-3f5c-40cc-aa17-a9a0dc82f41a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1899845556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.1899845556
Directory /workspace/138.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_endpoint_types.2578997746
Short name T433
Test name
Test status
Simulation time 399180434 ps
CPU time 1.47 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207536 kb
Host smart-bf1a2e60-8ed1-4e15-82e1-ce193ff9f050
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2578997746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2578997746
Directory /workspace/154.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3031439304
Short name T356
Test name
Test status
Simulation time 842229487 ps
CPU time 2.15 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:41 PM PDT 24
Peak memory 207768 kb
Host smart-eb32e4ab-f896-469e-bdd9-bf5486ad7176
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3031439304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3031439304
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_types.4024990398
Short name T413
Test name
Test status
Simulation time 363087252 ps
CPU time 1.16 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:28 PM PDT 24
Peak memory 207404 kb
Host smart-95331d86-e5b8-4b89-ac5f-9b9219a91fd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4024990398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.4024990398
Directory /workspace/23.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1665222366
Short name T535
Test name
Test status
Simulation time 3492928433 ps
CPU time 25.75 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:49 PM PDT 24
Peak memory 224216 kb
Host smart-e34a9f88-8910-4c24-8d3f-1b6f3c4583fc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1665222366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1665222366
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/70.usbdev_endpoint_types.3151142128
Short name T396
Test name
Test status
Simulation time 842829142 ps
CPU time 1.93 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207500 kb
Host smart-64e705a6-5f24-4aac-b4e0-43e37ae22622
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3151142128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.3151142128
Directory /workspace/70.usbdev_endpoint_types/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2321124156
Short name T293
Test name
Test status
Simulation time 129038647 ps
CPU time 2.44 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 222996 kb
Host smart-878092fd-658b-47f7-91fc-c02766d6cdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321124156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2321124156
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4109847208
Short name T67
Test name
Test status
Simulation time 16406405504 ps
CPU time 40.39 seconds
Started Aug 10 07:02:49 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 216052 kb
Host smart-0468896e-16cd-45e4-b58f-d86c44d4948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41098
47208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4109847208
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4128143523
Short name T28
Test name
Test status
Simulation time 214049036 ps
CPU time 1.05 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207504 kb
Host smart-7f027c5d-6e6f-4c44-9b09-0659b4d14985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
43523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4128143523
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.4077552229
Short name T65
Test name
Test status
Simulation time 155811800 ps
CPU time 0.87 seconds
Started Aug 10 06:57:30 PM PDT 24
Finished Aug 10 06:57:31 PM PDT 24
Peak memory 207496 kb
Host smart-38a7033f-edbc-431d-bdab-d80f65f21726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
52229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.4077552229
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/42.usbdev_device_address.286452674
Short name T1433
Test name
Test status
Simulation time 32291854347 ps
CPU time 60.37 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207844 kb
Host smart-3434097c-8dac-4678-8d2f-02aa936e5339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28645
2674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.286452674
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2868596609
Short name T343
Test name
Test status
Simulation time 1302400501 ps
CPU time 5.58 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206912 kb
Host smart-59ad4115-10a4-4f7f-a046-f564cf71b3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2868596609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2868596609
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2379904246
Short name T368
Test name
Test status
Simulation time 5119400244 ps
CPU time 148.92 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 07:00:10 PM PDT 24
Peak memory 216008 kb
Host smart-185afd44-aa5f-4dda-8ed8-dfbe2fff1d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23799
04246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2379904246
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/11.usbdev_rx_full.2024636856
Short name T2878
Test name
Test status
Simulation time 252735799 ps
CPU time 1.08 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207528 kb
Host smart-ae1be68e-e1bb-432b-8635-172d4892a37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
36856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.2024636856
Directory /workspace/11.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_types.2045693768
Short name T458
Test name
Test status
Simulation time 295735000 ps
CPU time 1.08 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207488 kb
Host smart-f32988df-d96b-4d83-b33e-84b3da5bd9d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2045693768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.2045693768
Directory /workspace/12.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/147.usbdev_endpoint_types.1957454266
Short name T470
Test name
Test status
Simulation time 427599830 ps
CPU time 1.33 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207532 kb
Host smart-d91d97fb-c008-4458-b329-87c55b630065
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1957454266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.1957454266
Directory /workspace/147.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/166.usbdev_endpoint_types.3914783639
Short name T485
Test name
Test status
Simulation time 221768200 ps
CPU time 1 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207524 kb
Host smart-f0e928fe-cff8-45e5-a595-04d904b242ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3914783639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.3914783639
Directory /workspace/166.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/170.usbdev_endpoint_types.1229227302
Short name T431
Test name
Test status
Simulation time 525206951 ps
CPU time 1.44 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207568 kb
Host smart-3a654873-ee58-41a9-ae27-29471e8130fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1229227302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.1229227302
Directory /workspace/170.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_types.3583810942
Short name T391
Test name
Test status
Simulation time 779998114 ps
CPU time 1.74 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207556 kb
Host smart-4992895e-f339-4b4d-bb3d-1452d282ad3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3583810942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.3583810942
Directory /workspace/41.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/68.usbdev_endpoint_types.1131291871
Short name T384
Test name
Test status
Simulation time 644225230 ps
CPU time 1.55 seconds
Started Aug 10 07:17:10 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207532 kb
Host smart-95284b5a-67c3-40f9-a1ec-bd8ceed0af80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1131291871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.1131291871
Directory /workspace/68.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3127430469
Short name T205
Test name
Test status
Simulation time 5378611273 ps
CPU time 41.21 seconds
Started Aug 10 07:02:13 PM PDT 24
Finished Aug 10 07:02:54 PM PDT 24
Peak memory 224308 kb
Host smart-4ce63529-202b-4f49-9eb5-dde4e42ae3c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127430469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3127430469
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2469351663
Short name T169
Test name
Test status
Simulation time 3636659295 ps
CPU time 103.61 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:07:56 PM PDT 24
Peak memory 224252 kb
Host smart-de0d3216-2097-4646-8764-6495c2f49108
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2469351663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2469351663
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1187109857
Short name T184
Test name
Test status
Simulation time 4001223213 ps
CPU time 93.98 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 218692 kb
Host smart-0f32ac25-71af-4d1c-ac91-6b49c5bced01
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1187109857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1187109857
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_types.1461908363
Short name T119
Test name
Test status
Simulation time 492677272 ps
CPU time 1.48 seconds
Started Aug 10 07:12:17 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207492 kb
Host smart-1ec573f7-8826-4d73-9b91-ba8abccaff9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1461908363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.1461908363
Directory /workspace/29.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1659710468
Short name T26
Test name
Test status
Simulation time 84586005 ps
CPU time 0.74 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 207472 kb
Host smart-2d95126f-93bc-4b7e-92dd-53d0905362d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16597
10468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1659710468
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3010805245
Short name T278
Test name
Test status
Simulation time 2054381348 ps
CPU time 5.9 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:52 PM PDT 24
Peak memory 206940 kb
Host smart-fc3b84b0-9c2d-4499-a29e-ed658cf577f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3010805245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3010805245
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3376322357
Short name T373
Test name
Test status
Simulation time 33851893 ps
CPU time 0.68 seconds
Started Aug 10 05:57:49 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 206484 kb
Host smart-5d5f6652-e2ab-4e9d-abe9-c51adb8401d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376322357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3376322357
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_rx_full.231615633
Short name T3590
Test name
Test status
Simulation time 326793248 ps
CPU time 1.19 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207464 kb
Host smart-955ba777-d59a-4b25-93a5-3045721ebb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
5633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.231615633
Directory /workspace/10.usbdev_rx_full/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2055885365
Short name T19
Test name
Test status
Simulation time 176832700 ps
CPU time 0.89 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:13 PM PDT 24
Peak memory 207572 kb
Host smart-559d035f-220b-44a1-bed2-ad8696b37225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20558
85365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2055885365
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/101.usbdev_endpoint_types.143241680
Short name T421
Test name
Test status
Simulation time 504118677 ps
CPU time 1.32 seconds
Started Aug 10 07:17:08 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207452 kb
Host smart-3e5a4c04-d818-4ec3-a6ce-a3ec130ba69d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=143241680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.143241680
Directory /workspace/101.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/102.usbdev_endpoint_types.2126524736
Short name T380
Test name
Test status
Simulation time 602182651 ps
CPU time 1.56 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207528 kb
Host smart-27752601-4e9c-4653-b3c7-2e440ccdf777
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2126524736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.2126524736
Directory /workspace/102.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1136915044
Short name T422
Test name
Test status
Simulation time 27771212992 ps
CPU time 45.52 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 208036 kb
Host smart-7c08afc9-fe5e-4e41-8ea8-a7a645638784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
15044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1136915044
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/110.usbdev_endpoint_types.175275126
Short name T402
Test name
Test status
Simulation time 422553739 ps
CPU time 1.19 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207516 kb
Host smart-8204477c-ce86-43a6-8acb-26028048cf8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=175275126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.175275126
Directory /workspace/110.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/123.usbdev_endpoint_types.1867701985
Short name T426
Test name
Test status
Simulation time 701699203 ps
CPU time 1.6 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207568 kb
Host smart-bd5ed3f3-f255-4d79-b0c2-eaf821277133
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1867701985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.1867701985
Directory /workspace/123.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/126.usbdev_endpoint_types.2607207532
Short name T173
Test name
Test status
Simulation time 344339220 ps
CPU time 1.15 seconds
Started Aug 10 07:17:12 PM PDT 24
Finished Aug 10 07:17:13 PM PDT 24
Peak memory 207516 kb
Host smart-56091f8c-c638-4ed6-9665-c963db304d7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2607207532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.2607207532
Directory /workspace/126.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/128.usbdev_endpoint_types.832116808
Short name T414
Test name
Test status
Simulation time 835033994 ps
CPU time 1.91 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:19 PM PDT 24
Peak memory 207536 kb
Host smart-8ca63302-5032-4eee-b473-f44212bcad03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=832116808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.832116808
Directory /workspace/128.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_rx_full.4196475845
Short name T3529
Test name
Test status
Simulation time 298017457 ps
CPU time 1.1 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:07:48 PM PDT 24
Peak memory 207576 kb
Host smart-8f2bebda-27ba-4b89-a660-f22cea0d825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41964
75845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.4196475845
Directory /workspace/14.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_types.4285762553
Short name T91
Test name
Test status
Simulation time 372924311 ps
CPU time 1.09 seconds
Started Aug 10 07:10:46 PM PDT 24
Finished Aug 10 07:10:47 PM PDT 24
Peak memory 207500 kb
Host smart-ea0ccd90-65f4-46cb-9566-5af360d3153c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4285762553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.4285762553
Directory /workspace/24.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2025778994
Short name T365
Test name
Test status
Simulation time 141079169 ps
CPU time 0.81 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207532 kb
Host smart-b6a08b85-fe62-4ae9-86f2-ec349414c5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
78994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2025778994
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/56.usbdev_endpoint_types.2820000463
Short name T517
Test name
Test status
Simulation time 407066707 ps
CPU time 1.29 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207532 kb
Host smart-47e6554a-5af3-4190-9522-9745ee545088
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2820000463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.2820000463
Directory /workspace/56.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/74.usbdev_endpoint_types.150430434
Short name T120
Test name
Test status
Simulation time 522924075 ps
CPU time 1.47 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207384 kb
Host smart-911a1c23-b674-4721-97cc-3784bccd1d74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=150430434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.150430434
Directory /workspace/74.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4056504398
Short name T633
Test name
Test status
Simulation time 217362097 ps
CPU time 0.88 seconds
Started Aug 10 07:06:34 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 207476 kb
Host smart-971519c5-d11b-4ddf-b70b-09a10c4fa4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40565
04398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4056504398
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/424.usbdev_tx_rx_disruption.1040322235
Short name T227
Test name
Test status
Simulation time 473912142 ps
CPU time 1.49 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207564 kb
Host smart-08af825d-d0bc-49b3-9b53-db4890d70ca7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040322235 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 424.usbdev_tx_rx_disruption.1040322235
Directory /workspace/424.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3606270822
Short name T292
Test name
Test status
Simulation time 310934502 ps
CPU time 3.57 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206940 kb
Host smart-ef91e85c-2fba-4ddc-a4b1-22785299f74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3606270822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3606270822
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1802049295
Short name T93
Test name
Test status
Simulation time 149155291 ps
CPU time 0.86 seconds
Started Aug 10 07:00:38 PM PDT 24
Finished Aug 10 07:00:39 PM PDT 24
Peak memory 207440 kb
Host smart-78bcc97f-6a3e-4bbf-a62f-84f4a25c5358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18020
49295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1802049295
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.1458697509
Short name T48
Test name
Test status
Simulation time 216621021 ps
CPU time 0.96 seconds
Started Aug 10 06:57:30 PM PDT 24
Finished Aug 10 06:57:31 PM PDT 24
Peak memory 207540 kb
Host smart-46099691-aba8-48af-9a88-b8855609270d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14586
97509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1458697509
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.562279384
Short name T69
Test name
Test status
Simulation time 4173072051 ps
CPU time 10.01 seconds
Started Aug 10 06:58:06 PM PDT 24
Finished Aug 10 06:58:16 PM PDT 24
Peak memory 207804 kb
Host smart-af6da649-e398-4a5b-ad8f-a1ec0dc27f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56227
9384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.562279384
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2691834808
Short name T74
Test name
Test status
Simulation time 479102895 ps
CPU time 1.44 seconds
Started Aug 10 06:58:05 PM PDT 24
Finished Aug 10 06:58:07 PM PDT 24
Peak memory 207552 kb
Host smart-ec9491a6-2655-40ea-b154-a927ca5b5434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
34808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2691834808
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1271143125
Short name T70
Test name
Test status
Simulation time 174105173 ps
CPU time 0.82 seconds
Started Aug 10 06:58:15 PM PDT 24
Finished Aug 10 06:58:15 PM PDT 24
Peak memory 207468 kb
Host smart-66275d9c-fa16-4a3c-83ff-5e5c41208e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
43125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1271143125
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.442080878
Short name T3270
Test name
Test status
Simulation time 225873748 ps
CPU time 0.95 seconds
Started Aug 10 06:59:05 PM PDT 24
Finished Aug 10 06:59:06 PM PDT 24
Peak memory 207560 kb
Host smart-7b60b8de-61fd-4067-b9f4-29c26348b8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44208
0878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.442080878
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3605705375
Short name T58
Test name
Test status
Simulation time 156625615 ps
CPU time 0.86 seconds
Started Aug 10 07:01:25 PM PDT 24
Finished Aug 10 07:01:26 PM PDT 24
Peak memory 207568 kb
Host smart-c0da350d-81f3-440e-a760-7fe58cb1f975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057
05375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3605705375
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/36.usbdev_device_address.4049566663
Short name T115
Test name
Test status
Simulation time 30446112076 ps
CPU time 46.06 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207736 kb
Host smart-8a528b08-19ce-4f78-81b3-0f92524c769b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
66663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.4049566663
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1048402035
Short name T593
Test name
Test status
Simulation time 233663519 ps
CPU time 2.3 seconds
Started Aug 10 06:57:56 PM PDT 24
Finished Aug 10 06:57:58 PM PDT 24
Peak memory 207700 kb
Host smart-af8b79e5-d405-4846-992d-eb396cbd8f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
02035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1048402035
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3008375460
Short name T3410
Test name
Test status
Simulation time 200289054 ps
CPU time 0.9 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207556 kb
Host smart-3d84344b-ca8a-421c-b39e-5051d6c52f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30083
75460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3008375460
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1060822650
Short name T2560
Test name
Test status
Simulation time 197437943 ps
CPU time 0.94 seconds
Started Aug 10 06:59:59 PM PDT 24
Finished Aug 10 07:00:00 PM PDT 24
Peak memory 207552 kb
Host smart-b5bfb180-76f6-47ea-ab85-89be551a473f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10608
22650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1060822650
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.111568705
Short name T3127
Test name
Test status
Simulation time 175104175 ps
CPU time 0.9 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207576 kb
Host smart-c5a1b2b1-3d65-4481-b4ea-4ba1a4c9af9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11156
8705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.111568705
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1342537005
Short name T213
Test name
Test status
Simulation time 157865422 ps
CPU time 0.86 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207496 kb
Host smart-c51d2a47-119a-489d-b9ff-dd25a96ce3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13425
37005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1342537005
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.80151449
Short name T138
Test name
Test status
Simulation time 228134034 ps
CPU time 1.15 seconds
Started Aug 10 07:06:56 PM PDT 24
Finished Aug 10 07:06:58 PM PDT 24
Peak memory 207476 kb
Host smart-0b56b963-ee17-43bf-9da7-b5503ca59147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80151
449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.80151449
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2241099884
Short name T141
Test name
Test status
Simulation time 221144558 ps
CPU time 0.96 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:15 PM PDT 24
Peak memory 207488 kb
Host smart-e9303e5b-1743-491c-abd0-00b4eb4b6bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22410
99884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2241099884
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/143.usbdev_tx_rx_disruption.1229778959
Short name T179
Test name
Test status
Simulation time 633257046 ps
CPU time 1.84 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207520 kb
Host smart-0ecfe717-fbcd-46b7-abb8-971216632539
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229778959 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.usbdev_tx_rx_disruption.1229778959
Directory /workspace/143.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_tx_rx_disruption.827131053
Short name T1941
Test name
Test status
Simulation time 504201057 ps
CPU time 1.74 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207504 kb
Host smart-a26f8a5a-955f-4efe-bfa7-06041be9729e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827131053 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 148.usbdev_tx_rx_disruption.827131053
Directory /workspace/148.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_tx_rx_disruption.499868366
Short name T1029
Test name
Test status
Simulation time 538236889 ps
CPU time 1.52 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:38 PM PDT 24
Peak memory 207564 kb
Host smart-28cc2233-094e-493e-9882-cce7dc5bef4e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499868366 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 153.usbdev_tx_rx_disruption.499868366
Directory /workspace/153.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1554222930
Short name T162
Test name
Test status
Simulation time 204373814 ps
CPU time 0.97 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207444 kb
Host smart-723aa10b-3dc4-4e11-8c8d-9b2983460146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
22930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1554222930
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.74301525
Short name T144
Test name
Test status
Simulation time 239885147 ps
CPU time 0.98 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207512 kb
Host smart-f78c8bd3-78e1-46ec-97f1-300f3f5b8e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74301
525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.74301525
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.442902725
Short name T148
Test name
Test status
Simulation time 202793296 ps
CPU time 0.93 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:04 PM PDT 24
Peak memory 207580 kb
Host smart-e193a1af-3dfb-4f8a-9104-f83ed4c57bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44290
2725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.442902725
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3532754150
Short name T133
Test name
Test status
Simulation time 185801619 ps
CPU time 0.86 seconds
Started Aug 10 07:09:24 PM PDT 24
Finished Aug 10 07:09:25 PM PDT 24
Peak memory 207400 kb
Host smart-dc3783fa-614d-4073-b37a-b8279e702458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
54150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3532754150
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/212.usbdev_tx_rx_disruption.796275058
Short name T197
Test name
Test status
Simulation time 543013150 ps
CPU time 1.59 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207596 kb
Host smart-31bb8f85-638c-4222-a517-03d89dd50213
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796275058 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 212.usbdev_tx_rx_disruption.796275058
Directory /workspace/212.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1988363179
Short name T151
Test name
Test status
Simulation time 241234842 ps
CPU time 0.97 seconds
Started Aug 10 07:11:54 PM PDT 24
Finished Aug 10 07:11:55 PM PDT 24
Peak memory 207572 kb
Host smart-e606d956-690e-4629-89aa-3819a3714755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19883
63179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1988363179
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2581646715
Short name T152
Test name
Test status
Simulation time 179947510 ps
CPU time 0.96 seconds
Started Aug 10 07:12:17 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207508 kb
Host smart-ca5465a0-4a9b-41f2-9457-a2137053bd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816
46715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2581646715
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3591971386
Short name T323
Test name
Test status
Simulation time 311224259 ps
CPU time 3.81 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:50 PM PDT 24
Peak memory 206968 kb
Host smart-707b550d-71f7-4190-81a0-46a6f5f6c3d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3591971386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3591971386
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.626533928
Short name T3691
Test name
Test status
Simulation time 830787043 ps
CPU time 4.89 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 207048 kb
Host smart-7609f059-2250-47ef-a868-a886e84ce505
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=626533928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.626533928
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.512834687
Short name T334
Test name
Test status
Simulation time 116164311 ps
CPU time 0.97 seconds
Started Aug 10 05:57:34 PM PDT 24
Finished Aug 10 05:57:35 PM PDT 24
Peak memory 206788 kb
Host smart-50acb0b4-7e40-49de-a3fa-1bc16939d0d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=512834687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.512834687
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1737972431
Short name T3730
Test name
Test status
Simulation time 165294346 ps
CPU time 2.1 seconds
Started Aug 10 05:58:00 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 215284 kb
Host smart-a20223a4-516a-48f5-8a9a-54231e14f8df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737972431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1737972431
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2852262738
Short name T335
Test name
Test status
Simulation time 72235788 ps
CPU time 1.06 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206768 kb
Host smart-22dae122-bf84-4d94-9071-4b93c6332284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2852262738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2852262738
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.981980145
Short name T3679
Test name
Test status
Simulation time 33727088 ps
CPU time 0.7 seconds
Started Aug 10 05:57:35 PM PDT 24
Finished Aug 10 05:57:36 PM PDT 24
Peak memory 206632 kb
Host smart-2b77351d-4653-4790-b34b-64bb725f68fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=981980145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.981980145
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3775502515
Short name T3670
Test name
Test status
Simulation time 201318260 ps
CPU time 2.5 seconds
Started Aug 10 05:57:36 PM PDT 24
Finished Aug 10 05:57:38 PM PDT 24
Peak memory 215128 kb
Host smart-7cabf0d3-020e-4e8f-82c9-15757e6d548f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3775502515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3775502515
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2376420124
Short name T3650
Test name
Test status
Simulation time 272923822 ps
CPU time 2.69 seconds
Started Aug 10 05:57:35 PM PDT 24
Finished Aug 10 05:57:38 PM PDT 24
Peak memory 206860 kb
Host smart-e5559bd1-3ca1-4c5f-9f13-fc3cea75a91c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2376420124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2376420124
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1248968432
Short name T3728
Test name
Test status
Simulation time 140180750 ps
CPU time 1.61 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206832 kb
Host smart-43219ac6-e3d7-4c8a-b425-95e618996b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1248968432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1248968432
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2629457862
Short name T295
Test name
Test status
Simulation time 74269159 ps
CPU time 1.36 seconds
Started Aug 10 05:57:37 PM PDT 24
Finished Aug 10 05:57:38 PM PDT 24
Peak memory 206936 kb
Host smart-4d096a6f-a7ad-41da-b12f-784fd4664d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2629457862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2629457862
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1940755001
Short name T3718
Test name
Test status
Simulation time 144957649 ps
CPU time 3.2 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 206952 kb
Host smart-ab5a6bfb-9d07-44d5-940f-fcd04fed58bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1940755001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1940755001
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.26821902
Short name T330
Test name
Test status
Simulation time 772629911 ps
CPU time 4.7 seconds
Started Aug 10 05:57:41 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 206864 kb
Host smart-243af27e-847b-4955-972c-0115723e3a54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=26821902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.26821902
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1325727992
Short name T3732
Test name
Test status
Simulation time 79772155 ps
CPU time 0.92 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206660 kb
Host smart-d44c7e87-1790-4676-8a36-1b5aade06507
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1325727992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1325727992
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1034452563
Short name T298
Test name
Test status
Simulation time 121028005 ps
CPU time 2.81 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 215212 kb
Host smart-4593d635-58ee-4bd9-b336-0d007086c967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034452563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1034452563
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3419613249
Short name T3655
Test name
Test status
Simulation time 50128062 ps
CPU time 0.82 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 206616 kb
Host smart-2a0cbd5d-2591-4c75-a43d-ce34bc487afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3419613249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3419613249
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2550450322
Short name T370
Test name
Test status
Simulation time 103267452 ps
CPU time 0.78 seconds
Started Aug 10 05:57:44 PM PDT 24
Finished Aug 10 05:57:45 PM PDT 24
Peak memory 206760 kb
Host smart-143a2abf-cacc-488e-b467-9b18b88baf70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2550450322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2550450322
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2545121805
Short name T324
Test name
Test status
Simulation time 98657952 ps
CPU time 1.52 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206784 kb
Host smart-5c5f70dc-2e01-4b64-a032-12ea4cfe5fe1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2545121805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2545121805
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2888502820
Short name T3667
Test name
Test status
Simulation time 370137740 ps
CPU time 2.85 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:50 PM PDT 24
Peak memory 206868 kb
Host smart-c28955ac-fbf6-4505-abc2-5cd1056a3578
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2888502820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2888502820
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3244220364
Short name T344
Test name
Test status
Simulation time 158660010 ps
CPU time 1.24 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206944 kb
Host smart-f2a01182-56e7-4e7e-905f-9419879f5c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3244220364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3244220364
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.171291542
Short name T244
Test name
Test status
Simulation time 102411306 ps
CPU time 1.31 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 206864 kb
Host smart-c0794dcb-a85a-47c7-a4ad-3ecb1bc9d811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=171291542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.171291542
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2975756889
Short name T521
Test name
Test status
Simulation time 709673168 ps
CPU time 4.41 seconds
Started Aug 10 05:57:41 PM PDT 24
Finished Aug 10 05:57:45 PM PDT 24
Peak memory 206964 kb
Host smart-b0c5c8ca-d93d-4784-945e-9ed38697603c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2975756889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2975756889
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2337504434
Short name T303
Test name
Test status
Simulation time 152184689 ps
CPU time 1.89 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 215200 kb
Host smart-19aa83a5-28ba-4cfb-ba32-f1f11f1409fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337504434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2337504434
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2396760908
Short name T3644
Test name
Test status
Simulation time 106039917 ps
CPU time 0.84 seconds
Started Aug 10 05:57:50 PM PDT 24
Finished Aug 10 05:57:51 PM PDT 24
Peak memory 206716 kb
Host smart-4d190015-2862-44fb-be5c-4aca9d1f2c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2396760908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2396760908
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.814005998
Short name T3676
Test name
Test status
Simulation time 52124213 ps
CPU time 0.74 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206636 kb
Host smart-638fdec3-4294-438e-8ff9-a54337bd15ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=814005998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.814005998
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3028470191
Short name T3700
Test name
Test status
Simulation time 206097137 ps
CPU time 1.26 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:53 PM PDT 24
Peak memory 206912 kb
Host smart-22113c07-1f1f-48b3-8416-cb3cf1db1f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3028470191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3028470191
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2414813610
Short name T306
Test name
Test status
Simulation time 113643317 ps
CPU time 1.33 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 215116 kb
Host smart-450d8c37-7c2a-4780-ae9f-b388ebb60dfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414813610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2414813610
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.504533226
Short name T321
Test name
Test status
Simulation time 112436310 ps
CPU time 1.02 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206604 kb
Host smart-45165357-0c99-4a68-bd15-9d09fe0ff1ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=504533226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.504533226
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.488916752
Short name T337
Test name
Test status
Simulation time 215833830 ps
CPU time 1.7 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 207008 kb
Host smart-c27a0f9c-3996-4a81-8d67-4947f9d79c32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=488916752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.488916752
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2465888602
Short name T297
Test name
Test status
Simulation time 176088104 ps
CPU time 2.2 seconds
Started Aug 10 05:57:58 PM PDT 24
Finished Aug 10 05:58:00 PM PDT 24
Peak memory 222508 kb
Host smart-2d1baee9-45dc-4eea-af0c-ba7fb1153696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2465888602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2465888602
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1046843225
Short name T299
Test name
Test status
Simulation time 184709783 ps
CPU time 1.99 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 215148 kb
Host smart-169c97a6-7ddc-4ca0-993a-27b7320ac6cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046843225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1046843225
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3210579145
Short name T3660
Test name
Test status
Simulation time 48127878 ps
CPU time 0.83 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206752 kb
Host smart-9bd24c03-83bc-40cb-b9e4-83fddba02f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3210579145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3210579145
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.339261693
Short name T3706
Test name
Test status
Simulation time 90860227 ps
CPU time 0.83 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206592 kb
Host smart-03d1b982-cf36-451c-b9c5-9f6d81ba9734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=339261693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.339261693
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.627847651
Short name T3643
Test name
Test status
Simulation time 86128695 ps
CPU time 1.1 seconds
Started Aug 10 05:57:49 PM PDT 24
Finished Aug 10 05:57:50 PM PDT 24
Peak memory 206940 kb
Host smart-f5f765f0-5a8f-46c5-ab14-518d25a0e59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=627847651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.627847651
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4257477506
Short name T300
Test name
Test status
Simulation time 210040372 ps
CPU time 2.89 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 220552 kb
Host smart-716dedbf-fe8e-430d-aebe-b50fd7b25bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4257477506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4257477506
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1066597425
Short name T520
Test name
Test status
Simulation time 654977649 ps
CPU time 2.86 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206940 kb
Host smart-69b5e436-aa60-4188-9c8e-21bcdb23531a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1066597425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1066597425
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1205186155
Short name T3666
Test name
Test status
Simulation time 86687031 ps
CPU time 1.28 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 215268 kb
Host smart-6de7f8e2-21f4-408b-8fd0-40f834414106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205186155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1205186155
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.245672088
Short name T3710
Test name
Test status
Simulation time 72844242 ps
CPU time 1.06 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206768 kb
Host smart-9e0e121f-0990-4000-9146-7636da1dc6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=245672088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.245672088
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.103933247
Short name T3652
Test name
Test status
Simulation time 168294999 ps
CPU time 1.21 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206916 kb
Host smart-e4e6e6b2-1836-425f-91be-fb3ad7a1cb52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=103933247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.103933247
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.508973188
Short name T286
Test name
Test status
Simulation time 182952619 ps
CPU time 2.48 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 207024 kb
Host smart-6aa8b771-95ef-4307-a9c4-e35cfaa37dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508973188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.508973188
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3747778364
Short name T3689
Test name
Test status
Simulation time 875637731 ps
CPU time 5.23 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 206952 kb
Host smart-aa200646-69c7-4ee7-ad9a-23ec6b2a2942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3747778364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3747778364
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1905847872
Short name T294
Test name
Test status
Simulation time 72525886 ps
CPU time 1.79 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 215132 kb
Host smart-1e65a4ab-3d77-482f-9696-248bb5b2e466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905847872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1905847872
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1795421950
Short name T3677
Test name
Test status
Simulation time 78113154 ps
CPU time 1 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 206824 kb
Host smart-58995ff3-822b-4c84-8c88-ad23ece03daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1795421950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1795421950
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.43058440
Short name T3675
Test name
Test status
Simulation time 39856790 ps
CPU time 0.77 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206592 kb
Host smart-d5201baa-7421-47bb-a2d8-d6cbe408b3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=43058440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.43058440
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2209711066
Short name T3734
Test name
Test status
Simulation time 195983795 ps
CPU time 1.59 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206932 kb
Host smart-e9b492b0-1ff5-470b-af66-b87fbbb33d0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2209711066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2209711066
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3861322017
Short name T3662
Test name
Test status
Simulation time 133378385 ps
CPU time 1.6 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 206896 kb
Host smart-7028f673-6ccb-4bde-8efa-fe4ff4227fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861322017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3861322017
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.912500097
Short name T285
Test name
Test status
Simulation time 349138192 ps
CPU time 2.61 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206952 kb
Host smart-babc6b44-447a-4975-b9e5-2dd084c401d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=912500097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.912500097
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2350187859
Short name T3661
Test name
Test status
Simulation time 135521994 ps
CPU time 1.8 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 215196 kb
Host smart-dce3c161-3344-460a-a004-ec4969dce3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350187859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2350187859
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3425649561
Short name T3658
Test name
Test status
Simulation time 77692505 ps
CPU time 0.97 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 206748 kb
Host smart-d9c33e6c-4851-423e-941a-2b653d56346b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3425649561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3425649561
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.404382248
Short name T3637
Test name
Test status
Simulation time 69385076 ps
CPU time 0.78 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206572 kb
Host smart-9d50a99a-954c-4ad5-b721-f8c3802929f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404382248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.404382248
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3411391182
Short name T3709
Test name
Test status
Simulation time 173918114 ps
CPU time 1.58 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 206916 kb
Host smart-986b196d-dc6f-4e65-bb54-429458d94a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3411391182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3411391182
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1406134484
Short name T296
Test name
Test status
Simulation time 96086088 ps
CPU time 2.53 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 220248 kb
Host smart-ff7512b4-8a3a-4440-a98b-57e28f887b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1406134484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1406134484
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.371521166
Short name T3668
Test name
Test status
Simulation time 406568116 ps
CPU time 2.48 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 206920 kb
Host smart-f74cfca7-42eb-4957-95d8-ca5fc2fb4e00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=371521166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.371521166
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3065864975
Short name T242
Test name
Test status
Simulation time 76272183 ps
CPU time 1.29 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 215012 kb
Host smart-5de84c42-e76f-4c1b-a324-daf7a27bee10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065864975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3065864975
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.816513135
Short name T3694
Test name
Test status
Simulation time 46668106 ps
CPU time 0.77 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206564 kb
Host smart-5e67a85a-1b5c-4bea-a610-8551dba3befd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=816513135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.816513135
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1648070764
Short name T336
Test name
Test status
Simulation time 122146022 ps
CPU time 1.17 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206800 kb
Host smart-0a8db02a-4118-42d7-a3b5-2bdbcd7aa3cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1648070764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1648070764
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3137995905
Short name T3682
Test name
Test status
Simulation time 130460755 ps
CPU time 2.21 seconds
Started Aug 10 05:57:58 PM PDT 24
Finished Aug 10 05:58:00 PM PDT 24
Peak memory 215264 kb
Host smart-f80952ed-9819-455e-9cb2-095e3fb68ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137995905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3137995905
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4069600973
Short name T3731
Test name
Test status
Simulation time 80495142 ps
CPU time 0.86 seconds
Started Aug 10 05:57:58 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 206684 kb
Host smart-0e352e0a-0713-491e-8cb9-55be176c77ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4069600973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4069600973
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3069490575
Short name T3654
Test name
Test status
Simulation time 42393643 ps
CPU time 0.74 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206472 kb
Host smart-a91514ee-dfb5-41f8-b964-1ff87bdfbcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069490575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3069490575
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1489725500
Short name T338
Test name
Test status
Simulation time 99579277 ps
CPU time 1.19 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 207000 kb
Host smart-64ff3c33-e1d7-4d3c-af97-3be761e2b549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1489725500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1489725500
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764909030
Short name T3727
Test name
Test status
Simulation time 196527293 ps
CPU time 2.21 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206908 kb
Host smart-89571f00-12c0-4502-86f0-ddcaa970ab2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764909030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2764909030
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.996774175
Short name T3735
Test name
Test status
Simulation time 281415884 ps
CPU time 2.4 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206980 kb
Host smart-178cb625-e647-4edf-abab-f7614734d450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=996774175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.996774175
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.172878655
Short name T3692
Test name
Test status
Simulation time 67154691 ps
CPU time 1.24 seconds
Started Aug 10 05:57:58 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 215100 kb
Host smart-41aee287-80ab-4d6c-b8e7-30452536fe34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172878655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.172878655
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4158161470
Short name T281
Test name
Test status
Simulation time 74080394 ps
CPU time 0.84 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 206672 kb
Host smart-89fe616e-d14e-4187-abb3-dd81d5e8ec78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4158161470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4158161470
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.573064587
Short name T3698
Test name
Test status
Simulation time 50851461 ps
CPU time 0.77 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:53 PM PDT 24
Peak memory 206624 kb
Host smart-c3ba5d25-b5c4-40ea-b5a5-a0bf7684e49e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=573064587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.573064587
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3379752862
Short name T3678
Test name
Test status
Simulation time 161190261 ps
CPU time 1.54 seconds
Started Aug 10 05:57:59 PM PDT 24
Finished Aug 10 05:58:01 PM PDT 24
Peak memory 206916 kb
Host smart-c5e823dd-1920-465a-916b-976a9ed5c5cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379752862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3379752862
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.687421827
Short name T3715
Test name
Test status
Simulation time 258243113 ps
CPU time 2.35 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206892 kb
Host smart-0966454a-8f43-401d-b830-d84207c6dd25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=687421827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.687421827
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.915935794
Short name T3635
Test name
Test status
Simulation time 85464614 ps
CPU time 1.26 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 216872 kb
Host smart-94e51ed8-b47a-432a-b1df-eb8048a36fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915935794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.915935794
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.454036578
Short name T328
Test name
Test status
Simulation time 78342489 ps
CPU time 1 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 206632 kb
Host smart-3cdb7b73-49bd-4dec-a302-c5afd4e00e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=454036578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.454036578
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3283806289
Short name T3642
Test name
Test status
Simulation time 40826664 ps
CPU time 0.73 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206564 kb
Host smart-d0c03e90-3383-45b1-83ab-af9feae94f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3283806289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3283806289
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.495404318
Short name T3640
Test name
Test status
Simulation time 129091412 ps
CPU time 1.56 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206952 kb
Host smart-1e3902b4-93b1-4019-9448-871f9e8a2be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=495404318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.495404318
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2196188678
Short name T3712
Test name
Test status
Simulation time 144995769 ps
CPU time 3.02 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206872 kb
Host smart-213a61a3-2f24-471d-b3da-5580caa101cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2196188678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2196188678
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1132128399
Short name T526
Test name
Test status
Simulation time 2082086642 ps
CPU time 5.45 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 206952 kb
Host smart-18ec033e-2a21-4606-9747-2c528fba05fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1132128399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1132128399
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2284235874
Short name T332
Test name
Test status
Simulation time 392310265 ps
CPU time 3.79 seconds
Started Aug 10 05:57:44 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206900 kb
Host smart-da8f1a42-f144-448c-ae6f-7e4a235c9548
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2284235874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2284235874
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3420091450
Short name T3704
Test name
Test status
Simulation time 1754975353 ps
CPU time 8.3 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 206836 kb
Host smart-99e4551a-f320-430a-b5ad-2f7ee49baac0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3420091450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3420091450
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3456931142
Short name T3726
Test name
Test status
Simulation time 91511403 ps
CPU time 0.94 seconds
Started Aug 10 05:57:44 PM PDT 24
Finished Aug 10 05:57:45 PM PDT 24
Peak memory 206788 kb
Host smart-45c2a650-6b4a-46f0-8063-4c3c382531a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3456931142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3456931142
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3986916759
Short name T3711
Test name
Test status
Simulation time 79043838 ps
CPU time 1.62 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 215060 kb
Host smart-47751737-5f70-470d-9179-af7f1950d223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986916759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3986916759
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2541397900
Short name T3687
Test name
Test status
Simulation time 66812997 ps
CPU time 0.85 seconds
Started Aug 10 05:57:41 PM PDT 24
Finished Aug 10 05:57:42 PM PDT 24
Peak memory 206628 kb
Host smart-998e228c-f49a-4f68-8347-2d765ea7c441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2541397900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2541397900
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1344945960
Short name T3631
Test name
Test status
Simulation time 103699953 ps
CPU time 1.57 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206828 kb
Host smart-47a6081e-2551-452e-8a13-d1bbf6dd84ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1344945960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1344945960
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4207013432
Short name T3684
Test name
Test status
Simulation time 318782588 ps
CPU time 2.57 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 206820 kb
Host smart-f27862bd-d9a0-4b8b-8c7a-8d7bdf4689bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4207013432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4207013432
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3996311413
Short name T3663
Test name
Test status
Simulation time 196309697 ps
CPU time 1.86 seconds
Started Aug 10 05:57:50 PM PDT 24
Finished Aug 10 05:57:52 PM PDT 24
Peak memory 206980 kb
Host smart-f19ff463-32a7-448e-854a-00e59aec8347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3996311413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3996311413
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2438966767
Short name T3673
Test name
Test status
Simulation time 144625311 ps
CPU time 1.71 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:53 PM PDT 24
Peak memory 206864 kb
Host smart-cf2e7d26-77b9-4a06-9532-3fa7ba351d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2438966767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2438966767
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1733622368
Short name T3737
Test name
Test status
Simulation time 434972905 ps
CPU time 2.68 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 206964 kb
Host smart-22766367-b6db-4071-93ef-d512f7b72a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1733622368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1733622368
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2188342157
Short name T3725
Test name
Test status
Simulation time 43843744 ps
CPU time 0.74 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:53 PM PDT 24
Peak memory 206516 kb
Host smart-fbc1485b-5f41-4939-88b2-1437e302c250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2188342157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2188342157
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2875532398
Short name T3708
Test name
Test status
Simulation time 38904620 ps
CPU time 0.73 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206492 kb
Host smart-7b7827ec-7940-42da-8442-aa341d942df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2875532398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2875532398
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4219948044
Short name T372
Test name
Test status
Simulation time 48839102 ps
CPU time 0.73 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 206648 kb
Host smart-a359209f-a45b-4d58-9a2e-08869a79eafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4219948044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4219948044
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2877304919
Short name T3641
Test name
Test status
Simulation time 39638363 ps
CPU time 0.71 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206596 kb
Host smart-f5ca152f-fb39-4e2d-8979-e0d01b7619d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2877304919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2877304919
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.204339858
Short name T347
Test name
Test status
Simulation time 38738844 ps
CPU time 0.71 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206592 kb
Host smart-8c74cd53-a0fe-49e0-a9cf-05d5e2213456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=204339858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.204339858
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2292101519
Short name T3632
Test name
Test status
Simulation time 55052050 ps
CPU time 0.74 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206616 kb
Host smart-2824714d-5266-4908-8589-357428e1ad62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2292101519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2292101519
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2861191251
Short name T3701
Test name
Test status
Simulation time 72252696 ps
CPU time 0.79 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206592 kb
Host smart-74b7cced-1403-417c-832a-9bed12de47c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2861191251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2861191251
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1420617205
Short name T3674
Test name
Test status
Simulation time 114410212 ps
CPU time 0.82 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 206636 kb
Host smart-834aae2d-6d7e-4faf-8057-fdc2d9ee032c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420617205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1420617205
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2053940940
Short name T3722
Test name
Test status
Simulation time 90081203 ps
CPU time 0.79 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:57 PM PDT 24
Peak memory 206592 kb
Host smart-37a265ab-f749-419d-aa69-6d28405ab36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2053940940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2053940940
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3706996138
Short name T3647
Test name
Test status
Simulation time 50769717 ps
CPU time 0.79 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206472 kb
Host smart-26869ca2-dc59-4721-96f6-818e354511b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3706996138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3706996138
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.39430534
Short name T3672
Test name
Test status
Simulation time 182294607 ps
CPU time 2.2 seconds
Started Aug 10 05:57:40 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206780 kb
Host smart-fb31928b-e2f7-403b-9e5b-c5ff6f177d6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=39430534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.39430534
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2972735429
Short name T342
Test name
Test status
Simulation time 915484969 ps
CPU time 4.97 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206956 kb
Host smart-f8e3a209-9bac-4934-b390-1e7ec18b1fb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2972735429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2972735429
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2181524673
Short name T326
Test name
Test status
Simulation time 122690629 ps
CPU time 0.96 seconds
Started Aug 10 05:58:00 PM PDT 24
Finished Aug 10 05:58:01 PM PDT 24
Peak memory 206688 kb
Host smart-d5baa46d-0803-40d7-8aa7-3197274f14aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2181524673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2181524673
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1498833801
Short name T3713
Test name
Test status
Simulation time 82741419 ps
CPU time 1.43 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 215192 kb
Host smart-7734d8b0-a2ce-49ac-a18f-3d55ec158d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498833801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.1498833801
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1591648457
Short name T3697
Test name
Test status
Simulation time 60267188 ps
CPU time 0.79 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:51 PM PDT 24
Peak memory 206700 kb
Host smart-03923837-aae9-4292-830e-9fc3f111daf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1591648457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1591648457
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2717710979
Short name T3695
Test name
Test status
Simulation time 56496804 ps
CPU time 0.73 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206616 kb
Host smart-32b08a90-5f65-40f3-ac9b-8ebee90e9642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2717710979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2717710979
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2541160767
Short name T329
Test name
Test status
Simulation time 170203890 ps
CPU time 2.41 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 206916 kb
Host smart-9c5eacb6-4375-4dc8-8f43-ddf1e44f0b34
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2541160767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2541160767
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3660946742
Short name T3680
Test name
Test status
Simulation time 490015323 ps
CPU time 4.41 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206716 kb
Host smart-bdc74022-44db-4ec5-86cb-538591d9ed48
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3660946742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3660946742
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.770838831
Short name T3729
Test name
Test status
Simulation time 46126564 ps
CPU time 1.09 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206940 kb
Host smart-420150a9-0a4c-4984-b42e-1905b38ff8a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=770838831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.770838831
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2331207658
Short name T3702
Test name
Test status
Simulation time 274393528 ps
CPU time 2.87 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 219900 kb
Host smart-a23d12bb-5054-4989-8562-aad320468d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2331207658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2331207658
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2420269961
Short name T522
Test name
Test status
Simulation time 640045773 ps
CPU time 2.99 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206960 kb
Host smart-9ce83c98-4029-4aa2-bac0-60d551bb1fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2420269961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2420269961
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.751763564
Short name T3719
Test name
Test status
Simulation time 68328706 ps
CPU time 0.83 seconds
Started Aug 10 05:58:04 PM PDT 24
Finished Aug 10 05:58:05 PM PDT 24
Peak memory 206492 kb
Host smart-9bf88fad-ad2b-48ec-b0f5-5ac6becf7124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=751763564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.751763564
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.569236972
Short name T3639
Test name
Test status
Simulation time 43802895 ps
CPU time 0.71 seconds
Started Aug 10 05:57:55 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206584 kb
Host smart-9cf9035e-f14d-41a0-90f1-95b355a5c4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=569236972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.569236972
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2965382504
Short name T3721
Test name
Test status
Simulation time 41123125 ps
CPU time 0.75 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206620 kb
Host smart-5e29e76d-ce7c-4b07-8d3b-a2f674dc746f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2965382504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2965382504
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2519216029
Short name T3656
Test name
Test status
Simulation time 48870374 ps
CPU time 0.73 seconds
Started Aug 10 05:58:01 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 206596 kb
Host smart-b9f1137f-1ec6-4b55-80a1-551350be851e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519216029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2519216029
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.549636933
Short name T3696
Test name
Test status
Simulation time 36205986 ps
CPU time 0.72 seconds
Started Aug 10 05:58:17 PM PDT 24
Finished Aug 10 05:58:18 PM PDT 24
Peak memory 206568 kb
Host smart-803bc3c0-1718-4ad0-9aaa-4241922ece92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=549636933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.549636933
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4243230629
Short name T3649
Test name
Test status
Simulation time 57278982 ps
CPU time 0.71 seconds
Started Aug 10 05:58:09 PM PDT 24
Finished Aug 10 05:58:10 PM PDT 24
Peak memory 206648 kb
Host smart-5a109abc-f61c-4b49-a5c9-e2dcfc0918e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4243230629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4243230629
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4226515787
Short name T3636
Test name
Test status
Simulation time 59409699 ps
CPU time 0.78 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206628 kb
Host smart-3c9971c7-a7e9-465f-8738-fc6190373b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4226515787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4226515787
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2807745922
Short name T248
Test name
Test status
Simulation time 66970431 ps
CPU time 0.76 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206572 kb
Host smart-86d17310-50fd-49af-a151-4b4808b93e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807745922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2807745922
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1210932557
Short name T3653
Test name
Test status
Simulation time 55004317 ps
CPU time 0.76 seconds
Started Aug 10 05:58:08 PM PDT 24
Finished Aug 10 05:58:09 PM PDT 24
Peak memory 206568 kb
Host smart-1e19e4ef-7e49-4950-a0f9-bf42e1fb46de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210932557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1210932557
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1813237160
Short name T3705
Test name
Test status
Simulation time 44642706 ps
CPU time 0.73 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 206616 kb
Host smart-e84b62c8-33ee-438e-936f-6e66278f187f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1813237160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1813237160
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3231666433
Short name T3634
Test name
Test status
Simulation time 87765512 ps
CPU time 2.04 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:45 PM PDT 24
Peak memory 206872 kb
Host smart-5f6e347e-4a7a-4cf6-b1f5-af4eb2a08674
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3231666433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3231666433
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1227171695
Short name T327
Test name
Test status
Simulation time 306793581 ps
CPU time 4.48 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 207008 kb
Host smart-fa72d75d-7a85-4087-be39-e9df65437399
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1227171695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1227171695
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4294771217
Short name T331
Test name
Test status
Simulation time 231787287 ps
CPU time 1.02 seconds
Started Aug 10 05:57:41 PM PDT 24
Finished Aug 10 05:57:42 PM PDT 24
Peak memory 206680 kb
Host smart-2ce411c2-40cb-45d8-9db8-65d6328375ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4294771217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.4294771217
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.764795527
Short name T3703
Test name
Test status
Simulation time 90635358 ps
CPU time 1.72 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 215124 kb
Host smart-91c6bbe4-4674-4413-b072-94e139bffd26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764795527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.764795527
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.506920687
Short name T3638
Test name
Test status
Simulation time 83550737 ps
CPU time 0.91 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206776 kb
Host smart-21d9ea5e-f7c6-4069-a871-b18a400df330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=506920687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.506920687
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1995752504
Short name T3669
Test name
Test status
Simulation time 42566039 ps
CPU time 0.74 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206624 kb
Host smart-75bb9b13-1aa7-4098-823b-e8d095cc5c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1995752504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1995752504
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1431830253
Short name T3716
Test name
Test status
Simulation time 139034800 ps
CPU time 1.53 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206800 kb
Host smart-609d557b-b380-421a-bc38-788a28035d50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1431830253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1431830253
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.733590636
Short name T3738
Test name
Test status
Simulation time 635489573 ps
CPU time 4.61 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:51 PM PDT 24
Peak memory 206880 kb
Host smart-128cae89-0868-4f9c-bb40-5694c552d1b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=733590636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.733590636
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3000522042
Short name T3733
Test name
Test status
Simulation time 285259696 ps
CPU time 1.8 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206944 kb
Host smart-087af0d3-3f7a-4252-9958-a21f01ac2160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3000522042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3000522042
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1847276893
Short name T3714
Test name
Test status
Simulation time 165437403 ps
CPU time 1.97 seconds
Started Aug 10 05:57:40 PM PDT 24
Finished Aug 10 05:57:42 PM PDT 24
Peak memory 206964 kb
Host smart-76a11b81-d40c-472a-b037-1952a1105fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1847276893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1847276893
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.381988898
Short name T3664
Test name
Test status
Simulation time 267791811 ps
CPU time 2.51 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206960 kb
Host smart-8b7aa302-5d1c-40e0-a0c6-b1a5cbe3df1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=381988898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.381988898
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1449874816
Short name T374
Test name
Test status
Simulation time 38585557 ps
CPU time 0.73 seconds
Started Aug 10 05:58:19 PM PDT 24
Finished Aug 10 05:58:19 PM PDT 24
Peak memory 206528 kb
Host smart-77ddb573-927a-49bd-9823-c5ea5cac02d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1449874816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1449874816
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2930979224
Short name T3688
Test name
Test status
Simulation time 106688486 ps
CPU time 0.85 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206580 kb
Host smart-b78da364-e2bd-4140-b1ce-011a0e26c964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930979224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2930979224
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4148758031
Short name T3648
Test name
Test status
Simulation time 33531723 ps
CPU time 0.73 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:08 PM PDT 24
Peak memory 206636 kb
Host smart-da863602-989c-410d-9557-1a28ac9321d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4148758031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4148758031
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2788334382
Short name T251
Test name
Test status
Simulation time 39688042 ps
CPU time 0.73 seconds
Started Aug 10 05:58:03 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206612 kb
Host smart-c91aa1bc-ae6c-4ee9-adba-3660f0cd4e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2788334382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2788334382
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3022497758
Short name T3646
Test name
Test status
Simulation time 71452750 ps
CPU time 0.73 seconds
Started Aug 10 05:58:06 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 206484 kb
Host smart-a16fa7cf-c22c-4aa6-8fbb-341be1c684ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3022497758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3022497758
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2501312113
Short name T346
Test name
Test status
Simulation time 46609189 ps
CPU time 0.75 seconds
Started Aug 10 05:58:07 PM PDT 24
Finished Aug 10 05:58:07 PM PDT 24
Peak memory 206484 kb
Host smart-c9354f77-f1bc-4686-9f5b-759812632cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2501312113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2501312113
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2495104750
Short name T3657
Test name
Test status
Simulation time 63835516 ps
CPU time 0.78 seconds
Started Aug 10 05:58:02 PM PDT 24
Finished Aug 10 05:58:03 PM PDT 24
Peak memory 206612 kb
Host smart-764cb121-ed10-4c33-9d89-abbb712e9876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2495104750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2495104750
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3492173716
Short name T3665
Test name
Test status
Simulation time 44340813 ps
CPU time 0.74 seconds
Started Aug 10 05:58:05 PM PDT 24
Finished Aug 10 05:58:06 PM PDT 24
Peak memory 206596 kb
Host smart-7b2caf06-bcd0-4c1e-bdf9-946717694a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3492173716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3492173716
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.143340343
Short name T3633
Test name
Test status
Simulation time 54178227 ps
CPU time 0.77 seconds
Started Aug 10 05:58:12 PM PDT 24
Finished Aug 10 05:58:13 PM PDT 24
Peak memory 206568 kb
Host smart-ef58f194-30f6-42e5-abdc-f48542df2f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=143340343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.143340343
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4209216011
Short name T304
Test name
Test status
Simulation time 106752713 ps
CPU time 1.19 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 217124 kb
Host smart-480d7c3d-c1c8-4b36-b6fc-ae1d893a7638
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209216011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4209216011
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3163554188
Short name T301
Test name
Test status
Simulation time 46613709 ps
CPU time 0.82 seconds
Started Aug 10 05:57:43 PM PDT 24
Finished Aug 10 05:57:43 PM PDT 24
Peak memory 206772 kb
Host smart-99906d3b-35f4-45cd-9c7b-c9aa1b341c68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3163554188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3163554188
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2129370691
Short name T3683
Test name
Test status
Simulation time 32846132 ps
CPU time 0.71 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:52 PM PDT 24
Peak memory 206560 kb
Host smart-4b62977c-4df6-497c-8b37-e2a683aa7d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2129370691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2129370691
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.350876272
Short name T3724
Test name
Test status
Simulation time 303251979 ps
CPU time 1.81 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206872 kb
Host smart-3a540481-2dd1-4f69-b036-fc378a29f219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=350876272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.350876272
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2363183622
Short name T3707
Test name
Test status
Simulation time 109827035 ps
CPU time 2.97 seconds
Started Aug 10 05:57:42 PM PDT 24
Finished Aug 10 05:57:45 PM PDT 24
Peak memory 223064 kb
Host smart-6ba7d871-f6d6-4d1a-a272-fab7cdadb459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2363183622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2363183622
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3881545935
Short name T305
Test name
Test status
Simulation time 997140679 ps
CPU time 3.06 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 206852 kb
Host smart-dc271c23-3477-4eda-920d-020b0dd6e22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3881545935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3881545935
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4110370857
Short name T3686
Test name
Test status
Simulation time 172229213 ps
CPU time 1.76 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 223340 kb
Host smart-0039b6f6-ba64-46df-a4ad-e4d464ae57c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110370857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.4110370857
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1468040176
Short name T325
Test name
Test status
Simulation time 79695934 ps
CPU time 1 seconds
Started Aug 10 05:57:41 PM PDT 24
Finished Aug 10 05:57:42 PM PDT 24
Peak memory 206760 kb
Host smart-acd71dab-548e-41f1-a641-bad52aab305f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1468040176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1468040176
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1177051613
Short name T3717
Test name
Test status
Simulation time 49232401 ps
CPU time 0.74 seconds
Started Aug 10 05:57:51 PM PDT 24
Finished Aug 10 05:57:52 PM PDT 24
Peak memory 206572 kb
Host smart-d1c1eadb-d35b-43f5-be5a-9755c4b592e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1177051613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1177051613
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1296080289
Short name T3699
Test name
Test status
Simulation time 207477094 ps
CPU time 1.28 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206944 kb
Host smart-2409e6ab-bb36-470d-9f57-88b1dd64b6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1296080289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1296080289
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2745625990
Short name T3693
Test name
Test status
Simulation time 62101657 ps
CPU time 1.39 seconds
Started Aug 10 05:57:44 PM PDT 24
Finished Aug 10 05:57:46 PM PDT 24
Peak memory 207144 kb
Host smart-d40e9fea-1bdb-412a-9a7c-44aa6cb4075c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745625990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2745625990
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3274219213
Short name T3720
Test name
Test status
Simulation time 1043696523 ps
CPU time 3.56 seconds
Started Aug 10 05:58:00 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206924 kb
Host smart-63b9cd0e-1dfb-4293-be94-0b5b54c4843d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3274219213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3274219213
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2249958788
Short name T277
Test name
Test status
Simulation time 89103519 ps
CPU time 1.31 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 215172 kb
Host smart-1ea8ab7b-e618-40cc-a3c1-36b80e64b26f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249958788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2249958788
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1840994887
Short name T333
Test name
Test status
Simulation time 50104208 ps
CPU time 0.93 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:55 PM PDT 24
Peak memory 206724 kb
Host smart-83422d27-8175-4537-91f7-998494ea16db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1840994887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1840994887
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2431265269
Short name T3671
Test name
Test status
Simulation time 46240181 ps
CPU time 0.72 seconds
Started Aug 10 05:57:52 PM PDT 24
Finished Aug 10 05:57:53 PM PDT 24
Peak memory 206640 kb
Host smart-20328d2e-96a0-481d-8ac1-ce3260b6cc3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2431265269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2431265269
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.741077300
Short name T3736
Test name
Test status
Simulation time 144535967 ps
CPU time 1.34 seconds
Started Aug 10 05:57:54 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206856 kb
Host smart-795c7e1a-5472-48c7-905f-a7791484934b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=741077300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.741077300
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2539105341
Short name T243
Test name
Test status
Simulation time 148217582 ps
CPU time 1.98 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 223252 kb
Host smart-e7c6c304-4d3e-4aa1-b4b1-a44b0bb0febc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2539105341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2539105341
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3839744278
Short name T523
Test name
Test status
Simulation time 1508171872 ps
CPU time 5.97 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:59 PM PDT 24
Peak memory 206892 kb
Host smart-764f35ad-9115-4fd2-884d-2d90b5cd864c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3839744278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3839744278
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.426324564
Short name T3685
Test name
Test status
Simulation time 114247041 ps
CPU time 1.29 seconds
Started Aug 10 05:57:48 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 215176 kb
Host smart-69673c52-af7e-4dcc-8357-4f8960e8469c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426324564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.426324564
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2699040600
Short name T3681
Test name
Test status
Simulation time 46110399 ps
CPU time 0.86 seconds
Started Aug 10 05:57:59 PM PDT 24
Finished Aug 10 05:58:04 PM PDT 24
Peak memory 206716 kb
Host smart-9c01f88f-9c2d-4f4a-8c4b-3908573fa36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2699040600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2699040600
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.410189133
Short name T3659
Test name
Test status
Simulation time 53879566 ps
CPU time 0.71 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 206620 kb
Host smart-1812a80a-7036-4801-90c9-ddf8ab00f293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410189133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.410189133
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1857348725
Short name T345
Test name
Test status
Simulation time 105735472 ps
CPU time 1.13 seconds
Started Aug 10 05:57:48 PM PDT 24
Finished Aug 10 05:57:49 PM PDT 24
Peak memory 206944 kb
Host smart-b7515651-7004-4f35-89e3-a990f83d71af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1857348725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1857348725
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3455736315
Short name T3723
Test name
Test status
Simulation time 117798269 ps
CPU time 1.75 seconds
Started Aug 10 05:57:56 PM PDT 24
Finished Aug 10 05:57:58 PM PDT 24
Peak memory 206980 kb
Host smart-8bfa02f9-7457-4a25-878d-dde351ec619a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3455736315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3455736315
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1991038147
Short name T524
Test name
Test status
Simulation time 699149327 ps
CPU time 2.64 seconds
Started Aug 10 05:57:53 PM PDT 24
Finished Aug 10 05:57:56 PM PDT 24
Peak memory 206968 kb
Host smart-336676a6-734f-4301-8ecd-1bd0275925e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1991038147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1991038147
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.952537735
Short name T291
Test name
Test status
Simulation time 82246315 ps
CPU time 2.26 seconds
Started Aug 10 05:58:00 PM PDT 24
Finished Aug 10 05:58:02 PM PDT 24
Peak memory 215220 kb
Host smart-45bf66b0-316c-4b94-a813-0740549bf1a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952537735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.952537735
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.896206321
Short name T280
Test name
Test status
Simulation time 106002636 ps
CPU time 1.01 seconds
Started Aug 10 05:57:47 PM PDT 24
Finished Aug 10 05:57:48 PM PDT 24
Peak memory 206724 kb
Host smart-5e270903-dad3-45ad-be22-9d636ca00dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=896206321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.896206321
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2656687326
Short name T3645
Test name
Test status
Simulation time 67097284 ps
CPU time 0.71 seconds
Started Aug 10 05:57:46 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206616 kb
Host smart-69e8c0f2-e348-4ac3-86e6-a86ba7e946ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2656687326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2656687326
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1539257109
Short name T3651
Test name
Test status
Simulation time 97018884 ps
CPU time 1.45 seconds
Started Aug 10 05:57:45 PM PDT 24
Finished Aug 10 05:57:47 PM PDT 24
Peak memory 206900 kb
Host smart-60ce3e73-577c-4226-b6b0-a18659e1c234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1539257109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1539257109
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2310698188
Short name T3690
Test name
Test status
Simulation time 138043908 ps
CPU time 3.42 seconds
Started Aug 10 05:57:57 PM PDT 24
Finished Aug 10 05:58:01 PM PDT 24
Peak memory 206996 kb
Host smart-e7130258-1ec2-47e1-ab4f-6639ad8daf32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2310698188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2310698188
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2748235563
Short name T525
Test name
Test status
Simulation time 1270032312 ps
CPU time 5.52 seconds
Started Aug 10 05:57:49 PM PDT 24
Finished Aug 10 05:57:54 PM PDT 24
Peak memory 207004 kb
Host smart-27256093-2d91-400c-8e48-2f1e7035610a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2748235563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2748235563
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.554748579
Short name T2095
Test name
Test status
Simulation time 68562429 ps
CPU time 0.66 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 207528 kb
Host smart-e1371a40-4eaa-44be-9189-2afd1ca8dda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=554748579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.554748579
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3563406990
Short name T2715
Test name
Test status
Simulation time 10755050559 ps
CPU time 15.07 seconds
Started Aug 10 06:57:09 PM PDT 24
Finished Aug 10 06:57:24 PM PDT 24
Peak memory 207744 kb
Host smart-b3a13dfd-287f-48b0-892a-11d3ee607285
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563406990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.3563406990
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.102722107
Short name T852
Test name
Test status
Simulation time 20712147855 ps
CPU time 22.37 seconds
Started Aug 10 06:57:09 PM PDT 24
Finished Aug 10 06:57:32 PM PDT 24
Peak memory 207816 kb
Host smart-cfbaf670-d921-41ca-8a5e-1e0f22ba75b8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=102722107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.102722107
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1104971556
Short name T1642
Test name
Test status
Simulation time 24765348756 ps
CPU time 31.58 seconds
Started Aug 10 06:57:20 PM PDT 24
Finished Aug 10 06:57:52 PM PDT 24
Peak memory 215984 kb
Host smart-72b31e38-31b1-4b6c-9658-5eeef73a4e09
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104971556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1104971556
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.509001144
Short name T1456
Test name
Test status
Simulation time 215798863 ps
CPU time 0.94 seconds
Started Aug 10 06:57:19 PM PDT 24
Finished Aug 10 06:57:20 PM PDT 24
Peak memory 207524 kb
Host smart-8f0fbbd0-e940-4517-98a8-99027527348e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50900
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.509001144
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.717040226
Short name T843
Test name
Test status
Simulation time 144328354 ps
CPU time 0.85 seconds
Started Aug 10 06:57:31 PM PDT 24
Finished Aug 10 06:57:32 PM PDT 24
Peak memory 207524 kb
Host smart-60dbd6f5-8a50-4ad8-bf77-51749eab1586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71704
0226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.717040226
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.552494238
Short name T1007
Test name
Test status
Simulation time 354774829 ps
CPU time 1.28 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 06:57:42 PM PDT 24
Peak memory 207508 kb
Host smart-b0c69249-4c38-421a-8dfb-8834b97c92fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55249
4238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.552494238
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.4126900860
Short name T1703
Test name
Test status
Simulation time 755808144 ps
CPU time 2.02 seconds
Started Aug 10 06:57:42 PM PDT 24
Finished Aug 10 06:57:44 PM PDT 24
Peak memory 207760 kb
Host smart-89d68022-014c-426a-9916-b2cbef27365d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4126900860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.4126900860
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3523201337
Short name T2207
Test name
Test status
Simulation time 18137803141 ps
CPU time 27.84 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 06:58:09 PM PDT 24
Peak memory 207680 kb
Host smart-9335f05d-f874-46b9-ba8c-dedeb5d201fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232
01337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3523201337
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.330764739
Short name T728
Test name
Test status
Simulation time 1416003889 ps
CPU time 32.9 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 06:58:14 PM PDT 24
Peak memory 207784 kb
Host smart-e6b3a789-f64c-4572-8af3-3568928b7942
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330764739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.330764739
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2258965173
Short name T533
Test name
Test status
Simulation time 580286802 ps
CPU time 1.53 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 06:57:43 PM PDT 24
Peak memory 207532 kb
Host smart-2b7b6d54-f877-4272-8cef-ea5adc2e3c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22589
65173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2258965173
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2502188614
Short name T2155
Test name
Test status
Simulation time 190670459 ps
CPU time 0.87 seconds
Started Aug 10 06:57:42 PM PDT 24
Finished Aug 10 06:57:43 PM PDT 24
Peak memory 207548 kb
Host smart-1c564944-0da7-4a7a-a05c-1724ea8bb766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
88614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2502188614
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1306135367
Short name T1795
Test name
Test status
Simulation time 50153125 ps
CPU time 0.71 seconds
Started Aug 10 06:57:55 PM PDT 24
Finished Aug 10 06:57:56 PM PDT 24
Peak memory 207512 kb
Host smart-a7140310-497a-4f50-a4e2-f37570e9b181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
35367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1306135367
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1532665955
Short name T1695
Test name
Test status
Simulation time 973332375 ps
CPU time 2.3 seconds
Started Aug 10 06:57:55 PM PDT 24
Finished Aug 10 06:57:57 PM PDT 24
Peak memory 207760 kb
Host smart-3f1331ec-dabc-406a-bf02-38400f2a605d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
65955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1532665955
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_types.2348436296
Short name T411
Test name
Test status
Simulation time 776635660 ps
CPU time 1.82 seconds
Started Aug 10 06:57:56 PM PDT 24
Finished Aug 10 06:57:58 PM PDT 24
Peak memory 207476 kb
Host smart-da265907-9245-491d-acfc-47f3be206819
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2348436296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.2348436296
Directory /workspace/0.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.428497066
Short name T1716
Test name
Test status
Simulation time 110211191081 ps
CPU time 174.83 seconds
Started Aug 10 06:57:55 PM PDT 24
Finished Aug 10 07:00:50 PM PDT 24
Peak memory 207740 kb
Host smart-ce90ee05-b01b-4f7a-85dd-22063e96e9f8
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=428497066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.428497066
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.926613875
Short name T3187
Test name
Test status
Simulation time 101324580514 ps
CPU time 187.49 seconds
Started Aug 10 06:58:06 PM PDT 24
Finished Aug 10 07:01:14 PM PDT 24
Peak memory 207848 kb
Host smart-aa5062c9-48b2-4864-87ba-5b086fc78045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926613875 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.926613875
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3180311242
Short name T1205
Test name
Test status
Simulation time 97107934742 ps
CPU time 177.19 seconds
Started Aug 10 06:58:06 PM PDT 24
Finished Aug 10 07:01:03 PM PDT 24
Peak memory 207884 kb
Host smart-24643a53-e58b-4604-9656-cd453568ee69
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3180311242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3180311242
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.221406865
Short name T2995
Test name
Test status
Simulation time 102120470660 ps
CPU time 167 seconds
Started Aug 10 06:58:06 PM PDT 24
Finished Aug 10 07:00:53 PM PDT 24
Peak memory 207944 kb
Host smart-f6983af9-1fb0-4627-9e83-20647b100116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221406865 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.221406865
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.950094828
Short name T1066
Test name
Test status
Simulation time 115178905028 ps
CPU time 179.52 seconds
Started Aug 10 06:58:05 PM PDT 24
Finished Aug 10 07:01:05 PM PDT 24
Peak memory 207828 kb
Host smart-7196ce46-29e4-4e9c-b004-47ee4650d2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95009
4828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.950094828
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2662332534
Short name T2669
Test name
Test status
Simulation time 193029156 ps
CPU time 1.08 seconds
Started Aug 10 06:58:07 PM PDT 24
Finished Aug 10 06:58:08 PM PDT 24
Peak memory 215888 kb
Host smart-4f0fdb96-bd90-4f29-82f6-5bbe2526f51a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2662332534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2662332534
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3223399789
Short name T2466
Test name
Test status
Simulation time 154157269 ps
CPU time 0.85 seconds
Started Aug 10 06:58:05 PM PDT 24
Finished Aug 10 06:58:06 PM PDT 24
Peak memory 207704 kb
Host smart-f420b3a3-8dd7-40e5-99d4-d65c9b452355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233
99789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3223399789
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2136945711
Short name T2055
Test name
Test status
Simulation time 231029527 ps
CPU time 1.03 seconds
Started Aug 10 06:58:03 PM PDT 24
Finished Aug 10 06:58:04 PM PDT 24
Peak memory 207400 kb
Host smart-9475d8ab-d296-49fa-9ef1-1ffb6571e098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21369
45711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2136945711
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.160362406
Short name T2108
Test name
Test status
Simulation time 4630532392 ps
CPU time 39.57 seconds
Started Aug 10 06:58:06 PM PDT 24
Finished Aug 10 06:58:45 PM PDT 24
Peak memory 216108 kb
Host smart-bdbd8ad2-c102-4c14-a54f-78fe73260b62
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=160362406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.160362406
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.130495307
Short name T1958
Test name
Test status
Simulation time 11100297010 ps
CPU time 78.01 seconds
Started Aug 10 06:58:14 PM PDT 24
Finished Aug 10 06:59:32 PM PDT 24
Peak memory 207788 kb
Host smart-250ab0f6-e547-4a92-84eb-38549195eb67
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=130495307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.130495307
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1147248244
Short name T783
Test name
Test status
Simulation time 261751297 ps
CPU time 0.97 seconds
Started Aug 10 06:58:14 PM PDT 24
Finished Aug 10 06:58:15 PM PDT 24
Peak memory 207456 kb
Host smart-a7fb066c-2fa6-4f64-abf1-e3c95fb0a22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
48244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1147248244
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3177993468
Short name T73
Test name
Test status
Simulation time 429481132 ps
CPU time 1.37 seconds
Started Aug 10 06:58:14 PM PDT 24
Finished Aug 10 06:58:16 PM PDT 24
Peak memory 207540 kb
Host smart-832d0059-1b96-49f0-bce4-e792a0dfdae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31779
93468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3177993468
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.272465091
Short name T1340
Test name
Test status
Simulation time 29368226915 ps
CPU time 43.75 seconds
Started Aug 10 06:58:13 PM PDT 24
Finished Aug 10 06:58:57 PM PDT 24
Peak memory 207816 kb
Host smart-3880046f-1127-4bf4-9ea3-202a5818e3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27246
5091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.272465091
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.826030588
Short name T1480
Test name
Test status
Simulation time 8369291003 ps
CPU time 10.52 seconds
Started Aug 10 06:58:23 PM PDT 24
Finished Aug 10 06:58:34 PM PDT 24
Peak memory 207868 kb
Host smart-37dd0e4f-e895-4a0c-bbf0-c0767a61f353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82603
0588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.826030588
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2799274893
Short name T3406
Test name
Test status
Simulation time 5179665325 ps
CPU time 147.24 seconds
Started Aug 10 06:58:22 PM PDT 24
Finished Aug 10 07:00:49 PM PDT 24
Peak memory 218348 kb
Host smart-c2037fb7-4726-4769-9c79-fe00ef49cfe3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2799274893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2799274893
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2659026312
Short name T574
Test name
Test status
Simulation time 2190834531 ps
CPU time 16.28 seconds
Started Aug 10 06:58:22 PM PDT 24
Finished Aug 10 06:58:39 PM PDT 24
Peak memory 216116 kb
Host smart-808d4e37-4383-4be9-990b-07e6cfc68659
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2659026312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2659026312
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1078597505
Short name T2026
Test name
Test status
Simulation time 246674760 ps
CPU time 1.02 seconds
Started Aug 10 06:58:23 PM PDT 24
Finished Aug 10 06:58:24 PM PDT 24
Peak memory 207576 kb
Host smart-f70e5dbc-950f-438c-a95a-5114f921ab1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1078597505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1078597505
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.4076910755
Short name T1483
Test name
Test status
Simulation time 192891957 ps
CPU time 0.92 seconds
Started Aug 10 06:58:30 PM PDT 24
Finished Aug 10 06:58:31 PM PDT 24
Peak memory 207508 kb
Host smart-167ce18f-4a87-420d-9ae3-f3254c9cd13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
10755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4076910755
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.2325393765
Short name T1618
Test name
Test status
Simulation time 3173533414 ps
CPU time 87.88 seconds
Started Aug 10 06:58:30 PM PDT 24
Finished Aug 10 06:59:58 PM PDT 24
Peak memory 215984 kb
Host smart-a6740d84-aba1-45ff-acf2-f86052bb3b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
93765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.2325393765
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.538423474
Short name T3449
Test name
Test status
Simulation time 2361819487 ps
CPU time 69.74 seconds
Started Aug 10 06:58:30 PM PDT 24
Finished Aug 10 06:59:40 PM PDT 24
Peak memory 217992 kb
Host smart-b19c42b6-e6de-435a-880a-3f09d2d32f94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=538423474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.538423474
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.4149851157
Short name T2756
Test name
Test status
Simulation time 2686507773 ps
CPU time 78.61 seconds
Started Aug 10 06:58:31 PM PDT 24
Finished Aug 10 06:59:50 PM PDT 24
Peak memory 217404 kb
Host smart-c813411a-3347-45c9-a68e-1800f659c8f0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4149851157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.4149851157
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1819029363
Short name T3571
Test name
Test status
Simulation time 165973322 ps
CPU time 0.87 seconds
Started Aug 10 06:58:39 PM PDT 24
Finished Aug 10 06:58:40 PM PDT 24
Peak memory 207516 kb
Host smart-495b7bd7-fd05-4ab0-b20c-79cefd9eb4dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1819029363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1819029363
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1406646791
Short name T759
Test name
Test status
Simulation time 198230839 ps
CPU time 0.84 seconds
Started Aug 10 06:58:38 PM PDT 24
Finished Aug 10 06:58:39 PM PDT 24
Peak memory 207544 kb
Host smart-949ac3b5-02aa-40ce-a9ca-ccdf4222f3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
46791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1406646791
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4211600867
Short name T75
Test name
Test status
Simulation time 437408749 ps
CPU time 1.39 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:42 PM PDT 24
Peak memory 207516 kb
Host smart-505c1000-6884-4499-8fe2-995cc2cec239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116
00867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.4211600867
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1473716284
Short name T2264
Test name
Test status
Simulation time 213046586 ps
CPU time 0.93 seconds
Started Aug 10 06:58:42 PM PDT 24
Finished Aug 10 06:58:43 PM PDT 24
Peak memory 207580 kb
Host smart-871a9994-43e5-45a4-9ff0-83e82d91e34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14737
16284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1473716284
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1655590060
Short name T714
Test name
Test status
Simulation time 213418258 ps
CPU time 0.91 seconds
Started Aug 10 06:58:42 PM PDT 24
Finished Aug 10 06:58:43 PM PDT 24
Peak memory 207468 kb
Host smart-f10e15ec-a492-4cf4-b626-5d87f3d6da55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16555
90060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1655590060
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3420971547
Short name T2701
Test name
Test status
Simulation time 185590919 ps
CPU time 0.9 seconds
Started Aug 10 06:58:39 PM PDT 24
Finished Aug 10 06:58:40 PM PDT 24
Peak memory 207512 kb
Host smart-786c456e-3074-49ed-a948-cb0866c03f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34209
71547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3420971547
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4209181655
Short name T3297
Test name
Test status
Simulation time 214837841 ps
CPU time 0.89 seconds
Started Aug 10 06:58:41 PM PDT 24
Finished Aug 10 06:58:42 PM PDT 24
Peak memory 207480 kb
Host smart-214a1f64-7c76-4879-8a16-fd8f1295390f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
81655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4209181655
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1192460385
Short name T823
Test name
Test status
Simulation time 166215652 ps
CPU time 0.84 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207584 kb
Host smart-ffe06d89-8d72-4d89-b25b-c3d89972d21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
60385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1192460385
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1193526441
Short name T3006
Test name
Test status
Simulation time 219084413 ps
CPU time 1.03 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207552 kb
Host smart-b9ba2584-a160-4f86-b049-22ca08c8242a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1193526441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1193526441
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.31034176
Short name T1873
Test name
Test status
Simulation time 210274252 ps
CPU time 1 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207516 kb
Host smart-52c45cec-3566-4499-8861-72f596c018bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.31034176
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1826011510
Short name T846
Test name
Test status
Simulation time 214782234 ps
CPU time 1.04 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207568 kb
Host smart-35198cfd-c01d-4bc7-a1e0-c98e7f47ffce
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1826011510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1826011510
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.121628625
Short name T2953
Test name
Test status
Simulation time 239098876 ps
CPU time 1 seconds
Started Aug 10 06:58:40 PM PDT 24
Finished Aug 10 06:58:41 PM PDT 24
Peak memory 207416 kb
Host smart-d1e2fcfc-bbef-484e-89a1-a9aa3376d44c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=121628625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.121628625
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.608420704
Short name T952
Test name
Test status
Simulation time 200951614 ps
CPU time 0.91 seconds
Started Aug 10 06:58:47 PM PDT 24
Finished Aug 10 06:58:48 PM PDT 24
Peak memory 207528 kb
Host smart-725cef72-126d-45cf-a790-5fd7043de48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60842
0704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.608420704
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.29552701
Short name T1786
Test name
Test status
Simulation time 88005129 ps
CPU time 0.72 seconds
Started Aug 10 06:58:48 PM PDT 24
Finished Aug 10 06:58:49 PM PDT 24
Peak memory 207380 kb
Host smart-ac54335f-2b33-459a-99a8-188746f0908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552
701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.29552701
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.974164308
Short name T317
Test name
Test status
Simulation time 20551888609 ps
CPU time 55.49 seconds
Started Aug 10 06:58:48 PM PDT 24
Finished Aug 10 06:59:43 PM PDT 24
Peak memory 216060 kb
Host smart-b4222468-057e-4cb8-8acb-aea2ce61dd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97416
4308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.974164308
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3708616947
Short name T3605
Test name
Test status
Simulation time 273259761 ps
CPU time 1.02 seconds
Started Aug 10 06:58:50 PM PDT 24
Finished Aug 10 06:58:51 PM PDT 24
Peak memory 207484 kb
Host smart-1f5c44bc-07c1-4943-bbaa-cf612b5843a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086
16947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3708616947
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.738531375
Short name T3292
Test name
Test status
Simulation time 219859155 ps
CPU time 0.93 seconds
Started Aug 10 06:58:49 PM PDT 24
Finished Aug 10 06:58:50 PM PDT 24
Peak memory 207520 kb
Host smart-9eb38b07-ae98-4d07-829d-7ce4422f0fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73853
1375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.738531375
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2966536001
Short name T1235
Test name
Test status
Simulation time 10755967768 ps
CPU time 71.43 seconds
Started Aug 10 06:58:58 PM PDT 24
Finished Aug 10 07:00:09 PM PDT 24
Peak memory 224236 kb
Host smart-f6c207d2-73a5-4c23-a347-8e9b13594857
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966536001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2966536001
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1452455539
Short name T168
Test name
Test status
Simulation time 6535492524 ps
CPU time 90.05 seconds
Started Aug 10 06:58:57 PM PDT 24
Finished Aug 10 07:00:27 PM PDT 24
Peak memory 219848 kb
Host smart-55694c7c-17c1-49fd-8db8-b55a86a2d554
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1452455539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1452455539
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.695872629
Short name T3212
Test name
Test status
Simulation time 13812404133 ps
CPU time 296.34 seconds
Started Aug 10 06:58:57 PM PDT 24
Finished Aug 10 07:03:54 PM PDT 24
Peak memory 216076 kb
Host smart-76034bd6-18ed-40db-b937-254274833e27
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=695872629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.695872629
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3990353153
Short name T2436
Test name
Test status
Simulation time 191030525 ps
CPU time 0.9 seconds
Started Aug 10 06:58:49 PM PDT 24
Finished Aug 10 06:58:50 PM PDT 24
Peak memory 207572 kb
Host smart-a98ef101-b647-4627-b939-0191c35f4a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
53153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3990353153
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3204656813
Short name T3058
Test name
Test status
Simulation time 175177035 ps
CPU time 0.92 seconds
Started Aug 10 06:58:47 PM PDT 24
Finished Aug 10 06:58:49 PM PDT 24
Peak memory 207740 kb
Host smart-78bc86ae-0ff0-4aec-989e-3f93b4e94f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32046
56813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3204656813
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2520954195
Short name T2583
Test name
Test status
Simulation time 20169084428 ps
CPU time 24.76 seconds
Started Aug 10 06:58:58 PM PDT 24
Finished Aug 10 06:59:23 PM PDT 24
Peak memory 207544 kb
Host smart-ca70074d-05a8-41b4-a210-91765be1cc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209
54195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2520954195
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1634305157
Short name T2651
Test name
Test status
Simulation time 213689594 ps
CPU time 0.89 seconds
Started Aug 10 06:58:57 PM PDT 24
Finished Aug 10 06:58:58 PM PDT 24
Peak memory 207448 kb
Host smart-958d3a7c-c0a2-49aa-b163-9f29edcddaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
05157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1634305157
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2527498666
Short name T3105
Test name
Test status
Simulation time 261143610 ps
CPU time 1.1 seconds
Started Aug 10 06:58:57 PM PDT 24
Finished Aug 10 06:58:58 PM PDT 24
Peak memory 207508 kb
Host smart-2a4d0e71-e27c-46e3-9a5e-3eee98969c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
98666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2527498666
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.757794861
Short name T255
Test name
Test status
Simulation time 1018084704 ps
CPU time 1.8 seconds
Started Aug 10 06:59:23 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 224544 kb
Host smart-ba339ae8-5841-4ac5-ad1d-a6252188741e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=757794861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.757794861
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1191875428
Short name T3377
Test name
Test status
Simulation time 303472792 ps
CPU time 1.05 seconds
Started Aug 10 06:59:06 PM PDT 24
Finished Aug 10 06:59:08 PM PDT 24
Peak memory 207540 kb
Host smart-b11f1c1c-6f94-45c9-848e-7cbdb936c8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
75428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1191875428
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1189297343
Short name T1748
Test name
Test status
Simulation time 151121673 ps
CPU time 0.85 seconds
Started Aug 10 06:59:05 PM PDT 24
Finished Aug 10 06:59:06 PM PDT 24
Peak memory 207540 kb
Host smart-228f49b7-b05c-4023-bd9e-bb3eafd4ddfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11892
97343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1189297343
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1197978360
Short name T3185
Test name
Test status
Simulation time 175156863 ps
CPU time 0.88 seconds
Started Aug 10 06:59:15 PM PDT 24
Finished Aug 10 06:59:16 PM PDT 24
Peak memory 207568 kb
Host smart-b2ad0c4e-f698-4f6c-a5be-3fac47cca14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
78360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1197978360
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1243368250
Short name T3438
Test name
Test status
Simulation time 210414844 ps
CPU time 0.99 seconds
Started Aug 10 06:59:14 PM PDT 24
Finished Aug 10 06:59:15 PM PDT 24
Peak memory 207528 kb
Host smart-cc96b60a-b0d7-489c-be6b-a77ca972cffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12433
68250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1243368250
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1063277961
Short name T539
Test name
Test status
Simulation time 2264528749 ps
CPU time 18.14 seconds
Started Aug 10 06:59:15 PM PDT 24
Finished Aug 10 06:59:33 PM PDT 24
Peak memory 216096 kb
Host smart-11f59d2d-cd25-4cd6-9cb2-601b4730fa84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1063277961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1063277961
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.637971374
Short name T757
Test name
Test status
Simulation time 157540673 ps
CPU time 0.84 seconds
Started Aug 10 06:59:14 PM PDT 24
Finished Aug 10 06:59:15 PM PDT 24
Peak memory 207508 kb
Host smart-defd923a-7980-4e10-bd47-81fd6f146c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63797
1374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.637971374
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2788121114
Short name T1589
Test name
Test status
Simulation time 161598629 ps
CPU time 0.86 seconds
Started Aug 10 06:59:14 PM PDT 24
Finished Aug 10 06:59:15 PM PDT 24
Peak memory 207512 kb
Host smart-108e6481-1867-48ff-aa61-5057a72508b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
21114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2788121114
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.941517242
Short name T1921
Test name
Test status
Simulation time 431988508 ps
CPU time 1.38 seconds
Started Aug 10 06:59:14 PM PDT 24
Finished Aug 10 06:59:16 PM PDT 24
Peak memory 207492 kb
Host smart-57022a52-b94b-4f5a-9bb5-4f096b9136bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94151
7242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.941517242
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2128543451
Short name T3093
Test name
Test status
Simulation time 2535671482 ps
CPU time 23.74 seconds
Started Aug 10 06:59:15 PM PDT 24
Finished Aug 10 06:59:38 PM PDT 24
Peak memory 216168 kb
Host smart-760033b9-50f9-470f-b85c-68fc0f30832e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
43451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2128543451
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2951530116
Short name T108
Test name
Test status
Simulation time 5903585230 ps
CPU time 67.05 seconds
Started Aug 10 06:59:23 PM PDT 24
Finished Aug 10 07:00:30 PM PDT 24
Peak memory 219908 kb
Host smart-d7972f28-e4df-43b7-a62b-c2de8b314ef3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951530116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2951530116
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.3156136449
Short name T1331
Test name
Test status
Simulation time 1007151410 ps
CPU time 22.3 seconds
Started Aug 10 06:57:41 PM PDT 24
Finished Aug 10 06:58:03 PM PDT 24
Peak memory 207736 kb
Host smart-eec1bf02-9629-4cea-b1af-008cd589343d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156136449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.3156136449
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/0.usbdev_tx_rx_disruption.1795698608
Short name T2165
Test name
Test status
Simulation time 625710064 ps
CPU time 1.56 seconds
Started Aug 10 06:59:26 PM PDT 24
Finished Aug 10 06:59:27 PM PDT 24
Peak memory 207416 kb
Host smart-402961b2-ceb4-40d7-bf7c-5f233ed170a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795698608 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.usbdev_tx_rx_disruption.1795698608
Directory /workspace/0.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3339714532
Short name T3483
Test name
Test status
Simulation time 54998299 ps
CPU time 0.68 seconds
Started Aug 10 07:00:29 PM PDT 24
Finished Aug 10 07:00:30 PM PDT 24
Peak memory 207536 kb
Host smart-e531e97c-66a4-4de8-9c4d-daac473806c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3339714532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3339714532
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1681847338
Short name T3266
Test name
Test status
Simulation time 11561465029 ps
CPU time 14.98 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:39 PM PDT 24
Peak memory 207852 kb
Host smart-2c05e3aa-2133-45b1-9429-942c199c661b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681847338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.1681847338
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3842587078
Short name T2595
Test name
Test status
Simulation time 20818342081 ps
CPU time 26.79 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:50 PM PDT 24
Peak memory 207660 kb
Host smart-2abbb0fa-e0a8-4ea7-98ae-856b7eb667ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842587078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3842587078
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1846245718
Short name T3395
Test name
Test status
Simulation time 156167843 ps
CPU time 0.85 seconds
Started Aug 10 06:59:25 PM PDT 24
Finished Aug 10 06:59:26 PM PDT 24
Peak memory 207568 kb
Host smart-951b3c76-d60a-40ff-92a9-2cf0b6e93722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18462
45718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1846245718
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2273391668
Short name T49
Test name
Test status
Simulation time 196253699 ps
CPU time 0.92 seconds
Started Aug 10 06:59:22 PM PDT 24
Finished Aug 10 06:59:23 PM PDT 24
Peak memory 207560 kb
Host smart-6e95a4ba-2946-45b6-9e14-161df946932d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22733
91668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2273391668
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.3250583766
Short name T63
Test name
Test status
Simulation time 155398777 ps
CPU time 0.86 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 207448 kb
Host smart-7e51aea0-8bcc-421c-abf0-d7f74cc7311a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32505
83766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3250583766
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3804787060
Short name T1761
Test name
Test status
Simulation time 143717727 ps
CPU time 0.85 seconds
Started Aug 10 06:59:26 PM PDT 24
Finished Aug 10 06:59:27 PM PDT 24
Peak memory 207412 kb
Host smart-1ddc6c40-35b9-4465-8d20-7f209a3c9a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38047
87060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3804787060
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1786693022
Short name T1886
Test name
Test status
Simulation time 198366850 ps
CPU time 1.02 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:26 PM PDT 24
Peak memory 207520 kb
Host smart-20c04747-3120-47e4-82e7-d0aef026ca4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866
93022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1786693022
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3239949860
Short name T3610
Test name
Test status
Simulation time 819293688 ps
CPU time 2.15 seconds
Started Aug 10 06:59:23 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 207724 kb
Host smart-e4bf4bde-e536-4aa5-aec4-49691136d9d6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3239949860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3239949860
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1250528639
Short name T1391
Test name
Test status
Simulation time 18071931928 ps
CPU time 29.31 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:53 PM PDT 24
Peak memory 207776 kb
Host smart-52e51405-3c53-4b65-8286-0a2e4114118c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
28639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1250528639
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.1729855268
Short name T2104
Test name
Test status
Simulation time 4289715932 ps
CPU time 35.77 seconds
Started Aug 10 06:59:23 PM PDT 24
Finished Aug 10 06:59:59 PM PDT 24
Peak memory 207800 kb
Host smart-9b456029-7284-4473-9409-235421c3d6b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729855268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.1729855268
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1070490477
Short name T1737
Test name
Test status
Simulation time 688791562 ps
CPU time 1.63 seconds
Started Aug 10 06:59:23 PM PDT 24
Finished Aug 10 06:59:24 PM PDT 24
Peak memory 207488 kb
Host smart-06bc2917-08b4-4020-b3a3-46f93a9b2ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10704
90477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1070490477
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_enable.1762398779
Short name T1156
Test name
Test status
Simulation time 61075076 ps
CPU time 0.72 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 06:59:25 PM PDT 24
Peak memory 207548 kb
Host smart-756ee362-83e8-4514-874e-cf2cf6bcebf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
98779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1762398779
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3992705936
Short name T2324
Test name
Test status
Simulation time 953087105 ps
CPU time 2.43 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 06:59:34 PM PDT 24
Peak memory 207928 kb
Host smart-e3cc280f-4a83-405f-aef5-feb6aff073c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
05936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3992705936
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_types.2094068551
Short name T1989
Test name
Test status
Simulation time 219680258 ps
CPU time 0.91 seconds
Started Aug 10 06:59:36 PM PDT 24
Finished Aug 10 06:59:37 PM PDT 24
Peak memory 207564 kb
Host smart-a857e2d2-4aed-40c0-aaed-4c7c40f8ab79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2094068551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.2094068551
Directory /workspace/1.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4129043276
Short name T3159
Test name
Test status
Simulation time 220050111 ps
CPU time 1.57 seconds
Started Aug 10 06:59:33 PM PDT 24
Finished Aug 10 06:59:34 PM PDT 24
Peak memory 207644 kb
Host smart-d1fdd0e3-6301-4559-af90-f42b4a5b7f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41290
43276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4129043276
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3970860518
Short name T1738
Test name
Test status
Simulation time 82172128403 ps
CPU time 141.92 seconds
Started Aug 10 06:59:33 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207816 kb
Host smart-8e7c7008-146d-4471-98be-1c564a4a41f5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3970860518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3970860518
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.4172996836
Short name T3520
Test name
Test status
Simulation time 111379647407 ps
CPU time 194.37 seconds
Started Aug 10 06:59:36 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207928 kb
Host smart-09475732-a8b7-4ebf-9da8-ad77738e4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172996836 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.4172996836
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2834448185
Short name T1109
Test name
Test status
Simulation time 119126103988 ps
CPU time 200.34 seconds
Started Aug 10 06:59:31 PM PDT 24
Finished Aug 10 07:02:52 PM PDT 24
Peak memory 207720 kb
Host smart-1bf63caf-cdd4-4168-8974-b6f40ad32772
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2834448185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2834448185
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1861474501
Short name T2113
Test name
Test status
Simulation time 108194904725 ps
CPU time 185.03 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 07:02:37 PM PDT 24
Peak memory 207848 kb
Host smart-e3accaeb-7e66-4e8b-96d3-05fe6e5123f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861474501 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1861474501
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1870354571
Short name T367
Test name
Test status
Simulation time 110178497085 ps
CPU time 179.69 seconds
Started Aug 10 06:59:37 PM PDT 24
Finished Aug 10 07:02:36 PM PDT 24
Peak memory 207880 kb
Host smart-bb919553-bb6c-4767-8cea-1f47502ab513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18703
54571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1870354571
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2133604110
Short name T990
Test name
Test status
Simulation time 229909883 ps
CPU time 1.13 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 06:59:33 PM PDT 24
Peak memory 215988 kb
Host smart-9668557a-85dc-4d40-9967-7e4b3e386d70
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2133604110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2133604110
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.251655656
Short name T994
Test name
Test status
Simulation time 140915364 ps
CPU time 0.83 seconds
Started Aug 10 06:59:36 PM PDT 24
Finished Aug 10 06:59:37 PM PDT 24
Peak memory 207568 kb
Host smart-fc799180-825c-4b3f-aa81-1c785fa7f138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25165
5656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.251655656
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.243448066
Short name T557
Test name
Test status
Simulation time 219144697 ps
CPU time 0.92 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 06:59:33 PM PDT 24
Peak memory 207548 kb
Host smart-e0fbbd4b-ce2e-4517-8d57-674067009b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
8066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.243448066
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3612906583
Short name T1663
Test name
Test status
Simulation time 3841651496 ps
CPU time 105.09 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 07:01:18 PM PDT 24
Peak memory 218452 kb
Host smart-1c11be3d-d811-40b3-91e9-5a83718b7e40
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3612906583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3612906583
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.1078683119
Short name T95
Test name
Test status
Simulation time 10235254394 ps
CPU time 64.58 seconds
Started Aug 10 06:59:32 PM PDT 24
Finished Aug 10 07:00:37 PM PDT 24
Peak memory 207828 kb
Host smart-fd711ce9-99b7-4ef8-880f-61f6eecf5e0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1078683119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.1078683119
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2959182282
Short name T655
Test name
Test status
Simulation time 170557294 ps
CPU time 0.82 seconds
Started Aug 10 06:59:42 PM PDT 24
Finished Aug 10 06:59:43 PM PDT 24
Peak memory 207552 kb
Host smart-d76dcf90-27b3-477b-a86a-a401dfed3a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591
82282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2959182282
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2069135804
Short name T527
Test name
Test status
Simulation time 30038612250 ps
CPU time 44.09 seconds
Started Aug 10 06:59:42 PM PDT 24
Finished Aug 10 07:00:26 PM PDT 24
Peak memory 207872 kb
Host smart-2135439f-f4c9-4317-b0fd-c7a2625b2895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20691
35804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2069135804
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1472381567
Short name T2265
Test name
Test status
Simulation time 10013827153 ps
CPU time 12.89 seconds
Started Aug 10 06:59:50 PM PDT 24
Finished Aug 10 07:00:03 PM PDT 24
Peak memory 207876 kb
Host smart-0d2a686f-a203-4b3e-8e6e-2db97fef94f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14723
81567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1472381567
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3463636377
Short name T1734
Test name
Test status
Simulation time 4147320586 ps
CPU time 117.23 seconds
Started Aug 10 06:59:50 PM PDT 24
Finished Aug 10 07:01:48 PM PDT 24
Peak memory 216028 kb
Host smart-fa4a72ee-30fb-4a89-9fd6-15af6341ed42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3463636377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3463636377
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2074846073
Short name T2946
Test name
Test status
Simulation time 2381325523 ps
CPU time 18.85 seconds
Started Aug 10 06:59:50 PM PDT 24
Finished Aug 10 07:00:09 PM PDT 24
Peak memory 207932 kb
Host smart-d37555d1-d95b-40ef-b812-fd98db4d714c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2074846073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2074846073
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3308657980
Short name T2866
Test name
Test status
Simulation time 233967995 ps
CPU time 1.01 seconds
Started Aug 10 06:59:49 PM PDT 24
Finished Aug 10 06:59:50 PM PDT 24
Peak memory 207528 kb
Host smart-0844e1a1-e8c6-4725-b4a5-115ac5c6e013
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3308657980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3308657980
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3131133900
Short name T1063
Test name
Test status
Simulation time 198764331 ps
CPU time 0.92 seconds
Started Aug 10 06:59:51 PM PDT 24
Finished Aug 10 06:59:52 PM PDT 24
Peak memory 207512 kb
Host smart-59b26402-38bc-4d9e-9c42-8e0e7787b990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31311
33900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3131133900
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.3110038374
Short name T2517
Test name
Test status
Simulation time 3215598999 ps
CPU time 23.26 seconds
Started Aug 10 06:59:50 PM PDT 24
Finished Aug 10 07:00:13 PM PDT 24
Peak memory 224344 kb
Host smart-2a026bce-e15f-43e4-b6f1-b43f8bc3bc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100
38374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.3110038374
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1896183291
Short name T223
Test name
Test status
Simulation time 1454701799 ps
CPU time 41.17 seconds
Started Aug 10 06:59:50 PM PDT 24
Finished Aug 10 07:00:32 PM PDT 24
Peak memory 215928 kb
Host smart-9888ec21-623b-4683-aa57-e2fbf9ae8bc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1896183291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1896183291
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3424339093
Short name T1651
Test name
Test status
Simulation time 2128628218 ps
CPU time 16.06 seconds
Started Aug 10 06:59:51 PM PDT 24
Finished Aug 10 07:00:07 PM PDT 24
Peak memory 224140 kb
Host smart-127a2c75-e13a-4304-b479-57027bf63524
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3424339093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3424339093
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3113084040
Short name T1626
Test name
Test status
Simulation time 160459402 ps
CPU time 0.88 seconds
Started Aug 10 06:59:58 PM PDT 24
Finished Aug 10 06:59:59 PM PDT 24
Peak memory 207480 kb
Host smart-e150e230-4f88-448f-b713-fde748bec26e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3113084040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3113084040
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1153697443
Short name T309
Test name
Test status
Simulation time 224083810 ps
CPU time 0.94 seconds
Started Aug 10 06:59:59 PM PDT 24
Finished Aug 10 07:00:00 PM PDT 24
Peak memory 207484 kb
Host smart-0b4e2cfd-9d36-4b86-be2b-ff961bc9d5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
97443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1153697443
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1923660033
Short name T688
Test name
Test status
Simulation time 149249790 ps
CPU time 0.83 seconds
Started Aug 10 06:59:59 PM PDT 24
Finished Aug 10 07:00:00 PM PDT 24
Peak memory 207544 kb
Host smart-452a1114-492b-48f5-af20-595203f4250e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
60033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1923660033
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3664985749
Short name T3581
Test name
Test status
Simulation time 196438429 ps
CPU time 0.91 seconds
Started Aug 10 06:59:58 PM PDT 24
Finished Aug 10 06:59:59 PM PDT 24
Peak memory 207496 kb
Host smart-ddecf00e-743e-4c87-a746-3aeb3e8f1ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
85749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3664985749
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3610697799
Short name T1419
Test name
Test status
Simulation time 151895394 ps
CPU time 0.84 seconds
Started Aug 10 06:59:59 PM PDT 24
Finished Aug 10 07:00:00 PM PDT 24
Peak memory 207536 kb
Host smart-39a95f18-91f5-423d-a99e-2e1d5368804a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106
97799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3610697799
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.4085077082
Short name T2452
Test name
Test status
Simulation time 148627099 ps
CPU time 0.91 seconds
Started Aug 10 06:59:59 PM PDT 24
Finished Aug 10 07:00:00 PM PDT 24
Peak memory 207572 kb
Host smart-dd1c8aa3-ccb5-4822-8ba8-835ec49eaf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
77082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.4085077082
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2803806630
Short name T1117
Test name
Test status
Simulation time 210284535 ps
CPU time 1.02 seconds
Started Aug 10 06:59:58 PM PDT 24
Finished Aug 10 06:59:59 PM PDT 24
Peak memory 207508 kb
Host smart-de4b15d1-f1a0-493b-bb7a-5519d86510b7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2803806630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2803806630
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.2683065387
Short name T1464
Test name
Test status
Simulation time 259534056 ps
CPU time 1.08 seconds
Started Aug 10 07:00:10 PM PDT 24
Finished Aug 10 07:00:11 PM PDT 24
Peak memory 207740 kb
Host smart-6967e0c4-72d7-48e1-87e2-6dc3d6bd4f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
65387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.2683065387
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.4208009212
Short name T2106
Test name
Test status
Simulation time 141817876 ps
CPU time 0.81 seconds
Started Aug 10 07:00:10 PM PDT 24
Finished Aug 10 07:00:11 PM PDT 24
Peak memory 207472 kb
Host smart-0aa17e57-4184-4a39-8e1c-fc999ba05265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
09212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.4208009212
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2991341099
Short name T1074
Test name
Test status
Simulation time 89647828 ps
CPU time 0.75 seconds
Started Aug 10 07:00:09 PM PDT 24
Finished Aug 10 07:00:10 PM PDT 24
Peak memory 207516 kb
Host smart-3bd21035-0b9c-4fc2-9aa3-92fe04006d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
41099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2991341099
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3795752732
Short name T3180
Test name
Test status
Simulation time 18978110051 ps
CPU time 46.9 seconds
Started Aug 10 07:00:09 PM PDT 24
Finished Aug 10 07:00:56 PM PDT 24
Peak memory 216084 kb
Host smart-3e4d3130-528b-4848-ae73-57f489b9fda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
52732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3795752732
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4013545829
Short name T1995
Test name
Test status
Simulation time 141993818 ps
CPU time 0.85 seconds
Started Aug 10 07:00:10 PM PDT 24
Finished Aug 10 07:00:11 PM PDT 24
Peak memory 207576 kb
Host smart-0690d7c2-03c9-4d5f-a8e4-d045cff61823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40135
45829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4013545829
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3453544078
Short name T3109
Test name
Test status
Simulation time 234600798 ps
CPU time 0.95 seconds
Started Aug 10 07:00:09 PM PDT 24
Finished Aug 10 07:00:10 PM PDT 24
Peak memory 207452 kb
Host smart-71aa70c7-5cac-4071-9347-0a45dad50cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
44078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3453544078
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1764578778
Short name T2984
Test name
Test status
Simulation time 6461256677 ps
CPU time 23.07 seconds
Started Aug 10 07:00:09 PM PDT 24
Finished Aug 10 07:00:33 PM PDT 24
Peak memory 218212 kb
Host smart-db2740ea-c240-4431-a85b-ca81a0f8bb65
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764578778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1764578778
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.335561223
Short name T1471
Test name
Test status
Simulation time 2083459613 ps
CPU time 11.8 seconds
Started Aug 10 07:00:10 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 218064 kb
Host smart-a95f4a62-888d-4bc9-90c0-3d09076a6b19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=335561223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.335561223
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3219669327
Short name T1185
Test name
Test status
Simulation time 10148100061 ps
CPU time 205.21 seconds
Started Aug 10 07:00:10 PM PDT 24
Finished Aug 10 07:03:35 PM PDT 24
Peak memory 224248 kb
Host smart-f61bcc87-10e5-454b-8012-c01406b8c37d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219669327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3219669327
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.740636664
Short name T2476
Test name
Test status
Simulation time 259335873 ps
CPU time 0.99 seconds
Started Aug 10 07:00:11 PM PDT 24
Finished Aug 10 07:00:12 PM PDT 24
Peak memory 207532 kb
Host smart-e3362bf8-b7cc-4bac-bdfe-4d5406f9d17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74063
6664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.740636664
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.165041993
Short name T1144
Test name
Test status
Simulation time 194700382 ps
CPU time 0.98 seconds
Started Aug 10 07:00:11 PM PDT 24
Finished Aug 10 07:00:12 PM PDT 24
Peak memory 207468 kb
Host smart-a131bd74-f90d-421b-9eab-2bdcf5aebf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
1993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.165041993
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_resume_link_active.378970718
Short name T1036
Test name
Test status
Simulation time 20166309874 ps
CPU time 26.26 seconds
Started Aug 10 07:00:09 PM PDT 24
Finished Aug 10 07:00:35 PM PDT 24
Peak memory 207636 kb
Host smart-abaddc68-5d27-40df-93c9-48b194f6dea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37897
0718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_resume_link_active.378970718
Directory /workspace/1.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3031319477
Short name T1202
Test name
Test status
Simulation time 160493424 ps
CPU time 0.81 seconds
Started Aug 10 07:00:12 PM PDT 24
Finished Aug 10 07:00:13 PM PDT 24
Peak memory 207476 kb
Host smart-4cb3457d-4ba7-4e7a-a1a1-a11be4b437d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
19477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3031319477
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_full.2607394003
Short name T3084
Test name
Test status
Simulation time 358557402 ps
CPU time 1.3 seconds
Started Aug 10 07:00:24 PM PDT 24
Finished Aug 10 07:00:26 PM PDT 24
Peak memory 207484 kb
Host smart-6463a81f-d290-44c0-9535-05c823d92d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
94003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.2607394003
Directory /workspace/1.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3297484168
Short name T3510
Test name
Test status
Simulation time 168278065 ps
CPU time 0.88 seconds
Started Aug 10 07:00:24 PM PDT 24
Finished Aug 10 07:00:25 PM PDT 24
Peak memory 207480 kb
Host smart-f8684958-d8b7-48c1-8a47-610875c8637b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
84168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3297484168
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.679945033
Short name T254
Test name
Test status
Simulation time 671185978 ps
CPU time 1.69 seconds
Started Aug 10 07:00:29 PM PDT 24
Finished Aug 10 07:00:31 PM PDT 24
Peak memory 224560 kb
Host smart-e337239b-4b08-41c1-bc7e-951e3ca2c816
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=679945033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.679945033
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1472374714
Short name T56
Test name
Test status
Simulation time 398960536 ps
CPU time 1.33 seconds
Started Aug 10 07:00:19 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207488 kb
Host smart-b0e37c45-1c5a-4339-867a-34c21005d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14723
74714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1472374714
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3955590257
Short name T2837
Test name
Test status
Simulation time 214367178 ps
CPU time 1.08 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207572 kb
Host smart-f7d103ed-c36b-4583-8f8f-cb7cedfa2806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39555
90257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3955590257
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3867575664
Short name T167
Test name
Test status
Simulation time 168322060 ps
CPU time 0.85 seconds
Started Aug 10 07:00:21 PM PDT 24
Finished Aug 10 07:00:22 PM PDT 24
Peak memory 207456 kb
Host smart-6a68ff1b-9660-45b9-8dc9-2d96bdccf8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
75664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3867575664
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3977888735
Short name T1743
Test name
Test status
Simulation time 172643180 ps
CPU time 0.86 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207560 kb
Host smart-b9614c1d-6703-4e5f-9c31-909272327a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39778
88735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3977888735
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1290320872
Short name T3345
Test name
Test status
Simulation time 196831824 ps
CPU time 0.95 seconds
Started Aug 10 07:00:21 PM PDT 24
Finished Aug 10 07:00:22 PM PDT 24
Peak memory 207528 kb
Host smart-ef900cf5-66a0-4940-8a56-28cb62235668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
20872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1290320872
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2253020615
Short name T1633
Test name
Test status
Simulation time 2183998623 ps
CPU time 19.2 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:40 PM PDT 24
Peak memory 217812 kb
Host smart-3677daff-b978-4494-b58e-7eb456562687
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2253020615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2253020615
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.55621598
Short name T1560
Test name
Test status
Simulation time 181704732 ps
CPU time 0.9 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207528 kb
Host smart-8896e515-1325-4305-a446-86aa645a3cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55621
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.55621598
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2002713677
Short name T835
Test name
Test status
Simulation time 139928352 ps
CPU time 0.85 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207560 kb
Host smart-e0a2cdfc-9807-4024-989d-68d5d0fe5134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
13677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2002713677
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3022065622
Short name T1191
Test name
Test status
Simulation time 651489225 ps
CPU time 1.75 seconds
Started Aug 10 07:00:19 PM PDT 24
Finished Aug 10 07:00:21 PM PDT 24
Peak memory 207556 kb
Host smart-b8a52d92-5523-403a-86e6-3aab6fceecbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
65622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3022065622
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3610303233
Short name T1225
Test name
Test status
Simulation time 3664240679 ps
CPU time 37.4 seconds
Started Aug 10 07:00:20 PM PDT 24
Finished Aug 10 07:00:58 PM PDT 24
Peak memory 216080 kb
Host smart-d65d73e4-826b-4bfa-a4bb-61c2e4cb6843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36103
03233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3610303233
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.3016669546
Short name T3489
Test name
Test status
Simulation time 1531067328 ps
CPU time 36.63 seconds
Started Aug 10 06:59:24 PM PDT 24
Finished Aug 10 07:00:01 PM PDT 24
Peak memory 207612 kb
Host smart-38958af2-1bad-4b6e-9bc0-c9390de145c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016669546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.3016669546
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_tx_rx_disruption.941620600
Short name T589
Test name
Test status
Simulation time 461563633 ps
CPU time 1.48 seconds
Started Aug 10 07:00:21 PM PDT 24
Finished Aug 10 07:00:23 PM PDT 24
Peak memory 207532 kb
Host smart-392ea9d6-3483-4973-87b9-5c7828546820
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941620600 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.usbdev_tx_rx_disruption.941620600
Directory /workspace/1.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.36454438
Short name T2661
Test name
Test status
Simulation time 47130484 ps
CPU time 0.65 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207532 kb
Host smart-3843aa5c-0982-449c-89f6-7457ab76e650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=36454438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.36454438
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3374554399
Short name T2698
Test name
Test status
Simulation time 9849306993 ps
CPU time 14.32 seconds
Started Aug 10 07:05:45 PM PDT 24
Finished Aug 10 07:05:59 PM PDT 24
Peak memory 207872 kb
Host smart-74efde5f-37ec-48a1-88c3-e19710dd758a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374554399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3374554399
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1635438275
Short name T2516
Test name
Test status
Simulation time 16026496758 ps
CPU time 18.24 seconds
Started Aug 10 07:05:47 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 215924 kb
Host smart-47818898-58f1-4452-b7d8-946c34470ff0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635438275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1635438275
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3088906448
Short name T2057
Test name
Test status
Simulation time 30896768000 ps
CPU time 41.02 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 207748 kb
Host smart-f89bde0f-8497-4174-a9ba-8f9ff455c5ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088906448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.3088906448
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3855232532
Short name T1749
Test name
Test status
Simulation time 174226082 ps
CPU time 0.88 seconds
Started Aug 10 07:05:55 PM PDT 24
Finished Aug 10 07:05:56 PM PDT 24
Peak memory 207560 kb
Host smart-c49fdd3c-0b99-41cb-b92b-4710b30be1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38552
32532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3855232532
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3534392747
Short name T3552
Test name
Test status
Simulation time 154750027 ps
CPU time 0.89 seconds
Started Aug 10 07:05:56 PM PDT 24
Finished Aug 10 07:05:57 PM PDT 24
Peak memory 207540 kb
Host smart-af1564b8-3b5f-4bc0-8749-e873bb8d6202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35343
92747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3534392747
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2143283268
Short name T2274
Test name
Test status
Simulation time 209725518 ps
CPU time 0.97 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207596 kb
Host smart-cea67c98-6e3c-448d-8f07-473969864fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21432
83268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2143283268
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.800421428
Short name T3409
Test name
Test status
Simulation time 752993373 ps
CPU time 1.93 seconds
Started Aug 10 07:05:53 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207584 kb
Host smart-dcf616b0-1033-4dd1-88dc-1f8d8faedc0c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=800421428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.800421428
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.588111844
Short name T3037
Test name
Test status
Simulation time 17571703512 ps
CPU time 29.17 seconds
Started Aug 10 07:05:55 PM PDT 24
Finished Aug 10 07:06:25 PM PDT 24
Peak memory 207864 kb
Host smart-51b59cc2-8185-4f7c-9833-229fbfc926d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58811
1844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.588111844
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3849904196
Short name T1649
Test name
Test status
Simulation time 2282138483 ps
CPU time 14.3 seconds
Started Aug 10 07:05:53 PM PDT 24
Finished Aug 10 07:06:08 PM PDT 24
Peak memory 207744 kb
Host smart-80c7756e-9be6-485c-af15-5d0b42b53978
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849904196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3849904196
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2922324819
Short name T2140
Test name
Test status
Simulation time 778157575 ps
CPU time 1.81 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:56 PM PDT 24
Peak memory 207464 kb
Host smart-8c6eaa1f-ac10-4391-b6e8-1884c91a0e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
24819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2922324819
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1561677796
Short name T2589
Test name
Test status
Simulation time 139802363 ps
CPU time 0.84 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207728 kb
Host smart-d7087db3-e6fc-4521-ae00-ef9d006a2265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
77796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1561677796
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1503375104
Short name T2366
Test name
Test status
Simulation time 36277630 ps
CPU time 0.67 seconds
Started Aug 10 07:05:56 PM PDT 24
Finished Aug 10 07:05:56 PM PDT 24
Peak memory 207516 kb
Host smart-8ba60be9-e8de-4ef5-bdd1-27ae3206fb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15033
75104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1503375104
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2399131345
Short name T925
Test name
Test status
Simulation time 956050516 ps
CPU time 2.44 seconds
Started Aug 10 07:05:53 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207788 kb
Host smart-d1e31c20-e75c-4bd7-b67a-693959f709a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
31345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2399131345
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_types.966165140
Short name T479
Test name
Test status
Simulation time 575999436 ps
CPU time 1.45 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:56 PM PDT 24
Peak memory 207512 kb
Host smart-b68af545-b95a-47dc-9b47-c37db13c7b68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=966165140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.966165140
Directory /workspace/10.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2003723471
Short name T3320
Test name
Test status
Simulation time 149291008 ps
CPU time 1.31 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:56 PM PDT 24
Peak memory 207656 kb
Host smart-f13782e0-d89e-4fc5-b244-255440a7ebe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037
23471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2003723471
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2131445198
Short name T1753
Test name
Test status
Simulation time 200682574 ps
CPU time 0.99 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 215892 kb
Host smart-152fe55c-2a48-44c7-9a6e-7e3b1fd40c99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2131445198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2131445198
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.230131014
Short name T1176
Test name
Test status
Simulation time 140430651 ps
CPU time 0.81 seconds
Started Aug 10 07:05:53 PM PDT 24
Finished Aug 10 07:05:54 PM PDT 24
Peak memory 207496 kb
Host smart-350d49e7-2070-4bf0-8d34-d9068c0cd31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23013
1014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.230131014
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3284584815
Short name T2843
Test name
Test status
Simulation time 164163095 ps
CPU time 0.92 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207456 kb
Host smart-d6ce2779-8bb6-4a44-85c7-6e83f22d74d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32845
84815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3284584815
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2703385897
Short name T2796
Test name
Test status
Simulation time 4874134220 ps
CPU time 139.14 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:08:13 PM PDT 24
Peak memory 218520 kb
Host smart-918694ea-41da-4a5c-9405-2f8abb8fcdf7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2703385897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2703385897
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.4201930011
Short name T2194
Test name
Test status
Simulation time 12172677635 ps
CPU time 154.14 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207812 kb
Host smart-8597d237-d3d2-4d66-b98f-48686f674fb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4201930011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.4201930011
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4100453374
Short name T660
Test name
Test status
Simulation time 186971553 ps
CPU time 0.91 seconds
Started Aug 10 07:05:54 PM PDT 24
Finished Aug 10 07:05:55 PM PDT 24
Peak memory 207604 kb
Host smart-c876e193-3098-4e69-bb6a-fc00e7553caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41004
53374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4100453374
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.855184294
Short name T1416
Test name
Test status
Simulation time 34128738946 ps
CPU time 57.81 seconds
Started Aug 10 07:05:53 PM PDT 24
Finished Aug 10 07:06:51 PM PDT 24
Peak memory 207876 kb
Host smart-93e03538-9ff9-4ef5-95d4-6f94ed751be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85518
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.855184294
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2907715670
Short name T1037
Test name
Test status
Simulation time 6192186297 ps
CPU time 7.58 seconds
Started Aug 10 07:05:55 PM PDT 24
Finished Aug 10 07:06:02 PM PDT 24
Peak memory 215912 kb
Host smart-6a6164df-e715-402d-b2cb-4837d99faeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
15670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2907715670
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.1917504363
Short name T3081
Test name
Test status
Simulation time 3645324228 ps
CPU time 30.96 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 219204 kb
Host smart-4c4a4804-5eb5-40d3-a054-4877679f2c9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1917504363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.1917504363
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3797675452
Short name T3071
Test name
Test status
Simulation time 1671942122 ps
CPU time 16.19 seconds
Started Aug 10 07:06:02 PM PDT 24
Finished Aug 10 07:06:19 PM PDT 24
Peak memory 216084 kb
Host smart-f77b107a-7e29-4a98-8da5-f34ceae2b318
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3797675452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3797675452
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2815838652
Short name T1527
Test name
Test status
Simulation time 260608880 ps
CPU time 1.02 seconds
Started Aug 10 07:06:05 PM PDT 24
Finished Aug 10 07:06:06 PM PDT 24
Peak memory 207544 kb
Host smart-ebc2e54b-3446-4b5e-b7d6-3e1bf8c81ffc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2815838652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2815838652
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2598635287
Short name T955
Test name
Test status
Simulation time 192562145 ps
CPU time 0.9 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207584 kb
Host smart-0130bd31-dfe1-4dfb-b8ed-2e74ff9ba5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25986
35287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2598635287
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.878652472
Short name T832
Test name
Test status
Simulation time 2563469435 ps
CPU time 25.11 seconds
Started Aug 10 07:06:03 PM PDT 24
Finished Aug 10 07:06:28 PM PDT 24
Peak memory 224368 kb
Host smart-e550c622-bf2e-47dd-9764-c65d3605af0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87865
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.878652472
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2847381192
Short name T2488
Test name
Test status
Simulation time 2576750034 ps
CPU time 76.49 seconds
Started Aug 10 07:06:03 PM PDT 24
Finished Aug 10 07:07:19 PM PDT 24
Peak memory 224092 kb
Host smart-a49ab8c4-45cb-4c7e-a553-049dc22af437
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2847381192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2847381192
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1335908787
Short name T1881
Test name
Test status
Simulation time 2144659071 ps
CPU time 17.31 seconds
Started Aug 10 07:06:06 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 217376 kb
Host smart-3c160847-66df-4102-9e62-e147b674acb9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1335908787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1335908787
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1066790396
Short name T3302
Test name
Test status
Simulation time 161742145 ps
CPU time 0.89 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207596 kb
Host smart-7db06e5a-88fa-4ab0-8973-3b8d2c827120
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1066790396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1066790396
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.13704801
Short name T1526
Test name
Test status
Simulation time 184455072 ps
CPU time 0.88 seconds
Started Aug 10 07:06:05 PM PDT 24
Finished Aug 10 07:06:06 PM PDT 24
Peak memory 207556 kb
Host smart-b6b4c386-5f51-4d64-9bc2-dee6b07644bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.13704801
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3015934487
Short name T1428
Test name
Test status
Simulation time 161988258 ps
CPU time 0.88 seconds
Started Aug 10 07:06:03 PM PDT 24
Finished Aug 10 07:06:04 PM PDT 24
Peak memory 207504 kb
Host smart-13cb95f3-67a1-48be-b20a-05e26bd440e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
34487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3015934487
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1893470312
Short name T684
Test name
Test status
Simulation time 190798007 ps
CPU time 0.89 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207604 kb
Host smart-f78bff65-4193-476b-aba6-63d40348cb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18934
70312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1893470312
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3088108590
Short name T2544
Test name
Test status
Simulation time 186842629 ps
CPU time 0.91 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:05 PM PDT 24
Peak memory 207480 kb
Host smart-4384121a-7cbf-4d96-beb8-3386245629b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30881
08590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3088108590
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1013061763
Short name T2847
Test name
Test status
Simulation time 242220548 ps
CPU time 1.09 seconds
Started Aug 10 07:06:05 PM PDT 24
Finished Aug 10 07:06:06 PM PDT 24
Peak memory 207504 kb
Host smart-f01da576-b94b-4772-93e4-209870e05575
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1013061763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1013061763
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.325377248
Short name T1453
Test name
Test status
Simulation time 150660514 ps
CPU time 0.88 seconds
Started Aug 10 07:06:05 PM PDT 24
Finished Aug 10 07:06:06 PM PDT 24
Peak memory 207576 kb
Host smart-c32a325f-ce03-4ef0-9d60-47f30969f454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
7248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.325377248
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2128804809
Short name T2857
Test name
Test status
Simulation time 27859964 ps
CPU time 0.7 seconds
Started Aug 10 07:06:06 PM PDT 24
Finished Aug 10 07:06:07 PM PDT 24
Peak memory 207484 kb
Host smart-fcbc5224-a688-44dd-bed7-5bc7d4669540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
04809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2128804809
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2530904613
Short name T2730
Test name
Test status
Simulation time 17791211846 ps
CPU time 43.35 seconds
Started Aug 10 07:06:04 PM PDT 24
Finished Aug 10 07:06:47 PM PDT 24
Peak memory 221192 kb
Host smart-94361c28-6a01-4a4f-9c5f-4d555bf97288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
04613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2530904613
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3903506906
Short name T2312
Test name
Test status
Simulation time 210230383 ps
CPU time 0.91 seconds
Started Aug 10 07:06:03 PM PDT 24
Finished Aug 10 07:06:04 PM PDT 24
Peak memory 207576 kb
Host smart-a43d84b2-1d52-4c26-bb91-f10d029c3b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
06906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3903506906
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1366626536
Short name T549
Test name
Test status
Simulation time 190761218 ps
CPU time 0.89 seconds
Started Aug 10 07:06:11 PM PDT 24
Finished Aug 10 07:06:12 PM PDT 24
Peak memory 207536 kb
Host smart-6c85dfba-6ecb-4c35-81d4-be982376bbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13666
26536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1366626536
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.743407733
Short name T880
Test name
Test status
Simulation time 166521677 ps
CPU time 0.87 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207512 kb
Host smart-311012e7-681d-43c7-81c4-a6b8cc8aa66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74340
7733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.743407733
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.940787002
Short name T1181
Test name
Test status
Simulation time 191284981 ps
CPU time 0.89 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207536 kb
Host smart-00f1c70d-0ffe-44a5-be9e-76bc9900d209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94078
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.940787002
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_resume_link_active.2562756627
Short name T2746
Test name
Test status
Simulation time 20158751269 ps
CPU time 23.3 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 207648 kb
Host smart-e65d2e58-3a7e-4528-9a15-6529f31a536a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
56627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_resume_link_active.2562756627
Directory /workspace/10.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3713552310
Short name T1253
Test name
Test status
Simulation time 215692000 ps
CPU time 0.94 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207492 kb
Host smart-f48cada5-0efc-4bb7-b85f-0cb65655809e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37135
52310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3713552310
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.92392629
Short name T2316
Test name
Test status
Simulation time 149354610 ps
CPU time 0.79 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207512 kb
Host smart-14f8550a-1f24-4059-a86f-3f9c4812e1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92392
629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.92392629
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3734915629
Short name T1186
Test name
Test status
Simulation time 155915594 ps
CPU time 0.85 seconds
Started Aug 10 07:06:14 PM PDT 24
Finished Aug 10 07:06:15 PM PDT 24
Peak memory 207540 kb
Host smart-92e4073e-86c3-41b5-b833-d0d7c060432d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
15629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3734915629
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2998346799
Short name T3291
Test name
Test status
Simulation time 286196454 ps
CPU time 1.03 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207532 kb
Host smart-a8403ba1-70e5-40e4-8202-a43c8a678516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
46799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2998346799
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3949577964
Short name T2703
Test name
Test status
Simulation time 187105973 ps
CPU time 0.89 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:13 PM PDT 24
Peak memory 207652 kb
Host smart-cd8ff62c-ff22-40ea-b4c9-d7ed69a59319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39495
77964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3949577964
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3991414477
Short name T3356
Test name
Test status
Simulation time 253057252 ps
CPU time 1.04 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:13 PM PDT 24
Peak memory 207480 kb
Host smart-277815c2-6c66-4a19-b18b-db27a8843b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39914
14477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3991414477
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.4020595441
Short name T1395
Test name
Test status
Simulation time 2339585987 ps
CPU time 17.4 seconds
Started Aug 10 07:06:14 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 217864 kb
Host smart-9b047ce4-7228-443a-b11c-5d52ab5ce7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
95441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.4020595441
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1718288631
Short name T3174
Test name
Test status
Simulation time 1539774504 ps
CPU time 13.37 seconds
Started Aug 10 07:05:55 PM PDT 24
Finished Aug 10 07:06:08 PM PDT 24
Peak memory 207704 kb
Host smart-8b15fa5b-0709-4857-9e39-fe37cabccba2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718288631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1718288631
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_tx_rx_disruption.4123585639
Short name T2376
Test name
Test status
Simulation time 496071459 ps
CPU time 1.76 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207512 kb
Host smart-63d5d64b-fec4-4c4e-b15c-95bda4597c18
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123585639 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.usbdev_tx_rx_disruption.4123585639
Directory /workspace/10.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/100.usbdev_endpoint_types.2877462259
Short name T664
Test name
Test status
Simulation time 208524361 ps
CPU time 0.98 seconds
Started Aug 10 07:17:12 PM PDT 24
Finished Aug 10 07:17:13 PM PDT 24
Peak memory 207448 kb
Host smart-4c01d7e2-afb2-4f64-8009-c71026cf79ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2877462259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.2877462259
Directory /workspace/100.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/100.usbdev_tx_rx_disruption.2536863400
Short name T2296
Test name
Test status
Simulation time 512134832 ps
CPU time 1.49 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:10 PM PDT 24
Peak memory 207508 kb
Host smart-5d896392-e913-4d2f-8b42-76365ccd95d5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536863400 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.usbdev_tx_rx_disruption.2536863400
Directory /workspace/100.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/101.usbdev_tx_rx_disruption.3124364148
Short name T1418
Test name
Test status
Simulation time 450236602 ps
CPU time 1.5 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207556 kb
Host smart-03b7800f-9592-4d7b-8157-1cdc1834d27c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124364148 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.usbdev_tx_rx_disruption.3124364148
Directory /workspace/101.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/102.usbdev_tx_rx_disruption.291319298
Short name T79
Test name
Test status
Simulation time 530680474 ps
CPU time 1.59 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207528 kb
Host smart-3b1ee01a-5150-4856-ab6c-15ea4c1c140c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291319298 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 102.usbdev_tx_rx_disruption.291319298
Directory /workspace/102.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/103.usbdev_endpoint_types.3325332895
Short name T3233
Test name
Test status
Simulation time 232805842 ps
CPU time 0.91 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:10 PM PDT 24
Peak memory 207528 kb
Host smart-215c9007-8faa-4cd2-8074-d696784279e8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3325332895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.3325332895
Directory /workspace/103.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/103.usbdev_tx_rx_disruption.2780930458
Short name T275
Test name
Test status
Simulation time 540357827 ps
CPU time 1.66 seconds
Started Aug 10 07:17:11 PM PDT 24
Finished Aug 10 07:17:13 PM PDT 24
Peak memory 207480 kb
Host smart-e23dadd8-9d83-4251-bd2b-8f0511de333a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780930458 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.usbdev_tx_rx_disruption.2780930458
Directory /workspace/103.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/104.usbdev_endpoint_types.1740582623
Short name T483
Test name
Test status
Simulation time 294490463 ps
CPU time 1.17 seconds
Started Aug 10 07:17:12 PM PDT 24
Finished Aug 10 07:17:13 PM PDT 24
Peak memory 207448 kb
Host smart-08d355b6-887a-4bc3-810f-2a434a2a961e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1740582623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1740582623
Directory /workspace/104.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/104.usbdev_tx_rx_disruption.3955872253
Short name T731
Test name
Test status
Simulation time 454360905 ps
CPU time 1.43 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207560 kb
Host smart-65463f8a-1b73-4ca1-a425-f3165fb9b18a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955872253 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.usbdev_tx_rx_disruption.3955872253
Directory /workspace/104.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/105.usbdev_endpoint_types.2895895305
Short name T3300
Test name
Test status
Simulation time 256543412 ps
CPU time 0.96 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207516 kb
Host smart-b1a5c42a-4a92-4ab0-9b7a-899b7c85e94f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2895895305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.2895895305
Directory /workspace/105.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/105.usbdev_tx_rx_disruption.1394015816
Short name T1538
Test name
Test status
Simulation time 446342203 ps
CPU time 1.51 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207604 kb
Host smart-929192bf-976d-46a7-af99-874b56bef12b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394015816 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.usbdev_tx_rx_disruption.1394015816
Directory /workspace/105.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/106.usbdev_endpoint_types.4270591956
Short name T486
Test name
Test status
Simulation time 301193492 ps
CPU time 1.08 seconds
Started Aug 10 07:17:08 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207452 kb
Host smart-29614702-36eb-4354-a543-6a18f8270059
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4270591956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.4270591956
Directory /workspace/106.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/106.usbdev_tx_rx_disruption.650026698
Short name T3337
Test name
Test status
Simulation time 513521997 ps
CPU time 1.63 seconds
Started Aug 10 07:17:10 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207572 kb
Host smart-26ea6d0b-aa4c-4a46-b823-063d9cf807b9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650026698 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 106.usbdev_tx_rx_disruption.650026698
Directory /workspace/106.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/107.usbdev_endpoint_types.1210310349
Short name T3553
Test name
Test status
Simulation time 332629465 ps
CPU time 1.16 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207572 kb
Host smart-06a2d177-18da-4cb3-8254-99e4097f51ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1210310349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1210310349
Directory /workspace/107.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/107.usbdev_tx_rx_disruption.1470617742
Short name T3029
Test name
Test status
Simulation time 667450800 ps
CPU time 1.77 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207604 kb
Host smart-f5888dd6-4ee7-491e-9c5f-e51e3b7cef98
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470617742 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.usbdev_tx_rx_disruption.1470617742
Directory /workspace/107.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/108.usbdev_endpoint_types.3976509838
Short name T502
Test name
Test status
Simulation time 215287902 ps
CPU time 1 seconds
Started Aug 10 07:17:11 PM PDT 24
Finished Aug 10 07:17:12 PM PDT 24
Peak memory 207448 kb
Host smart-21a864ea-e746-4aad-a850-52a120284b61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3976509838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.3976509838
Directory /workspace/108.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/108.usbdev_tx_rx_disruption.1946390868
Short name T1076
Test name
Test status
Simulation time 519767347 ps
CPU time 1.6 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207404 kb
Host smart-cc714f09-8169-40f6-8aa9-5435fdf9d6b8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946390868 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.usbdev_tx_rx_disruption.1946390868
Directory /workspace/108.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/109.usbdev_endpoint_types.4245662833
Short name T3023
Test name
Test status
Simulation time 493695227 ps
CPU time 1.36 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:06 PM PDT 24
Peak memory 207524 kb
Host smart-d009dfd5-5936-4d45-a31a-da111de7bd4f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4245662833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.4245662833
Directory /workspace/109.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/109.usbdev_tx_rx_disruption.735260962
Short name T1243
Test name
Test status
Simulation time 529935906 ps
CPU time 1.63 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207420 kb
Host smart-9d01d6a3-08fa-4618-b7c3-e2ec8f03f808
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735260962 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 109.usbdev_tx_rx_disruption.735260962
Directory /workspace/109.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1658279665
Short name T2799
Test name
Test status
Simulation time 49322717 ps
CPU time 0.66 seconds
Started Aug 10 07:06:41 PM PDT 24
Finished Aug 10 07:06:42 PM PDT 24
Peak memory 207580 kb
Host smart-f91fc1fc-b58c-42d0-950b-dab3e351ecd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1658279665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1658279665
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.789174909
Short name T3055
Test name
Test status
Simulation time 7013178188 ps
CPU time 8.94 seconds
Started Aug 10 07:06:13 PM PDT 24
Finished Aug 10 07:06:22 PM PDT 24
Peak memory 216040 kb
Host smart-231f2458-eb59-4560-983a-04e99b3a497b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789174909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_ao
n_wake_disconnect.789174909
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3342939958
Short name T1914
Test name
Test status
Simulation time 13437565472 ps
CPU time 18.9 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:31 PM PDT 24
Peak memory 215872 kb
Host smart-d590a897-0cd3-4812-82da-8fd18b050f4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342939958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3342939958
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3553624686
Short name T16
Test name
Test status
Simulation time 24593470035 ps
CPU time 33.32 seconds
Started Aug 10 07:06:11 PM PDT 24
Finished Aug 10 07:06:45 PM PDT 24
Peak memory 215940 kb
Host smart-33fedefe-f027-41d0-9590-3f288a9997ec
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553624686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.3553624686
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2145791474
Short name T663
Test name
Test status
Simulation time 158457278 ps
CPU time 0.92 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:13 PM PDT 24
Peak memory 207508 kb
Host smart-239b0dcd-96ab-45ba-b2a5-82057f6388d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
91474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2145791474
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2250194941
Short name T2711
Test name
Test status
Simulation time 147597206 ps
CPU time 0.82 seconds
Started Aug 10 07:06:12 PM PDT 24
Finished Aug 10 07:06:13 PM PDT 24
Peak memory 207576 kb
Host smart-9641101a-c740-4109-8fbe-92f6d22a0a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501
94941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2250194941
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3104344749
Short name T131
Test name
Test status
Simulation time 516727357 ps
CPU time 1.77 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:06:26 PM PDT 24
Peak memory 207540 kb
Host smart-f9b34583-f9e7-4f39-9368-d57ee486fd28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31043
44749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3104344749
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1998090242
Short name T1447
Test name
Test status
Simulation time 292421517 ps
CPU time 1.08 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:06:25 PM PDT 24
Peak memory 207528 kb
Host smart-d0ca84a6-e9b4-482c-9330-08adb72c941b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1998090242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1998090242
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.3795569601
Short name T3601
Test name
Test status
Simulation time 4328642191 ps
CPU time 27.92 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:06:51 PM PDT 24
Peak memory 207684 kb
Host smart-ec4b67e2-0c8d-4c5d-ab48-7c42119c0354
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795569601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3795569601
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3046694057
Short name T2056
Test name
Test status
Simulation time 635958786 ps
CPU time 1.69 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:06:25 PM PDT 24
Peak memory 207612 kb
Host smart-5a902aac-4384-4e13-9564-aa4d3b5c38cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30466
94057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3046694057
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1373688045
Short name T1848
Test name
Test status
Simulation time 143299340 ps
CPU time 0.81 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:06:24 PM PDT 24
Peak memory 207544 kb
Host smart-7b1d007d-4c03-49d0-92bd-3a9f3f537f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
88045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1373688045
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1749717817
Short name T1108
Test name
Test status
Simulation time 31934379 ps
CPU time 0.67 seconds
Started Aug 10 07:06:21 PM PDT 24
Finished Aug 10 07:06:22 PM PDT 24
Peak memory 207460 kb
Host smart-d836f930-4dcf-46f1-9b14-6a1bfcafe32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
17817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1749717817
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2879673019
Short name T2781
Test name
Test status
Simulation time 918913936 ps
CPU time 2.37 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:06:26 PM PDT 24
Peak memory 207688 kb
Host smart-4f77b437-765f-42ca-95e7-e253c496b842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
73019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2879673019
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_types.454512505
Short name T2144
Test name
Test status
Simulation time 255634770 ps
CPU time 1.01 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 207380 kb
Host smart-47fac144-cd38-4f17-8746-1b5f4e9c4b80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=454512505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.454512505
Directory /workspace/11.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1889331717
Short name T893
Test name
Test status
Simulation time 276363639 ps
CPU time 1.93 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:06:25 PM PDT 24
Peak memory 207668 kb
Host smart-fccdc80b-306e-45f0-9531-eb49e140fa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18893
31717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1889331717
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3777021500
Short name T2223
Test name
Test status
Simulation time 220873329 ps
CPU time 1.16 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 215920 kb
Host smart-1fcab12d-bab8-4b5a-9922-7e4a45f1754b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3777021500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3777021500
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2515774616
Short name T3518
Test name
Test status
Simulation time 189984823 ps
CPU time 0.89 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:06:25 PM PDT 24
Peak memory 207572 kb
Host smart-6ab5384f-3256-4944-bb89-7e3a072bd4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157
74616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2515774616
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.788736902
Short name T2418
Test name
Test status
Simulation time 186602386 ps
CPU time 0.91 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:06:24 PM PDT 24
Peak memory 207508 kb
Host smart-f3267cba-13a0-4730-9f1b-70c36da43cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78873
6902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.788736902
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1213351917
Short name T3619
Test name
Test status
Simulation time 2927710113 ps
CPU time 81.11 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:07:44 PM PDT 24
Peak memory 224316 kb
Host smart-b736f4ec-f372-454f-ba5b-4627646deda7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1213351917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1213351917
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.4159002739
Short name T2910
Test name
Test status
Simulation time 9414607570 ps
CPU time 112.27 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:08:15 PM PDT 24
Peak memory 207768 kb
Host smart-1f5355c4-d31a-4918-992e-a4a28dc87d14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4159002739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.4159002739
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2397618224
Short name T2576
Test name
Test status
Simulation time 288701600 ps
CPU time 1.08 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 207440 kb
Host smart-6a63ffc5-7cdd-45a1-98be-2eb078a43e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
18224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2397618224
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3922851362
Short name T1949
Test name
Test status
Simulation time 4942768584 ps
CPU time 6.44 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:29 PM PDT 24
Peak memory 215976 kb
Host smart-91b42cb3-23c5-455d-81bc-9be1eca7dee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
51362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3922851362
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2892733233
Short name T844
Test name
Test status
Simulation time 8924283155 ps
CPU time 11.03 seconds
Started Aug 10 07:06:25 PM PDT 24
Finished Aug 10 07:06:36 PM PDT 24
Peak memory 207804 kb
Host smart-e4f03eef-da18-41f8-99da-cc6836845231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
33233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2892733233
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3434849669
Short name T2912
Test name
Test status
Simulation time 2557400351 ps
CPU time 25.16 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:47 PM PDT 24
Peak memory 217836 kb
Host smart-b16690ca-a196-42ac-96d4-8c107d64d4eb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3434849669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3434849669
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3332036233
Short name T1948
Test name
Test status
Simulation time 313499393 ps
CPU time 1.05 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 207592 kb
Host smart-f7943895-f7c1-4c93-9a70-8946d0069646
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3332036233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3332036233
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.691582115
Short name T3477
Test name
Test status
Simulation time 193158623 ps
CPU time 0.92 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:23 PM PDT 24
Peak memory 207568 kb
Host smart-58b69061-92e3-4d82-9b97-a9e211eb4b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69158
2115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.691582115
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.3161085862
Short name T1322
Test name
Test status
Simulation time 1793438914 ps
CPU time 13.87 seconds
Started Aug 10 07:06:22 PM PDT 24
Finished Aug 10 07:06:36 PM PDT 24
Peak memory 217240 kb
Host smart-f6adf5ee-834d-4507-b456-3a39eda8e28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
85862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.3161085862
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.867056105
Short name T1709
Test name
Test status
Simulation time 2778759538 ps
CPU time 81.33 seconds
Started Aug 10 07:06:23 PM PDT 24
Finished Aug 10 07:07:45 PM PDT 24
Peak memory 217972 kb
Host smart-0a21653d-88d4-4537-aeac-b04a60f74318
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=867056105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.867056105
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.4151679915
Short name T1964
Test name
Test status
Simulation time 2550274483 ps
CPU time 25.74 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:57 PM PDT 24
Peak memory 215980 kb
Host smart-fe66fdf3-4bda-4ad3-b5c8-df0584eb6c62
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4151679915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.4151679915
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1302525411
Short name T2613
Test name
Test status
Simulation time 149879228 ps
CPU time 0.84 seconds
Started Aug 10 07:06:33 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 207600 kb
Host smart-ececa1a7-1b46-440a-89d6-6610427cfb24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1302525411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1302525411
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1083489539
Short name T1477
Test name
Test status
Simulation time 159162402 ps
CPU time 0.85 seconds
Started Aug 10 07:06:34 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 207548 kb
Host smart-e007d681-f1d4-4648-8ca7-426b87d0dba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10834
89539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1083489539
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.380409776
Short name T137
Test name
Test status
Simulation time 226302531 ps
CPU time 1.01 seconds
Started Aug 10 07:06:34 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 207552 kb
Host smart-2e2178c4-4e3e-4cec-b018-80052f33ef4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
9776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.380409776
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1617914840
Short name T972
Test name
Test status
Simulation time 230143724 ps
CPU time 0.94 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207536 kb
Host smart-229f8ab7-55d6-4bb2-b382-7019863e396b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16179
14840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1617914840
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2734607688
Short name T2379
Test name
Test status
Simulation time 153932650 ps
CPU time 0.82 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207484 kb
Host smart-d886c6e6-13b3-4f7b-896b-2458945d13eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27346
07688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2734607688
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1512028053
Short name T1957
Test name
Test status
Simulation time 144699101 ps
CPU time 0.82 seconds
Started Aug 10 07:06:30 PM PDT 24
Finished Aug 10 07:06:30 PM PDT 24
Peak memory 207524 kb
Host smart-87883658-e31c-4e92-a857-eabdf766e033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15120
28053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1512028053
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1069376994
Short name T2691
Test name
Test status
Simulation time 167113898 ps
CPU time 0.85 seconds
Started Aug 10 07:06:33 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 207424 kb
Host smart-56a429a4-973a-4a6f-8dba-4fa92fef64fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10693
76994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1069376994
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1718106552
Short name T694
Test name
Test status
Simulation time 188889729 ps
CPU time 0.89 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207488 kb
Host smart-245b0233-8693-4dd0-872f-6813edbd4c91
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1718106552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1718106552
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1340809520
Short name T2792
Test name
Test status
Simulation time 40424007 ps
CPU time 0.68 seconds
Started Aug 10 07:06:30 PM PDT 24
Finished Aug 10 07:06:31 PM PDT 24
Peak memory 207544 kb
Host smart-59d42e2c-45f4-4a6c-8b75-bfd9a7a55350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408
09520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1340809520
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2459938074
Short name T1627
Test name
Test status
Simulation time 10431114936 ps
CPU time 25.93 seconds
Started Aug 10 07:06:34 PM PDT 24
Finished Aug 10 07:07:01 PM PDT 24
Peak memory 216000 kb
Host smart-d786a3ff-5084-435c-a030-67047750fcdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24599
38074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2459938074
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2082934640
Short name T1505
Test name
Test status
Simulation time 158230597 ps
CPU time 0.9 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207608 kb
Host smart-2333fc1f-291b-403e-944a-8aac09585bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20829
34640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2082934640
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.942392766
Short name T3207
Test name
Test status
Simulation time 237192637 ps
CPU time 1.07 seconds
Started Aug 10 07:06:33 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 207560 kb
Host smart-b1bcdf9b-1b15-4a39-93f0-ff03939266d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94239
2766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.942392766
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2680657976
Short name T1931
Test name
Test status
Simulation time 238972461 ps
CPU time 1 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207736 kb
Host smart-9873dc88-b29e-4693-a875-14c36c577761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
57976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2680657976
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.498303801
Short name T3418
Test name
Test status
Simulation time 166950970 ps
CPU time 0.88 seconds
Started Aug 10 07:06:32 PM PDT 24
Finished Aug 10 07:06:33 PM PDT 24
Peak memory 207460 kb
Host smart-2d6a3af2-7504-402b-9fc4-7f1cd260e245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49830
3801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.498303801
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_resume_link_active.2879860302
Short name T1658
Test name
Test status
Simulation time 20153839762 ps
CPU time 25.93 seconds
Started Aug 10 07:06:32 PM PDT 24
Finished Aug 10 07:06:58 PM PDT 24
Peak memory 207576 kb
Host smart-5905a209-949e-437e-984c-feef2c0e6f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
60302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_resume_link_active.2879860302
Directory /workspace/11.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.576832302
Short name T2204
Test name
Test status
Simulation time 235793990 ps
CPU time 0.96 seconds
Started Aug 10 07:06:33 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 207412 kb
Host smart-645c5d8a-9076-4d1b-abaa-90650fb5a5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57683
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.576832302
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.926984967
Short name T1654
Test name
Test status
Simulation time 145130503 ps
CPU time 0.82 seconds
Started Aug 10 07:06:32 PM PDT 24
Finished Aug 10 07:06:33 PM PDT 24
Peak memory 207520 kb
Host smart-7d170fd1-2e5a-410f-8980-56c0bde84d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92698
4967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.926984967
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2202757264
Short name T2526
Test name
Test status
Simulation time 166945463 ps
CPU time 0.94 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207604 kb
Host smart-25cb8339-8aa5-4e08-8cc4-139bc38d9572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22027
57264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2202757264
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2714395807
Short name T2448
Test name
Test status
Simulation time 228855991 ps
CPU time 1.01 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207516 kb
Host smart-8fc323a0-3f9f-4b60-b4ce-2e5511b1b0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27143
95807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2714395807
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1816030108
Short name T165
Test name
Test status
Simulation time 2432564370 ps
CPU time 68.8 seconds
Started Aug 10 07:06:34 PM PDT 24
Finished Aug 10 07:07:43 PM PDT 24
Peak memory 217996 kb
Host smart-925e62e8-ff41-4498-923a-492274cc1f9d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1816030108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1816030108
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.143345774
Short name T1766
Test name
Test status
Simulation time 179145597 ps
CPU time 0.9 seconds
Started Aug 10 07:06:31 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 207592 kb
Host smart-55383894-720b-436f-a832-a5a7c5ab0355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14334
5774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.143345774
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.104867892
Short name T2047
Test name
Test status
Simulation time 164032672 ps
CPU time 0.86 seconds
Started Aug 10 07:06:33 PM PDT 24
Finished Aug 10 07:06:34 PM PDT 24
Peak memory 207512 kb
Host smart-d7ff86ec-5a98-4c68-9667-fecdb9a3ab2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
7892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.104867892
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.437176982
Short name T3333
Test name
Test status
Simulation time 452044717 ps
CPU time 1.52 seconds
Started Aug 10 07:06:43 PM PDT 24
Finished Aug 10 07:06:44 PM PDT 24
Peak memory 207524 kb
Host smart-23b69d5b-ae64-4080-ba96-6056bd0926a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43717
6982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.437176982
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3898424169
Short name T860
Test name
Test status
Simulation time 2011576122 ps
CPU time 15.38 seconds
Started Aug 10 07:06:42 PM PDT 24
Finished Aug 10 07:06:58 PM PDT 24
Peak memory 217256 kb
Host smart-1a20f011-9fc1-4236-81c9-ded4ef3f1aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984
24169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3898424169
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.2549251008
Short name T3343
Test name
Test status
Simulation time 3444113858 ps
CPU time 32.12 seconds
Started Aug 10 07:06:24 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207892 kb
Host smart-3a64d0cc-b268-4573-9ae4-e021103daef4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549251008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.2549251008
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_tx_rx_disruption.222314597
Short name T2168
Test name
Test status
Simulation time 472941726 ps
CPU time 1.48 seconds
Started Aug 10 07:06:42 PM PDT 24
Finished Aug 10 07:06:43 PM PDT 24
Peak memory 207500 kb
Host smart-8630f55d-a65f-4fb7-bb63-29f4139d5aa8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222314597 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.usbdev_tx_rx_disruption.222314597
Directory /workspace/11.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/110.usbdev_tx_rx_disruption.2189828259
Short name T1491
Test name
Test status
Simulation time 525922112 ps
CPU time 1.53 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207588 kb
Host smart-e6783f1a-ae19-49c0-a8ef-c7d35b3f2d70
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189828259 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.usbdev_tx_rx_disruption.2189828259
Directory /workspace/110.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/111.usbdev_endpoint_types.3717462795
Short name T464
Test name
Test status
Simulation time 487086985 ps
CPU time 1.46 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:19 PM PDT 24
Peak memory 207540 kb
Host smart-9924ad7e-0f70-4e70-9115-4738e50e7f52
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3717462795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.3717462795
Directory /workspace/111.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/111.usbdev_tx_rx_disruption.1686539592
Short name T1296
Test name
Test status
Simulation time 562376394 ps
CPU time 1.48 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207560 kb
Host smart-e5b4d505-52ea-4943-99e5-9ffb0c3478a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686539592 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.usbdev_tx_rx_disruption.1686539592
Directory /workspace/111.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/112.usbdev_endpoint_types.648116477
Short name T3209
Test name
Test status
Simulation time 162183982 ps
CPU time 0.92 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207508 kb
Host smart-167a2514-2ffb-458e-85ef-ae645d570ff5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=648116477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.648116477
Directory /workspace/112.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/112.usbdev_tx_rx_disruption.3134781605
Short name T2491
Test name
Test status
Simulation time 520350265 ps
CPU time 1.62 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207460 kb
Host smart-a370146d-6bfb-42b1-8cb8-6e4f4aa6229e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134781605 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.usbdev_tx_rx_disruption.3134781605
Directory /workspace/112.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/114.usbdev_tx_rx_disruption.3036169018
Short name T865
Test name
Test status
Simulation time 487404148 ps
CPU time 1.54 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207552 kb
Host smart-d094bc4a-a2af-4f5c-8d0e-b6ae5d13940e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036169018 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.usbdev_tx_rx_disruption.3036169018
Directory /workspace/114.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/115.usbdev_endpoint_types.1660552146
Short name T394
Test name
Test status
Simulation time 749565655 ps
CPU time 1.72 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207552 kb
Host smart-377da6d7-1a93-449e-8598-05173d49fcb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1660552146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.1660552146
Directory /workspace/115.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/115.usbdev_tx_rx_disruption.977518523
Short name T1645
Test name
Test status
Simulation time 497126884 ps
CPU time 1.47 seconds
Started Aug 10 07:17:15 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207520 kb
Host smart-a72d6e25-135c-4195-acbf-a5e75bc6577a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977518523 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 115.usbdev_tx_rx_disruption.977518523
Directory /workspace/115.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/116.usbdev_endpoint_types.3312472748
Short name T497
Test name
Test status
Simulation time 252369679 ps
CPU time 1.05 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207492 kb
Host smart-7c6240bf-f1c2-4a18-98fe-a1aae8541c5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3312472748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.3312472748
Directory /workspace/116.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/116.usbdev_tx_rx_disruption.807670550
Short name T1887
Test name
Test status
Simulation time 616988049 ps
CPU time 1.59 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207500 kb
Host smart-413dcfd6-0fea-4a2b-9a22-e4f9b0075043
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807670550 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 116.usbdev_tx_rx_disruption.807670550
Directory /workspace/116.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/117.usbdev_tx_rx_disruption.1227975442
Short name T2822
Test name
Test status
Simulation time 501787826 ps
CPU time 1.74 seconds
Started Aug 10 07:17:18 PM PDT 24
Finished Aug 10 07:17:20 PM PDT 24
Peak memory 207604 kb
Host smart-ffea3da7-b390-4f24-9cb2-d5dfe087718e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227975442 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.usbdev_tx_rx_disruption.1227975442
Directory /workspace/117.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/118.usbdev_endpoint_types.1031665308
Short name T513
Test name
Test status
Simulation time 315517780 ps
CPU time 1.14 seconds
Started Aug 10 07:17:15 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207540 kb
Host smart-04f5f1f3-888e-4c5f-bb71-4c419e71d554
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1031665308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.1031665308
Directory /workspace/118.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/118.usbdev_tx_rx_disruption.3184924857
Short name T1229
Test name
Test status
Simulation time 484227438 ps
CPU time 1.51 seconds
Started Aug 10 07:17:13 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207516 kb
Host smart-233d49e1-939e-4744-8de6-9bc7a409a2c1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184924857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.usbdev_tx_rx_disruption.3184924857
Directory /workspace/118.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/119.usbdev_tx_rx_disruption.1179201973
Short name T212
Test name
Test status
Simulation time 640990750 ps
CPU time 1.74 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207580 kb
Host smart-c98a2b24-c022-423b-b549-5a425c114cce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179201973 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.usbdev_tx_rx_disruption.1179201973
Directory /workspace/119.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.600427340
Short name T3133
Test name
Test status
Simulation time 72153822 ps
CPU time 0.69 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207600 kb
Host smart-31e11ce5-9865-4e72-bda7-f0e804418cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=600427340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.600427340
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1352628255
Short name T862
Test name
Test status
Simulation time 11116438258 ps
CPU time 17.02 seconds
Started Aug 10 07:06:42 PM PDT 24
Finished Aug 10 07:06:59 PM PDT 24
Peak memory 207904 kb
Host smart-d98e4bdc-65de-4c49-addc-f22ec737f60d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352628255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.1352628255
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2998997288
Short name T1028
Test name
Test status
Simulation time 19915526584 ps
CPU time 23.52 seconds
Started Aug 10 07:06:41 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207816 kb
Host smart-565ea95b-8a15-48c6-a9ff-be6fb4528715
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998997288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2998997288
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2730944362
Short name T1840
Test name
Test status
Simulation time 31490362385 ps
CPU time 37.94 seconds
Started Aug 10 07:06:41 PM PDT 24
Finished Aug 10 07:07:20 PM PDT 24
Peak memory 207840 kb
Host smart-91b375b1-0baf-4081-b03c-9c79eec22ae4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730944362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.2730944362
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1230689132
Short name T3507
Test name
Test status
Simulation time 187673897 ps
CPU time 0.91 seconds
Started Aug 10 07:06:41 PM PDT 24
Finished Aug 10 07:06:42 PM PDT 24
Peak memory 207608 kb
Host smart-cda0a633-c545-4d1b-8e61-53aed18b1f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
89132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1230689132
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1004372132
Short name T2844
Test name
Test status
Simulation time 162794031 ps
CPU time 0.87 seconds
Started Aug 10 07:06:42 PM PDT 24
Finished Aug 10 07:06:43 PM PDT 24
Peak memory 207564 kb
Host smart-8d52fa2b-aba0-4820-b609-29f1ff8ea470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10043
72132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1004372132
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1984971259
Short name T3497
Test name
Test status
Simulation time 526025216 ps
CPU time 1.77 seconds
Started Aug 10 07:06:42 PM PDT 24
Finished Aug 10 07:06:43 PM PDT 24
Peak memory 207444 kb
Host smart-28a0e573-2d15-4e84-9ee5-9b1dcea25746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19849
71259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1984971259
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3948460942
Short name T3390
Test name
Test status
Simulation time 1040852528 ps
CPU time 2.73 seconds
Started Aug 10 07:06:43 PM PDT 24
Finished Aug 10 07:06:46 PM PDT 24
Peak memory 207652 kb
Host smart-f3a4258b-f9b0-463f-85a1-3fde453549fd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3948460942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3948460942
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1008996452
Short name T2395
Test name
Test status
Simulation time 40273256505 ps
CPU time 67.27 seconds
Started Aug 10 07:06:39 PM PDT 24
Finished Aug 10 07:07:46 PM PDT 24
Peak memory 207808 kb
Host smart-8c74397d-f166-44d1-a96c-ca20884a7fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10089
96452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1008996452
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3980539457
Short name T1276
Test name
Test status
Simulation time 2960831699 ps
CPU time 25.55 seconds
Started Aug 10 07:06:41 PM PDT 24
Finished Aug 10 07:07:07 PM PDT 24
Peak memory 207896 kb
Host smart-840ab124-f8b0-44db-b1eb-c7f79020e830
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980539457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3980539457
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4079393627
Short name T2683
Test name
Test status
Simulation time 489426267 ps
CPU time 1.42 seconds
Started Aug 10 07:06:54 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207520 kb
Host smart-fe20add7-b86c-4654-a257-afa7001a5534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
93627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4079393627
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1087625310
Short name T2877
Test name
Test status
Simulation time 152621001 ps
CPU time 0.82 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207500 kb
Host smart-0e1ef093-fef9-44f8-bd02-43b7435245ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10876
25310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1087625310
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.4030492032
Short name T629
Test name
Test status
Simulation time 58371210 ps
CPU time 0.73 seconds
Started Aug 10 07:06:54 PM PDT 24
Finished Aug 10 07:06:55 PM PDT 24
Peak memory 207488 kb
Host smart-6314938c-0725-43e9-b436-5a919397da75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40304
92032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4030492032
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.369534696
Short name T3342
Test name
Test status
Simulation time 760703188 ps
CPU time 2.3 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:55 PM PDT 24
Peak memory 207748 kb
Host smart-b96de82f-72c3-4c4a-b3f9-6c3084f40427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
4696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.369534696
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2155141890
Short name T2620
Test name
Test status
Simulation time 173646370 ps
CPU time 1.6 seconds
Started Aug 10 07:06:52 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 207580 kb
Host smart-91d5b9be-3e26-4293-9efe-7c119ab5828d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21551
41890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2155141890
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2247231098
Short name T2078
Test name
Test status
Simulation time 294922254 ps
CPU time 1.26 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:55 PM PDT 24
Peak memory 215960 kb
Host smart-3a66498f-39cf-4310-b225-d8addbabf7ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2247231098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2247231098
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1033924829
Short name T2304
Test name
Test status
Simulation time 151673582 ps
CPU time 0.82 seconds
Started Aug 10 07:06:54 PM PDT 24
Finished Aug 10 07:06:55 PM PDT 24
Peak memory 207508 kb
Host smart-0722242f-9665-4a91-9b72-e219c8c7bcc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10339
24829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1033924829
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1218585645
Short name T1469
Test name
Test status
Simulation time 222021140 ps
CPU time 0.96 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 207500 kb
Host smart-65886d7d-8e40-4b2c-a63f-c1123b0050b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185
85645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1218585645
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1242436959
Short name T1996
Test name
Test status
Simulation time 3425579573 ps
CPU time 94.79 seconds
Started Aug 10 07:06:54 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 217580 kb
Host smart-5cb12d57-46ca-4e99-81ce-39a88242c57b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1242436959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1242436959
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.3422733100
Short name T763
Test name
Test status
Simulation time 5208626649 ps
CPU time 34.35 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:07:28 PM PDT 24
Peak memory 207764 kb
Host smart-545f3db1-7603-4ac0-b39d-6b15aef42d3d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3422733100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.3422733100
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.754263427
Short name T1291
Test name
Test status
Simulation time 234892242 ps
CPU time 1.02 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 207512 kb
Host smart-a2f629c8-cfc7-48ba-83d5-02ff3f2930b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75426
3427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.754263427
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3638192923
Short name T645
Test name
Test status
Simulation time 7424249234 ps
CPU time 11.64 seconds
Started Aug 10 07:06:58 PM PDT 24
Finished Aug 10 07:07:10 PM PDT 24
Peak memory 216068 kb
Host smart-31fd1de2-f712-4d82-a640-bef758b55df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
92923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3638192923
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3405961829
Short name T2498
Test name
Test status
Simulation time 9087373349 ps
CPU time 12.76 seconds
Started Aug 10 07:06:54 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207816 kb
Host smart-c04bf9b3-40c6-42e2-94ff-8e06b9019920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34059
61829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3405961829
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2348473280
Short name T1330
Test name
Test status
Simulation time 4714341849 ps
CPU time 37.47 seconds
Started Aug 10 07:06:56 PM PDT 24
Finished Aug 10 07:07:34 PM PDT 24
Peak memory 224204 kb
Host smart-b304ae33-26a5-46dc-8cd5-2ab7fdfbc9c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2348473280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2348473280
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.584907177
Short name T1246
Test name
Test status
Simulation time 3210612000 ps
CPU time 23.83 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 216084 kb
Host smart-8646e946-a955-4183-8c53-50bcb99056cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=584907177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.584907177
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.2315881950
Short name T2769
Test name
Test status
Simulation time 271232149 ps
CPU time 1.08 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207544 kb
Host smart-9d73cfd4-e231-4f8d-8022-f997af4b70d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2315881950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2315881950
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4193468737
Short name T1899
Test name
Test status
Simulation time 199727882 ps
CPU time 0.96 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207532 kb
Host smart-fbc0db62-3162-4971-9503-3d5b7f6c70bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
68737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4193468737
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.55454288
Short name T3491
Test name
Test status
Simulation time 2626262644 ps
CPU time 78.64 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:08:14 PM PDT 24
Peak memory 216028 kb
Host smart-72520413-def1-4967-8f2d-b806acba14e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55454
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.55454288
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4028026227
Short name T943
Test name
Test status
Simulation time 1607702842 ps
CPU time 12.16 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:07:07 PM PDT 24
Peak memory 224168 kb
Host smart-4a2b062e-fa50-4918-b3dc-8a7595b582a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4028026227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4028026227
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.785664580
Short name T2546
Test name
Test status
Simulation time 3787645107 ps
CPU time 30.31 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:07:23 PM PDT 24
Peak memory 216164 kb
Host smart-6aec810c-d7cd-4c65-bca0-931f0ed7cf07
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=785664580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.785664580
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.240235804
Short name T2697
Test name
Test status
Simulation time 166584922 ps
CPU time 0.88 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207600 kb
Host smart-9d574595-7eb3-4b00-bf90-93d173bf1544
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=240235804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.240235804
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2150041847
Short name T1811
Test name
Test status
Simulation time 140257221 ps
CPU time 0.8 seconds
Started Aug 10 07:06:52 PM PDT 24
Finished Aug 10 07:06:53 PM PDT 24
Peak memory 207580 kb
Host smart-9142cfae-7aa9-45ce-9916-f780266ab92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
41847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2150041847
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1650117251
Short name T661
Test name
Test status
Simulation time 141145525 ps
CPU time 0.85 seconds
Started Aug 10 07:06:55 PM PDT 24
Finished Aug 10 07:06:56 PM PDT 24
Peak memory 207468 kb
Host smart-7f6c382b-8d80-49b9-af93-2e71f4bae243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16501
17251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1650117251
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.453369259
Short name T1442
Test name
Test status
Simulation time 189648320 ps
CPU time 0.92 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 207604 kb
Host smart-d2c20222-0f2d-439a-b702-f804ca532054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45336
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.453369259
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1982694427
Short name T2760
Test name
Test status
Simulation time 143030184 ps
CPU time 0.84 seconds
Started Aug 10 07:06:53 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 207576 kb
Host smart-e1ba62d1-32b8-49c5-9000-d5b15286ad87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19826
94427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1982694427
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.637592267
Short name T2206
Test name
Test status
Simulation time 148817756 ps
CPU time 0.83 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207588 kb
Host smart-3149fd6f-53ac-4157-a654-16519954ff3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63759
2267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.637592267
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.4246761150
Short name T956
Test name
Test status
Simulation time 210476437 ps
CPU time 1 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207544 kb
Host smart-30763294-96a4-4a9b-a820-a0e59f2326c1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4246761150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.4246761150
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2624942825
Short name T238
Test name
Test status
Simulation time 148439298 ps
CPU time 0.85 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207504 kb
Host smart-ab8e335c-f9be-4fe1-ad6d-d32be05c1fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26249
42825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2624942825
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4084244130
Short name T38
Test name
Test status
Simulation time 34018541 ps
CPU time 0.72 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207516 kb
Host smart-faf008fe-c0ab-4927-8ddc-9a7efc5ab15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
44130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4084244130
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3580095645
Short name T340
Test name
Test status
Simulation time 14772873332 ps
CPU time 36.58 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:45 PM PDT 24
Peak memory 216184 kb
Host smart-6fe0adec-7399-4303-94d9-6c06f26d17b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35800
95645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3580095645
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1521244220
Short name T837
Test name
Test status
Simulation time 162803936 ps
CPU time 0.88 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207568 kb
Host smart-bc7434ac-50d3-4f56-a144-2cf3499f27ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
44220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1521244220
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.709200966
Short name T1938
Test name
Test status
Simulation time 248948575 ps
CPU time 1.06 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207548 kb
Host smart-69f173bb-b199-4c27-b5ad-504a0a2ba2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70920
0966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.709200966
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.75418477
Short name T2231
Test name
Test status
Simulation time 188315821 ps
CPU time 0.92 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207588 kb
Host smart-c4962da0-6c39-4a94-9815-e63a39d37a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75418
477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.75418477
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.2375935594
Short name T1636
Test name
Test status
Simulation time 195924467 ps
CPU time 0.99 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207532 kb
Host smart-6beadf78-56b3-44e8-8565-81ee473885b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
35594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.2375935594
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_resume_link_active.3659076006
Short name T102
Test name
Test status
Simulation time 20156621643 ps
CPU time 24.64 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:31 PM PDT 24
Peak memory 207684 kb
Host smart-341ad763-4567-422f-bb67-e4429903cea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36590
76006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_resume_link_active.3659076006
Directory /workspace/12.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.335374935
Short name T788
Test name
Test status
Simulation time 202100110 ps
CPU time 0.87 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207500 kb
Host smart-c1c5aa71-0ac5-488b-8204-abeda164e8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33537
4935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.335374935
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_rx_full.1016150082
Short name T2080
Test name
Test status
Simulation time 383603817 ps
CPU time 1.29 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207452 kb
Host smart-5cdc6460-e954-476a-9831-712c8356c6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10161
50082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1016150082
Directory /workspace/12.usbdev_rx_full/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.589530025
Short name T2181
Test name
Test status
Simulation time 153585868 ps
CPU time 0.8 seconds
Started Aug 10 07:07:03 PM PDT 24
Finished Aug 10 07:07:04 PM PDT 24
Peak memory 207492 kb
Host smart-02584ef1-b3ad-47c4-8156-bee7685297cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58953
0025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.589530025
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3446177121
Short name T2358
Test name
Test status
Simulation time 161946940 ps
CPU time 0.88 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207644 kb
Host smart-99d099ad-b313-4593-93ae-423a581a9b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34461
77121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3446177121
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2379305775
Short name T772
Test name
Test status
Simulation time 212184595 ps
CPU time 0.98 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:07 PM PDT 24
Peak memory 207584 kb
Host smart-f2484490-4da4-4c8e-9be1-33d0b71be25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
05775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2379305775
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3110637044
Short name T874
Test name
Test status
Simulation time 2133321497 ps
CPU time 20.19 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:24 PM PDT 24
Peak memory 223996 kb
Host smart-2bb52c8f-fcc7-404d-80b8-3cc5b0598d2b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3110637044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3110637044
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3458041121
Short name T21
Test name
Test status
Simulation time 137353322 ps
CPU time 0.82 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207596 kb
Host smart-9b62a0e4-ddd1-4103-9281-ff09520ee437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34580
41121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3458041121
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3433261469
Short name T793
Test name
Test status
Simulation time 168642162 ps
CPU time 0.88 seconds
Started Aug 10 07:07:03 PM PDT 24
Finished Aug 10 07:07:04 PM PDT 24
Peak memory 207556 kb
Host smart-6206bc6f-093e-4980-b291-6c7767141265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34332
61469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3433261469
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.4014383037
Short name T3090
Test name
Test status
Simulation time 1284143964 ps
CPU time 3.26 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207696 kb
Host smart-ad8293f9-22be-4d56-94e0-27579188a3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40143
83037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.4014383037
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2472939850
Short name T1885
Test name
Test status
Simulation time 3058701703 ps
CPU time 92.65 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:08:36 PM PDT 24
Peak memory 216064 kb
Host smart-7934ac39-fec8-4792-beb3-158625b1c2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24729
39850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2472939850
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.2564069430
Short name T3041
Test name
Test status
Simulation time 1285728615 ps
CPU time 29.78 seconds
Started Aug 10 07:06:40 PM PDT 24
Finished Aug 10 07:07:10 PM PDT 24
Peak memory 207764 kb
Host smart-46fdc6ce-91b9-4b8e-a292-7a0d3632600a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564069430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.2564069430
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_tx_rx_disruption.3949603361
Short name T1448
Test name
Test status
Simulation time 571545340 ps
CPU time 1.78 seconds
Started Aug 10 07:07:03 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207420 kb
Host smart-60b01e32-4282-453f-b626-0a61a3c56f28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949603361 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.usbdev_tx_rx_disruption.3949603361
Directory /workspace/12.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/120.usbdev_endpoint_types.2873584319
Short name T388
Test name
Test status
Simulation time 701738925 ps
CPU time 1.57 seconds
Started Aug 10 07:17:17 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207544 kb
Host smart-cca7b55b-a9ca-430d-afc8-afb3ba2a04e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2873584319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.2873584319
Directory /workspace/120.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/120.usbdev_tx_rx_disruption.4134810020
Short name T1877
Test name
Test status
Simulation time 549572538 ps
CPU time 1.55 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207516 kb
Host smart-1c13cd8e-b89b-4508-9018-2b28cbabee61
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134810020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.usbdev_tx_rx_disruption.4134810020
Directory /workspace/120.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/121.usbdev_endpoint_types.3276089081
Short name T472
Test name
Test status
Simulation time 556389987 ps
CPU time 1.57 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207504 kb
Host smart-295e47b5-af76-4de0-b60b-c9b2be32681d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3276089081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.3276089081
Directory /workspace/121.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/121.usbdev_tx_rx_disruption.1108801844
Short name T1562
Test name
Test status
Simulation time 607824059 ps
CPU time 1.7 seconds
Started Aug 10 07:17:15 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207776 kb
Host smart-2023a68a-d301-4c06-89ad-94f25288f85b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108801844 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.usbdev_tx_rx_disruption.1108801844
Directory /workspace/121.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/122.usbdev_tx_rx_disruption.1819182595
Short name T1784
Test name
Test status
Simulation time 574968572 ps
CPU time 1.49 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207584 kb
Host smart-339b687b-69e7-45ee-93e4-85f8adaf3ed3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819182595 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.usbdev_tx_rx_disruption.1819182595
Directory /workspace/122.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/123.usbdev_tx_rx_disruption.2220592495
Short name T1969
Test name
Test status
Simulation time 550887925 ps
CPU time 1.63 seconds
Started Aug 10 07:17:13 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207492 kb
Host smart-3ef1ec55-298b-4716-a109-ae801e755bd6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220592495 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.usbdev_tx_rx_disruption.2220592495
Directory /workspace/123.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/124.usbdev_tx_rx_disruption.3816532001
Short name T276
Test name
Test status
Simulation time 525794344 ps
CPU time 1.69 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207604 kb
Host smart-d11b0c85-8dcb-4427-b00b-24a4d9233075
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816532001 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.usbdev_tx_rx_disruption.3816532001
Directory /workspace/124.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/125.usbdev_endpoint_types.3777907884
Short name T1922
Test name
Test status
Simulation time 299943280 ps
CPU time 1.06 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207528 kb
Host smart-6c9dd49d-a614-4d50-a937-db1d8bf46b3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3777907884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.3777907884
Directory /workspace/125.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/125.usbdev_tx_rx_disruption.3334862397
Short name T639
Test name
Test status
Simulation time 654831095 ps
CPU time 1.76 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:18 PM PDT 24
Peak memory 207556 kb
Host smart-cd8eb668-9de8-4f58-bfb2-1ca9f2b31369
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334862397 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.usbdev_tx_rx_disruption.3334862397
Directory /workspace/125.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/126.usbdev_tx_rx_disruption.957947211
Short name T185
Test name
Test status
Simulation time 578935849 ps
CPU time 1.59 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207520 kb
Host smart-8f82aabd-e076-420c-8fe8-cb6b85c54974
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957947211 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 126.usbdev_tx_rx_disruption.957947211
Directory /workspace/126.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/127.usbdev_endpoint_types.3088670771
Short name T498
Test name
Test status
Simulation time 181229915 ps
CPU time 0.92 seconds
Started Aug 10 07:17:16 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207552 kb
Host smart-f356f3e3-94d1-4b1f-b049-46a481d0dba7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3088670771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.3088670771
Directory /workspace/127.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/127.usbdev_tx_rx_disruption.796835424
Short name T3135
Test name
Test status
Simulation time 528100566 ps
CPU time 1.56 seconds
Started Aug 10 07:17:15 PM PDT 24
Finished Aug 10 07:17:17 PM PDT 24
Peak memory 207564 kb
Host smart-330d1b4a-82cb-4de9-b56e-aaf30a69790e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796835424 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 127.usbdev_tx_rx_disruption.796835424
Directory /workspace/127.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/128.usbdev_tx_rx_disruption.2236847855
Short name T2256
Test name
Test status
Simulation time 593213809 ps
CPU time 1.72 seconds
Started Aug 10 07:17:14 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 207604 kb
Host smart-d115cf9f-d93e-4233-b7f9-561873a61d37
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236847855 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.usbdev_tx_rx_disruption.2236847855
Directory /workspace/128.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/129.usbdev_endpoint_types.3737462039
Short name T1160
Test name
Test status
Simulation time 165375540 ps
CPU time 0.87 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207344 kb
Host smart-e1a9ed0e-58d2-4b77-84af-6b4f09698c15
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3737462039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.3737462039
Directory /workspace/129.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/129.usbdev_tx_rx_disruption.3587303713
Short name T1404
Test name
Test status
Simulation time 565026226 ps
CPU time 1.82 seconds
Started Aug 10 07:17:28 PM PDT 24
Finished Aug 10 07:17:30 PM PDT 24
Peak memory 207548 kb
Host smart-72f80566-e753-47b5-a2a7-a338372f6d0b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587303713 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.usbdev_tx_rx_disruption.3587303713
Directory /workspace/129.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.3777677774
Short name T3305
Test name
Test status
Simulation time 44204874 ps
CPU time 0.67 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:25 PM PDT 24
Peak memory 207500 kb
Host smart-8e3e41ab-76e2-488b-9a5b-e1e5369fb095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3777677774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.3777677774
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.499594776
Short name T2124
Test name
Test status
Simulation time 11992475630 ps
CPU time 15.22 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:21 PM PDT 24
Peak memory 207816 kb
Host smart-f2585d0e-f48e-4b51-8dad-c013820a8a26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499594776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_disconnect.499594776
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1398320466
Short name T899
Test name
Test status
Simulation time 18571641656 ps
CPU time 20.76 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:25 PM PDT 24
Peak memory 207816 kb
Host smart-bafc3d08-115d-4989-af4e-82820fb58cb5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398320466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1398320466
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.860245611
Short name T2752
Test name
Test status
Simulation time 29433887982 ps
CPU time 35.29 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:40 PM PDT 24
Peak memory 207872 kb
Host smart-fae1c677-419d-4250-a42d-b3307d2132cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860245611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_ao
n_wake_resume.860245611
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3826711482
Short name T3350
Test name
Test status
Simulation time 162843976 ps
CPU time 0.85 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:05 PM PDT 24
Peak memory 207564 kb
Host smart-90a8e641-4e1e-4346-ad52-3814f3499943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267
11482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3826711482
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2280703615
Short name T3427
Test name
Test status
Simulation time 149181064 ps
CPU time 0.83 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207612 kb
Host smart-e5d678af-dffd-49dc-aca0-ed6c31e11d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22807
03615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2280703615
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3840038158
Short name T3403
Test name
Test status
Simulation time 222478182 ps
CPU time 1.02 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:07 PM PDT 24
Peak memory 207508 kb
Host smart-160d90df-00ca-4f27-9b32-764785c08087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38400
38158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3840038158
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1005743789
Short name T1272
Test name
Test status
Simulation time 572495224 ps
CPU time 1.62 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207568 kb
Host smart-434fe808-66e8-49f1-9fb4-f17d0966d1a7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1005743789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1005743789
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3412805222
Short name T2759
Test name
Test status
Simulation time 43961478101 ps
CPU time 70.79 seconds
Started Aug 10 07:07:04 PM PDT 24
Finished Aug 10 07:08:14 PM PDT 24
Peak memory 207716 kb
Host smart-256a6f90-3752-4fe4-bbd6-e111660d82ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
05222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3412805222
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.3050985114
Short name T2694
Test name
Test status
Simulation time 1294821600 ps
CPU time 28.05 seconds
Started Aug 10 07:07:08 PM PDT 24
Finished Aug 10 07:07:36 PM PDT 24
Peak memory 207820 kb
Host smart-2d21ca22-7883-4814-9c77-16c020bdd321
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050985114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.3050985114
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1067895040
Short name T2040
Test name
Test status
Simulation time 728568907 ps
CPU time 1.82 seconds
Started Aug 10 07:07:07 PM PDT 24
Finished Aug 10 07:07:09 PM PDT 24
Peak memory 207492 kb
Host smart-af90cf93-81dd-410c-92d1-76c869ca719b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
95040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1067895040
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1384644655
Short name T44
Test name
Test status
Simulation time 153479582 ps
CPU time 0.82 seconds
Started Aug 10 07:07:05 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207472 kb
Host smart-eb570595-a186-4788-affb-d3b81df40005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
44655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1384644655
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2998421011
Short name T1644
Test name
Test status
Simulation time 38697704 ps
CPU time 0.7 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:06 PM PDT 24
Peak memory 207508 kb
Host smart-ded64d35-a0d3-4359-adc1-2397fd58e8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29984
21011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2998421011
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.941127223
Short name T2537
Test name
Test status
Simulation time 960693668 ps
CPU time 2.53 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207752 kb
Host smart-a288a7f1-e6ac-4210-8cb1-606482d8f423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94112
7223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.941127223
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_types.989700872
Short name T491
Test name
Test status
Simulation time 442015046 ps
CPU time 1.31 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 207428 kb
Host smart-4ec8752f-609d-45d8-b057-569eb11430de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=989700872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.989700872
Directory /workspace/13.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2503883326
Short name T816
Test name
Test status
Simulation time 272806592 ps
CPU time 2.23 seconds
Started Aug 10 07:07:16 PM PDT 24
Finished Aug 10 07:07:18 PM PDT 24
Peak memory 207604 kb
Host smart-936e5e2e-8580-4dba-b6af-8f0fc483cf1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25038
83326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2503883326
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.47402964
Short name T3016
Test name
Test status
Simulation time 268405101 ps
CPU time 1.16 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 216120 kb
Host smart-1041f05e-20b5-444c-840c-95dc72674a7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=47402964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.47402964
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.218023919
Short name T1382
Test name
Test status
Simulation time 152354423 ps
CPU time 0.86 seconds
Started Aug 10 07:07:13 PM PDT 24
Finished Aug 10 07:07:14 PM PDT 24
Peak memory 207560 kb
Host smart-246ab456-f6ab-4307-8bfa-755a9b9cd641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21802
3919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.218023919
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3872630730
Short name T3546
Test name
Test status
Simulation time 226809220 ps
CPU time 0.98 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207528 kb
Host smart-3e210cbb-af2d-4bd7-a064-0694650453d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38726
30730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3872630730
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.4228422318
Short name T1812
Test name
Test status
Simulation time 3265166663 ps
CPU time 33.84 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:48 PM PDT 24
Peak memory 224284 kb
Host smart-bdb4ee2f-22db-45f6-a7d2-d7b64f06156b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4228422318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.4228422318
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.4045243709
Short name T2031
Test name
Test status
Simulation time 9053491071 ps
CPU time 107.6 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:09:03 PM PDT 24
Peak memory 207828 kb
Host smart-9a2c988c-6dfe-48b9-a58b-c516244085fa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4045243709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.4045243709
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2477429307
Short name T2833
Test name
Test status
Simulation time 191107719 ps
CPU time 0.93 seconds
Started Aug 10 07:07:18 PM PDT 24
Finished Aug 10 07:07:19 PM PDT 24
Peak memory 207520 kb
Host smart-6ee42656-66c4-4f15-ac15-9d5a81d8e420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24774
29307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2477429307
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.343957448
Short name T3594
Test name
Test status
Simulation time 27226336783 ps
CPU time 48.42 seconds
Started Aug 10 07:07:16 PM PDT 24
Finished Aug 10 07:08:05 PM PDT 24
Peak memory 216084 kb
Host smart-9c0b2ea6-f22e-48d3-83ce-815bc845161f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34395
7448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.343957448
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.272083076
Short name T3424
Test name
Test status
Simulation time 10010766391 ps
CPU time 12.75 seconds
Started Aug 10 07:07:12 PM PDT 24
Finished Aug 10 07:07:25 PM PDT 24
Peak memory 207844 kb
Host smart-82fb828c-7bfc-484a-9c33-7c158d304846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27208
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.272083076
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.317112330
Short name T2695
Test name
Test status
Simulation time 3896469269 ps
CPU time 114.85 seconds
Started Aug 10 07:07:16 PM PDT 24
Finished Aug 10 07:09:11 PM PDT 24
Peak memory 216024 kb
Host smart-2634d4df-488f-4d31-b693-7de29267173b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=317112330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.317112330
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.717356703
Short name T2116
Test name
Test status
Simulation time 4331546240 ps
CPU time 46.12 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 217532 kb
Host smart-41d01f8f-2fcc-4d86-85e8-49ab93a5613c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=717356703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.717356703
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.547073348
Short name T1437
Test name
Test status
Simulation time 288740751 ps
CPU time 0.99 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 207536 kb
Host smart-2c1a6179-8aa5-4db0-8712-67e1fa075a56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=547073348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.547073348
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.732816984
Short name T692
Test name
Test status
Simulation time 202109258 ps
CPU time 1.02 seconds
Started Aug 10 07:07:17 PM PDT 24
Finished Aug 10 07:07:18 PM PDT 24
Peak memory 207588 kb
Host smart-b92c03f7-e061-4ba9-a6ee-95a424aa2077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73281
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.732816984
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.2441437213
Short name T2437
Test name
Test status
Simulation time 1821911102 ps
CPU time 49.2 seconds
Started Aug 10 07:07:19 PM PDT 24
Finished Aug 10 07:08:08 PM PDT 24
Peak memory 224076 kb
Host smart-68da6cb3-3566-441c-8c5f-87ba456cb7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24414
37213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.2441437213
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.668369039
Short name T2380
Test name
Test status
Simulation time 2710216740 ps
CPU time 78.29 seconds
Started Aug 10 07:07:13 PM PDT 24
Finished Aug 10 07:08:32 PM PDT 24
Peak memory 217880 kb
Host smart-a4d91c06-22ee-40f0-8b28-b82707bc9ed1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=668369039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.668369039
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3461870785
Short name T1723
Test name
Test status
Simulation time 2554751844 ps
CPU time 25.75 seconds
Started Aug 10 07:07:19 PM PDT 24
Finished Aug 10 07:07:45 PM PDT 24
Peak memory 216080 kb
Host smart-ec166644-8aab-43f8-b5ac-15b923bbce93
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3461870785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3461870785
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.1906677555
Short name T3161
Test name
Test status
Simulation time 153641118 ps
CPU time 0.87 seconds
Started Aug 10 07:07:16 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 207556 kb
Host smart-19d7dea5-9461-4217-85cb-75cce41c1c1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1906677555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.1906677555
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.722444524
Short name T312
Test name
Test status
Simulation time 153906402 ps
CPU time 0.87 seconds
Started Aug 10 07:07:16 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 207464 kb
Host smart-c0522cc9-f765-4c32-84d0-abae9e69fba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72244
4524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.722444524
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1099506401
Short name T2123
Test name
Test status
Simulation time 186097747 ps
CPU time 0.93 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:15 PM PDT 24
Peak memory 207608 kb
Host smart-59039816-78a8-4ba4-a73d-0f96522ef7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
06401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1099506401
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1952024982
Short name T673
Test name
Test status
Simulation time 175013583 ps
CPU time 0.83 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207412 kb
Host smart-998fc82f-37b3-414a-8fe2-8e5f79b4f660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
24982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1952024982
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.589169434
Short name T3586
Test name
Test status
Simulation time 154734828 ps
CPU time 0.83 seconds
Started Aug 10 07:07:19 PM PDT 24
Finished Aug 10 07:07:20 PM PDT 24
Peak memory 207516 kb
Host smart-209719d4-ad7c-4061-9393-73786564ca40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58916
9434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.589169434
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2525977213
Short name T3267
Test name
Test status
Simulation time 157890640 ps
CPU time 0.82 seconds
Started Aug 10 07:07:13 PM PDT 24
Finished Aug 10 07:07:14 PM PDT 24
Peak memory 207560 kb
Host smart-416af1b0-df49-4eff-a299-7a76c79e37d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
77213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2525977213
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2884350875
Short name T3227
Test name
Test status
Simulation time 184868570 ps
CPU time 0.94 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:15 PM PDT 24
Peak memory 207556 kb
Host smart-fdc66216-30c6-4cf7-a075-62c1f21ef9a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2884350875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2884350875
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1812065745
Short name T1793
Test name
Test status
Simulation time 143499921 ps
CPU time 0.81 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207516 kb
Host smart-ca1f19e1-c026-4476-8dcd-edd76a257fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18120
65745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1812065745
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3822134403
Short name T1510
Test name
Test status
Simulation time 62111796 ps
CPU time 0.73 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207480 kb
Host smart-5f96f853-277d-4886-839d-be232d83df73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
34403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3822134403
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1786879695
Short name T2944
Test name
Test status
Simulation time 19033945151 ps
CPU time 49.87 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:08:04 PM PDT 24
Peak memory 216136 kb
Host smart-4fc6f67c-0b41-4e69-8804-81c4d6dd978a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
79695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1786879695
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2360457626
Short name T2786
Test name
Test status
Simulation time 200775825 ps
CPU time 0.91 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:15 PM PDT 24
Peak memory 207476 kb
Host smart-49c9b43e-fea9-4fb7-b63a-0df57cd908d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23604
57626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2360457626
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.608356621
Short name T3293
Test name
Test status
Simulation time 187076045 ps
CPU time 0.95 seconds
Started Aug 10 07:07:17 PM PDT 24
Finished Aug 10 07:07:18 PM PDT 24
Peak memory 207588 kb
Host smart-d29be2a9-6684-4306-9ab2-0863394bedce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60835
6621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.608356621
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3576078168
Short name T2674
Test name
Test status
Simulation time 188215181 ps
CPU time 0.96 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:17 PM PDT 24
Peak memory 207420 kb
Host smart-fc94d48e-e393-42f4-8aab-326c1a40e1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35760
78168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3576078168
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_resume_link_active.4053427938
Short name T2179
Test name
Test status
Simulation time 20167858077 ps
CPU time 25.68 seconds
Started Aug 10 07:07:14 PM PDT 24
Finished Aug 10 07:07:40 PM PDT 24
Peak memory 207644 kb
Host smart-6b0f9013-ed10-4b6f-8a19-7c8aa754252d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40534
27938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_resume_link_active.4053427938
Directory /workspace/13.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.13324436
Short name T1746
Test name
Test status
Simulation time 141121138 ps
CPU time 0.82 seconds
Started Aug 10 07:07:13 PM PDT 24
Finished Aug 10 07:07:14 PM PDT 24
Peak memory 207528 kb
Host smart-73576223-dac3-4c88-a699-3f07abebf183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13324
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.13324436
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_rx_full.2996481904
Short name T1104
Test name
Test status
Simulation time 378907392 ps
CPU time 1.24 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207416 kb
Host smart-57395c03-db5e-4ad1-a464-b3cac4d9eb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964
81904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2996481904
Directory /workspace/13.usbdev_rx_full/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.741654374
Short name T623
Test name
Test status
Simulation time 168335092 ps
CPU time 0.81 seconds
Started Aug 10 07:07:15 PM PDT 24
Finished Aug 10 07:07:16 PM PDT 24
Peak memory 207476 kb
Host smart-8a01f15c-f50d-4aff-81f9-3f0f9a2bb11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74165
4374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.741654374
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.602114594
Short name T3027
Test name
Test status
Simulation time 210359349 ps
CPU time 0.93 seconds
Started Aug 10 07:07:13 PM PDT 24
Finished Aug 10 07:07:14 PM PDT 24
Peak memory 207604 kb
Host smart-f0b46e15-c980-41a5-bf38-2205b68f3f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60211
4594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.602114594
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1724412926
Short name T2239
Test name
Test status
Simulation time 218544805 ps
CPU time 1.03 seconds
Started Aug 10 07:07:27 PM PDT 24
Finished Aug 10 07:07:29 PM PDT 24
Peak memory 207284 kb
Host smart-5b070b19-90dc-4f39-8f4c-a224247ee7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
12926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1724412926
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.841522168
Short name T3385
Test name
Test status
Simulation time 2088015876 ps
CPU time 16.08 seconds
Started Aug 10 07:07:27 PM PDT 24
Finished Aug 10 07:07:44 PM PDT 24
Peak memory 223760 kb
Host smart-7d040f68-78de-4935-8e84-59339b142134
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=841522168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.841522168
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4066419536
Short name T509
Test name
Test status
Simulation time 172242225 ps
CPU time 0.89 seconds
Started Aug 10 07:07:26 PM PDT 24
Finished Aug 10 07:07:27 PM PDT 24
Peak memory 207444 kb
Host smart-685b985e-c45a-4ea4-bc35-766c4c6e37b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
19536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4066419536
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.815373294
Short name T1282
Test name
Test status
Simulation time 142096322 ps
CPU time 0.84 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:26 PM PDT 24
Peak memory 207560 kb
Host smart-51770ea7-4732-44ce-8cac-375ce543a4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81537
3294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.815373294
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2998398225
Short name T2030
Test name
Test status
Simulation time 486868106 ps
CPU time 1.46 seconds
Started Aug 10 07:07:27 PM PDT 24
Finished Aug 10 07:07:28 PM PDT 24
Peak memory 207388 kb
Host smart-a91aa077-ac2f-4e9f-ae00-65c0475756c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
98225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2998398225
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2163109881
Short name T1213
Test name
Test status
Simulation time 2321520495 ps
CPU time 63.72 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 216112 kb
Host smart-ff1921b1-5c5d-440d-baa6-07993086d019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
09881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2163109881
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.3504736506
Short name T1388
Test name
Test status
Simulation time 5179879442 ps
CPU time 45.59 seconds
Started Aug 10 07:07:06 PM PDT 24
Finished Aug 10 07:07:51 PM PDT 24
Peak memory 207752 kb
Host smart-f2fef056-d24d-43a0-b075-b73c06d34f7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504736506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.3504736506
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_tx_rx_disruption.1895353467
Short name T1819
Test name
Test status
Simulation time 444414546 ps
CPU time 1.43 seconds
Started Aug 10 07:07:24 PM PDT 24
Finished Aug 10 07:07:26 PM PDT 24
Peak memory 207568 kb
Host smart-e48af06c-ba2b-4bd8-a143-cade1c287357
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895353467 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.usbdev_tx_rx_disruption.1895353467
Directory /workspace/13.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/130.usbdev_endpoint_types.2155020663
Short name T450
Test name
Test status
Simulation time 409507916 ps
CPU time 1.16 seconds
Started Aug 10 07:17:23 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207564 kb
Host smart-1f68065a-95b2-4578-82d6-6f92d6816b94
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2155020663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.2155020663
Directory /workspace/130.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/130.usbdev_tx_rx_disruption.4116688886
Short name T1091
Test name
Test status
Simulation time 493070487 ps
CPU time 1.53 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207560 kb
Host smart-40fd55b9-3fdc-4e5a-bf2b-f507498e313f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116688886 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.usbdev_tx_rx_disruption.4116688886
Directory /workspace/130.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/131.usbdev_tx_rx_disruption.626913387
Short name T2684
Test name
Test status
Simulation time 532323640 ps
CPU time 1.7 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207528 kb
Host smart-4f6176e6-9ddc-4187-9a0d-8008e8ba2150
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626913387 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 131.usbdev_tx_rx_disruption.626913387
Directory /workspace/131.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/132.usbdev_endpoint_types.3060666982
Short name T471
Test name
Test status
Simulation time 226665434 ps
CPU time 1.09 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207540 kb
Host smart-65a26f3a-7efb-44ff-9a6f-04bc41e6c8da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3060666982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3060666982
Directory /workspace/132.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/132.usbdev_tx_rx_disruption.2920891019
Short name T2336
Test name
Test status
Simulation time 495484369 ps
CPU time 1.48 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207572 kb
Host smart-6c101a88-8d64-4066-b222-965002873958
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920891019 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.usbdev_tx_rx_disruption.2920891019
Directory /workspace/132.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/133.usbdev_endpoint_types.19496992
Short name T481
Test name
Test status
Simulation time 303116656 ps
CPU time 1.06 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207572 kb
Host smart-1f65dfe1-75d8-4fd6-97f4-c3ef3c5f79d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=19496992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.19496992
Directory /workspace/133.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/133.usbdev_tx_rx_disruption.172577785
Short name T3164
Test name
Test status
Simulation time 446571612 ps
CPU time 1.57 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207572 kb
Host smart-d93d6db0-19d5-4d65-9089-110282e81871
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172577785 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 133.usbdev_tx_rx_disruption.172577785
Directory /workspace/133.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/134.usbdev_endpoint_types.2650491762
Short name T436
Test name
Test status
Simulation time 555809853 ps
CPU time 1.42 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207500 kb
Host smart-0a0345b1-96ea-492c-bc89-bfd674812a8b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2650491762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.2650491762
Directory /workspace/134.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/134.usbdev_tx_rx_disruption.1710083618
Short name T702
Test name
Test status
Simulation time 462088713 ps
CPU time 1.44 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207444 kb
Host smart-d33dc6f9-bbb6-4bdb-881a-ae9c3e34d93e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710083618 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.usbdev_tx_rx_disruption.1710083618
Directory /workspace/134.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/135.usbdev_endpoint_types.267986050
Short name T3481
Test name
Test status
Simulation time 372291808 ps
CPU time 1.15 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207528 kb
Host smart-7248da9f-e979-4113-b397-76d4d511bd8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=267986050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.267986050
Directory /workspace/135.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_endpoint_types.3455655240
Short name T451
Test name
Test status
Simulation time 355356251 ps
CPU time 1.27 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207628 kb
Host smart-d0edebc1-4143-4a5e-a54b-e3b033c42ca7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3455655240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.3455655240
Directory /workspace/136.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/136.usbdev_tx_rx_disruption.1922229048
Short name T2310
Test name
Test status
Simulation time 449964491 ps
CPU time 1.37 seconds
Started Aug 10 07:17:28 PM PDT 24
Finished Aug 10 07:17:30 PM PDT 24
Peak memory 207572 kb
Host smart-668de757-de9f-4801-b82b-c264c4eb8403
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922229048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.usbdev_tx_rx_disruption.1922229048
Directory /workspace/136.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/137.usbdev_endpoint_types.1643489747
Short name T1977
Test name
Test status
Simulation time 158429098 ps
CPU time 0.89 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207540 kb
Host smart-c5e0407e-46ab-46b3-bf57-695c668920ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1643489747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.1643489747
Directory /workspace/137.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/137.usbdev_tx_rx_disruption.343484060
Short name T3283
Test name
Test status
Simulation time 524618936 ps
CPU time 1.74 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207424 kb
Host smart-81cc89c9-9bad-4fd5-92d9-8db4f63299f7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343484060 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 137.usbdev_tx_rx_disruption.343484060
Directory /workspace/137.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/138.usbdev_tx_rx_disruption.2671439897
Short name T3117
Test name
Test status
Simulation time 616855094 ps
CPU time 1.69 seconds
Started Aug 10 07:17:23 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207548 kb
Host smart-4a527242-f8ac-4be5-bfef-50c57675a0d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671439897 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.usbdev_tx_rx_disruption.2671439897
Directory /workspace/138.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/139.usbdev_tx_rx_disruption.2666232515
Short name T1045
Test name
Test status
Simulation time 551774057 ps
CPU time 1.66 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207528 kb
Host smart-1b9d8f87-8e15-4ae5-8930-e217600b7c3d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666232515 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.usbdev_tx_rx_disruption.2666232515
Directory /workspace/139.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3781858816
Short name T1838
Test name
Test status
Simulation time 4699879066 ps
CPU time 7.97 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:33 PM PDT 24
Peak memory 215972 kb
Host smart-501c158d-9fae-48ab-92b6-c02150b009ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781858816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.3781858816
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.290568548
Short name T896
Test name
Test status
Simulation time 30870707079 ps
CPU time 35.64 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207680 kb
Host smart-7e6f956f-e098-4ced-8fab-63be0525a02a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290568548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_resume.290568548
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2120664798
Short name T2315
Test name
Test status
Simulation time 168497335 ps
CPU time 0.87 seconds
Started Aug 10 07:07:24 PM PDT 24
Finished Aug 10 07:07:25 PM PDT 24
Peak memory 207608 kb
Host smart-797d01fb-b307-43c3-99b0-bcbd82263957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206
64798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2120664798
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1884413613
Short name T1862
Test name
Test status
Simulation time 204703236 ps
CPU time 0.93 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:26 PM PDT 24
Peak memory 207448 kb
Host smart-cfe51bb7-94c7-4f61-9104-8224fdf1666d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
13613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1884413613
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3458481553
Short name T2725
Test name
Test status
Simulation time 385060357 ps
CPU time 1.37 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:27 PM PDT 24
Peak memory 207468 kb
Host smart-1349f205-6ee6-4d4b-95fe-aeac39547574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
81553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3458481553
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1666869241
Short name T2503
Test name
Test status
Simulation time 1096155886 ps
CPU time 3.23 seconds
Started Aug 10 07:07:25 PM PDT 24
Finished Aug 10 07:07:28 PM PDT 24
Peak memory 207768 kb
Host smart-ee64a6d4-f332-4062-baa2-86396c49816b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1666869241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1666869241
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.359082302
Short name T3205
Test name
Test status
Simulation time 25797805546 ps
CPU time 46.31 seconds
Started Aug 10 07:07:26 PM PDT 24
Finished Aug 10 07:08:12 PM PDT 24
Peak memory 207852 kb
Host smart-de36199d-f1bf-4575-973e-2ab8121590a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35908
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.359082302
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.100837773
Short name T2527
Test name
Test status
Simulation time 3383162606 ps
CPU time 29.37 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:08:06 PM PDT 24
Peak memory 207696 kb
Host smart-f8847dd5-b432-4815-9d1a-6ca1abd82d3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100837773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.100837773
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.968406870
Short name T1772
Test name
Test status
Simulation time 681127095 ps
CPU time 1.69 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:39 PM PDT 24
Peak memory 207560 kb
Host smart-aa012f45-4704-48e1-bb54-ed43aee1d86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96840
6870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.968406870
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3699838105
Short name T3332
Test name
Test status
Simulation time 213218214 ps
CPU time 0.94 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:07:36 PM PDT 24
Peak memory 207436 kb
Host smart-98918914-450a-48b8-8aed-1d7f86870236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36998
38105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3699838105
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1503515188
Short name T1603
Test name
Test status
Simulation time 74693500 ps
CPU time 0.77 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:07:36 PM PDT 24
Peak memory 207572 kb
Host smart-be493197-bb4a-4b10-8bfe-6683ee217bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
15188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1503515188
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1462168364
Short name T3065
Test name
Test status
Simulation time 816379563 ps
CPU time 2.17 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207700 kb
Host smart-a991fc9e-5ab6-4846-ab4e-09cdfc353a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
68364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1462168364
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_types.4019095266
Short name T2965
Test name
Test status
Simulation time 272658058 ps
CPU time 1.08 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:39 PM PDT 24
Peak memory 207524 kb
Host smart-8928edf0-3d24-44f8-b2cf-e064e30ab91e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4019095266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.4019095266
Directory /workspace/14.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1400442844
Short name T1211
Test name
Test status
Simulation time 279921339 ps
CPU time 1.83 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207740 kb
Host smart-5280a395-ea54-45c7-9e39-5cfe60fe5e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004
42844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1400442844
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1255664951
Short name T27
Test name
Test status
Simulation time 178170588 ps
CPU time 0.91 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:37 PM PDT 24
Peak memory 207540 kb
Host smart-c9067610-5a13-40c5-ab28-77880064c8be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1255664951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1255664951
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1858466594
Short name T609
Test name
Test status
Simulation time 140548810 ps
CPU time 0.82 seconds
Started Aug 10 07:07:34 PM PDT 24
Finished Aug 10 07:07:35 PM PDT 24
Peak memory 207404 kb
Host smart-a7094e11-68ea-419e-8ef9-fa919a3677d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18584
66594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1858466594
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3976562836
Short name T1429
Test name
Test status
Simulation time 205862215 ps
CPU time 1.02 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207464 kb
Host smart-07c504e3-6853-41bb-ae9f-ed4777eca18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
62836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3976562836
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.154548851
Short name T839
Test name
Test status
Simulation time 5073746660 ps
CPU time 47.95 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:08:24 PM PDT 24
Peak memory 217316 kb
Host smart-7b986e35-7759-4427-9c1c-747d1f691c19
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=154548851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.154548851
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.259340040
Short name T850
Test name
Test status
Simulation time 11154621822 ps
CPU time 75.65 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:08:53 PM PDT 24
Peak memory 207796 kb
Host smart-7a2ddbcf-05f6-4421-884e-203f79fa7e16
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=259340040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.259340040
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2119275754
Short name T3154
Test name
Test status
Simulation time 225624216 ps
CPU time 1.02 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:37 PM PDT 24
Peak memory 207604 kb
Host smart-2539b9fd-fdc2-49fc-a8c9-48b68840fc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21192
75754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2119275754
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3927488925
Short name T1390
Test name
Test status
Simulation time 29126311168 ps
CPU time 42.5 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:08:18 PM PDT 24
Peak memory 207884 kb
Host smart-bda6a1ae-444c-4098-888f-4648b988cb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39274
88925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3927488925
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1321289693
Short name T99
Test name
Test status
Simulation time 10887128781 ps
CPU time 13.95 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207872 kb
Host smart-70e20662-d612-4da0-92a5-7372777fb9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
89693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1321289693
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.1332706680
Short name T2826
Test name
Test status
Simulation time 5034945851 ps
CPU time 146.62 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 216084 kb
Host smart-fa645557-ec6b-4f0b-8786-61851c2455b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1332706680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.1332706680
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2517312595
Short name T5
Test name
Test status
Simulation time 3091129904 ps
CPU time 89.63 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 216004 kb
Host smart-b96349dc-93d1-4d9f-83a4-3cd2c7645cc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2517312595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2517312595
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2466866267
Short name T2148
Test name
Test status
Simulation time 235558565 ps
CPU time 0.96 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207568 kb
Host smart-feb38954-11b7-4208-b13b-e0fcfe1d3a2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2466866267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2466866267
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3467713080
Short name T1240
Test name
Test status
Simulation time 182283895 ps
CPU time 0.9 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207552 kb
Host smart-d1d106a1-ebb0-40a2-b8dc-c458309e6d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34677
13080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3467713080
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.3080400506
Short name T1700
Test name
Test status
Simulation time 2404455908 ps
CPU time 17.57 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:07:52 PM PDT 24
Peak memory 216048 kb
Host smart-40eb103c-958a-435d-8168-2da72a2799ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30804
00506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.3080400506
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.419733482
Short name T1514
Test name
Test status
Simulation time 2933257583 ps
CPU time 23.62 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 224196 kb
Host smart-9fbc0b4f-655d-4dc0-921f-282f13b9d1ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=419733482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.419733482
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3245106478
Short name T1466
Test name
Test status
Simulation time 2042499454 ps
CPU time 55.66 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:08:31 PM PDT 24
Peak memory 224080 kb
Host smart-bbf6dd13-a0d9-41cd-aaba-979e47400b69
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3245106478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3245106478
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.225731268
Short name T1218
Test name
Test status
Simulation time 168777546 ps
CPU time 0.83 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:07:36 PM PDT 24
Peak memory 207560 kb
Host smart-3b9f75a6-4abd-48ee-8737-6cb8845c2850
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=225731268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.225731268
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.593236984
Short name T875
Test name
Test status
Simulation time 166331410 ps
CPU time 0.86 seconds
Started Aug 10 07:07:37 PM PDT 24
Finished Aug 10 07:07:38 PM PDT 24
Peak memory 207520 kb
Host smart-d5f12406-f1b9-4a10-96de-9563ab9914fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59323
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.593236984
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1042241601
Short name T2275
Test name
Test status
Simulation time 198620377 ps
CPU time 1.08 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:37 PM PDT 24
Peak memory 207480 kb
Host smart-b78d6852-3479-402c-9e70-0c31949fb35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10422
41601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1042241601
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3501710107
Short name T2904
Test name
Test status
Simulation time 182678963 ps
CPU time 0.89 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:37 PM PDT 24
Peak memory 207456 kb
Host smart-f0aac943-714a-4296-9991-8ea16b5ddc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35017
10107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3501710107
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1844676017
Short name T3025
Test name
Test status
Simulation time 160890594 ps
CPU time 0.92 seconds
Started Aug 10 07:07:35 PM PDT 24
Finished Aug 10 07:07:36 PM PDT 24
Peak memory 207544 kb
Host smart-94051b87-081d-494a-94ca-d704fb162b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
76017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1844676017
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3923286496
Short name T1511
Test name
Test status
Simulation time 168935792 ps
CPU time 0.88 seconds
Started Aug 10 07:07:36 PM PDT 24
Finished Aug 10 07:07:37 PM PDT 24
Peak memory 207568 kb
Host smart-434b5774-32ed-4d61-8706-34e5e5211c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39232
86496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3923286496
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3957896396
Short name T207
Test name
Test status
Simulation time 161710033 ps
CPU time 0.83 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:07:48 PM PDT 24
Peak memory 207552 kb
Host smart-94f1ec67-b0f5-4a86-be8e-9356b245f63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39578
96396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3957896396
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2609419952
Short name T1756
Test name
Test status
Simulation time 216137624 ps
CPU time 0.98 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207544 kb
Host smart-c9a3e7d8-8ef3-439f-bf33-0f70e483158d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2609419952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2609419952
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.44127706
Short name T1559
Test name
Test status
Simulation time 173485728 ps
CPU time 0.84 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207524 kb
Host smart-262e2f2f-0649-47e8-932d-41587ff53515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44127
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.44127706
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3532806578
Short name T39
Test name
Test status
Simulation time 127091702 ps
CPU time 0.76 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:07:48 PM PDT 24
Peak memory 207424 kb
Host smart-c1955e68-1a37-46cb-b6a8-305741f25da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
06578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3532806578
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.651474555
Short name T314
Test name
Test status
Simulation time 18947828758 ps
CPU time 46.47 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:08:35 PM PDT 24
Peak memory 220596 kb
Host smart-856f198b-8364-4544-a084-55b08b59c017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65147
4555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.651474555
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1019985397
Short name T2590
Test name
Test status
Simulation time 224332324 ps
CPU time 0.97 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207576 kb
Host smart-a6fdaa44-f962-457f-bdfe-4f7cd727a478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10199
85397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1019985397
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2356362737
Short name T3189
Test name
Test status
Simulation time 276387894 ps
CPU time 1.02 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:07:48 PM PDT 24
Peak memory 207568 kb
Host smart-e4dc77e5-d0ff-4e04-97c5-5d4ce5304163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23563
62737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2356362737
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2685755077
Short name T3119
Test name
Test status
Simulation time 195572589 ps
CPU time 0.95 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207580 kb
Host smart-533a1094-37ba-4eae-be89-c76f28e4ba5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26857
55077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2685755077
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4078927914
Short name T2779
Test name
Test status
Simulation time 156052487 ps
CPU time 0.85 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207400 kb
Host smart-d2616728-697c-40a0-b3cf-64d7934ce091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40789
27914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4078927914
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_resume_link_active.4185878281
Short name T1835
Test name
Test status
Simulation time 20160584946 ps
CPU time 24.51 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:08:11 PM PDT 24
Peak memory 207600 kb
Host smart-50293151-888b-466b-8ac1-f3275d69a95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
78281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_resume_link_active.4185878281
Directory /workspace/14.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3519291238
Short name T2957
Test name
Test status
Simulation time 245976928 ps
CPU time 0.95 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207528 kb
Host smart-c6ba9df6-7959-4267-a051-a56d5e878d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35192
91238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3519291238
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.4267352237
Short name T2658
Test name
Test status
Simulation time 159328972 ps
CPU time 0.85 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207480 kb
Host smart-78df1f86-a03b-479b-94bf-3dfd705a59aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42673
52237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.4267352237
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.327503456
Short name T2763
Test name
Test status
Simulation time 147173280 ps
CPU time 0.81 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207552 kb
Host smart-379186d3-eb03-44f3-8f30-4bf881b5e349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32750
3456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.327503456
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1211692042
Short name T1290
Test name
Test status
Simulation time 203724826 ps
CPU time 0.98 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207516 kb
Host smart-765b6c95-d25f-4f78-ba3b-61f0e3b77f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12116
92042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1211692042
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3223806568
Short name T2688
Test name
Test status
Simulation time 2332848025 ps
CPU time 18.43 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:08:05 PM PDT 24
Peak memory 218120 kb
Host smart-fbcdfddb-a5ec-47dc-8810-12520aa7a72a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3223806568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3223806568
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2744436178
Short name T821
Test name
Test status
Simulation time 169293651 ps
CPU time 0.85 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207564 kb
Host smart-cc3ec10f-b0c8-4a91-a281-f47f15b477e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27444
36178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2744436178
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2885440575
Short name T1794
Test name
Test status
Simulation time 174831825 ps
CPU time 0.85 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:49 PM PDT 24
Peak memory 207564 kb
Host smart-ea9e3b3a-e5a8-453b-964c-e92785a9a44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854
40575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2885440575
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.673102883
Short name T311
Test name
Test status
Simulation time 612038265 ps
CPU time 1.67 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:51 PM PDT 24
Peak memory 207504 kb
Host smart-924b0ae6-a3d2-4c28-a561-f353a3850cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67310
2883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.673102883
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1451038264
Short name T1816
Test name
Test status
Simulation time 1824088266 ps
CPU time 52.59 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:08:42 PM PDT 24
Peak memory 216004 kb
Host smart-a96f31f3-9097-43ec-a283-24ca46789c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14510
38264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1451038264
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.3425281493
Short name T1640
Test name
Test status
Simulation time 2519026846 ps
CPU time 22.89 seconds
Started Aug 10 07:07:38 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207736 kb
Host smart-8f8177fe-6f52-46a9-8aa9-5845e8378d8d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425281493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.3425281493
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_tx_rx_disruption.4018708127
Short name T2362
Test name
Test status
Simulation time 603440025 ps
CPU time 1.69 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207508 kb
Host smart-d3b080ae-4b4a-4504-b688-76ecc809e235
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018708127 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.usbdev_tx_rx_disruption.4018708127
Directory /workspace/14.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/140.usbdev_tx_rx_disruption.1079421915
Short name T3353
Test name
Test status
Simulation time 470010990 ps
CPU time 1.51 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207536 kb
Host smart-e6a3bc69-975f-4e2d-ada9-4b6e70513c52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079421915 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.usbdev_tx_rx_disruption.1079421915
Directory /workspace/140.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/141.usbdev_endpoint_types.4253651072
Short name T1673
Test name
Test status
Simulation time 158921115 ps
CPU time 0.86 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207532 kb
Host smart-c6415cec-8e23-4bf1-8f81-bccde95e755f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4253651072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.4253651072
Directory /workspace/141.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/141.usbdev_tx_rx_disruption.188988201
Short name T944
Test name
Test status
Simulation time 543830496 ps
CPU time 1.55 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:26 PM PDT 24
Peak memory 207600 kb
Host smart-b80d3dbe-4b4e-42f5-af8a-0647fc0e6bb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188988201 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 141.usbdev_tx_rx_disruption.188988201
Directory /workspace/141.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/142.usbdev_endpoint_types.2125806218
Short name T3280
Test name
Test status
Simulation time 224986160 ps
CPU time 0.98 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207368 kb
Host smart-e0fd6ba9-4f9c-4119-b42e-985838f2649b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2125806218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.2125806218
Directory /workspace/142.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/142.usbdev_tx_rx_disruption.2030256845
Short name T3248
Test name
Test status
Simulation time 657255980 ps
CPU time 1.62 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207600 kb
Host smart-9e61e29b-3261-4fd7-bbc8-522d7bd5abbc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030256845 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.usbdev_tx_rx_disruption.2030256845
Directory /workspace/142.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/143.usbdev_endpoint_types.3540438098
Short name T395
Test name
Test status
Simulation time 403960605 ps
CPU time 1.2 seconds
Started Aug 10 07:17:28 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207516 kb
Host smart-998696fa-744b-4570-b649-bdb9843ab641
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540438098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.3540438098
Directory /workspace/143.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_endpoint_types.1746100673
Short name T425
Test name
Test status
Simulation time 784250843 ps
CPU time 1.99 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207628 kb
Host smart-d662767e-f967-44f3-92ec-bd9b3fa86015
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1746100673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.1746100673
Directory /workspace/144.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/144.usbdev_tx_rx_disruption.3530718612
Short name T1686
Test name
Test status
Simulation time 654374260 ps
CPU time 1.89 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207528 kb
Host smart-25e6011d-1728-4015-bcd5-14e57d93e7e4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530718612 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.usbdev_tx_rx_disruption.3530718612
Directory /workspace/144.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/145.usbdev_endpoint_types.4089448401
Short name T466
Test name
Test status
Simulation time 421451540 ps
CPU time 1.28 seconds
Started Aug 10 07:17:28 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207516 kb
Host smart-02d8b1d9-6732-49c5-9444-36a74d1949fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4089448401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.4089448401
Directory /workspace/145.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/145.usbdev_tx_rx_disruption.4061734991
Short name T2299
Test name
Test status
Simulation time 579909536 ps
CPU time 1.51 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207572 kb
Host smart-71db120e-4c2d-4fd9-b7f3-9b518f267219
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061734991 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.usbdev_tx_rx_disruption.4061734991
Directory /workspace/145.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/146.usbdev_endpoint_types.105417869
Short name T438
Test name
Test status
Simulation time 466334017 ps
CPU time 1.33 seconds
Started Aug 10 07:17:28 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207532 kb
Host smart-221184e8-b5c9-40d8-a52d-8104892291c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=105417869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.105417869
Directory /workspace/146.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/146.usbdev_tx_rx_disruption.1593828646
Short name T2764
Test name
Test status
Simulation time 609282878 ps
CPU time 1.56 seconds
Started Aug 10 07:17:27 PM PDT 24
Finished Aug 10 07:17:29 PM PDT 24
Peak memory 207548 kb
Host smart-1c6295a9-578b-4b4a-8635-6c88ed48e9a0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593828646 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.usbdev_tx_rx_disruption.1593828646
Directory /workspace/146.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/147.usbdev_tx_rx_disruption.3236456757
Short name T2238
Test name
Test status
Simulation time 477266983 ps
CPU time 1.5 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207532 kb
Host smart-dc835223-fed5-4189-b3b9-8448adddbe49
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236456757 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.usbdev_tx_rx_disruption.3236456757
Directory /workspace/147.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/148.usbdev_endpoint_types.2956282187
Short name T514
Test name
Test status
Simulation time 308393445 ps
CPU time 1.12 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207536 kb
Host smart-6c72a450-f08f-41e8-a058-173aef71d34f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2956282187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.2956282187
Directory /workspace/148.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_endpoint_types.415656158
Short name T3626
Test name
Test status
Simulation time 549423359 ps
CPU time 1.34 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207488 kb
Host smart-0bcae42a-3720-44c9-9065-ded3dd071689
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=415656158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.415656158
Directory /workspace/149.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/149.usbdev_tx_rx_disruption.3306812274
Short name T1032
Test name
Test status
Simulation time 556478962 ps
CPU time 1.63 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207488 kb
Host smart-605d1d0b-454a-4efb-b5c5-1d5a967c9e65
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306812274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.usbdev_tx_rx_disruption.3306812274
Directory /workspace/149.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2228017988
Short name T3623
Test name
Test status
Simulation time 66093698 ps
CPU time 0.72 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:08 PM PDT 24
Peak memory 207556 kb
Host smart-289047a1-0402-4f0d-84de-01a778c78521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2228017988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2228017988
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3726324220
Short name T2625
Test name
Test status
Simulation time 6143314454 ps
CPU time 9.84 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:57 PM PDT 24
Peak memory 216072 kb
Host smart-aafef86c-abc8-4c3f-b235-30aed69d05e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726324220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.3726324220
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4114174888
Short name T2190
Test name
Test status
Simulation time 14226346030 ps
CPU time 17.82 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:08:06 PM PDT 24
Peak memory 216200 kb
Host smart-ecd594f1-6c22-4eea-88dc-3464abe2fa1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114174888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4114174888
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2817990163
Short name T3264
Test name
Test status
Simulation time 28701576629 ps
CPU time 32.43 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:08:22 PM PDT 24
Peak memory 207868 kb
Host smart-6a8351ce-b2a2-470b-a346-c2f740a1061d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817990163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2817990163
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.617942578
Short name T1003
Test name
Test status
Simulation time 186121334 ps
CPU time 0.88 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207576 kb
Host smart-44332313-8a18-42f1-ae1b-7486449064b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61794
2578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.617942578
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2261178633
Short name T2107
Test name
Test status
Simulation time 155264372 ps
CPU time 0.87 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207508 kb
Host smart-9e768439-89ce-4c64-8f97-e667ccfc0647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
78633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2261178633
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1413321667
Short name T774
Test name
Test status
Simulation time 460907626 ps
CPU time 1.53 seconds
Started Aug 10 07:07:49 PM PDT 24
Finished Aug 10 07:07:51 PM PDT 24
Peak memory 207660 kb
Host smart-9153d9b0-e2ac-4c7f-b92c-ace792906166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
21667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1413321667
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1746021212
Short name T1056
Test name
Test status
Simulation time 713449105 ps
CPU time 1.95 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:07:50 PM PDT 24
Peak memory 207544 kb
Host smart-d72a20c7-c0b8-45c7-bd23-618aa4e165b5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1746021212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1746021212
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3603887983
Short name T1947
Test name
Test status
Simulation time 26595842712 ps
CPU time 45.59 seconds
Started Aug 10 07:07:47 PM PDT 24
Finished Aug 10 07:08:33 PM PDT 24
Peak memory 207800 kb
Host smart-aad76f1f-c88a-48e0-bf08-bedccf859d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36038
87983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3603887983
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.2153059242
Short name T3434
Test name
Test status
Simulation time 1126589848 ps
CPU time 26.57 seconds
Started Aug 10 07:07:48 PM PDT 24
Finished Aug 10 07:08:15 PM PDT 24
Peak memory 207744 kb
Host smart-b4954ae5-2471-41e7-9ef4-12012d6b9050
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153059242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.2153059242
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2252373463
Short name T2444
Test name
Test status
Simulation time 979706707 ps
CPU time 2.29 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:02 PM PDT 24
Peak memory 207572 kb
Host smart-371c989d-a1cb-496f-9c03-0bafb9e536fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
73463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2252373463
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.676719402
Short name T1967
Test name
Test status
Simulation time 143289454 ps
CPU time 0.79 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207504 kb
Host smart-4ee7019a-457a-42e5-aafe-ab89e9a69de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67671
9402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.676719402
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3411557734
Short name T2258
Test name
Test status
Simulation time 38115148 ps
CPU time 0.7 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:07:59 PM PDT 24
Peak memory 207520 kb
Host smart-ef76a6ee-f9be-4cc7-a403-001b87ad79ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34115
57734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3411557734
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3889545890
Short name T1929
Test name
Test status
Simulation time 845100092 ps
CPU time 2.21 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207700 kb
Host smart-9f261a4d-d821-4699-93dc-685a3217961f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38895
45890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3889545890
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_types.2098879154
Short name T418
Test name
Test status
Simulation time 380499502 ps
CPU time 1.2 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207480 kb
Host smart-0609f6f8-52c8-43b8-b486-03933210e7bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2098879154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.2098879154
Directory /workspace/15.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.331588508
Short name T1664
Test name
Test status
Simulation time 158017546 ps
CPU time 1.37 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207724 kb
Host smart-74781b86-cbfc-4d6d-8599-d2c7d8d6e83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
8508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.331588508
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.4021615192
Short name T1068
Test name
Test status
Simulation time 245024106 ps
CPU time 1.15 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 215964 kb
Host smart-f0a8682d-0014-4d31-b372-3e55409c37bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4021615192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4021615192
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1547107251
Short name T1492
Test name
Test status
Simulation time 138302814 ps
CPU time 0.84 seconds
Started Aug 10 07:08:02 PM PDT 24
Finished Aug 10 07:08:02 PM PDT 24
Peak memory 207544 kb
Host smart-55b40267-a183-4265-9080-0a405f2f2dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
07251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1547107251
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1981175298
Short name T963
Test name
Test status
Simulation time 225157963 ps
CPU time 0.96 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207484 kb
Host smart-328827f4-9c14-4cab-ac74-548bd5e0b901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
75298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1981175298
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1636513791
Short name T962
Test name
Test status
Simulation time 2415683933 ps
CPU time 71.39 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:09:10 PM PDT 24
Peak memory 224160 kb
Host smart-0c812a8d-13fa-4d8f-9207-3cca9322f6ab
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1636513791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1636513791
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.481335397
Short name T3259
Test name
Test status
Simulation time 8541647058 ps
CPU time 59.82 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:59 PM PDT 24
Peak memory 207788 kb
Host smart-37d1d94b-2fe8-48c1-a776-4330014d3ef3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=481335397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.481335397
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3271571238
Short name T2034
Test name
Test status
Simulation time 211951593 ps
CPU time 0.94 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207536 kb
Host smart-837aead4-9f55-41f8-a131-fcb3f4573038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32715
71238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3271571238
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3766142405
Short name T3622
Test name
Test status
Simulation time 33462997628 ps
CPU time 49.02 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:50 PM PDT 24
Peak memory 207712 kb
Host smart-cca3d0e5-fd01-47b4-a605-44ba9b58c9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
42405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3766142405
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2854999922
Short name T3521
Test name
Test status
Simulation time 3652386617 ps
CPU time 5.2 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:04 PM PDT 24
Peak memory 216192 kb
Host smart-d3eff646-b166-4d2d-8f01-04beb0822a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28549
99922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2854999922
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2734178422
Short name T2530
Test name
Test status
Simulation time 4216374273 ps
CPU time 129.69 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 218572 kb
Host smart-88ffae98-4905-4597-acc0-dde148ed0bbf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2734178422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2734178422
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3676374215
Short name T2135
Test name
Test status
Simulation time 2737689825 ps
CPU time 77.47 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 217536 kb
Host smart-c5d2fb26-7d4f-4337-9f0c-2fcc2759e3f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3676374215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3676374215
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3467670069
Short name T3543
Test name
Test status
Simulation time 283216948 ps
CPU time 1.11 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207604 kb
Host smart-298894de-9138-46d0-87ea-865170406fee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3467670069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3467670069
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.463866501
Short name T2733
Test name
Test status
Simulation time 217914231 ps
CPU time 1 seconds
Started Aug 10 07:08:01 PM PDT 24
Finished Aug 10 07:08:02 PM PDT 24
Peak memory 207568 kb
Host smart-98539b10-c7b2-4581-b0d5-28bb72c217aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46386
6501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.463866501
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.611639263
Short name T2028
Test name
Test status
Simulation time 2334397788 ps
CPU time 66.56 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:09:07 PM PDT 24
Peak memory 217500 kb
Host smart-bf79ddbf-edc3-4351-8f3f-d98890a9edb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=611639263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.611639263
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3132232200
Short name T584
Test name
Test status
Simulation time 172923713 ps
CPU time 0.88 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207516 kb
Host smart-a55dffb2-0c36-441e-ad73-ee91da34ad94
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3132232200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3132232200
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3864862508
Short name T3555
Test name
Test status
Simulation time 183674126 ps
CPU time 0.9 seconds
Started Aug 10 07:07:57 PM PDT 24
Finished Aug 10 07:07:58 PM PDT 24
Peak memory 207732 kb
Host smart-2dc48712-05f5-468b-b1cd-602538640560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38648
62508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3864862508
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3825821703
Short name T3411
Test name
Test status
Simulation time 216883914 ps
CPU time 0.88 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207512 kb
Host smart-459a16b1-1de0-4f96-83c3-0c29e6f4ef5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
21703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3825821703
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1331940371
Short name T2085
Test name
Test status
Simulation time 197942763 ps
CPU time 0.94 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207456 kb
Host smart-0c176749-e041-4495-b744-30b454d710bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
40371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1331940371
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4247166928
Short name T979
Test name
Test status
Simulation time 164021991 ps
CPU time 0.87 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207488 kb
Host smart-a171129b-27a5-4533-b069-cb7bbfe47d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
66928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4247166928
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3936069156
Short name T505
Test name
Test status
Simulation time 191321935 ps
CPU time 0.93 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207564 kb
Host smart-959ded18-3e77-49b5-8a7f-9868ae31a4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39360
69156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3936069156
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3546003660
Short name T200
Test name
Test status
Simulation time 187265400 ps
CPU time 0.89 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207604 kb
Host smart-493ee692-57c2-420c-8d9b-3eaaf9c4d013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35460
03660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3546003660
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.4056856232
Short name T2893
Test name
Test status
Simulation time 168162968 ps
CPU time 0.89 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207568 kb
Host smart-fadd747b-3e7a-42fb-a509-b3ae6e27eb90
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4056856232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.4056856232
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3160205844
Short name T1919
Test name
Test status
Simulation time 170199751 ps
CPU time 0.9 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207476 kb
Host smart-2fb0be5f-89ad-46b0-815b-79f961a582b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31602
05844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3160205844
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1403135317
Short name T41
Test name
Test status
Simulation time 51430819 ps
CPU time 0.67 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:01 PM PDT 24
Peak memory 207504 kb
Host smart-652e2387-7dae-403c-9942-475adc108aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
35317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1403135317
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.814914900
Short name T1401
Test name
Test status
Simulation time 18938225470 ps
CPU time 48.97 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 216064 kb
Host smart-26b836dd-65ee-4d19-bdd5-1c60a2075765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81491
4900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.814914900
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2309977010
Short name T3561
Test name
Test status
Simulation time 176061586 ps
CPU time 0.96 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207592 kb
Host smart-4483108a-33be-4988-9219-228f726e162c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
77010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2309977010
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3570474143
Short name T2105
Test name
Test status
Simulation time 253694893 ps
CPU time 1.06 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:02 PM PDT 24
Peak memory 207564 kb
Host smart-ac1a1b6d-6ae8-4b32-adfa-f42d742f8100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
74143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3570474143
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.333105941
Short name T2109
Test name
Test status
Simulation time 183959363 ps
CPU time 0.87 seconds
Started Aug 10 07:07:59 PM PDT 24
Finished Aug 10 07:08:00 PM PDT 24
Peak memory 207420 kb
Host smart-c006856e-f203-46b9-9ac2-b744d9223803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
5941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.333105941
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.824857133
Short name T1976
Test name
Test status
Simulation time 232863547 ps
CPU time 0.98 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:07:59 PM PDT 24
Peak memory 207580 kb
Host smart-68d8108a-3e2e-4b92-8625-7310e2838a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82485
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.824857133
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_resume_link_active.4145532449
Short name T1146
Test name
Test status
Simulation time 20170630954 ps
CPU time 24.65 seconds
Started Aug 10 07:08:01 PM PDT 24
Finished Aug 10 07:08:26 PM PDT 24
Peak memory 207684 kb
Host smart-48282a01-d3f3-4b19-97cb-dcca6dd6444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41455
32449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_resume_link_active.4145532449
Directory /workspace/15.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2961503983
Short name T2130
Test name
Test status
Simulation time 253428328 ps
CPU time 0.96 seconds
Started Aug 10 07:07:58 PM PDT 24
Finished Aug 10 07:07:59 PM PDT 24
Peak memory 207548 kb
Host smart-43532cd6-740d-49c8-9e44-e367f56b0017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29615
03983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2961503983
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_rx_full.2801336675
Short name T3261
Test name
Test status
Simulation time 351294070 ps
CPU time 1.24 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207560 kb
Host smart-af058d99-ef09-4ef4-bba2-88ed1401fef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
36675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.2801336675
Directory /workspace/15.usbdev_rx_full/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.684077803
Short name T1764
Test name
Test status
Simulation time 151054876 ps
CPU time 0.83 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207544 kb
Host smart-f5683a62-32a8-4cd4-8333-fd939b49dfa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68407
7803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.684077803
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1557298601
Short name T2719
Test name
Test status
Simulation time 202442267 ps
CPU time 0.87 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207416 kb
Host smart-10ac50db-ae9f-49d9-a8e7-0f64703586dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15572
98601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1557298601
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.829873523
Short name T709
Test name
Test status
Simulation time 305750326 ps
CPU time 1.2 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207416 kb
Host smart-7af28050-f591-4c45-a281-e2496612592c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82987
3523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.829873523
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2097871873
Short name T1550
Test name
Test status
Simulation time 2346721776 ps
CPU time 72.75 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:09:21 PM PDT 24
Peak memory 217760 kb
Host smart-b2cfa387-c874-45c6-9603-17ad2bc927ab
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2097871873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2097871873
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1795048926
Short name T2747
Test name
Test status
Simulation time 165832494 ps
CPU time 0.86 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:09 PM PDT 24
Peak memory 207532 kb
Host smart-abe4493a-1ce6-4d9f-98c5-75fa170c1e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950
48926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1795048926
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4174633520
Short name T785
Test name
Test status
Simulation time 182899417 ps
CPU time 0.9 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207604 kb
Host smart-5267c603-3748-4c1d-8d8b-ae21cf62d19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41746
33520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4174633520
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.776042263
Short name T1944
Test name
Test status
Simulation time 188179124 ps
CPU time 0.91 seconds
Started Aug 10 07:08:11 PM PDT 24
Finished Aug 10 07:08:12 PM PDT 24
Peak memory 207532 kb
Host smart-ffcbccac-da19-4848-8477-a2b3b866b23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77604
2263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.776042263
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2390539235
Short name T569
Test name
Test status
Simulation time 2526281555 ps
CPU time 20.43 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 217056 kb
Host smart-87f2d9b4-47bc-4746-a85d-58468d4d7f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23905
39235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2390539235
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.2362709813
Short name T594
Test name
Test status
Simulation time 6783899567 ps
CPU time 47.26 seconds
Started Aug 10 07:08:00 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207760 kb
Host smart-2dceb365-72e6-455a-b13f-7a0b4cfe22ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362709813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.2362709813
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_tx_rx_disruption.3338146792
Short name T2875
Test name
Test status
Simulation time 504612647 ps
CPU time 1.47 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207480 kb
Host smart-b2018185-49ed-4b45-98c7-6ac5b2284423
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338146792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.usbdev_tx_rx_disruption.3338146792
Directory /workspace/15.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/150.usbdev_endpoint_types.2226379881
Short name T1515
Test name
Test status
Simulation time 257656210 ps
CPU time 1.01 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207524 kb
Host smart-6b0f7b67-611f-4c99-8127-362a0732f1ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2226379881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.2226379881
Directory /workspace/150.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/150.usbdev_tx_rx_disruption.2116538250
Short name T942
Test name
Test status
Simulation time 511165528 ps
CPU time 1.58 seconds
Started Aug 10 07:17:26 PM PDT 24
Finished Aug 10 07:17:28 PM PDT 24
Peak memory 207528 kb
Host smart-9c775bf5-efc7-4388-8497-c94818f05dc9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116538250 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.usbdev_tx_rx_disruption.2116538250
Directory /workspace/150.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/151.usbdev_tx_rx_disruption.1299153629
Short name T3462
Test name
Test status
Simulation time 446279732 ps
CPU time 1.52 seconds
Started Aug 10 07:17:25 PM PDT 24
Finished Aug 10 07:17:27 PM PDT 24
Peak memory 207564 kb
Host smart-a026b7df-e75a-488e-9dd1-7a8c124367d2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299153629 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.usbdev_tx_rx_disruption.1299153629
Directory /workspace/151.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/152.usbdev_endpoint_types.1904539614
Short name T2237
Test name
Test status
Simulation time 226762362 ps
CPU time 0.94 seconds
Started Aug 10 07:17:24 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 207516 kb
Host smart-a9a6d2bd-bb23-4f0e-8bbf-15b133bbb293
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1904539614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.1904539614
Directory /workspace/152.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/152.usbdev_tx_rx_disruption.4255981569
Short name T2051
Test name
Test status
Simulation time 604445841 ps
CPU time 1.75 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:42 PM PDT 24
Peak memory 207524 kb
Host smart-79d4f7c2-2665-4c89-b9f2-ce31fa04bc61
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255981569 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.usbdev_tx_rx_disruption.4255981569
Directory /workspace/152.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/153.usbdev_endpoint_types.500984003
Short name T2835
Test name
Test status
Simulation time 280367807 ps
CPU time 1.07 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207516 kb
Host smart-ca48d6a1-fbac-45e0-af98-db8a4c42cc45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=500984003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.500984003
Directory /workspace/153.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/154.usbdev_tx_rx_disruption.3587028266
Short name T1545
Test name
Test status
Simulation time 604823394 ps
CPU time 1.67 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207420 kb
Host smart-c9f9d40d-0aea-4bb0-9896-13b46840703b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587028266 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.usbdev_tx_rx_disruption.3587028266
Directory /workspace/154.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/155.usbdev_endpoint_types.2510327160
Short name T379
Test name
Test status
Simulation time 631225100 ps
CPU time 1.78 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207496 kb
Host smart-f18319f1-157e-48d2-823e-1f64def5ec5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2510327160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2510327160
Directory /workspace/155.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/155.usbdev_tx_rx_disruption.1125906209
Short name T1573
Test name
Test status
Simulation time 650430027 ps
CPU time 1.79 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:38 PM PDT 24
Peak memory 207560 kb
Host smart-14a3d3b1-6b0d-4b14-9ff5-1ead1de6b055
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125906209 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.usbdev_tx_rx_disruption.1125906209
Directory /workspace/155.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/156.usbdev_endpoint_types.2045411127
Short name T518
Test name
Test status
Simulation time 599947550 ps
CPU time 1.58 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207460 kb
Host smart-62e12740-2fb4-4f01-bfdf-0ce92344e74f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2045411127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.2045411127
Directory /workspace/156.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/156.usbdev_tx_rx_disruption.3870163370
Short name T582
Test name
Test status
Simulation time 543530661 ps
CPU time 1.56 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207604 kb
Host smart-ef0ec98d-c20e-4ab7-839c-3a02335eb61a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870163370 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.usbdev_tx_rx_disruption.3870163370
Directory /workspace/156.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/157.usbdev_endpoint_types.1686378641
Short name T2507
Test name
Test status
Simulation time 249215218 ps
CPU time 1.1 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207560 kb
Host smart-4e7bb302-9c6f-4762-a31a-7f856419adcb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1686378641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1686378641
Directory /workspace/157.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/157.usbdev_tx_rx_disruption.338671922
Short name T1574
Test name
Test status
Simulation time 576032897 ps
CPU time 1.72 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207592 kb
Host smart-2c6ea42f-6d78-44c2-bc1d-a80fcf7e7767
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338671922 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 157.usbdev_tx_rx_disruption.338671922
Directory /workspace/157.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/158.usbdev_endpoint_types.2603495005
Short name T476
Test name
Test status
Simulation time 313153949 ps
CPU time 1.17 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207568 kb
Host smart-e60a9e0b-eb78-4cb5-ba20-fe5a4a7a40d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2603495005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.2603495005
Directory /workspace/158.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/158.usbdev_tx_rx_disruption.934029994
Short name T1134
Test name
Test status
Simulation time 484052179 ps
CPU time 1.55 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207768 kb
Host smart-58a7a48a-affb-409d-b44c-1cd256909010
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934029994 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 158.usbdev_tx_rx_disruption.934029994
Directory /workspace/158.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/159.usbdev_endpoint_types.2199244803
Short name T474
Test name
Test status
Simulation time 286298870 ps
CPU time 1.17 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207484 kb
Host smart-36450118-bd3f-46a0-b26a-3465723265aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2199244803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.2199244803
Directory /workspace/159.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/159.usbdev_tx_rx_disruption.4070398793
Short name T1033
Test name
Test status
Simulation time 601180788 ps
CPU time 1.7 seconds
Started Aug 10 07:17:33 PM PDT 24
Finished Aug 10 07:17:35 PM PDT 24
Peak memory 207536 kb
Host smart-07234603-f9bf-4076-9f90-e87fe3331030
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070398793 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.usbdev_tx_rx_disruption.4070398793
Directory /workspace/159.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3849233515
Short name T1513
Test name
Test status
Simulation time 51578029 ps
CPU time 0.7 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:08:31 PM PDT 24
Peak memory 207572 kb
Host smart-71895e32-9f0d-40c6-9cbf-e5bdd27ed197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3849233515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3849233515
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1706356806
Short name T8
Test name
Test status
Simulation time 10956589785 ps
CPU time 13.61 seconds
Started Aug 10 07:08:07 PM PDT 24
Finished Aug 10 07:08:21 PM PDT 24
Peak memory 207832 kb
Host smart-03a91598-9230-4180-ab49-1b1573ccf1c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706356806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.1706356806
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2295144733
Short name T1733
Test name
Test status
Simulation time 21462196034 ps
CPU time 26.82 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:35 PM PDT 24
Peak memory 207792 kb
Host smart-94eac395-2530-4208-8c19-f73ba7897fff
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295144733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2295144733
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.4085729805
Short name T2215
Test name
Test status
Simulation time 28446918451 ps
CPU time 33.28 seconds
Started Aug 10 07:08:07 PM PDT 24
Finished Aug 10 07:08:41 PM PDT 24
Peak memory 207872 kb
Host smart-7ea88dc3-5b0d-41b3-8cd6-f0b4a8998311
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085729805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.4085729805
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2883366803
Short name T792
Test name
Test status
Simulation time 173562807 ps
CPU time 0.84 seconds
Started Aug 10 07:08:08 PM PDT 24
Finished Aug 10 07:08:09 PM PDT 24
Peak memory 207608 kb
Host smart-988d48e7-9593-4a34-ae86-238267391f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
66803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2883366803
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2031187887
Short name T908
Test name
Test status
Simulation time 198940491 ps
CPU time 0.87 seconds
Started Aug 10 07:08:09 PM PDT 24
Finished Aug 10 07:08:10 PM PDT 24
Peak memory 207520 kb
Host smart-3a24dbe7-3fd1-47e0-a7f4-1e2bf6a95280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20311
87887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2031187887
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2970012327
Short name T2254
Test name
Test status
Simulation time 497901286 ps
CPU time 1.67 seconds
Started Aug 10 07:08:10 PM PDT 24
Finished Aug 10 07:08:11 PM PDT 24
Peak memory 207480 kb
Host smart-765d571a-21a8-4bca-a49b-2e220ff8c068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29700
12327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2970012327
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3859049437
Short name T359
Test name
Test status
Simulation time 1228540873 ps
CPU time 3.06 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:21 PM PDT 24
Peak memory 207752 kb
Host smart-bf7bb88c-7877-4e83-8ffe-50b6c40797cc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3859049437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3859049437
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.420917839
Short name T3193
Test name
Test status
Simulation time 48236408460 ps
CPU time 79.22 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:09:38 PM PDT 24
Peak memory 207884 kb
Host smart-67b84bae-9c3e-4e50-9b1c-5c3061e72ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
7839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.420917839
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.2670243205
Short name T2783
Test name
Test status
Simulation time 457717609 ps
CPU time 7.94 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:27 PM PDT 24
Peak memory 207756 kb
Host smart-4ce513a9-044b-4710-ad45-b43a1f262043
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670243205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2670243205
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3755367481
Short name T1875
Test name
Test status
Simulation time 822313551 ps
CPU time 2.02 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207556 kb
Host smart-1313f9f6-941d-4671-a5be-054a126cc842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37553
67481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3755367481
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.54392074
Short name T1641
Test name
Test status
Simulation time 156899320 ps
CPU time 0.85 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 207460 kb
Host smart-d9865926-38df-4e4b-bbbb-25000c658052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54392
074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.54392074
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1620721727
Short name T2020
Test name
Test status
Simulation time 35720731 ps
CPU time 0.72 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207532 kb
Host smart-fa4724e3-2323-4877-8f74-fc6db8d860f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16207
21727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1620721727
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.4171286780
Short name T796
Test name
Test status
Simulation time 964602543 ps
CPU time 2.33 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:21 PM PDT 24
Peak memory 207820 kb
Host smart-5551ebf6-d21a-4220-b7e9-58385dc1987c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
86780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.4171286780
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_types.3935053392
Short name T508
Test name
Test status
Simulation time 294655054 ps
CPU time 1.1 seconds
Started Aug 10 07:08:17 PM PDT 24
Finished Aug 10 07:08:18 PM PDT 24
Peak memory 207524 kb
Host smart-9fbdf0e7-b3d9-41ce-8aa6-09b1bae9c047
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3935053392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.3935053392
Directory /workspace/16.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3924092571
Short name T1214
Test name
Test status
Simulation time 412509127 ps
CPU time 2.95 seconds
Started Aug 10 07:08:17 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207620 kb
Host smart-fecc0b3c-4820-48b8-9877-84859d196301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39240
92571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3924092571
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3521030668
Short name T3544
Test name
Test status
Simulation time 241106284 ps
CPU time 1.34 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 215880 kb
Host smart-17e2abe0-abe8-4026-89ea-ede676d882a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3521030668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3521030668
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2627759197
Short name T884
Test name
Test status
Simulation time 147508888 ps
CPU time 0.81 seconds
Started Aug 10 07:08:20 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207576 kb
Host smart-8f94a08a-c8f2-4217-be6e-3a0cb435bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
59197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2627759197
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4151579784
Short name T2581
Test name
Test status
Simulation time 187401500 ps
CPU time 0.96 seconds
Started Aug 10 07:08:20 PM PDT 24
Finished Aug 10 07:08:21 PM PDT 24
Peak memory 207480 kb
Host smart-3e9d145c-e524-4e02-b710-b27e40f01134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41515
79784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4151579784
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2001688511
Short name T1465
Test name
Test status
Simulation time 4549209343 ps
CPU time 43.58 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:09:03 PM PDT 24
Peak memory 218340 kb
Host smart-c14ed62f-c1e9-4155-9c54-b347bf900fd5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2001688511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2001688511
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.1668624573
Short name T2603
Test name
Test status
Simulation time 5753943952 ps
CPU time 70.25 seconds
Started Aug 10 07:08:20 PM PDT 24
Finished Aug 10 07:09:30 PM PDT 24
Peak memory 207736 kb
Host smart-2d7caa16-b401-4d33-98df-99e3544feb83
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1668624573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.1668624573
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2090610297
Short name T2889
Test name
Test status
Simulation time 240046039 ps
CPU time 0.99 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 207484 kb
Host smart-482996d9-a7d3-48d3-9346-cc7fded3327f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20906
10297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2090610297
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3354463164
Short name T100
Test name
Test status
Simulation time 26532809789 ps
CPU time 39.25 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:59 PM PDT 24
Peak memory 207868 kb
Host smart-c7eb05b7-929e-4ba4-a995-30a836c1fb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
63164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3354463164
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2961275066
Short name T2442
Test name
Test status
Simulation time 3575264210 ps
CPU time 5.35 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:24 PM PDT 24
Peak memory 207720 kb
Host smart-46d4eda0-f5f1-43a8-adba-7bf5b101a0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
75066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2961275066
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3531562386
Short name T2374
Test name
Test status
Simulation time 3384220950 ps
CPU time 95.88 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:09:54 PM PDT 24
Peak memory 218600 kb
Host smart-b1b4a3d7-e615-4ee8-ab3d-14a3a6e20953
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3531562386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3531562386
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3297046751
Short name T1863
Test name
Test status
Simulation time 3375257489 ps
CPU time 98.17 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:09:56 PM PDT 24
Peak memory 217404 kb
Host smart-af6b937f-5292-405c-870e-1601c653cdc4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3297046751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3297046751
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.232972954
Short name T543
Test name
Test status
Simulation time 243435256 ps
CPU time 0.99 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 207556 kb
Host smart-be534386-02e6-4222-bdd6-52c9fb217a3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=232972954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.232972954
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.766472199
Short name T746
Test name
Test status
Simulation time 240420497 ps
CPU time 0.98 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207544 kb
Host smart-99df5b83-e54e-4c91-a16f-4ab2b46a91e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76647
2199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.766472199
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.3874035720
Short name T2129
Test name
Test status
Simulation time 1984423568 ps
CPU time 14.44 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:33 PM PDT 24
Peak memory 207844 kb
Host smart-11fe326d-cc46-486b-92ef-393d42e50ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
35720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.3874035720
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.180597013
Short name T1103
Test name
Test status
Simulation time 3316114965 ps
CPU time 33.72 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:53 PM PDT 24
Peak memory 216060 kb
Host smart-3f3dd806-0d25-43ce-affc-02e3a12f142d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=180597013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.180597013
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2957143971
Short name T2471
Test name
Test status
Simulation time 193285277 ps
CPU time 0.89 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 207564 kb
Host smart-fe2fea23-1cac-47e3-bee3-2cd232988dd1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2957143971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2957143971
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1250325334
Short name T3557
Test name
Test status
Simulation time 144137933 ps
CPU time 0.86 seconds
Started Aug 10 07:08:18 PM PDT 24
Finished Aug 10 07:08:19 PM PDT 24
Peak memory 207644 kb
Host smart-e6097ce3-2d86-4fc0-803c-9cc34db2bbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12503
25334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1250325334
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1743339748
Short name T863
Test name
Test status
Simulation time 176685961 ps
CPU time 0.96 seconds
Started Aug 10 07:08:26 PM PDT 24
Finished Aug 10 07:08:27 PM PDT 24
Peak memory 207420 kb
Host smart-4599e0b0-d672-44cc-a11e-bb36e063f840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
39748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1743339748
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1302872414
Short name T1744
Test name
Test status
Simulation time 153679002 ps
CPU time 0.87 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207512 kb
Host smart-f2ed1d03-7994-4db0-b8f5-dbe3fc0a24c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13028
72414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1302872414
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2061679536
Short name T2859
Test name
Test status
Simulation time 178478027 ps
CPU time 0.87 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:30 PM PDT 24
Peak memory 207580 kb
Host smart-2dbc19b6-548b-4d5f-80fd-49b6974711f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
79536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2061679536
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2022731350
Short name T3348
Test name
Test status
Simulation time 151849998 ps
CPU time 0.83 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207592 kb
Host smart-96f8bddc-1ddf-47f9-8810-e8844ebdd56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20227
31350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2022731350
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2858484001
Short name T3200
Test name
Test status
Simulation time 225646862 ps
CPU time 1.06 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207604 kb
Host smart-c2510a86-f7df-4389-b482-3046cdcad538
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2858484001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2858484001
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3552572142
Short name T735
Test name
Test status
Simulation time 191011715 ps
CPU time 0.92 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207520 kb
Host smart-9d11d746-fd14-4353-8d18-8a39c6068f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
72142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3552572142
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2283062739
Short name T2467
Test name
Test status
Simulation time 30353838 ps
CPU time 0.68 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207504 kb
Host smart-08536499-21fd-48f1-b5b2-b6315bf5dd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
62739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2283062739
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1713396975
Short name T3078
Test name
Test status
Simulation time 16367753904 ps
CPU time 39.88 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:09:08 PM PDT 24
Peak memory 216036 kb
Host smart-6bc9d6c9-fb44-45e7-94c3-feadcbccc7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17133
96975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1713396975
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2344765528
Short name T1458
Test name
Test status
Simulation time 186244029 ps
CPU time 0.95 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207564 kb
Host smart-4e67a080-02df-4128-a38c-79865614feb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23447
65528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2344765528
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1394944634
Short name T775
Test name
Test status
Simulation time 173147258 ps
CPU time 0.86 seconds
Started Aug 10 07:08:25 PM PDT 24
Finished Aug 10 07:08:26 PM PDT 24
Peak memory 207516 kb
Host smart-1a645d88-5c3a-46d1-8301-1c451d2ecc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
44634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1394944634
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2955008629
Short name T550
Test name
Test status
Simulation time 233053543 ps
CPU time 0.98 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207556 kb
Host smart-1a89b79d-c77d-4ffb-9ed7-7a64f8fdf8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29550
08629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2955008629
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3181851200
Short name T3149
Test name
Test status
Simulation time 152712749 ps
CPU time 0.88 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207532 kb
Host smart-d275f40a-b8c3-4abe-a37f-41a9b9c01b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
51200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3181851200
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_resume_link_active.1377225716
Short name T103
Test name
Test status
Simulation time 20187720112 ps
CPU time 24.89 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:53 PM PDT 24
Peak memory 207592 kb
Host smart-145de282-8b8e-47f5-86d7-f88f8c925516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13772
25716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_resume_link_active.1377225716
Directory /workspace/16.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3672967628
Short name T1706
Test name
Test status
Simulation time 160045097 ps
CPU time 0.85 seconds
Started Aug 10 07:08:25 PM PDT 24
Finished Aug 10 07:08:26 PM PDT 24
Peak memory 207600 kb
Host smart-a76b0894-9889-455a-914d-07e488dd3f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
67628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3672967628
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_rx_full.172788562
Short name T53
Test name
Test status
Simulation time 335789581 ps
CPU time 1.23 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207576 kb
Host smart-fdd1dbeb-4d13-4612-a007-22ea907eda23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17278
8562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.172788562
Directory /workspace/16.usbdev_rx_full/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2523324046
Short name T2660
Test name
Test status
Simulation time 199797903 ps
CPU time 0.93 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:30 PM PDT 24
Peak memory 207532 kb
Host smart-1bc4e58a-0e98-49f7-be57-4902564b6641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
24046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2523324046
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1653252164
Short name T2149
Test name
Test status
Simulation time 186246869 ps
CPU time 0.89 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207524 kb
Host smart-2701b966-9a9b-4549-8767-8b731c6fbe70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
52164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1653252164
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2909559969
Short name T798
Test name
Test status
Simulation time 255619780 ps
CPU time 1.02 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:08:31 PM PDT 24
Peak memory 207584 kb
Host smart-ca925faa-00d7-4f58-9a00-91805fa14ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
59969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2909559969
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1839684727
Short name T2997
Test name
Test status
Simulation time 2895372816 ps
CPU time 21.86 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:08:52 PM PDT 24
Peak memory 224260 kb
Host smart-d6a53064-080b-4130-a223-37f30e9abd7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1839684727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1839684727
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.31366230
Short name T650
Test name
Test status
Simulation time 195408715 ps
CPU time 0.93 seconds
Started Aug 10 07:08:26 PM PDT 24
Finished Aug 10 07:08:27 PM PDT 24
Peak memory 207584 kb
Host smart-89a3623b-8297-4934-b01b-052912875077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31366
230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.31366230
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.337354415
Short name T1945
Test name
Test status
Simulation time 175549162 ps
CPU time 0.9 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:28 PM PDT 24
Peak memory 207484 kb
Host smart-63838121-44d4-4193-b60a-ead5c233bd38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33735
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.337354415
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3500222490
Short name T912
Test name
Test status
Simulation time 429277803 ps
CPU time 1.33 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:30 PM PDT 24
Peak memory 207552 kb
Host smart-30d6b868-0883-4755-92ea-c6c4621abda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35002
22490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3500222490
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.148968421
Short name T2205
Test name
Test status
Simulation time 2517771627 ps
CPU time 72.25 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:09:42 PM PDT 24
Peak memory 217508 kb
Host smart-33c4e057-ef01-437f-9d97-2cbe0a03acea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14896
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.148968421
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.2971459409
Short name T1869
Test name
Test status
Simulation time 198638525 ps
CPU time 0.89 seconds
Started Aug 10 07:08:19 PM PDT 24
Finished Aug 10 07:08:20 PM PDT 24
Peak memory 207440 kb
Host smart-1a458aa7-24fb-4075-933a-9d17eca20ba2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971459409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.2971459409
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_tx_rx_disruption.3395615239
Short name T3030
Test name
Test status
Simulation time 553756079 ps
CPU time 1.82 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:08:32 PM PDT 24
Peak memory 207600 kb
Host smart-993ca989-967e-4a13-886b-26bd150d90e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395615239 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.usbdev_tx_rx_disruption.3395615239
Directory /workspace/16.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/160.usbdev_tx_rx_disruption.601816204
Short name T1057
Test name
Test status
Simulation time 564666013 ps
CPU time 1.53 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:38 PM PDT 24
Peak memory 207524 kb
Host smart-72d29205-849b-44e7-9a3c-ba891f504973
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601816204 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 160.usbdev_tx_rx_disruption.601816204
Directory /workspace/160.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/161.usbdev_endpoint_types.3314064164
Short name T389
Test name
Test status
Simulation time 689405026 ps
CPU time 1.69 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207472 kb
Host smart-c629fc41-c6f7-4ba3-9150-6e4fc212db2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3314064164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.3314064164
Directory /workspace/161.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/161.usbdev_tx_rx_disruption.517067309
Short name T1815
Test name
Test status
Simulation time 489558607 ps
CPU time 1.56 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:35 PM PDT 24
Peak memory 207512 kb
Host smart-1a49de35-a7a1-4fe4-b23d-9d0d828649bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517067309 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.usbdev_tx_rx_disruption.517067309
Directory /workspace/161.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/162.usbdev_endpoint_types.1890337292
Short name T2121
Test name
Test status
Simulation time 242912734 ps
CPU time 1.01 seconds
Started Aug 10 07:17:33 PM PDT 24
Finished Aug 10 07:17:35 PM PDT 24
Peak memory 207540 kb
Host smart-d2637e2c-d684-46c3-b5eb-552c5cf58a22
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1890337292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.1890337292
Directory /workspace/162.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/162.usbdev_tx_rx_disruption.783549146
Short name T3494
Test name
Test status
Simulation time 581907610 ps
CPU time 1.83 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207568 kb
Host smart-044b8f49-73b1-4564-9821-91d6793832ff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783549146 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 162.usbdev_tx_rx_disruption.783549146
Directory /workspace/162.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/163.usbdev_endpoint_types.3788068133
Short name T2119
Test name
Test status
Simulation time 236712091 ps
CPU time 0.99 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:41 PM PDT 24
Peak memory 207540 kb
Host smart-e31a0853-5c50-4557-b875-1ae2b745654e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3788068133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.3788068133
Directory /workspace/163.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/163.usbdev_tx_rx_disruption.706513928
Short name T2998
Test name
Test status
Simulation time 670489382 ps
CPU time 1.94 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207508 kb
Host smart-c6cf95e2-5128-4b5b-aa94-479778bb3896
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706513928 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 163.usbdev_tx_rx_disruption.706513928
Directory /workspace/163.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/164.usbdev_endpoint_types.938486518
Short name T468
Test name
Test status
Simulation time 595458381 ps
CPU time 1.67 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207500 kb
Host smart-22c64a2f-2315-4b88-829f-ee5e103e51dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=938486518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.938486518
Directory /workspace/164.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/164.usbdev_tx_rx_disruption.1185325588
Short name T2815
Test name
Test status
Simulation time 690820081 ps
CPU time 1.86 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207516 kb
Host smart-780402b7-1528-4deb-8286-7ba7825baca9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185325588 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.usbdev_tx_rx_disruption.1185325588
Directory /workspace/164.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/165.usbdev_endpoint_types.2502112981
Short name T381
Test name
Test status
Simulation time 647428674 ps
CPU time 1.64 seconds
Started Aug 10 07:17:39 PM PDT 24
Finished Aug 10 07:17:41 PM PDT 24
Peak memory 207628 kb
Host smart-0168afaf-835e-4502-8971-05a4e6698024
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2502112981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.2502112981
Directory /workspace/165.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/165.usbdev_tx_rx_disruption.1333323621
Short name T740
Test name
Test status
Simulation time 476471209 ps
CPU time 1.5 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:38 PM PDT 24
Peak memory 207548 kb
Host smart-fdda8e64-2ff0-499e-bf05-11fbc0ffc942
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333323621 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.usbdev_tx_rx_disruption.1333323621
Directory /workspace/165.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/166.usbdev_tx_rx_disruption.4154371254
Short name T2902
Test name
Test status
Simulation time 657137126 ps
CPU time 1.87 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:42 PM PDT 24
Peak memory 207568 kb
Host smart-7459105a-cc7f-4423-9be0-25093580af80
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154371254 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.usbdev_tx_rx_disruption.4154371254
Directory /workspace/166.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/167.usbdev_endpoint_types.3681704848
Short name T2588
Test name
Test status
Simulation time 267523777 ps
CPU time 1.08 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207552 kb
Host smart-e122f6a2-b631-40ac-8a19-eb442f392d31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3681704848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.3681704848
Directory /workspace/167.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/167.usbdev_tx_rx_disruption.4173233405
Short name T2460
Test name
Test status
Simulation time 476993009 ps
CPU time 1.63 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207588 kb
Host smart-161591a5-04cd-4090-9a5d-646378342a9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173233405 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.usbdev_tx_rx_disruption.4173233405
Directory /workspace/167.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/168.usbdev_endpoint_types.612219727
Short name T446
Test name
Test status
Simulation time 269513398 ps
CPU time 1.07 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207512 kb
Host smart-32e57cd8-06da-4c92-86e0-c21f4eed2b42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=612219727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.612219727
Directory /workspace/168.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/168.usbdev_tx_rx_disruption.2109841349
Short name T2302
Test name
Test status
Simulation time 422224323 ps
CPU time 1.32 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:38 PM PDT 24
Peak memory 207456 kb
Host smart-323fec77-2a23-4939-aef2-aef17ffc197a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109841349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.usbdev_tx_rx_disruption.2109841349
Directory /workspace/168.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/169.usbdev_endpoint_types.3744032361
Short name T415
Test name
Test status
Simulation time 513034841 ps
CPU time 1.46 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207524 kb
Host smart-00fab1e2-963d-4ee0-9324-09f726a16f61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3744032361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.3744032361
Directory /workspace/169.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/169.usbdev_tx_rx_disruption.2323621319
Short name T628
Test name
Test status
Simulation time 555537187 ps
CPU time 1.66 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207440 kb
Host smart-ca2a08c7-fcd5-47a1-a3e3-618a5f7519f9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323621319 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.usbdev_tx_rx_disruption.2323621319
Directory /workspace/169.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3381372780
Short name T733
Test name
Test status
Simulation time 35715121 ps
CPU time 0.67 seconds
Started Aug 10 07:08:56 PM PDT 24
Finished Aug 10 07:08:57 PM PDT 24
Peak memory 207596 kb
Host smart-0162dfbb-b02e-4b51-b2fb-c6a768708ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3381372780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3381372780
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3196457879
Short name T245
Test name
Test status
Simulation time 10841977187 ps
CPU time 14.87 seconds
Started Aug 10 07:08:26 PM PDT 24
Finished Aug 10 07:08:41 PM PDT 24
Peak memory 207868 kb
Host smart-3ad16553-6de4-4803-bf8e-9041d76193bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196457879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.3196457879
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3658994801
Short name T1027
Test name
Test status
Simulation time 15202054002 ps
CPU time 18.87 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:48 PM PDT 24
Peak memory 215772 kb
Host smart-8b7afb74-eb81-47c8-a8bb-e9c0e30110f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658994801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3658994801
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3969851415
Short name T3607
Test name
Test status
Simulation time 23862906201 ps
CPU time 29.52 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:58 PM PDT 24
Peak memory 215728 kb
Host smart-8795dcca-d7f6-4914-90a4-63aa27f70984
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969851415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.3969851415
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2871006795
Short name T3629
Test name
Test status
Simulation time 178260723 ps
CPU time 0.96 seconds
Started Aug 10 07:08:30 PM PDT 24
Finished Aug 10 07:08:31 PM PDT 24
Peak memory 207400 kb
Host smart-ee043573-6517-4877-a440-1eac0bee8255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28710
06795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2871006795
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4168236213
Short name T3413
Test name
Test status
Simulation time 162243273 ps
CPU time 0.87 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:08:29 PM PDT 24
Peak memory 207500 kb
Host smart-87e49214-95e9-41aa-96ab-58fc65297c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41682
36213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4168236213
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.881479687
Short name T1247
Test name
Test status
Simulation time 224502112 ps
CPU time 1.01 seconds
Started Aug 10 07:08:29 PM PDT 24
Finished Aug 10 07:08:30 PM PDT 24
Peak memory 207580 kb
Host smart-757827b5-db9a-4601-81b0-5bce6c4fb202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88147
9687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.881479687
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4195012379
Short name T2084
Test name
Test status
Simulation time 964821187 ps
CPU time 2.56 seconds
Started Aug 10 07:08:27 PM PDT 24
Finished Aug 10 07:08:30 PM PDT 24
Peak memory 207740 kb
Host smart-f4811ac9-dad7-49ce-bbf8-25cfae8bcc39
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4195012379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4195012379
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3270062095
Short name T1606
Test name
Test status
Simulation time 21381417030 ps
CPU time 33.94 seconds
Started Aug 10 07:08:28 PM PDT 24
Finished Aug 10 07:09:02 PM PDT 24
Peak memory 207836 kb
Host smart-05e2d1cb-8c34-4ea0-beec-9821ad432030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32700
62095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3270062095
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.3351029554
Short name T2153
Test name
Test status
Simulation time 2473063202 ps
CPU time 22.05 seconds
Started Aug 10 07:08:34 PM PDT 24
Finished Aug 10 07:08:57 PM PDT 24
Peak memory 207832 kb
Host smart-d6073064-cf02-49fb-a26b-b393fdfc753d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351029554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.3351029554
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1043968308
Short name T1422
Test name
Test status
Simulation time 856255461 ps
CPU time 2.08 seconds
Started Aug 10 07:08:35 PM PDT 24
Finished Aug 10 07:08:38 PM PDT 24
Peak memory 207540 kb
Host smart-0b5f2f26-ebfe-48e9-9cce-65b7396dbd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10439
68308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1043968308
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1513419612
Short name T2873
Test name
Test status
Simulation time 233808957 ps
CPU time 0.95 seconds
Started Aug 10 07:08:36 PM PDT 24
Finished Aug 10 07:08:37 PM PDT 24
Peak memory 207508 kb
Host smart-b25ba5fd-716f-4b86-a5df-38e576c8a0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15134
19612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1513419612
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2887762371
Short name T2553
Test name
Test status
Simulation time 63495244 ps
CPU time 0.77 seconds
Started Aug 10 07:08:34 PM PDT 24
Finished Aug 10 07:08:35 PM PDT 24
Peak memory 207472 kb
Host smart-ce99a5ef-ee78-4664-a143-336d3417b7c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28877
62371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2887762371
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1906769465
Short name T1201
Test name
Test status
Simulation time 1009383267 ps
CPU time 2.66 seconds
Started Aug 10 07:08:35 PM PDT 24
Finished Aug 10 07:08:38 PM PDT 24
Peak memory 207792 kb
Host smart-e1bff640-57a3-44bb-ae00-d23c70e9c94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067
69465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1906769465
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4247549930
Short name T556
Test name
Test status
Simulation time 280190897 ps
CPU time 2.31 seconds
Started Aug 10 07:08:35 PM PDT 24
Finished Aug 10 07:08:38 PM PDT 24
Peak memory 207724 kb
Host smart-0c07d500-be61-4395-a73a-5e22a2b4c28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42475
49930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4247549930
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1633197831
Short name T1345
Test name
Test status
Simulation time 154478421 ps
CPU time 0.88 seconds
Started Aug 10 07:08:35 PM PDT 24
Finished Aug 10 07:08:36 PM PDT 24
Peak memory 207460 kb
Host smart-88aeaa62-4bd3-4581-9d8f-2de79e8a2d75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1633197831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1633197831
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.690980384
Short name T3597
Test name
Test status
Simulation time 145004586 ps
CPU time 0.82 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207564 kb
Host smart-94f37f31-e420-4790-8d5e-dcc0e457d949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69098
0384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.690980384
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3037353086
Short name T1372
Test name
Test status
Simulation time 201480053 ps
CPU time 0.93 seconds
Started Aug 10 07:08:43 PM PDT 24
Finished Aug 10 07:08:44 PM PDT 24
Peak memory 207572 kb
Host smart-30797f1e-e86c-4489-ae36-53cf0814ea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30373
53086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3037353086
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.2160077958
Short name T3201
Test name
Test status
Simulation time 3804515394 ps
CPU time 38.52 seconds
Started Aug 10 07:08:36 PM PDT 24
Finished Aug 10 07:09:14 PM PDT 24
Peak memory 218516 kb
Host smart-8a9cf92a-736b-4c76-b9a5-09150fd70abd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2160077958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.2160077958
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1015074017
Short name T3593
Test name
Test status
Simulation time 6391637392 ps
CPU time 83.4 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 207740 kb
Host smart-c006c1d1-4f84-41ca-bdc0-615292df6bb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1015074017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1015074017
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3626226910
Short name T3487
Test name
Test status
Simulation time 163319672 ps
CPU time 0.89 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207608 kb
Host smart-40491554-49ce-41a5-a8cc-6f82278b80fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
26910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3626226910
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3469353224
Short name T2071
Test name
Test status
Simulation time 7278596159 ps
CPU time 10.97 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:55 PM PDT 24
Peak memory 207864 kb
Host smart-593219d7-760f-4dd4-b021-970ee48d2e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34693
53224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3469353224
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2625744240
Short name T3272
Test name
Test status
Simulation time 11209548712 ps
CPU time 14.41 seconds
Started Aug 10 07:08:43 PM PDT 24
Finished Aug 10 07:08:58 PM PDT 24
Peak memory 207776 kb
Host smart-0e707cf4-c9ea-434d-a722-078bce206687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257
44240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2625744240
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.527753854
Short name T764
Test name
Test status
Simulation time 2448590854 ps
CPU time 24.9 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:09:09 PM PDT 24
Peak memory 218556 kb
Host smart-c6efaf68-1896-414f-be2b-e015e2a145a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=527753854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.527753854
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3306345405
Short name T3026
Test name
Test status
Simulation time 2276342433 ps
CPU time 22.11 seconds
Started Aug 10 07:08:43 PM PDT 24
Finished Aug 10 07:09:05 PM PDT 24
Peak memory 216084 kb
Host smart-e6a770f3-cb65-40f4-a6bf-5fdce385581f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3306345405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3306345405
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.703788063
Short name T2722
Test name
Test status
Simulation time 269917408 ps
CPU time 1.12 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207416 kb
Host smart-4b5e80ae-2461-44e7-b10e-2d7b17178a2c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=703788063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.703788063
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2074631225
Short name T1220
Test name
Test status
Simulation time 199494096 ps
CPU time 0.94 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207564 kb
Host smart-24559955-edb0-4918-8d98-45aeeb91613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
31225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2074631225
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.1361887121
Short name T1123
Test name
Test status
Simulation time 3248665831 ps
CPU time 24.27 seconds
Started Aug 10 07:08:43 PM PDT 24
Finished Aug 10 07:09:07 PM PDT 24
Peak memory 224276 kb
Host smart-0828ac56-986c-4462-9a32-fe4ac1b0b198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
87121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.1361887121
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2189597470
Short name T646
Test name
Test status
Simulation time 2779473218 ps
CPU time 21.71 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 218048 kb
Host smart-886e11fe-b017-4155-b8e9-68f4483cada3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2189597470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2189597470
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1541830010
Short name T3171
Test name
Test status
Simulation time 160621142 ps
CPU time 0.85 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207600 kb
Host smart-8ae5de0e-ce03-4af2-8ee5-0cafbbd2c691
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1541830010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1541830010
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2175094243
Short name T1544
Test name
Test status
Simulation time 138741799 ps
CPU time 0.84 seconds
Started Aug 10 07:08:48 PM PDT 24
Finished Aug 10 07:08:49 PM PDT 24
Peak memory 207640 kb
Host smart-54e79166-6b14-4277-9e1c-7fe228dacd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750
94243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2175094243
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1691906383
Short name T1348
Test name
Test status
Simulation time 161481394 ps
CPU time 0.84 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207416 kb
Host smart-c65ded80-31fa-4c15-b626-372ac3b0abc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
06383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1691906383
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.172119723
Short name T2841
Test name
Test status
Simulation time 158846958 ps
CPU time 0.82 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207536 kb
Host smart-bbb9aa26-afd8-48c5-843d-614e66217a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17211
9723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.172119723
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.552323764
Short name T1455
Test name
Test status
Simulation time 189607962 ps
CPU time 0.89 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207612 kb
Host smart-74136af8-27ec-4b71-976c-9892c26715be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55232
3764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.552323764
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1065309654
Short name T3191
Test name
Test status
Simulation time 153563485 ps
CPU time 0.92 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207420 kb
Host smart-80ba304f-18f4-40f7-b9dd-968a39841102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10653
09654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1065309654
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1754636285
Short name T1843
Test name
Test status
Simulation time 170429709 ps
CPU time 0.91 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207500 kb
Host smart-747d52d1-d65e-44ad-89bc-30e018810b03
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1754636285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1754636285
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1984574045
Short name T1305
Test name
Test status
Simulation time 160601049 ps
CPU time 0.87 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207452 kb
Host smart-f1fcf985-40c5-4f18-a716-218d58ed6aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
74045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1984574045
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.251407135
Short name T1118
Test name
Test status
Simulation time 68522174 ps
CPU time 0.72 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207504 kb
Host smart-0715f3d3-180f-47f4-a670-e49846f9fbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25140
7135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.251407135
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1676127601
Short name T3141
Test name
Test status
Simulation time 22670725394 ps
CPU time 56.17 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:09:42 PM PDT 24
Peak memory 216040 kb
Host smart-0e651acb-b99b-40ec-aa3e-11e33332283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
27601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1676127601
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.4215676706
Short name T2508
Test name
Test status
Simulation time 165514365 ps
CPU time 0.87 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207580 kb
Host smart-b2cd35f2-e847-4923-acbd-6574594eb92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42156
76706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.4215676706
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.968194601
Short name T1864
Test name
Test status
Simulation time 219186595 ps
CPU time 0.95 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207532 kb
Host smart-1353e08d-1dad-49ff-9d7d-4bc4ee492dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96819
4601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.968194601
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1535005497
Short name T2198
Test name
Test status
Simulation time 237588757 ps
CPU time 1 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207404 kb
Host smart-d787f43a-e9e6-4b5d-9031-eade53d0bde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
05497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1535005497
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3320394495
Short name T686
Test name
Test status
Simulation time 171725034 ps
CPU time 0.88 seconds
Started Aug 10 07:08:48 PM PDT 24
Finished Aug 10 07:08:48 PM PDT 24
Peak memory 207608 kb
Host smart-e662824f-8768-4811-ad23-65e31aa42b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33203
94495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3320394495
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_resume_link_active.4111825770
Short name T1831
Test name
Test status
Simulation time 20228186271 ps
CPU time 26.06 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:09:13 PM PDT 24
Peak memory 207632 kb
Host smart-8d3104e0-c12c-476e-824b-6c0b61749a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41118
25770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_resume_link_active.4111825770
Directory /workspace/17.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2970404692
Short name T2657
Test name
Test status
Simulation time 158968413 ps
CPU time 0.8 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207532 kb
Host smart-5d7c3b8a-a475-48c3-ac82-4764cf57895c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704
04692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2970404692
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_rx_full.1158574760
Short name T2295
Test name
Test status
Simulation time 368713335 ps
CPU time 1.21 seconds
Started Aug 10 07:08:46 PM PDT 24
Finished Aug 10 07:08:47 PM PDT 24
Peak memory 207480 kb
Host smart-5de8ac4c-f3b0-4aa4-81c0-343ef396e714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
74760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.1158574760
Directory /workspace/17.usbdev_rx_full/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3745965976
Short name T2044
Test name
Test status
Simulation time 172349434 ps
CPU time 0.91 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207512 kb
Host smart-d59539c9-d3e6-4d37-b98a-30dea7fd25fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
65976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3745965976
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2714291825
Short name T2740
Test name
Test status
Simulation time 168550053 ps
CPU time 0.89 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:08:45 PM PDT 24
Peak memory 207516 kb
Host smart-a22d0193-ed11-4585-9dcc-efcba1d7d82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
91825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2714291825
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3778969393
Short name T1586
Test name
Test status
Simulation time 227787482 ps
CPU time 1.02 seconds
Started Aug 10 07:08:47 PM PDT 24
Finished Aug 10 07:08:48 PM PDT 24
Peak memory 207552 kb
Host smart-336cc82d-9221-4609-9f8e-5069b5fcce1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37789
69393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3778969393
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.319595247
Short name T3079
Test name
Test status
Simulation time 2552930393 ps
CPU time 75.36 seconds
Started Aug 10 07:08:44 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 217896 kb
Host smart-69e146cc-8161-4619-b748-d08d9d922701
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=319595247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.319595247
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.341793017
Short name T1690
Test name
Test status
Simulation time 183387588 ps
CPU time 0.87 seconds
Started Aug 10 07:08:45 PM PDT 24
Finished Aug 10 07:08:46 PM PDT 24
Peak memory 207424 kb
Host smart-8eb6662f-51b3-483b-b9bd-2bd3fd8320f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34179
3017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.341793017
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3098786721
Short name T2542
Test name
Test status
Simulation time 218365149 ps
CPU time 0.89 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:08:54 PM PDT 24
Peak memory 207560 kb
Host smart-1488e2a6-1e3b-4619-b538-35cfff370dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30987
86721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3098786721
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.728244850
Short name T1837
Test name
Test status
Simulation time 1233530368 ps
CPU time 2.72 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:08:57 PM PDT 24
Peak memory 207656 kb
Host smart-ff063ba1-76dd-490e-b923-2e50e9d56dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72824
4850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.728244850
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2183127045
Short name T1256
Test name
Test status
Simulation time 2786753355 ps
CPU time 30.41 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:09:25 PM PDT 24
Peak memory 217728 kb
Host smart-f32767b9-d374-4599-91dd-c13602b679fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21831
27045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2183127045
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4114358959
Short name T3621
Test name
Test status
Simulation time 2571929139 ps
CPU time 17.37 seconds
Started Aug 10 07:08:35 PM PDT 24
Finished Aug 10 07:08:52 PM PDT 24
Peak memory 208008 kb
Host smart-d5a964fd-075a-4c0d-b9cd-0444f10c1fb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114358959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.4114358959
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_tx_rx_disruption.3843362125
Short name T974
Test name
Test status
Simulation time 582973430 ps
CPU time 1.55 seconds
Started Aug 10 07:08:53 PM PDT 24
Finished Aug 10 07:08:55 PM PDT 24
Peak memory 207544 kb
Host smart-8160bb97-0c24-4e28-a2b6-1a27332b4d98
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843362125 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.usbdev_tx_rx_disruption.3843362125
Directory /workspace/17.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/170.usbdev_tx_rx_disruption.4196480419
Short name T2834
Test name
Test status
Simulation time 560391881 ps
CPU time 1.63 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:41 PM PDT 24
Peak memory 207528 kb
Host smart-7b87b5cc-739d-458c-9537-be3b0631c803
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196480419 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.usbdev_tx_rx_disruption.4196480419
Directory /workspace/170.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/171.usbdev_endpoint_types.1825876642
Short name T2739
Test name
Test status
Simulation time 199213075 ps
CPU time 0.99 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207536 kb
Host smart-df967fb0-8ab0-457c-b59f-2ad2d624bd72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1825876642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.1825876642
Directory /workspace/171.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/171.usbdev_tx_rx_disruption.3405334991
Short name T2150
Test name
Test status
Simulation time 554086153 ps
CPU time 1.81 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207556 kb
Host smart-3750b3f4-b622-4e5e-a0bd-3b33a683f742
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405334991 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.usbdev_tx_rx_disruption.3405334991
Directory /workspace/171.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/172.usbdev_endpoint_types.34246809
Short name T452
Test name
Test status
Simulation time 546431628 ps
CPU time 1.48 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207508 kb
Host smart-7055f321-1cf7-4048-82d5-cb943b3a09e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=34246809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.34246809
Directory /workspace/172.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/172.usbdev_tx_rx_disruption.198501940
Short name T2592
Test name
Test status
Simulation time 581017271 ps
CPU time 1.61 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207604 kb
Host smart-31bd49bc-c114-45ea-b86f-9734930c9d8f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198501940 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 172.usbdev_tx_rx_disruption.198501940
Directory /workspace/172.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/173.usbdev_endpoint_types.3321631393
Short name T2075
Test name
Test status
Simulation time 272718782 ps
CPU time 0.99 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:35 PM PDT 24
Peak memory 207424 kb
Host smart-04bdc102-9869-4513-8a0e-959d2e68751d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3321631393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.3321631393
Directory /workspace/173.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/173.usbdev_tx_rx_disruption.2036750488
Short name T2375
Test name
Test status
Simulation time 485016532 ps
CPU time 1.59 seconds
Started Aug 10 07:17:39 PM PDT 24
Finished Aug 10 07:17:41 PM PDT 24
Peak memory 207600 kb
Host smart-148efb8e-c227-4c57-96bc-e1681ccec87f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036750488 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.usbdev_tx_rx_disruption.2036750488
Directory /workspace/173.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/174.usbdev_endpoint_types.3342471365
Short name T512
Test name
Test status
Simulation time 155763610 ps
CPU time 0.97 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:41 PM PDT 24
Peak memory 207492 kb
Host smart-aa6d8267-0b10-455b-a0a2-7907ddfbc3d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3342471365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.3342471365
Directory /workspace/174.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/174.usbdev_tx_rx_disruption.3053250025
Short name T1339
Test name
Test status
Simulation time 530550039 ps
CPU time 1.64 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207556 kb
Host smart-925d9182-5221-4e6b-b7e0-35aec92294c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053250025 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.usbdev_tx_rx_disruption.3053250025
Directory /workspace/174.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/175.usbdev_endpoint_types.3111711659
Short name T499
Test name
Test status
Simulation time 286990548 ps
CPU time 1.01 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207492 kb
Host smart-e5a7b527-44dd-4249-bd46-40ed2a31ba6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3111711659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.3111711659
Directory /workspace/175.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/175.usbdev_tx_rx_disruption.1051003508
Short name T2681
Test name
Test status
Simulation time 546762548 ps
CPU time 1.8 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207520 kb
Host smart-8dd982ef-04a6-410b-a7c5-6ed205d9ff75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051003508 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.usbdev_tx_rx_disruption.1051003508
Directory /workspace/175.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/176.usbdev_endpoint_types.2880970673
Short name T403
Test name
Test status
Simulation time 669786632 ps
CPU time 1.98 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:40 PM PDT 24
Peak memory 207472 kb
Host smart-203d8b02-1b78-4c07-ba37-9543fbd159a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2880970673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.2880970673
Directory /workspace/176.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/176.usbdev_tx_rx_disruption.3444903744
Short name T2871
Test name
Test status
Simulation time 517786138 ps
CPU time 1.65 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207420 kb
Host smart-46a93810-8de5-4573-aaa3-0a6e4e1ceabd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444903744 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.usbdev_tx_rx_disruption.3444903744
Directory /workspace/176.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/177.usbdev_endpoint_types.2859541118
Short name T980
Test name
Test status
Simulation time 170552564 ps
CPU time 0.9 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207516 kb
Host smart-cf58e47c-5b9b-41e8-ad47-7b8331e1efcf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2859541118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.2859541118
Directory /workspace/177.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/177.usbdev_tx_rx_disruption.2243330634
Short name T2465
Test name
Test status
Simulation time 506707965 ps
CPU time 1.45 seconds
Started Aug 10 07:17:34 PM PDT 24
Finished Aug 10 07:17:35 PM PDT 24
Peak memory 207476 kb
Host smart-2b3f8968-2629-44fb-be8f-af130db6bd35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243330634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.usbdev_tx_rx_disruption.2243330634
Directory /workspace/177.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/178.usbdev_endpoint_types.345619148
Short name T113
Test name
Test status
Simulation time 316546714 ps
CPU time 1.17 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207544 kb
Host smart-2cf4b833-29ab-4ffd-9ebe-68922b9817fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=345619148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.345619148
Directory /workspace/178.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/178.usbdev_tx_rx_disruption.1572520163
Short name T175
Test name
Test status
Simulation time 512339315 ps
CPU time 1.63 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207552 kb
Host smart-41aac2b5-194b-4c26-ae97-66d702a4dd8b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572520163 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.usbdev_tx_rx_disruption.1572520163
Directory /workspace/178.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/179.usbdev_endpoint_types.3615830215
Short name T501
Test name
Test status
Simulation time 189531663 ps
CPU time 1.04 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207628 kb
Host smart-79cf484e-cc36-450a-ad1f-5bee4e4d6447
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3615830215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.3615830215
Directory /workspace/179.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/179.usbdev_tx_rx_disruption.1586519856
Short name T3223
Test name
Test status
Simulation time 474514282 ps
CPU time 1.46 seconds
Started Aug 10 07:17:35 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207584 kb
Host smart-c144fd3f-8289-4ec9-88b0-696b17915a20
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586519856 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.usbdev_tx_rx_disruption.1586519856
Directory /workspace/179.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1799763290
Short name T3372
Test name
Test status
Simulation time 91749450 ps
CPU time 0.77 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:14 PM PDT 24
Peak memory 207544 kb
Host smart-69d1b7ad-8eda-455a-bac3-1e85550372d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1799763290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1799763290
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2617622850
Short name T2257
Test name
Test status
Simulation time 6311734060 ps
CPU time 8.77 seconds
Started Aug 10 07:09:00 PM PDT 24
Finished Aug 10 07:09:09 PM PDT 24
Peak memory 215980 kb
Host smart-ba0547cc-f29b-427f-8d3a-6292d09fbd3b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617622850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.2617622850
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3739551682
Short name T1203
Test name
Test status
Simulation time 19923840385 ps
CPU time 23.47 seconds
Started Aug 10 07:09:00 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207804 kb
Host smart-546adcde-472a-4df7-a022-202a37d6d6cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739551682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3739551682
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2028016232
Short name T1942
Test name
Test status
Simulation time 24784269676 ps
CPU time 28.7 seconds
Started Aug 10 07:08:55 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 215992 kb
Host smart-b0cb6630-43a8-4060-a835-ae90af836369
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028016232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.2028016232
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1046161276
Short name T2524
Test name
Test status
Simulation time 167142573 ps
CPU time 0.96 seconds
Started Aug 10 07:08:59 PM PDT 24
Finished Aug 10 07:09:00 PM PDT 24
Peak memory 207520 kb
Host smart-183cb822-4ceb-4702-95c6-6076e3997050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10461
61276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1046161276
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3721973904
Short name T2093
Test name
Test status
Simulation time 248757085 ps
CPU time 1.04 seconds
Started Aug 10 07:08:56 PM PDT 24
Finished Aug 10 07:08:57 PM PDT 24
Peak memory 207420 kb
Host smart-744acdc0-aa12-4705-9823-920b4562ab51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
73904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3721973904
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.778599791
Short name T3103
Test name
Test status
Simulation time 555890384 ps
CPU time 1.66 seconds
Started Aug 10 07:08:56 PM PDT 24
Finished Aug 10 07:08:58 PM PDT 24
Peak memory 207564 kb
Host smart-c964cc70-0ed8-4181-a7fb-28c52bf3ac41
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=778599791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.778599791
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2730717137
Short name T2621
Test name
Test status
Simulation time 44468161071 ps
CPU time 72.04 seconds
Started Aug 10 07:08:56 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 207696 kb
Host smart-d3c26597-f511-44b2-9d57-ab29cc1ccaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
17137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2730717137
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.708318709
Short name T3490
Test name
Test status
Simulation time 176828152 ps
CPU time 0.88 seconds
Started Aug 10 07:08:55 PM PDT 24
Finished Aug 10 07:08:56 PM PDT 24
Peak memory 207520 kb
Host smart-c2c92da5-e149-4e75-b1ba-76d6429f5525
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708318709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.708318709
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.4079916877
Short name T2349
Test name
Test status
Simulation time 624578736 ps
CPU time 1.6 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:08:56 PM PDT 24
Peak memory 207388 kb
Host smart-31e0cddd-b551-4300-8ed8-c12334c6d267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799
16877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.4079916877
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.958560282
Short name T3407
Test name
Test status
Simulation time 155015866 ps
CPU time 0.8 seconds
Started Aug 10 07:08:55 PM PDT 24
Finished Aug 10 07:08:56 PM PDT 24
Peak memory 207528 kb
Host smart-869e2065-25b9-4dbc-9675-3e3ed5b1b80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95856
0282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.958560282
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2398068664
Short name T1810
Test name
Test status
Simulation time 29901438 ps
CPU time 0.69 seconds
Started Aug 10 07:08:52 PM PDT 24
Finished Aug 10 07:08:53 PM PDT 24
Peak memory 207456 kb
Host smart-a4ddb89f-c368-4d45-986c-650b44289161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23980
68664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2398068664
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2933794675
Short name T1787
Test name
Test status
Simulation time 861471822 ps
CPU time 2.48 seconds
Started Aug 10 07:08:52 PM PDT 24
Finished Aug 10 07:08:54 PM PDT 24
Peak memory 207772 kb
Host smart-7f92d02d-5f2e-4849-b02e-d6cb61da19ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337
94675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2933794675
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_types.4181810341
Short name T1236
Test name
Test status
Simulation time 214846462 ps
CPU time 0.98 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:08:55 PM PDT 24
Peak memory 207572 kb
Host smart-4ee5736c-522a-4347-8d16-34b1515989ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4181810341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.4181810341
Directory /workspace/18.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3785786018
Short name T230
Test name
Test status
Simulation time 165922334 ps
CPU time 1.6 seconds
Started Aug 10 07:08:53 PM PDT 24
Finished Aug 10 07:08:54 PM PDT 24
Peak memory 207764 kb
Host smart-dff85934-25a9-4e65-af50-e6ff90821c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37857
86018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3785786018
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.802757343
Short name T3519
Test name
Test status
Simulation time 222976924 ps
CPU time 1.05 seconds
Started Aug 10 07:08:53 PM PDT 24
Finished Aug 10 07:08:54 PM PDT 24
Peak memory 224104 kb
Host smart-28e964bc-64da-46b5-ab38-70379976dccd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=802757343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.802757343
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.563736764
Short name T1796
Test name
Test status
Simulation time 139337351 ps
CPU time 0.84 seconds
Started Aug 10 07:09:00 PM PDT 24
Finished Aug 10 07:09:01 PM PDT 24
Peak memory 207488 kb
Host smart-db829495-1968-4c22-b9ce-26ad6576b38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56373
6764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.563736764
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3797010722
Short name T1535
Test name
Test status
Simulation time 239377380 ps
CPU time 1.04 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:08:55 PM PDT 24
Peak memory 207536 kb
Host smart-25dfd070-2b3d-4a71-81ff-26605de9c522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
10722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3797010722
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.3282773096
Short name T2469
Test name
Test status
Simulation time 4941209374 ps
CPU time 141.56 seconds
Started Aug 10 07:08:53 PM PDT 24
Finished Aug 10 07:11:15 PM PDT 24
Peak memory 218556 kb
Host smart-e0876927-faa1-4e9f-a572-52daedd83d9f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3282773096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.3282773096
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.3542314833
Short name T3388
Test name
Test status
Simulation time 13280088200 ps
CPU time 90.91 seconds
Started Aug 10 07:08:56 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207812 kb
Host smart-c0cf6643-5bfa-4f81-abd6-37db846b4c6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3542314833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3542314833
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1719731754
Short name T2515
Test name
Test status
Simulation time 228753193 ps
CPU time 0.95 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 207608 kb
Host smart-5c581165-b753-4fc6-9802-1ea9527ce2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17197
31754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1719731754
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3471677886
Short name T3445
Test name
Test status
Simulation time 9903555450 ps
CPU time 15.12 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:18 PM PDT 24
Peak memory 216148 kb
Host smart-749297f8-2ad2-478b-a387-ab2f5755cb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34716
77886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3471677886
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3830140349
Short name T2329
Test name
Test status
Simulation time 11025064967 ps
CPU time 15.81 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:21 PM PDT 24
Peak memory 207876 kb
Host smart-3dd523c6-be8d-41f3-8f85-acc8620d4bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38301
40349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3830140349
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2672447342
Short name T2829
Test name
Test status
Simulation time 3373634934 ps
CPU time 34.7 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:39 PM PDT 24
Peak memory 216032 kb
Host smart-56a6da6d-9615-4ca2-91bf-6daada80e212
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2672447342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2672447342
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3797768940
Short name T2435
Test name
Test status
Simulation time 3176607533 ps
CPU time 24.45 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:28 PM PDT 24
Peak memory 217852 kb
Host smart-7f9af38e-a91f-407c-83f8-a3db5c2c3dc0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3797768940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3797768940
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2194670944
Short name T3461
Test name
Test status
Simulation time 261897461 ps
CPU time 1.06 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 207600 kb
Host smart-1b21369e-314c-489b-aba3-6c4ea69f7d83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2194670944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2194670944
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.4122364195
Short name T3310
Test name
Test status
Simulation time 197362162 ps
CPU time 0.92 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:04 PM PDT 24
Peak memory 207436 kb
Host smart-faeaf293-b7ba-4e86-8da0-fc170fab41ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
64195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.4122364195
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.1774339005
Short name T3287
Test name
Test status
Simulation time 4132333801 ps
CPU time 109.13 seconds
Started Aug 10 07:09:02 PM PDT 24
Finished Aug 10 07:10:51 PM PDT 24
Peak memory 217824 kb
Host smart-c0384b3b-f21a-467a-b3ef-e5a2a8399f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
39005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.1774339005
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.684715307
Short name T1883
Test name
Test status
Simulation time 2062674721 ps
CPU time 21.44 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:26 PM PDT 24
Peak memory 216672 kb
Host smart-dcea9942-48cf-49ba-8e3a-56ac4c145ce1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=684715307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.684715307
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1552414291
Short name T2916
Test name
Test status
Simulation time 177033982 ps
CPU time 0.89 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:04 PM PDT 24
Peak memory 207592 kb
Host smart-a8373faf-fd9b-47ba-a513-bbd786cbd15a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1552414291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1552414291
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1941370850
Short name T1539
Test name
Test status
Simulation time 153869763 ps
CPU time 0.85 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 207528 kb
Host smart-76945505-b006-4422-8c44-05330b69ed50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19413
70850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1941370850
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1626174355
Short name T1758
Test name
Test status
Simulation time 196741233 ps
CPU time 0.95 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:04 PM PDT 24
Peak memory 207496 kb
Host smart-ef17183e-da1a-4de6-bdc0-a4526805241c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261
74355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1626174355
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.566940911
Short name T2363
Test name
Test status
Simulation time 191436175 ps
CPU time 0.91 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:05 PM PDT 24
Peak memory 207536 kb
Host smart-91fa74b6-d55c-4b0b-97ed-4a1590f745a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56694
0911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.566940911
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.579786952
Short name T3572
Test name
Test status
Simulation time 177416174 ps
CPU time 0.86 seconds
Started Aug 10 07:09:06 PM PDT 24
Finished Aug 10 07:09:07 PM PDT 24
Peak memory 207576 kb
Host smart-d6537c27-ba0e-4d2b-b748-a520c4c4b2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57978
6952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.579786952
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3306289250
Short name T3336
Test name
Test status
Simulation time 147258737 ps
CPU time 0.8 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 207464 kb
Host smart-b1356f6c-fea5-45dc-b593-8aa80d082239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33062
89250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3306289250
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.367012989
Short name T1102
Test name
Test status
Simulation time 233935962 ps
CPU time 0.99 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:05 PM PDT 24
Peak memory 207496 kb
Host smart-d1b9101c-81be-48db-b2e3-ec7cd771a76e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=367012989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.367012989
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2534452570
Short name T932
Test name
Test status
Simulation time 147972393 ps
CPU time 0.81 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:05 PM PDT 24
Peak memory 207512 kb
Host smart-c31e4604-d90b-4966-b740-36cc624da880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
52570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2534452570
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1966772470
Short name T2266
Test name
Test status
Simulation time 62591272 ps
CPU time 0.72 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:04 PM PDT 24
Peak memory 207408 kb
Host smart-23163f89-c897-42a8-ba87-7e1ea1cd053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19667
72470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1966772470
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.169596914
Short name T302
Test name
Test status
Simulation time 7998608689 ps
CPU time 19.17 seconds
Started Aug 10 07:09:03 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 216012 kb
Host smart-7e8af8e4-edab-4622-af70-0e9ac3eb1661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16959
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.169596914
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3815748914
Short name T1129
Test name
Test status
Simulation time 189284177 ps
CPU time 0.95 seconds
Started Aug 10 07:09:05 PM PDT 24
Finished Aug 10 07:09:06 PM PDT 24
Peak memory 207540 kb
Host smart-5311149a-b0c6-4537-9a78-55a568ffc8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
48914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3815748914
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2826472379
Short name T1260
Test name
Test status
Simulation time 205278793 ps
CPU time 1.01 seconds
Started Aug 10 07:09:04 PM PDT 24
Finished Aug 10 07:09:05 PM PDT 24
Peak memory 207524 kb
Host smart-6b788ef7-2b4f-4a06-92fc-06ae59886551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28264
72379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2826472379
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2521941249
Short name T2644
Test name
Test status
Simulation time 266280483 ps
CPU time 0.99 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207544 kb
Host smart-28098e26-1296-4737-825b-5b2e5940dffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25219
41249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2521941249
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.419179782
Short name T2926
Test name
Test status
Simulation time 168838211 ps
CPU time 0.86 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207532 kb
Host smart-f9e8d2d2-61eb-4bc0-8ad2-bcc1790eb668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
9782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.419179782
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_resume_link_active.3028563110
Short name T1078
Test name
Test status
Simulation time 20247986119 ps
CPU time 24.42 seconds
Started Aug 10 07:09:12 PM PDT 24
Finished Aug 10 07:09:37 PM PDT 24
Peak memory 207604 kb
Host smart-6ac2d42e-eca4-48e8-9d77-580a6cbbec3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30285
63110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_resume_link_active.3028563110
Directory /workspace/18.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.180721836
Short name T3005
Test name
Test status
Simulation time 163386362 ps
CPU time 0.81 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:14 PM PDT 24
Peak memory 207572 kb
Host smart-c4b4acf2-d478-4692-9c7c-0932159f3d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
1836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.180721836
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_rx_full.1074780526
Short name T353
Test name
Test status
Simulation time 366725426 ps
CPU time 1.38 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207508 kb
Host smart-30c39176-21ba-407b-a5f7-863b2462d3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
80526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.1074780526
Directory /workspace/18.usbdev_rx_full/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4056474570
Short name T1681
Test name
Test status
Simulation time 194196590 ps
CPU time 0.93 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207540 kb
Host smart-9f8a2028-90c1-4303-af92-2b189079e047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
74570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4056474570
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1362254098
Short name T2845
Test name
Test status
Simulation time 149628246 ps
CPU time 0.82 seconds
Started Aug 10 07:09:11 PM PDT 24
Finished Aug 10 07:09:12 PM PDT 24
Peak memory 207596 kb
Host smart-6aadd14a-62e4-4b9c-8a7b-90b0899ff12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622
54098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1362254098
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.529215056
Short name T2935
Test name
Test status
Simulation time 226201783 ps
CPU time 0.99 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 207580 kb
Host smart-33a77e22-55b8-4f51-8ee2-35a1648d493b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52921
5056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.529215056
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.4143913
Short name T1783
Test name
Test status
Simulation time 2886561664 ps
CPU time 84.96 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:10:38 PM PDT 24
Peak memory 216112 kb
Host smart-76f7dddc-1a0e-4dd5-855f-99b71bffacf9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4143913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.4143913
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.705015650
Short name T776
Test name
Test status
Simulation time 164355236 ps
CPU time 0.86 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 207484 kb
Host smart-4ae09a2b-eace-4872-b0b0-f4e44c9bd83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70501
5650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.705015650
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.287657168
Short name T1500
Test name
Test status
Simulation time 196463758 ps
CPU time 0.91 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:14 PM PDT 24
Peak memory 207540 kb
Host smart-2f8151a0-2b57-43b9-b96a-11664d5f3590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.287657168
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3838425590
Short name T1238
Test name
Test status
Simulation time 745829826 ps
CPU time 2.11 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207556 kb
Host smart-3717efc9-0a85-4444-b3cd-41f0554185c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38384
25590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3838425590
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3924736153
Short name T3435
Test name
Test status
Simulation time 2549412463 ps
CPU time 20.77 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:35 PM PDT 24
Peak memory 217720 kb
Host smart-06021abc-9e61-4972-b0ac-46963a279a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39247
36153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3924736153
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.475847666
Short name T2839
Test name
Test status
Simulation time 455087635 ps
CPU time 8.22 seconds
Started Aug 10 07:08:54 PM PDT 24
Finished Aug 10 07:09:02 PM PDT 24
Peak memory 207772 kb
Host smart-ca9bdd0a-50a2-432f-b306-ef11e69c06d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475847666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.475847666
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_tx_rx_disruption.2578729433
Short name T3473
Test name
Test status
Simulation time 619162945 ps
CPU time 1.66 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207492 kb
Host smart-6d79107a-e38b-40f7-b540-0fe2bc05e5cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578729433 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.usbdev_tx_rx_disruption.2578729433
Directory /workspace/18.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/180.usbdev_endpoint_types.1560367412
Short name T3565
Test name
Test status
Simulation time 168517714 ps
CPU time 0.89 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207384 kb
Host smart-4a3bec72-d290-4a71-82db-02ce9dc6bb6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1560367412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.1560367412
Directory /workspace/180.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/180.usbdev_tx_rx_disruption.1777755244
Short name T188
Test name
Test status
Simulation time 528925919 ps
CPU time 1.55 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207520 kb
Host smart-7dfa1a63-264a-4db3-ba74-76c34c6ba194
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777755244 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.usbdev_tx_rx_disruption.1777755244
Directory /workspace/180.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/181.usbdev_endpoint_types.872372775
Short name T462
Test name
Test status
Simulation time 299616275 ps
CPU time 1.12 seconds
Started Aug 10 07:17:38 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207480 kb
Host smart-6ad4f351-7e65-4a32-8948-e6c1c5dabd07
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=872372775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.872372775
Directory /workspace/181.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/181.usbdev_tx_rx_disruption.3193234563
Short name T2383
Test name
Test status
Simulation time 520826896 ps
CPU time 1.66 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207568 kb
Host smart-4b9587c6-7193-454b-a2ee-ed126d359e04
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193234563 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.usbdev_tx_rx_disruption.3193234563
Directory /workspace/181.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/182.usbdev_endpoint_types.557191354
Short name T447
Test name
Test status
Simulation time 295613943 ps
CPU time 1.19 seconds
Started Aug 10 07:17:37 PM PDT 24
Finished Aug 10 07:17:39 PM PDT 24
Peak memory 207708 kb
Host smart-74776a75-2cba-4e42-a452-5e26298235d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=557191354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.557191354
Directory /workspace/182.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/182.usbdev_tx_rx_disruption.1372662941
Short name T2291
Test name
Test status
Simulation time 486359658 ps
CPU time 1.56 seconds
Started Aug 10 07:17:40 PM PDT 24
Finished Aug 10 07:17:42 PM PDT 24
Peak memory 207572 kb
Host smart-28da30b4-e4bd-489c-be6e-4b076a4864e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372662941 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.usbdev_tx_rx_disruption.1372662941
Directory /workspace/182.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/183.usbdev_endpoint_types.954966212
Short name T3339
Test name
Test status
Simulation time 287664616 ps
CPU time 1.09 seconds
Started Aug 10 07:17:36 PM PDT 24
Finished Aug 10 07:17:37 PM PDT 24
Peak memory 207380 kb
Host smart-6e138197-f4cc-4af9-ba88-9c7076c78582
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=954966212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.954966212
Directory /workspace/183.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/183.usbdev_tx_rx_disruption.3397104002
Short name T183
Test name
Test status
Simulation time 598138449 ps
CPU time 1.55 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207516 kb
Host smart-fe05e4fb-3218-421f-b722-501f42e75529
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397104002 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.usbdev_tx_rx_disruption.3397104002
Directory /workspace/183.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/184.usbdev_endpoint_types.704254814
Short name T477
Test name
Test status
Simulation time 508519570 ps
CPU time 1.4 seconds
Started Aug 10 07:17:51 PM PDT 24
Finished Aug 10 07:17:52 PM PDT 24
Peak memory 207488 kb
Host smart-c0e7be68-e478-45f5-a2f1-f297f45ef88f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=704254814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.704254814
Directory /workspace/184.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/184.usbdev_tx_rx_disruption.3026731627
Short name T618
Test name
Test status
Simulation time 469510641 ps
CPU time 1.62 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207540 kb
Host smart-82556bc5-75ae-4d35-b728-913d37c854a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026731627 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.usbdev_tx_rx_disruption.3026731627
Directory /workspace/184.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/185.usbdev_endpoint_types.269863533
Short name T463
Test name
Test status
Simulation time 224368784 ps
CPU time 0.96 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207488 kb
Host smart-781fbc44-b353-4a76-95c5-287b575737dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=269863533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.269863533
Directory /workspace/185.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/185.usbdev_tx_rx_disruption.1292054426
Short name T2178
Test name
Test status
Simulation time 597625989 ps
CPU time 1.74 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207528 kb
Host smart-573790a4-b000-4eb6-bfe4-e5d364665c5b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292054426 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.usbdev_tx_rx_disruption.1292054426
Directory /workspace/185.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/186.usbdev_endpoint_types.2919234419
Short name T496
Test name
Test status
Simulation time 430337288 ps
CPU time 1.39 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207524 kb
Host smart-5972b715-38a9-4c77-8e5b-bd82f7317bac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2919234419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.2919234419
Directory /workspace/186.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/186.usbdev_tx_rx_disruption.3193765946
Short name T1900
Test name
Test status
Simulation time 423849689 ps
CPU time 1.41 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207548 kb
Host smart-8fe46fe1-d4f2-466c-b615-8ac96eafbafe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193765946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.usbdev_tx_rx_disruption.3193765946
Directory /workspace/186.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/187.usbdev_endpoint_types.2736305136
Short name T400
Test name
Test status
Simulation time 367372158 ps
CPU time 1.16 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207536 kb
Host smart-04c5e1ef-3fcf-43d7-9e42-00aa3cedf322
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2736305136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.2736305136
Directory /workspace/187.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/187.usbdev_tx_rx_disruption.983690860
Short name T1692
Test name
Test status
Simulation time 432067377 ps
CPU time 1.32 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207572 kb
Host smart-c9eecfa1-7f91-4d4e-af34-a88bb7b4f707
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983690860 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 187.usbdev_tx_rx_disruption.983690860
Directory /workspace/187.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/188.usbdev_endpoint_types.1727715819
Short name T489
Test name
Test status
Simulation time 265273965 ps
CPU time 0.98 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207560 kb
Host smart-9318adfc-e8ce-4ac8-9914-267d97c952a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1727715819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.1727715819
Directory /workspace/188.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/188.usbdev_tx_rx_disruption.1065538193
Short name T3040
Test name
Test status
Simulation time 478937957 ps
CPU time 1.46 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207540 kb
Host smart-84b43729-94a3-4c01-b65f-9119feaf018e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065538193 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.usbdev_tx_rx_disruption.1065538193
Directory /workspace/188.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/189.usbdev_endpoint_types.3872280836
Short name T1992
Test name
Test status
Simulation time 157803022 ps
CPU time 0.89 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207572 kb
Host smart-3a14eadf-885b-42ca-8df8-7d797a71cf80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3872280836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3872280836
Directory /workspace/189.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/189.usbdev_tx_rx_disruption.4208138399
Short name T2750
Test name
Test status
Simulation time 526230376 ps
CPU time 1.66 seconds
Started Aug 10 07:17:56 PM PDT 24
Finished Aug 10 07:17:58 PM PDT 24
Peak memory 207516 kb
Host smart-5b32f626-fdfb-4dc5-be85-3219e9b85e56
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208138399 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.usbdev_tx_rx_disruption.4208138399
Directory /workspace/189.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2225825276
Short name T18
Test name
Test status
Simulation time 48369086 ps
CPU time 0.68 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207540 kb
Host smart-77fba677-f98c-4e80-bfdc-94710ae23ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2225825276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2225825276
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.191146243
Short name T283
Test name
Test status
Simulation time 9126295805 ps
CPU time 11.62 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:28 PM PDT 24
Peak memory 207760 kb
Host smart-2ea7b72c-ec80-4bee-9db1-b625c33378ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191146243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_disconnect.191146243
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3298427025
Short name T1099
Test name
Test status
Simulation time 16164187500 ps
CPU time 20.4 seconds
Started Aug 10 07:09:11 PM PDT 24
Finished Aug 10 07:09:31 PM PDT 24
Peak memory 216044 kb
Host smart-d2df32a0-54be-4057-aef1-4679e39c0220
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298427025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3298427025
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.4116269051
Short name T2052
Test name
Test status
Simulation time 30643665426 ps
CPU time 37.09 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207712 kb
Host smart-4df76ff2-7247-497e-ad9f-60382986e05a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116269051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.4116269051
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2613790654
Short name T1127
Test name
Test status
Simulation time 155554119 ps
CPU time 0.89 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 207460 kb
Host smart-d65b1045-df06-4ec2-9794-673a2c9d7000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
90654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2613790654
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2502554126
Short name T2810
Test name
Test status
Simulation time 159749490 ps
CPU time 0.89 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207556 kb
Host smart-7ba9abc0-be92-4917-9a05-8cc6356a3a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
54126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2502554126
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1315422338
Short name T3155
Test name
Test status
Simulation time 433595368 ps
CPU time 1.54 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 207564 kb
Host smart-3294bab2-ef59-4bf7-8f53-0df883d0e4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13154
22338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1315422338
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2096073859
Short name T3379
Test name
Test status
Simulation time 377609430 ps
CPU time 1.24 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207500 kb
Host smart-a638a269-9085-490f-9f24-2a10d48fb1bd
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2096073859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2096073859
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.873591679
Short name T1580
Test name
Test status
Simulation time 17442770395 ps
CPU time 31.01 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:47 PM PDT 24
Peak memory 207880 kb
Host smart-eddd881a-6b7b-4774-ac1b-89cc29caa804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87359
1679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.873591679
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.1510832152
Short name T62
Test name
Test status
Simulation time 426413372 ps
CPU time 8.34 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207692 kb
Host smart-049b3788-f6b8-4631-836d-ac929007f55d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510832152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1510832152
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3144038272
Short name T2459
Test name
Test status
Simulation time 1043536267 ps
CPU time 2.23 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 207496 kb
Host smart-4dd6c596-829d-4df2-9921-ba70df8964bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
38272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3144038272
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.833274376
Short name T1594
Test name
Test status
Simulation time 135473386 ps
CPU time 0.82 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:16 PM PDT 24
Peak memory 207500 kb
Host smart-b366bb9a-b19e-4bdb-bb5d-46ed8f8a9fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83327
4376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.833274376
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2621999550
Short name T2838
Test name
Test status
Simulation time 34742375 ps
CPU time 0.69 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:14 PM PDT 24
Peak memory 207468 kb
Host smart-f9ad7f3f-12a5-4ec9-bb4c-d73c328512b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219
99550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2621999550
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.921077813
Short name T868
Test name
Test status
Simulation time 938731441 ps
CPU time 2.8 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:18 PM PDT 24
Peak memory 207704 kb
Host smart-ffb4fa74-0237-4180-8b4d-8811154d0ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92107
7813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.921077813
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_types.3655404974
Short name T469
Test name
Test status
Simulation time 372980723 ps
CPU time 1.17 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207532 kb
Host smart-684a41ac-3ab3-45fe-9b8d-6a50a92c0676
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3655404974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.3655404974
Directory /workspace/19.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.4086595765
Short name T2723
Test name
Test status
Simulation time 171291882 ps
CPU time 1.96 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:18 PM PDT 24
Peak memory 207724 kb
Host smart-d40ea699-6324-4a4f-bd84-7f792312712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
95765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.4086595765
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2975828765
Short name T854
Test name
Test status
Simulation time 272647710 ps
CPU time 1.23 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:09:17 PM PDT 24
Peak memory 215948 kb
Host smart-fdae893e-d362-4bf1-9a3d-c3bce566f032
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2975828765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2975828765
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1713562279
Short name T3459
Test name
Test status
Simulation time 149456286 ps
CPU time 0.83 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207516 kb
Host smart-afbba112-2f10-4712-aadc-341591de9b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17135
62279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1713562279
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2350838758
Short name T802
Test name
Test status
Simulation time 245768383 ps
CPU time 0.95 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207540 kb
Host smart-4351be26-bad8-47d6-aa4b-e5544e56776c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508
38758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2350838758
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.9916727
Short name T1836
Test name
Test status
Simulation time 5102552110 ps
CPU time 41.27 seconds
Started Aug 10 07:09:16 PM PDT 24
Finished Aug 10 07:09:58 PM PDT 24
Peak memory 218416 kb
Host smart-c20a793a-5264-4e85-bb0c-a66039bfc554
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=9916727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.9916727
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.750187970
Short name T2823
Test name
Test status
Simulation time 8355398392 ps
CPU time 64.57 seconds
Started Aug 10 07:09:15 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207816 kb
Host smart-8c9c8363-6398-4772-82a4-1a1b13f7a6f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=750187970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.750187970
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.641278246
Short name T2500
Test name
Test status
Simulation time 198200976 ps
CPU time 0.94 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:15 PM PDT 24
Peak memory 207508 kb
Host smart-abdca6b6-aa31-4240-9b0c-538778503342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64127
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.641278246
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3653123090
Short name T2884
Test name
Test status
Simulation time 32138418069 ps
CPU time 45.39 seconds
Started Aug 10 07:09:12 PM PDT 24
Finished Aug 10 07:09:58 PM PDT 24
Peak memory 207852 kb
Host smart-2e05c9bc-bed3-462e-8a30-ac9b768d5a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531
23090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3653123090
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2421451473
Short name T2862
Test name
Test status
Simulation time 10537055086 ps
CPU time 13.03 seconds
Started Aug 10 07:09:14 PM PDT 24
Finished Aug 10 07:09:27 PM PDT 24
Peak memory 207688 kb
Host smart-92daaffa-3cc8-4dd3-8b12-5bca58c5af76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
51473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2421451473
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3707588068
Short name T2903
Test name
Test status
Simulation time 4017620357 ps
CPU time 30.24 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:09:44 PM PDT 24
Peak memory 216132 kb
Host smart-131171de-11a5-4d34-97c5-f000331ed2f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3707588068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3707588068
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1167088608
Short name T2708
Test name
Test status
Simulation time 3152407668 ps
CPU time 24.43 seconds
Started Aug 10 07:09:24 PM PDT 24
Finished Aug 10 07:09:48 PM PDT 24
Peak memory 217860 kb
Host smart-95d6415f-057f-4b60-a731-6940af1ca798
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1167088608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1167088608
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.901533171
Short name T2807
Test name
Test status
Simulation time 262129995 ps
CPU time 0.99 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207412 kb
Host smart-ee64d4cd-4589-47cb-a13d-1bb87372bc83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=901533171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.901533171
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.922359516
Short name T1090
Test name
Test status
Simulation time 258206290 ps
CPU time 1.05 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207512 kb
Host smart-174f41a2-195d-425e-a018-c516b66ddda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92235
9516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.922359516
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.2462278040
Short name T2112
Test name
Test status
Simulation time 2243915843 ps
CPU time 22.33 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:45 PM PDT 24
Peak memory 224256 kb
Host smart-701dce24-18e0-4e8f-9f0f-c16d9b59f1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
78040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.2462278040
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1350555482
Short name T1302
Test name
Test status
Simulation time 4216619228 ps
CPU time 117.05 seconds
Started Aug 10 07:09:21 PM PDT 24
Finished Aug 10 07:11:18 PM PDT 24
Peak memory 217544 kb
Host smart-25213efd-f5e0-4d2b-b7d3-61726a1be658
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1350555482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1350555482
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.1375809012
Short name T2664
Test name
Test status
Simulation time 179810065 ps
CPU time 0.87 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207476 kb
Host smart-63ca3117-83dd-4e9f-89be-d92018700305
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1375809012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1375809012
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.893420999
Short name T1999
Test name
Test status
Simulation time 211703550 ps
CPU time 0.87 seconds
Started Aug 10 07:09:21 PM PDT 24
Finished Aug 10 07:09:22 PM PDT 24
Peak memory 207564 kb
Host smart-d78854b7-0345-4e68-9e3e-b40e4bfe87ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89342
0999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.893420999
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2672716628
Short name T856
Test name
Test status
Simulation time 173098627 ps
CPU time 0.84 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207480 kb
Host smart-861dd81b-6295-4965-aed0-77f95e4c76e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
16628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2672716628
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.186696024
Short name T2794
Test name
Test status
Simulation time 175704781 ps
CPU time 0.84 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207568 kb
Host smart-67521a7e-daaa-4b23-a7dd-dae536a5e66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
6024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.186696024
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.838510789
Short name T1497
Test name
Test status
Simulation time 181381737 ps
CPU time 0.92 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207580 kb
Host smart-55926c88-bf32-4f4a-a478-825adf759f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83851
0789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.838510789
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.445769927
Short name T1905
Test name
Test status
Simulation time 152836912 ps
CPU time 0.82 seconds
Started Aug 10 07:09:21 PM PDT 24
Finished Aug 10 07:09:22 PM PDT 24
Peak memory 207556 kb
Host smart-f6279bf8-ee6a-45b0-98c4-bb949fa2e040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44576
9927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.445769927
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.188170100
Short name T2813
Test name
Test status
Simulation time 205741546 ps
CPU time 0.96 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207432 kb
Host smart-9e69a194-8a0a-4832-b62a-acf029f9a93a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=188170100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.188170100
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.4228469734
Short name T570
Test name
Test status
Simulation time 222768949 ps
CPU time 0.94 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207612 kb
Host smart-a659f560-9101-4691-b0c0-e31108ad6a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
69734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.4228469734
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3869722300
Short name T1509
Test name
Test status
Simulation time 39807926 ps
CPU time 0.69 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207520 kb
Host smart-b73d5870-c21c-4648-b9c7-399080e02b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
22300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3869722300
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2482873308
Short name T3262
Test name
Test status
Simulation time 18052057608 ps
CPU time 47.87 seconds
Started Aug 10 07:09:24 PM PDT 24
Finished Aug 10 07:10:12 PM PDT 24
Peak memory 224092 kb
Host smart-0a87df55-4d48-444f-94c6-7e04a43c077d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
73308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2482873308
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1686674690
Short name T287
Test name
Test status
Simulation time 168496206 ps
CPU time 0.85 seconds
Started Aug 10 07:09:21 PM PDT 24
Finished Aug 10 07:09:22 PM PDT 24
Peak memory 207600 kb
Host smart-444e5af6-679e-47d8-94cf-599f9dd0f5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866
74690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1686674690
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.957111953
Short name T1684
Test name
Test status
Simulation time 216520810 ps
CPU time 0.95 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207392 kb
Host smart-b8f90f23-c83b-4eb9-97a0-09140356b903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95711
1953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.957111953
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.326575733
Short name T3031
Test name
Test status
Simulation time 227668358 ps
CPU time 0.95 seconds
Started Aug 10 07:09:21 PM PDT 24
Finished Aug 10 07:09:22 PM PDT 24
Peak memory 207572 kb
Host smart-a40c6b25-0962-4e1c-981b-198ac8847a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32657
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.326575733
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1553106826
Short name T3008
Test name
Test status
Simulation time 185638507 ps
CPU time 0.97 seconds
Started Aug 10 07:09:24 PM PDT 24
Finished Aug 10 07:09:25 PM PDT 24
Peak memory 207540 kb
Host smart-ff9c19c9-cb4e-4207-8e7d-6a377e519530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
06826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1553106826
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_resume_link_active.3736849942
Short name T2159
Test name
Test status
Simulation time 20170824912 ps
CPU time 24.04 seconds
Started Aug 10 07:09:24 PM PDT 24
Finished Aug 10 07:09:48 PM PDT 24
Peak memory 207500 kb
Host smart-877431aa-ee27-4d0a-95f3-2815f8dea72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
49942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_resume_link_active.3736849942
Directory /workspace/19.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1260978798
Short name T78
Test name
Test status
Simulation time 143012582 ps
CPU time 0.82 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207516 kb
Host smart-056f7d83-8202-477d-87f6-e56eb9a9b032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12609
78798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1260978798
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_rx_full.4007162613
Short name T354
Test name
Test status
Simulation time 352249741 ps
CPU time 1.22 seconds
Started Aug 10 07:09:22 PM PDT 24
Finished Aug 10 07:09:23 PM PDT 24
Peak memory 207580 kb
Host smart-3f9f5737-832a-4f7c-a432-f075b89292dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40071
62613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.4007162613
Directory /workspace/19.usbdev_rx_full/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.503782353
Short name T2895
Test name
Test status
Simulation time 156623832 ps
CPU time 0.81 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207476 kb
Host smart-0d56e4da-6a8b-4b83-9651-bc6cd4a3de87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50378
2353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.503782353
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2692340252
Short name T2840
Test name
Test status
Simulation time 154749793 ps
CPU time 0.8 seconds
Started Aug 10 07:09:23 PM PDT 24
Finished Aug 10 07:09:24 PM PDT 24
Peak memory 207604 kb
Host smart-5b656cea-f70c-4f34-908f-b6aab9987d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
40252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2692340252
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1621243939
Short name T1578
Test name
Test status
Simulation time 228886734 ps
CPU time 1 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207504 kb
Host smart-228633d0-4cdd-4487-a6ea-ad8e7492cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16212
43939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1621243939
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1217663555
Short name T3197
Test name
Test status
Simulation time 3350739456 ps
CPU time 96.2 seconds
Started Aug 10 07:09:32 PM PDT 24
Finished Aug 10 07:11:08 PM PDT 24
Peak memory 224208 kb
Host smart-aebb666f-5f32-4c37-bdda-876848c4bc86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1217663555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1217663555
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.46296529
Short name T1577
Test name
Test status
Simulation time 162784521 ps
CPU time 0.83 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207532 kb
Host smart-3736cd07-9fed-4946-bb6d-68b611368b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46296
529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.46296529
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3903474124
Short name T2021
Test name
Test status
Simulation time 188566477 ps
CPU time 0.9 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:34 PM PDT 24
Peak memory 207532 kb
Host smart-25379deb-879b-46eb-8b40-b05cf0f87ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39034
74124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3903474124
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.1491166301
Short name T2986
Test name
Test status
Simulation time 454804860 ps
CPU time 1.35 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:31 PM PDT 24
Peak memory 207556 kb
Host smart-87f42057-0c5c-4639-a678-426286fac5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14911
66301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1491166301
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.962710455
Short name T1555
Test name
Test status
Simulation time 3009381857 ps
CPU time 24.68 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:56 PM PDT 24
Peak memory 217804 kb
Host smart-94c819d3-4307-40bf-9ae0-56b68668d8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96271
0455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.962710455
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.3949158027
Short name T2821
Test name
Test status
Simulation time 5243755836 ps
CPU time 48.8 seconds
Started Aug 10 07:09:13 PM PDT 24
Finished Aug 10 07:10:03 PM PDT 24
Peak memory 207816 kb
Host smart-6b4f7c5d-3060-4f61-8dc7-1eab6a62923d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949158027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.3949158027
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_tx_rx_disruption.262981276
Short name T2534
Test name
Test status
Simulation time 459453322 ps
CPU time 1.55 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207584 kb
Host smart-4e12d6c5-e13a-41ef-b80a-cc9f27f444af
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262981276 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.usbdev_tx_rx_disruption.262981276
Directory /workspace/19.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/190.usbdev_endpoint_types.3449685615
Short name T453
Test name
Test status
Simulation time 568019466 ps
CPU time 1.56 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207408 kb
Host smart-19b57338-51a3-451e-acb2-ba201fcc371b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3449685615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.3449685615
Directory /workspace/190.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/190.usbdev_tx_rx_disruption.2227725130
Short name T1145
Test name
Test status
Simulation time 589058978 ps
CPU time 1.68 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207592 kb
Host smart-b423c4c2-714b-4ce0-966c-d083624dd73a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227725130 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.usbdev_tx_rx_disruption.2227725130
Directory /workspace/190.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/191.usbdev_endpoint_types.3878286254
Short name T503
Test name
Test status
Simulation time 304251320 ps
CPU time 1.14 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207472 kb
Host smart-edfec630-57a3-4688-8738-33be6d2f5795
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3878286254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3878286254
Directory /workspace/191.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/191.usbdev_tx_rx_disruption.627445541
Short name T2805
Test name
Test status
Simulation time 519848417 ps
CPU time 1.69 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207584 kb
Host smart-f79c27f0-415b-486c-a450-0873bb4fe9c6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627445541 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.usbdev_tx_rx_disruption.627445541
Directory /workspace/191.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/192.usbdev_tx_rx_disruption.1726982743
Short name T2489
Test name
Test status
Simulation time 563480410 ps
CPU time 1.54 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207552 kb
Host smart-bbd02e46-068c-4b2f-b20c-7578815a964f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726982743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.usbdev_tx_rx_disruption.1726982743
Directory /workspace/192.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/193.usbdev_endpoint_types.4112844621
Short name T420
Test name
Test status
Simulation time 268392613 ps
CPU time 1.01 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207540 kb
Host smart-31521bbf-7b3f-4f75-8281-73c03a4259bf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4112844621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.4112844621
Directory /workspace/193.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/193.usbdev_tx_rx_disruption.260296138
Short name T949
Test name
Test status
Simulation time 607933428 ps
CPU time 1.61 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207560 kb
Host smart-8618fd66-f22a-4374-8080-75be2f394145
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260296138 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.usbdev_tx_rx_disruption.260296138
Directory /workspace/193.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/194.usbdev_endpoint_types.1252995137
Short name T2356
Test name
Test status
Simulation time 198665513 ps
CPU time 0.94 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207492 kb
Host smart-4b72f23b-1135-448a-b35c-285978692b1d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1252995137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.1252995137
Directory /workspace/194.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/194.usbdev_tx_rx_disruption.2355722144
Short name T204
Test name
Test status
Simulation time 416095871 ps
CPU time 1.45 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207560 kb
Host smart-c3640ea4-7672-4530-858a-1ae3cde771ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355722144 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.usbdev_tx_rx_disruption.2355722144
Directory /workspace/194.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/195.usbdev_endpoint_types.3823860281
Short name T390
Test name
Test status
Simulation time 518860001 ps
CPU time 1.41 seconds
Started Aug 10 07:17:56 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207480 kb
Host smart-7de7f078-6236-4d29-be27-920f69f4fcb1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3823860281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.3823860281
Directory /workspace/195.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/195.usbdev_tx_rx_disruption.1949189449
Short name T1750
Test name
Test status
Simulation time 602275264 ps
CPU time 1.69 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207564 kb
Host smart-94fcb7a5-2941-416c-89aa-f97005ee966b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949189449 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.usbdev_tx_rx_disruption.1949189449
Directory /workspace/195.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/196.usbdev_endpoint_types.4241435256
Short name T448
Test name
Test status
Simulation time 591115185 ps
CPU time 1.65 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207484 kb
Host smart-6d69a4dc-4207-4778-9ffb-79afe58b6e5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4241435256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.4241435256
Directory /workspace/196.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/196.usbdev_tx_rx_disruption.1647972264
Short name T3144
Test name
Test status
Simulation time 496521642 ps
CPU time 1.49 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207496 kb
Host smart-467816c1-5a88-496d-b042-775fff676820
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647972264 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.usbdev_tx_rx_disruption.1647972264
Directory /workspace/196.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/197.usbdev_endpoint_types.3712889618
Short name T226
Test name
Test status
Simulation time 200791002 ps
CPU time 0.92 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207460 kb
Host smart-aec982ec-d8e5-4029-b626-8ade5b4bf357
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3712889618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.3712889618
Directory /workspace/197.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/197.usbdev_tx_rx_disruption.2267834280
Short name T1321
Test name
Test status
Simulation time 582753129 ps
CPU time 1.54 seconds
Started Aug 10 07:17:51 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207568 kb
Host smart-85c3eba8-804d-4d9a-b5d8-7a85a6b31f11
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267834280 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.usbdev_tx_rx_disruption.2267834280
Directory /workspace/197.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/198.usbdev_endpoint_types.636795925
Short name T3397
Test name
Test status
Simulation time 161782559 ps
CPU time 0.91 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207532 kb
Host smart-078578e6-3929-4954-a1fc-cc81f1323496
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=636795925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.636795925
Directory /workspace/198.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/198.usbdev_tx_rx_disruption.499373532
Short name T2521
Test name
Test status
Simulation time 407502027 ps
CPU time 1.51 seconds
Started Aug 10 07:17:51 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207528 kb
Host smart-767e3dd8-2abf-4ba8-a6a8-6b446ecee4bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499373532 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 198.usbdev_tx_rx_disruption.499373532
Directory /workspace/198.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/199.usbdev_endpoint_types.809806907
Short name T614
Test name
Test status
Simulation time 177197978 ps
CPU time 0.89 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207404 kb
Host smart-c2e562df-5323-42ba-ac10-07a5e9080ffd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=809806907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.809806907
Directory /workspace/199.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/199.usbdev_tx_rx_disruption.3680832687
Short name T3048
Test name
Test status
Simulation time 506963865 ps
CPU time 1.69 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207564 kb
Host smart-6c5e50d3-0d65-4351-ad85-c7cf2162fa04
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680832687 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.usbdev_tx_rx_disruption.3680832687
Directory /workspace/199.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3865319651
Short name T2720
Test name
Test status
Simulation time 40065283 ps
CPU time 0.69 seconds
Started Aug 10 07:01:25 PM PDT 24
Finished Aug 10 07:01:26 PM PDT 24
Peak memory 207624 kb
Host smart-48c5b56b-5760-4e3c-9c31-60afd5963536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3865319651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3865319651
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1445969535
Short name T2141
Test name
Test status
Simulation time 10022456391 ps
CPU time 11.61 seconds
Started Aug 10 07:00:32 PM PDT 24
Finished Aug 10 07:00:44 PM PDT 24
Peak memory 207756 kb
Host smart-a5ab4f16-8493-4c86-8964-0a1446812765
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445969535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.1445969535
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1355714230
Short name T720
Test name
Test status
Simulation time 16241394640 ps
CPU time 20.57 seconds
Started Aug 10 07:00:29 PM PDT 24
Finished Aug 10 07:00:50 PM PDT 24
Peak memory 216004 kb
Host smart-cc6eace5-db89-4e10-9313-9c5104133c60
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355714230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1355714230
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2535565155
Short name T14
Test name
Test status
Simulation time 23950780791 ps
CPU time 31.54 seconds
Started Aug 10 07:00:29 PM PDT 24
Finished Aug 10 07:01:00 PM PDT 24
Peak memory 215964 kb
Host smart-b9c91489-2020-4844-93f8-ef52ff93e27a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535565155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.2535565155
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2265286059
Short name T3532
Test name
Test status
Simulation time 181214451 ps
CPU time 0.85 seconds
Started Aug 10 07:00:28 PM PDT 24
Finished Aug 10 07:00:29 PM PDT 24
Peak memory 207608 kb
Host smart-0c845ecd-3804-4913-8879-311c3d10b9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
86059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2265286059
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1625123993
Short name T47
Test name
Test status
Simulation time 188198043 ps
CPU time 0.91 seconds
Started Aug 10 07:00:28 PM PDT 24
Finished Aug 10 07:00:29 PM PDT 24
Peak memory 207416 kb
Host smart-f6e7e2dd-1645-409c-accf-a874c5fd2aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16251
23993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1625123993
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2310694881
Short name T2814
Test name
Test status
Simulation time 147350288 ps
CPU time 0.83 seconds
Started Aug 10 07:00:42 PM PDT 24
Finished Aug 10 07:00:43 PM PDT 24
Peak memory 207500 kb
Host smart-b7b3a27d-e011-48d2-891d-ea64099bb8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23106
94881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2310694881
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.4261113123
Short name T1142
Test name
Test status
Simulation time 288895368 ps
CPU time 1.14 seconds
Started Aug 10 07:00:37 PM PDT 24
Finished Aug 10 07:00:38 PM PDT 24
Peak memory 207528 kb
Host smart-ed9a7560-8257-40bd-ab3a-fe6a0625c34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
13123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.4261113123
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3074779318
Short name T2619
Test name
Test status
Simulation time 31316588540 ps
CPU time 49.64 seconds
Started Aug 10 07:00:37 PM PDT 24
Finished Aug 10 07:01:26 PM PDT 24
Peak memory 207880 kb
Host smart-7a014054-0954-4752-9cd8-e7a34cc86b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
79318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3074779318
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.3390983347
Short name T712
Test name
Test status
Simulation time 145258618 ps
CPU time 0.81 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:40 PM PDT 24
Peak memory 207436 kb
Host smart-1161d0bc-d877-47d8-b5d7-35ad77d788d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390983347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.3390983347
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.206663158
Short name T3130
Test name
Test status
Simulation time 646841537 ps
CPU time 1.65 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:41 PM PDT 24
Peak memory 207540 kb
Host smart-1e204c6d-bdec-4f14-9b55-5ae8bdb55031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
3158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.206663158
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1414914654
Short name T2151
Test name
Test status
Simulation time 208026076 ps
CPU time 0.88 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:40 PM PDT 24
Peak memory 207536 kb
Host smart-9ca95cc0-432b-4eec-ac33-2c757ae1d5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14149
14654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1414914654
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1737778267
Short name T3608
Test name
Test status
Simulation time 43688446 ps
CPU time 0.7 seconds
Started Aug 10 07:00:38 PM PDT 24
Finished Aug 10 07:00:39 PM PDT 24
Peak memory 207460 kb
Host smart-984ed7b1-4b9f-404a-bd94-07cc8d605b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17377
78267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1737778267
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3374490546
Short name T1351
Test name
Test status
Simulation time 1052938268 ps
CPU time 2.8 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:42 PM PDT 24
Peak memory 207672 kb
Host smart-a402b31e-0df8-4ebc-a613-3ed1416b7cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33744
90546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3374490546
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_types.1442445818
Short name T2381
Test name
Test status
Simulation time 450915134 ps
CPU time 1.41 seconds
Started Aug 10 07:00:38 PM PDT 24
Finished Aug 10 07:00:39 PM PDT 24
Peak memory 207452 kb
Host smart-5901e266-2725-4677-b947-5b5f7e8820bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1442445818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.1442445818
Directory /workspace/2.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2005708535
Short name T3528
Test name
Test status
Simulation time 198851366 ps
CPU time 1.44 seconds
Started Aug 10 07:00:39 PM PDT 24
Finished Aug 10 07:00:40 PM PDT 24
Peak memory 207652 kb
Host smart-ad1cf5a4-97c0-434c-aa9c-b07b008caba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20057
08535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2005708535
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.875939232
Short name T1676
Test name
Test status
Simulation time 96178114754 ps
CPU time 147.08 seconds
Started Aug 10 07:00:47 PM PDT 24
Finished Aug 10 07:03:14 PM PDT 24
Peak memory 207868 kb
Host smart-d3264e25-d3da-4edd-9d4e-411b51a819e9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=875939232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.875939232
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4140718294
Short name T1385
Test name
Test status
Simulation time 98384905248 ps
CPU time 160.85 seconds
Started Aug 10 07:00:45 PM PDT 24
Finished Aug 10 07:03:26 PM PDT 24
Peak memory 207844 kb
Host smart-3ccc5500-ea44-470f-a5ba-e09fc7b681b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140718294 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4140718294
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.334220676
Short name T288
Test name
Test status
Simulation time 114146207554 ps
CPU time 178.14 seconds
Started Aug 10 07:00:47 PM PDT 24
Finished Aug 10 07:03:45 PM PDT 24
Peak memory 207808 kb
Host smart-9827dc8a-6218-4813-9190-b59c83bec7e5
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=334220676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.334220676
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.3732134783
Short name T1495
Test name
Test status
Simulation time 95956694481 ps
CPU time 136.87 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:03:03 PM PDT 24
Peak memory 207840 kb
Host smart-03656ad9-2824-4b87-920c-cc6270ce70fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732134783 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3732134783
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.1885961386
Short name T1233
Test name
Test status
Simulation time 89133362271 ps
CPU time 139.88 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:03:06 PM PDT 24
Peak memory 208016 kb
Host smart-801d7d43-96bc-4289-b03b-b11f0e6901ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18859
61386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.1885961386
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2579161385
Short name T3181
Test name
Test status
Simulation time 259565622 ps
CPU time 1.15 seconds
Started Aug 10 07:00:47 PM PDT 24
Finished Aug 10 07:00:48 PM PDT 24
Peak memory 215916 kb
Host smart-0a4e02ec-6999-4c57-b8b8-35f51acb1e79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2579161385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2579161385
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1758909501
Short name T2707
Test name
Test status
Simulation time 165004349 ps
CPU time 0.83 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:00:47 PM PDT 24
Peak memory 207448 kb
Host smart-4ed5c71a-bd2e-4ba1-80d2-ba42e30dddeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17589
09501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1758909501
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1004895854
Short name T1026
Test name
Test status
Simulation time 189114917 ps
CPU time 0.87 seconds
Started Aug 10 07:00:47 PM PDT 24
Finished Aug 10 07:00:48 PM PDT 24
Peak memory 207488 kb
Host smart-2726253b-ecbc-4f1e-9c3e-7dc343bc9fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10048
95854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1004895854
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3154506018
Short name T3568
Test name
Test status
Simulation time 4006591254 ps
CPU time 36.08 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:01:22 PM PDT 24
Peak memory 224224 kb
Host smart-bbcc5241-044f-4482-b720-ebe973b94621
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3154506018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3154506018
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.2449170349
Short name T1125
Test name
Test status
Simulation time 3540094955 ps
CPU time 42.71 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:01:29 PM PDT 24
Peak memory 207836 kb
Host smart-306f60cd-f469-4882-9f4c-0dcc730f7b86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2449170349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2449170349
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.4271802395
Short name T60
Test name
Test status
Simulation time 212547288 ps
CPU time 0.92 seconds
Started Aug 10 07:00:46 PM PDT 24
Finished Aug 10 07:00:47 PM PDT 24
Peak memory 207580 kb
Host smart-dccd6f61-ec99-49d6-9128-5f6e134186c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42718
02395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.4271802395
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.423113927
Short name T866
Test name
Test status
Simulation time 24067064887 ps
CPU time 37.18 seconds
Started Aug 10 07:00:57 PM PDT 24
Finished Aug 10 07:01:34 PM PDT 24
Peak memory 216100 kb
Host smart-9285c232-6e40-4b58-915a-599c299b30d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
3927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.423113927
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1098366547
Short name T2767
Test name
Test status
Simulation time 10171465176 ps
CPU time 14.04 seconds
Started Aug 10 07:00:57 PM PDT 24
Finished Aug 10 07:01:11 PM PDT 24
Peak memory 207824 kb
Host smart-612b81ce-1309-465f-b2d8-28cb9d41554d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10983
66547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1098366547
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3684963585
Short name T1866
Test name
Test status
Simulation time 5245114991 ps
CPU time 158.49 seconds
Started Aug 10 07:00:55 PM PDT 24
Finished Aug 10 07:03:34 PM PDT 24
Peak memory 218432 kb
Host smart-e1242008-d8b2-482f-ae3c-4c6373f82355
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3684963585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3684963585
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3177067631
Short name T861
Test name
Test status
Simulation time 2713117271 ps
CPU time 27.08 seconds
Started Aug 10 07:00:56 PM PDT 24
Finished Aug 10 07:01:23 PM PDT 24
Peak memory 224268 kb
Host smart-e73e63ce-f409-48e1-bb54-80cdfb8e77c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3177067631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3177067631
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.764820023
Short name T2468
Test name
Test status
Simulation time 276959258 ps
CPU time 1.09 seconds
Started Aug 10 07:00:56 PM PDT 24
Finished Aug 10 07:00:58 PM PDT 24
Peak memory 207524 kb
Host smart-c5f92aec-4a4b-4a03-9916-a7337a0093c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=764820023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.764820023
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2832257109
Short name T2748
Test name
Test status
Simulation time 193301173 ps
CPU time 0.91 seconds
Started Aug 10 07:00:56 PM PDT 24
Finished Aug 10 07:00:57 PM PDT 24
Peak memory 207580 kb
Host smart-3e9a7afe-b524-4bc5-898e-a096d1b9af94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28322
57109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2832257109
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.2993662155
Short name T905
Test name
Test status
Simulation time 2836182714 ps
CPU time 81.52 seconds
Started Aug 10 07:00:56 PM PDT 24
Finished Aug 10 07:02:18 PM PDT 24
Peak memory 216064 kb
Host smart-895476a2-f3b5-4263-aee6-2a44c10639ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29936
62155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.2993662155
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3925662159
Short name T3533
Test name
Test status
Simulation time 3645189307 ps
CPU time 36.29 seconds
Started Aug 10 07:01:06 PM PDT 24
Finished Aug 10 07:01:42 PM PDT 24
Peak memory 224272 kb
Host smart-cd95dca8-9bc5-4bf9-a01f-5cfcc7f99578
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3925662159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3925662159
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.113935428
Short name T717
Test name
Test status
Simulation time 3895125453 ps
CPU time 114.51 seconds
Started Aug 10 07:01:08 PM PDT 24
Finished Aug 10 07:03:03 PM PDT 24
Peak memory 217564 kb
Host smart-d9ea215c-3869-452e-9921-f6db943f44cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=113935428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.113935428
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3430707478
Short name T1598
Test name
Test status
Simulation time 158548182 ps
CPU time 0.85 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207408 kb
Host smart-1c940075-bb9f-4b96-8e59-e578e747e3ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3430707478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3430707478
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.343277065
Short name T3525
Test name
Test status
Simulation time 148394087 ps
CPU time 0.85 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207560 kb
Host smart-3a470bd1-4876-426a-ae0b-317cb9886711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.343277065
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2703576574
Short name T2602
Test name
Test status
Simulation time 191281346 ps
CPU time 0.91 seconds
Started Aug 10 07:01:06 PM PDT 24
Finished Aug 10 07:01:07 PM PDT 24
Peak memory 207560 kb
Host smart-af2d157b-cd9c-4f95-a5a3-7e9e977f3210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27035
76574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2703576574
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2977381928
Short name T1267
Test name
Test status
Simulation time 148018584 ps
CPU time 0.85 seconds
Started Aug 10 07:01:06 PM PDT 24
Finished Aug 10 07:01:07 PM PDT 24
Peak memory 207652 kb
Host smart-caf66c67-9e03-4f1f-9ae1-a3b326b38e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
81928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2977381928
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.382365217
Short name T3069
Test name
Test status
Simulation time 151965502 ps
CPU time 0.81 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207608 kb
Host smart-b1c7f14b-2195-4a6e-bbe9-09293fb27d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38236
5217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.382365217
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.813498385
Short name T1304
Test name
Test status
Simulation time 152596602 ps
CPU time 0.85 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207528 kb
Host smart-3de3a8c2-e1f4-4202-a55b-306fe2c54b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81349
8385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.813498385
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3294591412
Short name T1542
Test name
Test status
Simulation time 154498938 ps
CPU time 0.83 seconds
Started Aug 10 07:01:06 PM PDT 24
Finished Aug 10 07:01:07 PM PDT 24
Peak memory 207572 kb
Host smart-e18a335c-ef71-41e5-8163-5eb589a33cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32945
91412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3294591412
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.713850664
Short name T1638
Test name
Test status
Simulation time 269443826 ps
CPU time 1.09 seconds
Started Aug 10 07:01:06 PM PDT 24
Finished Aug 10 07:01:07 PM PDT 24
Peak memory 207584 kb
Host smart-f4436ae3-894e-4e54-a3e9-f48c4ab693a8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=713850664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.713850664
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1587320244
Short name T1988
Test name
Test status
Simulation time 228092955 ps
CPU time 1.03 seconds
Started Aug 10 07:01:08 PM PDT 24
Finished Aug 10 07:01:09 PM PDT 24
Peak memory 207604 kb
Host smart-86b4b230-78ab-41b5-ad03-251a381adfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
20244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1587320244
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.677201074
Short name T1312
Test name
Test status
Simulation time 153377381 ps
CPU time 0.85 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207512 kb
Host smart-d26965a1-a066-4478-8282-91329bb75f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67720
1074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.677201074
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.255287130
Short name T2547
Test name
Test status
Simulation time 41870690 ps
CPU time 0.68 seconds
Started Aug 10 07:01:05 PM PDT 24
Finished Aug 10 07:01:06 PM PDT 24
Peak memory 207480 kb
Host smart-b6b2f9e4-5bff-465a-b6fa-0528303bd50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
7130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.255287130
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2231722402
Short name T3225
Test name
Test status
Simulation time 11767780301 ps
CPU time 28.45 seconds
Started Aug 10 07:01:08 PM PDT 24
Finished Aug 10 07:01:36 PM PDT 24
Peak memory 216032 kb
Host smart-6b7b907e-3705-4366-9a5d-b17a7a172f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22317
22402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2231722402
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.73599619
Short name T1366
Test name
Test status
Simulation time 176236639 ps
CPU time 0.89 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207424 kb
Host smart-6fa3490a-9656-4821-b608-2f6213ef3a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73599
619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.73599619
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1382938863
Short name T1307
Test name
Test status
Simulation time 274381548 ps
CPU time 1.03 seconds
Started Aug 10 07:01:07 PM PDT 24
Finished Aug 10 07:01:08 PM PDT 24
Peak memory 207396 kb
Host smart-b71683c2-ae0f-48ce-ad67-8f70829de084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
38863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1382938863
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.298845408
Short name T799
Test name
Test status
Simulation time 5545822824 ps
CPU time 24.89 seconds
Started Aug 10 07:01:17 PM PDT 24
Finished Aug 10 07:01:42 PM PDT 24
Peak memory 219516 kb
Host smart-56c72230-6910-45c3-98a2-ad4824abd7b8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=298845408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.298845408
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2568612584
Short name T2791
Test name
Test status
Simulation time 6104569428 ps
CPU time 27.01 seconds
Started Aug 10 07:01:17 PM PDT 24
Finished Aug 10 07:01:44 PM PDT 24
Peak memory 219308 kb
Host smart-98716fac-ff0d-428c-8220-682cae01b2d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568612584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2568612584
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2248266370
Short name T2600
Test name
Test status
Simulation time 238705716 ps
CPU time 1 seconds
Started Aug 10 07:01:15 PM PDT 24
Finished Aug 10 07:01:16 PM PDT 24
Peak memory 207572 kb
Host smart-27fcce92-0b75-480d-9ce3-3596b426c3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22482
66370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2248266370
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1775157349
Short name T1460
Test name
Test status
Simulation time 169539219 ps
CPU time 0.87 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:01:17 PM PDT 24
Peak memory 207464 kb
Host smart-7ea5c669-54cc-4c6f-b7fc-fa543dfc4e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
57349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1775157349
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_resume_link_active.2708053632
Short name T3273
Test name
Test status
Simulation time 20151839179 ps
CPU time 24.72 seconds
Started Aug 10 07:01:15 PM PDT 24
Finished Aug 10 07:01:40 PM PDT 24
Peak memory 207560 kb
Host smart-9f2c75f3-f784-4870-92f3-c1a057a43c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
53632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_resume_link_active.2708053632
Directory /workspace/2.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.463035016
Short name T2676
Test name
Test status
Simulation time 221909810 ps
CPU time 0.92 seconds
Started Aug 10 07:01:14 PM PDT 24
Finished Aug 10 07:01:15 PM PDT 24
Peak memory 207492 kb
Host smart-0d09d4bd-d78e-4883-8343-90438dbb70a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46303
5016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.463035016
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_full.2710336868
Short name T2743
Test name
Test status
Simulation time 265279632 ps
CPU time 1.14 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:01:17 PM PDT 24
Peak memory 207540 kb
Host smart-c60752b5-bd48-4d3d-9bcf-3ac19bedbf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103
36868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.2710336868
Directory /workspace/2.usbdev_rx_full/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.3341914917
Short name T85
Test name
Test status
Simulation time 172467437 ps
CPU time 0.86 seconds
Started Aug 10 07:01:15 PM PDT 24
Finished Aug 10 07:01:16 PM PDT 24
Peak memory 207476 kb
Host smart-da2d319a-24b0-4303-9541-944194c2256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33419
14917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.3341914917
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2620059613
Short name T256
Test name
Test status
Simulation time 921799550 ps
CPU time 1.84 seconds
Started Aug 10 07:01:27 PM PDT 24
Finished Aug 10 07:01:29 PM PDT 24
Peak memory 224464 kb
Host smart-41e5ac74-31c2-46ef-b57c-303421d0d5ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2620059613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2620059613
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1835877518
Short name T54
Test name
Test status
Simulation time 348567140 ps
CPU time 1.28 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:01:17 PM PDT 24
Peak memory 207548 kb
Host smart-76bf51bd-94fa-4b8b-a553-308651017247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
77518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1835877518
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.1607766581
Short name T516
Test name
Test status
Simulation time 237273206 ps
CPU time 1.06 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:01:17 PM PDT 24
Peak memory 207556 kb
Host smart-f1a74337-3435-48b0-8a88-85cc165e1318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16077
66581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.1607766581
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.984394371
Short name T1062
Test name
Test status
Simulation time 179969293 ps
CPU time 0.86 seconds
Started Aug 10 07:01:18 PM PDT 24
Finished Aug 10 07:01:18 PM PDT 24
Peak memory 207504 kb
Host smart-739b150c-8730-4b1a-8a08-50afe4867f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98439
4371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.984394371
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2816929471
Short name T3294
Test name
Test status
Simulation time 159601249 ps
CPU time 0.84 seconds
Started Aug 10 07:01:18 PM PDT 24
Finished Aug 10 07:01:19 PM PDT 24
Peak memory 207508 kb
Host smart-168de4e1-8573-430d-bc38-45bc1e4ed6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
29471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2816929471
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2133365049
Short name T2654
Test name
Test status
Simulation time 261794287 ps
CPU time 1.09 seconds
Started Aug 10 07:01:17 PM PDT 24
Finished Aug 10 07:01:18 PM PDT 24
Peak memory 207608 kb
Host smart-eb37ed6b-3dfc-404b-a7e1-bb7d55c2e831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21333
65049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2133365049
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1452392412
Short name T2357
Test name
Test status
Simulation time 3141252793 ps
CPU time 92.36 seconds
Started Aug 10 07:01:18 PM PDT 24
Finished Aug 10 07:02:50 PM PDT 24
Peak memory 217788 kb
Host smart-2bb8973c-33bb-471c-b170-86a94dbb9c86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1452392412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1452392412
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3932458283
Short name T1679
Test name
Test status
Simulation time 170841250 ps
CPU time 0.89 seconds
Started Aug 10 07:01:15 PM PDT 24
Finished Aug 10 07:01:16 PM PDT 24
Peak memory 207420 kb
Host smart-9280d81c-d632-4322-8b8c-d77d9c85fab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39324
58283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3932458283
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2927488684
Short name T2271
Test name
Test status
Simulation time 176393490 ps
CPU time 0.86 seconds
Started Aug 10 07:01:16 PM PDT 24
Finished Aug 10 07:01:17 PM PDT 24
Peak memory 207508 kb
Host smart-76597e5b-726d-4c96-90f6-2847145655f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
88684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2927488684
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.3921914384
Short name T864
Test name
Test status
Simulation time 258975338 ps
CPU time 1.04 seconds
Started Aug 10 07:01:28 PM PDT 24
Finished Aug 10 07:01:29 PM PDT 24
Peak memory 207488 kb
Host smart-ceff8f9f-290c-4cf4-aaf9-ab963c020d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39219
14384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.3921914384
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2248054250
Short name T1380
Test name
Test status
Simulation time 3014455092 ps
CPU time 30.96 seconds
Started Aug 10 07:01:25 PM PDT 24
Finished Aug 10 07:01:56 PM PDT 24
Peak memory 216004 kb
Host smart-06e7f9e2-2c0c-435b-8b35-2ee9e20fa041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
54250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2248054250
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.435536457
Short name T90
Test name
Test status
Simulation time 10170496517 ps
CPU time 53.81 seconds
Started Aug 10 07:01:26 PM PDT 24
Finished Aug 10 07:02:20 PM PDT 24
Peak memory 224192 kb
Host smart-92dff2c1-6e14-46fb-8e92-a126b5896a32
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435536457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.435536457
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.1924028341
Short name T2186
Test name
Test status
Simulation time 3602158249 ps
CPU time 23.08 seconds
Started Aug 10 07:00:38 PM PDT 24
Finished Aug 10 07:01:01 PM PDT 24
Peak memory 207760 kb
Host smart-4c8670ed-47f4-4daf-9385-db3aac0b0a73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924028341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.1924028341
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_tx_rx_disruption.3029919836
Short name T2591
Test name
Test status
Simulation time 470021500 ps
CPU time 1.49 seconds
Started Aug 10 07:01:24 PM PDT 24
Finished Aug 10 07:01:26 PM PDT 24
Peak memory 207504 kb
Host smart-720da1a4-148e-4e2f-864b-d423952ffa6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029919836 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.usbdev_tx_rx_disruption.3029919836
Directory /workspace/2.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3222083617
Short name T1683
Test name
Test status
Simulation time 68283543 ps
CPU time 0.72 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:51 PM PDT 24
Peak memory 207536 kb
Host smart-40dd7308-fe15-46a3-a800-d49e81ccae86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3222083617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3222083617
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.674512105
Short name T848
Test name
Test status
Simulation time 10664010905 ps
CPU time 13.52 seconds
Started Aug 10 07:09:32 PM PDT 24
Finished Aug 10 07:09:46 PM PDT 24
Peak memory 207840 kb
Host smart-738e52a2-e5f3-4ea1-a44f-c50406cca416
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674512105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_ao
n_wake_disconnect.674512105
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.4085921229
Short name T770
Test name
Test status
Simulation time 19568030661 ps
CPU time 21.76 seconds
Started Aug 10 07:09:32 PM PDT 24
Finished Aug 10 07:09:54 PM PDT 24
Peak memory 207764 kb
Host smart-b8a5b929-87a9-49bb-a628-b0bbd3b18d23
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085921229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.4085921229
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2899123027
Short name T2210
Test name
Test status
Simulation time 31501186510 ps
CPU time 41.38 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:10:12 PM PDT 24
Peak memory 207820 kb
Host smart-3f4b2cf7-7245-4947-b0ec-feea5820e3c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899123027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.2899123027
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.169607711
Short name T1052
Test name
Test status
Simulation time 151240669 ps
CPU time 0.81 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:34 PM PDT 24
Peak memory 207548 kb
Host smart-b7fec292-9e79-4022-a079-b34dd86b27f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16960
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.169607711
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3969600205
Short name T1449
Test name
Test status
Simulation time 180491904 ps
CPU time 0.85 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:33 PM PDT 24
Peak memory 207500 kb
Host smart-59ee403a-62bf-43f0-b062-472e4cfa86ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
00205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3969600205
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3768585302
Short name T1459
Test name
Test status
Simulation time 449158606 ps
CPU time 1.77 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:35 PM PDT 24
Peak memory 207608 kb
Host smart-75421f5c-2e35-4bbe-98f8-654625e15d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37685
85302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3768585302
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2178832884
Short name T361
Test name
Test status
Simulation time 887795585 ps
CPU time 2.36 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:36 PM PDT 24
Peak memory 207712 kb
Host smart-fe4bf5cf-3535-48dc-9bf5-57ec27a71de4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2178832884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2178832884
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3112148774
Short name T3281
Test name
Test status
Simulation time 15044789288 ps
CPU time 24.11 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:55 PM PDT 24
Peak memory 207940 kb
Host smart-cedd9afe-03de-4a62-8b16-3317f892d61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
48774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3112148774
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.3364135459
Short name T3387
Test name
Test status
Simulation time 432047108 ps
CPU time 8.25 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:39 PM PDT 24
Peak memory 207736 kb
Host smart-909cb7b1-c9a1-4e91-a747-32f688f9847b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364135459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.3364135459
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2006847123
Short name T392
Test name
Test status
Simulation time 537299909 ps
CPU time 1.49 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:33 PM PDT 24
Peak memory 207520 kb
Host smart-a0a0a347-17e4-4074-9d06-1240bd46156c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
47123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2006847123
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.682711772
Short name T2183
Test name
Test status
Simulation time 184814945 ps
CPU time 0.86 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207500 kb
Host smart-611f37be-fb7e-4f4a-891b-164e684e44a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68271
1772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.682711772
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1103227891
Short name T926
Test name
Test status
Simulation time 75186144 ps
CPU time 0.73 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:31 PM PDT 24
Peak memory 207700 kb
Host smart-d12b62c3-aeaf-4294-81df-9ecf0496d502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032
27891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1103227891
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2287587119
Short name T1152
Test name
Test status
Simulation time 926939757 ps
CPU time 2.43 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207596 kb
Host smart-81c87a1f-0941-49b3-a7a1-bfc1eb61e145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22875
87119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2287587119
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_types.2200414768
Short name T404
Test name
Test status
Simulation time 612336434 ps
CPU time 1.56 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:31 PM PDT 24
Peak memory 207520 kb
Host smart-9dca9cf3-3ceb-4dce-9737-398b2d30e89f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2200414768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.2200414768
Directory /workspace/20.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.386444003
Short name T1608
Test name
Test status
Simulation time 225120885 ps
CPU time 1.58 seconds
Started Aug 10 07:09:31 PM PDT 24
Finished Aug 10 07:09:32 PM PDT 24
Peak memory 207708 kb
Host smart-68e3f17f-954b-4545-843b-1470cc02419a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.386444003
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2615902759
Short name T554
Test name
Test status
Simulation time 232935668 ps
CPU time 1.08 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:34 PM PDT 24
Peak memory 215932 kb
Host smart-5d1febe5-dbab-48a1-a7cb-89b1a7323e68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2615902759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2615902759
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1037061145
Short name T128
Test name
Test status
Simulation time 179333288 ps
CPU time 0.87 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:41 PM PDT 24
Peak memory 207424 kb
Host smart-a22470ea-6880-4266-83f0-2cd9633d3f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
61145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1037061145
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.325416958
Short name T2334
Test name
Test status
Simulation time 222246509 ps
CPU time 0.99 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207416 kb
Host smart-1a5151d0-91bb-4443-8361-003fc6a00829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
6958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.325416958
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.4161863863
Short name T194
Test name
Test status
Simulation time 3016670453 ps
CPU time 27.46 seconds
Started Aug 10 07:09:30 PM PDT 24
Finished Aug 10 07:09:58 PM PDT 24
Peak memory 218596 kb
Host smart-aaa5c304-4eb5-4bec-9ac6-aa1107c8b973
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4161863863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.4161863863
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2845282521
Short name T1093
Test name
Test status
Simulation time 6008549658 ps
CPU time 67.6 seconds
Started Aug 10 07:09:41 PM PDT 24
Finished Aug 10 07:10:48 PM PDT 24
Peak memory 207828 kb
Host smart-474452c5-6eb6-4e52-9453-a1f51f92a614
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2845282521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2845282521
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.639359933
Short name T1047
Test name
Test status
Simulation time 207044962 ps
CPU time 0.97 seconds
Started Aug 10 07:09:44 PM PDT 24
Finished Aug 10 07:09:45 PM PDT 24
Peak memory 207440 kb
Host smart-38c7e85c-368e-44a2-a9a1-ca16d47c7da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63935
9933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.639359933
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1659100884
Short name T2154
Test name
Test status
Simulation time 7690454588 ps
CPU time 9.32 seconds
Started Aug 10 07:09:43 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207836 kb
Host smart-5728865f-8b80-42e5-9da0-f6bd2809d3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
00884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1659100884
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2905557180
Short name T2288
Test name
Test status
Simulation time 9564695883 ps
CPU time 12.95 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:55 PM PDT 24
Peak memory 207836 kb
Host smart-dd06da63-9bd2-4411-af59-121f3edabed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
57180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2905557180
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.447168307
Short name T529
Test name
Test status
Simulation time 4064485880 ps
CPU time 40.01 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:10:20 PM PDT 24
Peak memory 224316 kb
Host smart-0a6a2870-7228-444b-93c6-57e3aa62abb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=447168307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.447168307
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.792508230
Short name T1377
Test name
Test status
Simulation time 2436336683 ps
CPU time 25.42 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:10:05 PM PDT 24
Peak memory 217808 kb
Host smart-e1ec243b-5b79-4a18-a12d-6b2ab58ada12
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=792508230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.792508230
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.4046166282
Short name T1141
Test name
Test status
Simulation time 256277151 ps
CPU time 1.06 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:42 PM PDT 24
Peak memory 207544 kb
Host smart-3b952f0e-4ce3-4907-b000-7feb59eb8f9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4046166282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.4046166282
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1177668779
Short name T548
Test name
Test status
Simulation time 190903478 ps
CPU time 0.86 seconds
Started Aug 10 07:09:41 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207536 kb
Host smart-473c37ca-a37e-4a74-a353-ffffca440a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
68779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1177668779
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.3205476077
Short name T2263
Test name
Test status
Simulation time 2060097727 ps
CPU time 60.12 seconds
Started Aug 10 07:09:41 PM PDT 24
Finished Aug 10 07:10:42 PM PDT 24
Peak memory 217432 kb
Host smart-87aabc7c-fd83-459a-8e59-10116d82a9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
76077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.3205476077
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.4248218261
Short name T2713
Test name
Test status
Simulation time 3891188033 ps
CPU time 114.69 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 217504 kb
Host smart-c78f7770-fb14-45a5-933f-5bd1f9324aaa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4248218261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.4248218261
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2001447200
Short name T2736
Test name
Test status
Simulation time 237228648 ps
CPU time 0.95 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:41 PM PDT 24
Peak memory 207532 kb
Host smart-48017f2a-8ea0-484a-b6e4-1a75b6de835d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2001447200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2001447200
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2485525147
Short name T1098
Test name
Test status
Simulation time 152023032 ps
CPU time 0.85 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:41 PM PDT 24
Peak memory 207528 kb
Host smart-17eb39a2-f5c7-48d8-8133-ef9f161532ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
25147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2485525147
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1326798729
Short name T2960
Test name
Test status
Simulation time 200872001 ps
CPU time 0.91 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207608 kb
Host smart-9ef5dcb3-0adf-474a-adf8-5bf97ca7fe47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
98729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1326798729
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4270859021
Short name T3290
Test name
Test status
Simulation time 199682442 ps
CPU time 0.92 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:41 PM PDT 24
Peak memory 207576 kb
Host smart-d33eceed-73ca-43d8-8e9a-5a2aa6601bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708
59021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4270859021
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2535086733
Short name T2933
Test name
Test status
Simulation time 175624721 ps
CPU time 0.87 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207544 kb
Host smart-5a7b1216-b59d-4944-b852-7ae8d262534b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25350
86733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2535086733
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1971892145
Short name T1150
Test name
Test status
Simulation time 158382217 ps
CPU time 0.82 seconds
Started Aug 10 07:09:43 PM PDT 24
Finished Aug 10 07:09:44 PM PDT 24
Peak memory 207564 kb
Host smart-db5752c8-9308-4531-8e6e-76971d48369b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
92145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1971892145
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2227915670
Short name T166
Test name
Test status
Simulation time 158651167 ps
CPU time 0.82 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207552 kb
Host smart-a76a59d5-9ebb-4c47-824a-c2fa2f8427d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
15670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2227915670
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3541652619
Short name T3152
Test name
Test status
Simulation time 276112782 ps
CPU time 1.12 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207544 kb
Host smart-65ed80cb-d525-41be-bedc-915d18cacf30
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3541652619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3541652619
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2578887421
Short name T2
Test name
Test status
Simulation time 158726082 ps
CPU time 0.89 seconds
Started Aug 10 07:09:43 PM PDT 24
Finished Aug 10 07:09:44 PM PDT 24
Peak memory 207412 kb
Host smart-d0e28534-f3d1-475e-84c7-8cabfd32a30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
87421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2578887421
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.21563720
Short name T1077
Test name
Test status
Simulation time 71269858 ps
CPU time 0.74 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:09:41 PM PDT 24
Peak memory 207472 kb
Host smart-f8d76f26-f315-48d0-92b5-bd0787ffef70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.21563720
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1994608766
Short name T318
Test name
Test status
Simulation time 9708800092 ps
CPU time 25.85 seconds
Started Aug 10 07:09:40 PM PDT 24
Finished Aug 10 07:10:06 PM PDT 24
Peak memory 215956 kb
Host smart-f8e462fb-34e8-4a8d-b9d5-9fd770265b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19946
08766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1994608766
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3415826439
Short name T1299
Test name
Test status
Simulation time 180052548 ps
CPU time 0.9 seconds
Started Aug 10 07:09:43 PM PDT 24
Finished Aug 10 07:09:44 PM PDT 24
Peak memory 207104 kb
Host smart-6bac06a9-a844-4a2f-a2e8-22c75bcd974a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34158
26439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3415826439
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1173362874
Short name T2377
Test name
Test status
Simulation time 254561617 ps
CPU time 0.97 seconds
Started Aug 10 07:09:41 PM PDT 24
Finished Aug 10 07:09:42 PM PDT 24
Peak memory 207412 kb
Host smart-44a73636-5fa2-413c-bfe6-856bee331327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11733
62874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1173362874
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3414461965
Short name T1024
Test name
Test status
Simulation time 242169131 ps
CPU time 0.98 seconds
Started Aug 10 07:09:43 PM PDT 24
Finished Aug 10 07:09:45 PM PDT 24
Peak memory 207092 kb
Host smart-44c8b2cc-60e1-4e45-9714-6fa267ebce57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34144
61965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3414461965
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3579826993
Short name T1917
Test name
Test status
Simulation time 251185943 ps
CPU time 1 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:44 PM PDT 24
Peak memory 207420 kb
Host smart-8812b071-62a3-4de6-8e8a-e892ceee2553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798
26993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3579826993
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4280027176
Short name T2066
Test name
Test status
Simulation time 166991608 ps
CPU time 0.88 seconds
Started Aug 10 07:09:42 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207548 kb
Host smart-8272a832-272d-4e0a-b42b-1059db4f8cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
27176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4280027176
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_rx_full.4115396676
Short name T3206
Test name
Test status
Simulation time 254641148 ps
CPU time 1.12 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207652 kb
Host smart-91f350ab-c682-4787-ac89-079e8e6eab39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
96676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.4115396676
Directory /workspace/20.usbdev_rx_full/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1715208517
Short name T1467
Test name
Test status
Simulation time 154619199 ps
CPU time 0.8 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:51 PM PDT 24
Peak memory 207540 kb
Host smart-719f544f-b141-4e0e-837f-33868e2e9fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
08517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1715208517
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.4164380957
Short name T3249
Test name
Test status
Simulation time 159590845 ps
CPU time 0.84 seconds
Started Aug 10 07:09:51 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207512 kb
Host smart-bc419239-928e-4358-a6a9-fd55353a4032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
80957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.4164380957
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.793891653
Short name T1715
Test name
Test status
Simulation time 194312296 ps
CPU time 1 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207516 kb
Host smart-4c332630-9529-4c9c-8ca8-1153f9d58281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79389
1653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.793891653
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2684520344
Short name T2462
Test name
Test status
Simulation time 2839110918 ps
CPU time 22.25 seconds
Started Aug 10 07:09:51 PM PDT 24
Finished Aug 10 07:10:13 PM PDT 24
Peak memory 224304 kb
Host smart-f9d7f7d6-215c-40bc-9460-fff3bce146ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2684520344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2684520344
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1982965938
Short name T3033
Test name
Test status
Simulation time 176886730 ps
CPU time 0.92 seconds
Started Aug 10 07:09:51 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207536 kb
Host smart-e5f96be1-1e97-4c69-92cd-7485c58638d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
65938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1982965938
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3439491295
Short name T625
Test name
Test status
Simulation time 234245799 ps
CPU time 0.94 seconds
Started Aug 10 07:09:51 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207536 kb
Host smart-8a7cef9f-5def-41ac-b792-33625d4cef4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34394
91295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3439491295
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1616611580
Short name T1265
Test name
Test status
Simulation time 1205844508 ps
CPU time 2.89 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:55 PM PDT 24
Peak memory 207684 kb
Host smart-04dfef53-a55e-47c0-b44c-5dee477f4c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
11580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1616611580
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.4143942874
Short name T3452
Test name
Test status
Simulation time 4375537589 ps
CPU time 33.76 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:10:24 PM PDT 24
Peak memory 216004 kb
Host smart-7187524b-741a-4862-a878-e194032f9338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41439
42874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.4143942874
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.3114994799
Short name T2353
Test name
Test status
Simulation time 1057285669 ps
CPU time 9.48 seconds
Started Aug 10 07:09:33 PM PDT 24
Finished Aug 10 07:09:43 PM PDT 24
Peak memory 207696 kb
Host smart-919c8db4-4c78-486f-a0d3-6fc8f5f0f7ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114994799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.3114994799
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_tx_rx_disruption.2480531344
Short name T3163
Test name
Test status
Simulation time 536114128 ps
CPU time 1.52 seconds
Started Aug 10 07:09:48 PM PDT 24
Finished Aug 10 07:09:50 PM PDT 24
Peak memory 207588 kb
Host smart-4a05698d-2164-4c6f-8af1-f63dbdd917b0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480531344 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.usbdev_tx_rx_disruption.2480531344
Directory /workspace/20.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/200.usbdev_tx_rx_disruption.3279339479
Short name T2863
Test name
Test status
Simulation time 512732993 ps
CPU time 1.49 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207536 kb
Host smart-261877c3-619d-4da4-ae42-b98546f6eb32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279339479 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.usbdev_tx_rx_disruption.3279339479
Directory /workspace/200.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/201.usbdev_tx_rx_disruption.2758896829
Short name T2991
Test name
Test status
Simulation time 453868434 ps
CPU time 1.37 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207572 kb
Host smart-73d0fd98-a093-4716-8816-a526614f6d1c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758896829 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.usbdev_tx_rx_disruption.2758896829
Directory /workspace/201.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/202.usbdev_tx_rx_disruption.2908120023
Short name T2261
Test name
Test status
Simulation time 531552348 ps
CPU time 1.57 seconds
Started Aug 10 07:17:56 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207664 kb
Host smart-c10f6b5f-b8f3-4357-8a3b-9d3c6f26cbc7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908120023 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.usbdev_tx_rx_disruption.2908120023
Directory /workspace/202.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/203.usbdev_tx_rx_disruption.837946855
Short name T1830
Test name
Test status
Simulation time 641051096 ps
CPU time 1.74 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207808 kb
Host smart-c97fdc4f-2f88-43bd-bf93-5f1e09721e6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837946855 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 203.usbdev_tx_rx_disruption.837946855
Directory /workspace/203.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/204.usbdev_tx_rx_disruption.1223450263
Short name T1301
Test name
Test status
Simulation time 470929032 ps
CPU time 1.54 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207768 kb
Host smart-44654d69-fede-4f4f-b0c9-64ae93de9931
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223450263 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.usbdev_tx_rx_disruption.1223450263
Directory /workspace/204.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/205.usbdev_tx_rx_disruption.2331578434
Short name T218
Test name
Test status
Simulation time 459620154 ps
CPU time 1.5 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207600 kb
Host smart-be65bfa1-af7a-4418-bc5b-cc745f19f1eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331578434 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.usbdev_tx_rx_disruption.2331578434
Directory /workspace/205.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/206.usbdev_tx_rx_disruption.2736667935
Short name T2176
Test name
Test status
Simulation time 578168347 ps
CPU time 1.58 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207564 kb
Host smart-ad22f4ba-8a51-4aea-a8f5-7e5cf94ec115
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736667935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.usbdev_tx_rx_disruption.2736667935
Directory /workspace/206.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/207.usbdev_tx_rx_disruption.2701798246
Short name T1206
Test name
Test status
Simulation time 517244825 ps
CPU time 1.64 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207520 kb
Host smart-853a234a-5a69-4e47-89c9-00f373a1e464
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701798246 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.usbdev_tx_rx_disruption.2701798246
Directory /workspace/207.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/208.usbdev_tx_rx_disruption.2181667196
Short name T2450
Test name
Test status
Simulation time 582283322 ps
CPU time 1.66 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207668 kb
Host smart-5240f7be-1ebd-46d0-8e55-595c5c8d8b15
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181667196 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.usbdev_tx_rx_disruption.2181667196
Directory /workspace/208.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/209.usbdev_tx_rx_disruption.3899551178
Short name T3216
Test name
Test status
Simulation time 529362114 ps
CPU time 1.57 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207572 kb
Host smart-10585721-bd4b-43fb-a38d-f9ddca7c0a3b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899551178 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.usbdev_tx_rx_disruption.3899551178
Directory /workspace/209.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3806011490
Short name T3392
Test name
Test status
Simulation time 65419390 ps
CPU time 0.72 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 207544 kb
Host smart-b9226143-6d08-44a9-89d2-d4555f5b8251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3806011490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3806011490
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3408651375
Short name T3412
Test name
Test status
Simulation time 10307738417 ps
CPU time 15.32 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:10:06 PM PDT 24
Peak memory 207816 kb
Host smart-19073961-7556-43ca-8a8b-a80ec3a5cb17
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408651375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.3408651375
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.760259421
Short name T2343
Test name
Test status
Simulation time 15011745629 ps
CPU time 17.93 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 215960 kb
Host smart-d2db18f4-89e0-40eb-b207-7145957f99bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=760259421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.760259421
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.574170216
Short name T3522
Test name
Test status
Simulation time 24811571342 ps
CPU time 30.5 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:10:20 PM PDT 24
Peak memory 216016 kb
Host smart-505ea829-80b8-45d8-8fb9-0bf0eea2b3cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574170216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_ao
n_wake_resume.574170216
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3486439312
Short name T1532
Test name
Test status
Simulation time 191078128 ps
CPU time 0.94 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207476 kb
Host smart-94f615fd-8e9b-4062-abe1-f025c204860e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34864
39312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3486439312
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3782342593
Short name T1765
Test name
Test status
Simulation time 148847755 ps
CPU time 0.86 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207512 kb
Host smart-12c08ff4-4b93-4726-bebd-be41d0ca0136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
42593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3782342593
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2053277168
Short name T2175
Test name
Test status
Simulation time 267670788 ps
CPU time 1.14 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:54 PM PDT 24
Peak memory 207604 kb
Host smart-03b42f88-cd95-4b9b-a683-40282174cfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20532
77168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2053277168
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3856947915
Short name T364
Test name
Test status
Simulation time 1033697086 ps
CPU time 3.05 seconds
Started Aug 10 07:09:48 PM PDT 24
Finished Aug 10 07:09:51 PM PDT 24
Peak memory 207724 kb
Host smart-ad6e292a-e7ab-420f-80ee-1b91a2cf6d96
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3856947915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3856947915
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3197814069
Short name T3542
Test name
Test status
Simulation time 34921389274 ps
CPU time 58.13 seconds
Started Aug 10 07:09:49 PM PDT 24
Finished Aug 10 07:10:47 PM PDT 24
Peak memory 207888 kb
Host smart-9068593a-f47b-4784-8fd8-67117cbd4fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978
14069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3197814069
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.3370649106
Short name T559
Test name
Test status
Simulation time 462076388 ps
CPU time 7.9 seconds
Started Aug 10 07:09:51 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207648 kb
Host smart-f2697fe6-46c6-46f0-9aec-6380474a5a08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370649106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.3370649106
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1062380461
Short name T1038
Test name
Test status
Simulation time 563216440 ps
CPU time 1.6 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:52 PM PDT 24
Peak memory 207520 kb
Host smart-43d5fcf2-2efa-49d2-bf49-fc3dba5974c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10623
80461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1062380461
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3713305977
Short name T1004
Test name
Test status
Simulation time 139451198 ps
CPU time 0.84 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207388 kb
Host smart-f3d4841c-83eb-47b6-b28f-50a2b76d60e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37133
05977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3713305977
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.468499341
Short name T24
Test name
Test status
Simulation time 51394570 ps
CPU time 0.7 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207568 kb
Host smart-113f858d-b8eb-4554-bc34-bdf9de63638f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46849
9341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.468499341
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1528505368
Short name T876
Test name
Test status
Simulation time 816560833 ps
CPU time 2.23 seconds
Started Aug 10 07:09:50 PM PDT 24
Finished Aug 10 07:09:53 PM PDT 24
Peak memory 207912 kb
Host smart-e19fe005-a3e0-4d48-99dd-ae40fab18f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15285
05368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1528505368
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_types.2450252416
Short name T490
Test name
Test status
Simulation time 414832015 ps
CPU time 1.37 seconds
Started Aug 10 07:09:53 PM PDT 24
Finished Aug 10 07:09:54 PM PDT 24
Peak memory 207564 kb
Host smart-362f1965-7418-4b7f-8bff-26774140da91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2450252416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.2450252416
Directory /workspace/21.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1841710043
Short name T3072
Test name
Test status
Simulation time 174518295 ps
CPU time 2.07 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:09:54 PM PDT 24
Peak memory 207660 kb
Host smart-1c68b2e6-8764-402f-8828-c744ae763b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18417
10043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1841710043
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2773274098
Short name T624
Test name
Test status
Simulation time 211830191 ps
CPU time 1.11 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:01 PM PDT 24
Peak memory 215920 kb
Host smart-9594afca-41ce-46cf-bbee-f9b148ed385b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2773274098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2773274098
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2055039983
Short name T1596
Test name
Test status
Simulation time 138911293 ps
CPU time 0.84 seconds
Started Aug 10 07:10:02 PM PDT 24
Finished Aug 10 07:10:03 PM PDT 24
Peak memory 207052 kb
Host smart-46b29c07-0c30-46fe-81f8-e80083dce650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20550
39983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2055039983
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.238948242
Short name T540
Test name
Test status
Simulation time 212410132 ps
CPU time 0.94 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207568 kb
Host smart-9096d022-f3c2-43a9-9345-6f2c5e4248b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
8242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.238948242
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1976367782
Short name T2596
Test name
Test status
Simulation time 3177342006 ps
CPU time 25.56 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:10:24 PM PDT 24
Peak memory 218272 kb
Host smart-8a7e1177-002b-41b6-af01-e9d7e5e9f640
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1976367782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1976367782
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.857683829
Short name T3582
Test name
Test status
Simulation time 11410804209 ps
CPU time 133.22 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:12:12 PM PDT 24
Peak memory 207824 kb
Host smart-0f3e69af-69b8-4a0b-bb76-1070fcfcbe98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=857683829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.857683829
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.4055856911
Short name T1935
Test name
Test status
Simulation time 163748882 ps
CPU time 0.85 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207564 kb
Host smart-6a7f992a-7e88-4d14-8a66-20f14ab76665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
56911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.4055856911
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.149441072
Short name T2705
Test name
Test status
Simulation time 27966884071 ps
CPU time 39.43 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:39 PM PDT 24
Peak memory 207872 kb
Host smart-7fca9aeb-1727-4c0d-bac9-98ce595a3fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
1072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.149441072
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3655872444
Short name T3091
Test name
Test status
Simulation time 5678395018 ps
CPU time 8.77 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 207776 kb
Host smart-0b46a12c-fbe8-40df-9866-f4885c34f78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558
72444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3655872444
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1945734574
Short name T2096
Test name
Test status
Simulation time 5183383724 ps
CPU time 41.2 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 218404 kb
Host smart-f872ee9f-bc06-4329-b99a-e02d2f5c53de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1945734574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1945734574
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1920172744
Short name T1813
Test name
Test status
Simulation time 1950690186 ps
CPU time 19.76 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:20 PM PDT 24
Peak memory 216684 kb
Host smart-631302e9-6f8e-41d6-b532-fa20c835ad3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1920172744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1920172744
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.4086570961
Short name T2285
Test name
Test status
Simulation time 240850433 ps
CPU time 0.96 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:01 PM PDT 24
Peak memory 207356 kb
Host smart-341d472a-8709-46f1-a082-460ba45f062e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4086570961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4086570961
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2951506479
Short name T3021
Test name
Test status
Simulation time 199306056 ps
CPU time 0.89 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207528 kb
Host smart-45eceda7-6136-4d5e-b7d0-de599b489782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
06479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2951506479
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.2692648306
Short name T1055
Test name
Test status
Simulation time 2949975824 ps
CPU time 21.14 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:22 PM PDT 24
Peak memory 207888 kb
Host smart-7c65e410-ac5b-48ec-918d-1c719ed068a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
48306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.2692648306
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3570708085
Short name T2278
Test name
Test status
Simulation time 1979218221 ps
CPU time 14.77 seconds
Started Aug 10 07:10:02 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 224116 kb
Host smart-9a47cc89-d85c-4026-8034-0f142f5bcb51
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3570708085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3570708085
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2177920471
Short name T2578
Test name
Test status
Simulation time 176870262 ps
CPU time 0.9 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:01 PM PDT 24
Peak memory 207548 kb
Host smart-b02788a0-0674-4649-81c5-294487428bbd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2177920471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2177920471
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.851950187
Short name T2157
Test name
Test status
Simulation time 158233596 ps
CPU time 0.88 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207580 kb
Host smart-c921739d-7df2-4f1f-9688-f27b34cfa854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85195
0187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.851950187
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.879410783
Short name T2741
Test name
Test status
Simulation time 181704193 ps
CPU time 0.85 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207532 kb
Host smart-ef45bf42-fea1-45b7-b53a-1186d565ce7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87941
0783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.879410783
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.903227763
Short name T2158
Test name
Test status
Simulation time 191010031 ps
CPU time 0.98 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207412 kb
Host smart-43f13c92-02b9-4f08-b5a2-f2d2030f88b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90322
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.903227763
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.599185568
Short name T2679
Test name
Test status
Simulation time 143966840 ps
CPU time 0.87 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207604 kb
Host smart-e005a55e-c5c6-44a4-9f63-d7d88b7ad716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59918
5568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.599185568
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1921562586
Short name T1143
Test name
Test status
Simulation time 158266139 ps
CPU time 0.87 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207504 kb
Host smart-92b2ca90-e06d-4301-9400-f0a601527157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
62586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1921562586
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2801560611
Short name T2869
Test name
Test status
Simulation time 203939237 ps
CPU time 0.95 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207440 kb
Host smart-b3f5681d-fb6a-43e9-b606-4a774bc842e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28015
60611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2801560611
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2252465595
Short name T2575
Test name
Test status
Simulation time 174223895 ps
CPU time 0.9 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207572 kb
Host smart-7e53c972-926b-48fe-b3da-724c2b361625
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2252465595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2252465595
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2868077517
Short name T2319
Test name
Test status
Simulation time 147414890 ps
CPU time 0.87 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207448 kb
Host smart-d110a91f-4b59-449c-b706-dddbca4c0c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28680
77517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2868077517
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2086114330
Short name T3150
Test name
Test status
Simulation time 60646260 ps
CPU time 0.7 seconds
Started Aug 10 07:10:00 PM PDT 24
Finished Aug 10 07:10:01 PM PDT 24
Peak memory 207508 kb
Host smart-09e33266-c9a6-45f1-b298-0e97acea3cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
14330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2086114330
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1779829868
Short name T3286
Test name
Test status
Simulation time 14313268299 ps
CPU time 37.22 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:36 PM PDT 24
Peak memory 215988 kb
Host smart-0bfbec91-a83c-4931-9827-3a05d7c991f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
29868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1779829868
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1198595971
Short name T3240
Test name
Test status
Simulation time 215006797 ps
CPU time 0.94 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207516 kb
Host smart-319b5358-e485-4e4a-b7e0-8710483eff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11985
95971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1198595971
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2877130187
Short name T2802
Test name
Test status
Simulation time 227513073 ps
CPU time 0.96 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207564 kb
Host smart-ac874b92-6377-4c89-bc7d-091fd36ae046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
30187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2877130187
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3276645482
Short name T1983
Test name
Test status
Simulation time 237053399 ps
CPU time 0.97 seconds
Started Aug 10 07:09:58 PM PDT 24
Finished Aug 10 07:09:59 PM PDT 24
Peak memory 207576 kb
Host smart-a710cb04-dd4b-4300-a134-26d64fc57967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32766
45482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3276645482
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3247316968
Short name T598
Test name
Test status
Simulation time 202519868 ps
CPU time 0.99 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207564 kb
Host smart-b126b3b4-25f2-4a7d-842e-bc1d756b243c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
16968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3247316968
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3917185070
Short name T2221
Test name
Test status
Simulation time 202460243 ps
CPU time 0.94 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207648 kb
Host smart-28b2746b-dbc7-413c-9886-6e25bd89ca42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
85070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3917185070
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_rx_full.2997525014
Short name T3384
Test name
Test status
Simulation time 248179378 ps
CPU time 1.19 seconds
Started Aug 10 07:10:02 PM PDT 24
Finished Aug 10 07:10:03 PM PDT 24
Peak memory 206904 kb
Host smart-bbad9bdb-dcec-4fb6-b7b0-364a033e565a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
25014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.2997525014
Directory /workspace/21.usbdev_rx_full/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2136182082
Short name T118
Test name
Test status
Simulation time 166459358 ps
CPU time 0.87 seconds
Started Aug 10 07:09:59 PM PDT 24
Finished Aug 10 07:10:00 PM PDT 24
Peak memory 207572 kb
Host smart-3e902212-71b8-45d4-a99b-b96da30d8f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21361
82082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2136182082
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.163339975
Short name T2408
Test name
Test status
Simulation time 183439255 ps
CPU time 0.84 seconds
Started Aug 10 07:10:01 PM PDT 24
Finished Aug 10 07:10:02 PM PDT 24
Peak memory 207532 kb
Host smart-4764651d-4bc7-421b-b621-feafd1f1ad9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16333
9975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.163339975
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.294650592
Short name T1540
Test name
Test status
Simulation time 241744811 ps
CPU time 1.07 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:09 PM PDT 24
Peak memory 207512 kb
Host smart-fc3af2f9-2fd8-4c81-b56c-5b4db676efb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29465
0592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.294650592
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.975412688
Short name T1167
Test name
Test status
Simulation time 2912286502 ps
CPU time 84.22 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:11:33 PM PDT 24
Peak memory 224272 kb
Host smart-d87f6443-0082-4e78-a21d-072c165a2e25
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=975412688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.975412688
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.295608619
Short name T1319
Test name
Test status
Simulation time 222684788 ps
CPU time 0.9 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:09 PM PDT 24
Peak memory 207660 kb
Host smart-4cd94c79-c10a-498f-9cbd-1280c9061bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
8619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.295608619
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3295071567
Short name T2630
Test name
Test status
Simulation time 148090329 ps
CPU time 0.82 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:09 PM PDT 24
Peak memory 207608 kb
Host smart-ddb942f5-a70b-49d3-8d4b-8a186c4ac72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32950
71567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3295071567
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.2981498729
Short name T2566
Test name
Test status
Simulation time 1330455434 ps
CPU time 3.32 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:10:13 PM PDT 24
Peak memory 207784 kb
Host smart-13abeadd-87b7-4686-a805-b144f6dba65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
98729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.2981498729
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1621677673
Short name T3354
Test name
Test status
Simulation time 2575755419 ps
CPU time 18.59 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207920 kb
Host smart-f59c2745-273d-47ca-a9fe-d0fec54aacd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
77673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1621677673
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.3922087048
Short name T1722
Test name
Test status
Simulation time 6112160495 ps
CPU time 42.72 seconds
Started Aug 10 07:09:52 PM PDT 24
Finished Aug 10 07:10:34 PM PDT 24
Peak memory 207732 kb
Host smart-7b1a4547-65cb-42cc-aff9-92d110647195
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922087048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.3922087048
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/210.usbdev_tx_rx_disruption.140489960
Short name T3306
Test name
Test status
Simulation time 565779462 ps
CPU time 1.55 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207544 kb
Host smart-8ad4f348-0ffa-444f-b124-511886ae2816
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140489960 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.usbdev_tx_rx_disruption.140489960
Directory /workspace/210.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/211.usbdev_tx_rx_disruption.605744334
Short name T1124
Test name
Test status
Simulation time 558561032 ps
CPU time 1.72 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207496 kb
Host smart-0794f481-31ba-47f5-a879-04822dbe0d2f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605744334 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 211.usbdev_tx_rx_disruption.605744334
Directory /workspace/211.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/213.usbdev_tx_rx_disruption.1286276758
Short name T1680
Test name
Test status
Simulation time 445778280 ps
CPU time 1.46 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207564 kb
Host smart-b5783bc3-d5eb-4a72-bab2-feed94f306bb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286276758 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.usbdev_tx_rx_disruption.1286276758
Directory /workspace/213.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/214.usbdev_tx_rx_disruption.346770005
Short name T1780
Test name
Test status
Simulation time 492347357 ps
CPU time 1.44 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207600 kb
Host smart-c2cc43a1-4b5e-4875-a78c-983c93771cdf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346770005 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.usbdev_tx_rx_disruption.346770005
Directory /workspace/214.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/215.usbdev_tx_rx_disruption.3507944575
Short name T1396
Test name
Test status
Simulation time 528189161 ps
CPU time 1.53 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207544 kb
Host smart-dda98691-6946-42a1-8496-6259f578bf27
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507944575 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.usbdev_tx_rx_disruption.3507944575
Directory /workspace/215.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/216.usbdev_tx_rx_disruption.3919081835
Short name T1600
Test name
Test status
Simulation time 602204263 ps
CPU time 1.65 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207552 kb
Host smart-2400cd46-e4f6-4432-9fe5-274f2c182c42
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919081835 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.usbdev_tx_rx_disruption.3919081835
Directory /workspace/216.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/217.usbdev_tx_rx_disruption.2450184661
Short name T813
Test name
Test status
Simulation time 418990332 ps
CPU time 1.55 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:54 PM PDT 24
Peak memory 207500 kb
Host smart-50b09db5-c171-4b30-a8b8-05de44da5df7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450184661 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.usbdev_tx_rx_disruption.2450184661
Directory /workspace/217.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/218.usbdev_tx_rx_disruption.3349581478
Short name T1415
Test name
Test status
Simulation time 508649029 ps
CPU time 1.52 seconds
Started Aug 10 07:17:53 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207588 kb
Host smart-e5f0f2ce-024e-41aa-8c41-d74d0f91ffc7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349581478 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.usbdev_tx_rx_disruption.3349581478
Directory /workspace/218.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/219.usbdev_tx_rx_disruption.3485724250
Short name T2908
Test name
Test status
Simulation time 509390848 ps
CPU time 1.5 seconds
Started Aug 10 07:17:50 PM PDT 24
Finished Aug 10 07:17:52 PM PDT 24
Peak memory 207600 kb
Host smart-0ccccd70-86de-4c3f-adb0-687abd8fcafc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485724250 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.usbdev_tx_rx_disruption.3485724250
Directory /workspace/219.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.78049092
Short name T3311
Test name
Test status
Simulation time 47259961 ps
CPU time 0.69 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:10:26 PM PDT 24
Peak memory 207560 kb
Host smart-b73015e8-024a-49ed-88e9-eab168a0b6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=78049092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.78049092
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2946998849
Short name T2023
Test name
Test status
Simulation time 10449750479 ps
CPU time 16.43 seconds
Started Aug 10 07:10:10 PM PDT 24
Finished Aug 10 07:10:26 PM PDT 24
Peak memory 207832 kb
Host smart-0610c488-634e-4a15-b17f-9099d77a71d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946998849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.2946998849
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1724672581
Short name T999
Test name
Test status
Simulation time 14637834843 ps
CPU time 20.41 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:29 PM PDT 24
Peak memory 215940 kb
Host smart-1f4f7a81-092f-4f3d-b8e7-a2acb6c32f2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724672581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1724672581
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2619588917
Short name T3454
Test name
Test status
Simulation time 23836661313 ps
CPU time 29.13 seconds
Started Aug 10 07:10:07 PM PDT 24
Finished Aug 10 07:10:37 PM PDT 24
Peak memory 216044 kb
Host smart-bae27c7e-a36b-4c9d-ba98-f2cfcdb7a2af
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619588917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.2619588917
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.748024450
Short name T2662
Test name
Test status
Simulation time 154553039 ps
CPU time 0.87 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207556 kb
Host smart-f5b89a7e-5fd2-4ba3-83ea-8d69f4ff496b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74802
4450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.748024450
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2552531732
Short name T1241
Test name
Test status
Simulation time 164994426 ps
CPU time 0.83 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:09 PM PDT 24
Peak memory 207448 kb
Host smart-78a2b6ed-d11d-49bd-a25b-3d5a45612def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25525
31732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2552531732
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3058552754
Short name T1522
Test name
Test status
Simulation time 434790230 ps
CPU time 1.42 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207556 kb
Host smart-894f6fc4-c65c-4fe7-888b-44bc78a1be5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
52754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3058552754
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3847386512
Short name T2853
Test name
Test status
Simulation time 1309914518 ps
CPU time 3.28 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:20 PM PDT 24
Peak memory 207732 kb
Host smart-782d5b42-c54e-46ad-8917-c20d8a5e53ec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3847386512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3847386512
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1740276971
Short name T3458
Test name
Test status
Simulation time 43928302066 ps
CPU time 70.04 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207712 kb
Host smart-8c8a44af-ca3e-4250-ae43-6902893836f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17402
76971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1740276971
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.667113636
Short name T1590
Test name
Test status
Simulation time 5621473016 ps
CPU time 36.77 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:45 PM PDT 24
Peak memory 208040 kb
Host smart-1f4fe4b6-e3de-4167-b535-dd5b055cba01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667113636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.667113636
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.225536723
Short name T1994
Test name
Test status
Simulation time 606795455 ps
CPU time 1.65 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207524 kb
Host smart-5852d846-dc05-4edf-85b6-618d84225ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
6723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.225536723
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1811232864
Short name T2641
Test name
Test status
Simulation time 136208958 ps
CPU time 0.78 seconds
Started Aug 10 07:10:10 PM PDT 24
Finished Aug 10 07:10:11 PM PDT 24
Peak memory 207412 kb
Host smart-fc8469e2-1742-414b-9c3b-48589df3c851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
32864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1811232864
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.4173275013
Short name T289
Test name
Test status
Simulation time 36306331 ps
CPU time 0.7 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:09 PM PDT 24
Peak memory 207528 kb
Host smart-8b9d9448-8e5a-480f-9c22-27dded4928e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
75013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.4173275013
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3890482202
Short name T2865
Test name
Test status
Simulation time 844132787 ps
CPU time 2.15 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 207684 kb
Host smart-8a353310-58cd-4e90-bc36-42285205589e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38904
82202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3890482202
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_types.205116405
Short name T455
Test name
Test status
Simulation time 444337449 ps
CPU time 1.28 seconds
Started Aug 10 07:10:06 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 207508 kb
Host smart-c92f930a-1b95-4db6-a21c-3340adebe5ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=205116405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.205116405
Directory /workspace/22.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3438187322
Short name T2900
Test name
Test status
Simulation time 214081315 ps
CPU time 1.4 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 207720 kb
Host smart-3956484a-9286-49c7-878f-a4a00b4a2540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34381
87322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3438187322
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.142488554
Short name T1347
Test name
Test status
Simulation time 248361018 ps
CPU time 1.12 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 215888 kb
Host smart-a7ec1e44-2b25-45e6-b785-99cc137d39c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=142488554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.142488554
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2916742262
Short name T2177
Test name
Test status
Simulation time 174186838 ps
CPU time 0.84 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:10:10 PM PDT 24
Peak memory 207548 kb
Host smart-78709239-a844-4bff-97df-477248ee7b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
42262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2916742262
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3989292905
Short name T2757
Test name
Test status
Simulation time 213211654 ps
CPU time 0.98 seconds
Started Aug 10 07:10:10 PM PDT 24
Finished Aug 10 07:10:11 PM PDT 24
Peak memory 207400 kb
Host smart-00e9beb2-b0dd-4c97-89e0-45213591d788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
92905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3989292905
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.58838502
Short name T2766
Test name
Test status
Simulation time 5493927111 ps
CPU time 57.47 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:11:07 PM PDT 24
Peak memory 224240 kb
Host smart-9d95c5b8-58b3-4c07-8c7d-7c49a6b7ed87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=58838502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.58838502
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.300690755
Short name T3316
Test name
Test status
Simulation time 10372705368 ps
CPU time 138.02 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:12:27 PM PDT 24
Peak memory 207820 kb
Host smart-91af619e-51f9-44d9-bb3f-7ae4326c4264
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=300690755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.300690755
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2997692759
Short name T3271
Test name
Test status
Simulation time 204206127 ps
CPU time 0.87 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:16 PM PDT 24
Peak memory 207556 kb
Host smart-332016a0-67f2-4bd7-a09e-51420499dd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29976
92759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2997692759
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.4120922509
Short name T2352
Test name
Test status
Simulation time 14846179277 ps
CPU time 19.46 seconds
Started Aug 10 07:10:08 PM PDT 24
Finished Aug 10 07:10:28 PM PDT 24
Peak memory 207904 kb
Host smart-34bf5ce1-cedb-4dcb-8c7c-8568d8bc7de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
22509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.4120922509
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.4034747605
Short name T1252
Test name
Test status
Simulation time 9455152922 ps
CPU time 12.11 seconds
Started Aug 10 07:10:07 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207844 kb
Host smart-8fb96f51-295c-4a33-927b-73afa09f7157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
47605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.4034747605
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.4000143782
Short name T3448
Test name
Test status
Simulation time 4766669800 ps
CPU time 131.69 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:12:21 PM PDT 24
Peak memory 224284 kb
Host smart-466603fb-c26b-4afa-982d-0afd0af2beed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4000143782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.4000143782
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.701054876
Short name T1355
Test name
Test status
Simulation time 2420803270 ps
CPU time 18.03 seconds
Started Aug 10 07:10:09 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 217888 kb
Host smart-ed6e0149-01dd-48b9-aa5c-3f11dc96d151
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=701054876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.701054876
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.4088151453
Short name T2696
Test name
Test status
Simulation time 237231098 ps
CPU time 0.96 seconds
Started Aug 10 07:10:07 PM PDT 24
Finished Aug 10 07:10:08 PM PDT 24
Peak memory 207584 kb
Host smart-23378849-c986-4cd5-8107-bc07db9ddaa5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4088151453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4088151453
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2958046244
Short name T2053
Test name
Test status
Simulation time 190846234 ps
CPU time 0.92 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207548 kb
Host smart-92ae82e6-1382-4427-aee0-c18d8316d344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
46244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2958046244
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.849110103
Short name T3329
Test name
Test status
Simulation time 2118684262 ps
CPU time 55.39 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:11:21 PM PDT 24
Peak memory 224112 kb
Host smart-6b43490e-8544-4689-b224-d216115a830b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84911
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.849110103
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1764896404
Short name T988
Test name
Test status
Simulation time 1852261186 ps
CPU time 50.59 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:11:07 PM PDT 24
Peak memory 215928 kb
Host smart-857b38c3-08d8-455b-9ba0-ad032dbf2e9f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1764896404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1764896404
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1565025476
Short name T2086
Test name
Test status
Simulation time 153201752 ps
CPU time 0.84 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207592 kb
Host smart-19077113-c064-4e91-a8e7-3e7f2d473c99
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1565025476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1565025476
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.50821861
Short name T1010
Test name
Test status
Simulation time 147423892 ps
CPU time 0.83 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207548 kb
Host smart-fdb63738-7a29-464e-9050-79043316ec07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50821
861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.50821861
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2792331533
Short name T2511
Test name
Test status
Simulation time 217484597 ps
CPU time 0.96 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207528 kb
Host smart-277683a5-9300-4812-9c23-1025a3a4f8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
31533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2792331533
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1380624765
Short name T1239
Test name
Test status
Simulation time 178401815 ps
CPU time 0.91 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207548 kb
Host smart-6c49d179-733d-46a6-92f5-5dce3d08eb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13806
24765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1380624765
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.495452743
Short name T3393
Test name
Test status
Simulation time 173250143 ps
CPU time 0.85 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207524 kb
Host smart-e261f18e-fd16-4b7b-8333-32a1c41acb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49545
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.495452743
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2002894508
Short name T1490
Test name
Test status
Simulation time 162940262 ps
CPU time 0.84 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207500 kb
Host smart-d1e97fe5-c59e-41de-af4c-a2b2e609a63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
94508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2002894508
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3160792888
Short name T1798
Test name
Test status
Simulation time 164421198 ps
CPU time 0.86 seconds
Started Aug 10 07:10:18 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207552 kb
Host smart-fe8676ae-c13d-46e9-aa60-c5d53314dbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31607
92888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3160792888
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3163581178
Short name T1177
Test name
Test status
Simulation time 223919702 ps
CPU time 0.96 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:16 PM PDT 24
Peak memory 207500 kb
Host smart-70e48fd1-04ef-4675-9389-90cc1d11da85
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3163581178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3163581178
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3963933045
Short name T1279
Test name
Test status
Simulation time 149880776 ps
CPU time 0.84 seconds
Started Aug 10 07:10:17 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207412 kb
Host smart-a4c9b3aa-95f5-4e3c-8e21-3005ed390410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
33045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3963933045
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2021911643
Short name T2006
Test name
Test status
Simulation time 63060546 ps
CPU time 0.76 seconds
Started Aug 10 07:10:18 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207520 kb
Host smart-c3fb8707-5097-4638-a76a-fd26c04f988c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
11643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2021911643
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.772456196
Short name T1356
Test name
Test status
Simulation time 22305982752 ps
CPU time 57.48 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:11:23 PM PDT 24
Peak memory 216076 kb
Host smart-b19aec47-51d9-4ba7-8518-bef9b471cb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77245
6196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.772456196
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.232123082
Short name T1628
Test name
Test status
Simulation time 161960857 ps
CPU time 0.96 seconds
Started Aug 10 07:10:18 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207576 kb
Host smart-d6a1a963-5ce0-416e-b46a-d1d1a0f86974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23212
3082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.232123082
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2785143979
Short name T705
Test name
Test status
Simulation time 217153289 ps
CPU time 0.98 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207512 kb
Host smart-1fb73003-18a9-488b-96a0-be87f7a0077f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851
43979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2785143979
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2576246741
Short name T773
Test name
Test status
Simulation time 196085217 ps
CPU time 0.97 seconds
Started Aug 10 07:10:17 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207560 kb
Host smart-eb52fc64-22ed-423f-89c7-95ba51adc40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25762
46741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2576246741
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1386592841
Short name T3428
Test name
Test status
Simulation time 176537824 ps
CPU time 0.89 seconds
Started Aug 10 07:10:17 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207608 kb
Host smart-515bc484-4d7c-4262-9dfa-7534f0ef01b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13865
92841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1386592841
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3440356207
Short name T1374
Test name
Test status
Simulation time 203071222 ps
CPU time 1.01 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:18 PM PDT 24
Peak memory 207552 kb
Host smart-a0e3e4f6-de6e-4462-9462-ccdf39e00a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34403
56207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3440356207
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_rx_full.2255102308
Short name T350
Test name
Test status
Simulation time 275341227 ps
CPU time 1.09 seconds
Started Aug 10 07:10:16 PM PDT 24
Finished Aug 10 07:10:17 PM PDT 24
Peak memory 207540 kb
Host smart-3eb2852f-9715-4b7c-ad00-c0838973e976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22551
02308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.2255102308
Directory /workspace/22.usbdev_rx_full/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2886452109
Short name T805
Test name
Test status
Simulation time 149279551 ps
CPU time 0.92 seconds
Started Aug 10 07:10:17 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207508 kb
Host smart-e55e147c-cd25-4aac-9be2-edf99f5babe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
52109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2886452109
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.697868831
Short name T1436
Test name
Test status
Simulation time 145796498 ps
CPU time 0.88 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:26 PM PDT 24
Peak memory 207552 kb
Host smart-4eb96aea-2142-4e8a-841e-e4dc17afdb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69786
8831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.697868831
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1597575415
Short name T749
Test name
Test status
Simulation time 247831783 ps
CPU time 1.05 seconds
Started Aug 10 07:10:17 PM PDT 24
Finished Aug 10 07:10:19 PM PDT 24
Peak memory 207608 kb
Host smart-8d74fb96-3bf9-416c-8b46-0dae59b4b58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15975
75415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1597575415
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.967845586
Short name T2702
Test name
Test status
Simulation time 3917390430 ps
CPU time 109.16 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 217848 kb
Host smart-bfe28035-55a2-4818-973e-6abeec142671
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=967845586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.967845586
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3103923707
Short name T2321
Test name
Test status
Simulation time 154016326 ps
CPU time 0.82 seconds
Started Aug 10 07:10:14 PM PDT 24
Finished Aug 10 07:10:15 PM PDT 24
Peak memory 207548 kb
Host smart-37e993c7-3195-4328-b80d-fc402595a797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
23707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3103923707
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3989875439
Short name T3515
Test name
Test status
Simulation time 148863120 ps
CPU time 0.84 seconds
Started Aug 10 07:10:15 PM PDT 24
Finished Aug 10 07:10:16 PM PDT 24
Peak memory 207516 kb
Host smart-3ff848a9-8d6c-4a29-befc-f7e382e0b54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
75439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3989875439
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1281583133
Short name T2007
Test name
Test status
Simulation time 800075357 ps
CPU time 1.97 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:29 PM PDT 24
Peak memory 207372 kb
Host smart-2fb48051-bc6d-4af2-85ce-c61d7232f8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
83133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1281583133
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.1954317656
Short name T2643
Test name
Test status
Simulation time 2957404380 ps
CPU time 84.44 seconds
Started Aug 10 07:10:28 PM PDT 24
Finished Aug 10 07:11:53 PM PDT 24
Peak memory 217400 kb
Host smart-ffa54373-3fa8-450e-8361-d062df5a96e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19543
17656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1954317656
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.1777659616
Short name T2281
Test name
Test status
Simulation time 3965463899 ps
CPU time 34.32 seconds
Started Aug 10 07:10:10 PM PDT 24
Finished Aug 10 07:10:44 PM PDT 24
Peak memory 207704 kb
Host smart-fce61447-f883-4015-a27c-7a114dd2d356
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777659616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.1777659616
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_tx_rx_disruption.3768646148
Short name T3268
Test name
Test status
Simulation time 585054460 ps
CPU time 1.7 seconds
Started Aug 10 07:10:31 PM PDT 24
Finished Aug 10 07:10:33 PM PDT 24
Peak memory 207476 kb
Host smart-373eff88-01f0-443b-83a5-c0b868fbe1ad
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768646148 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.usbdev_tx_rx_disruption.3768646148
Directory /workspace/22.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/220.usbdev_tx_rx_disruption.1300452319
Short name T2122
Test name
Test status
Simulation time 468815869 ps
CPU time 1.42 seconds
Started Aug 10 07:17:52 PM PDT 24
Finished Aug 10 07:17:53 PM PDT 24
Peak memory 207560 kb
Host smart-e66af868-4b2b-4cfd-9be2-376904ec1887
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300452319 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.usbdev_tx_rx_disruption.1300452319
Directory /workspace/220.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/221.usbdev_tx_rx_disruption.3822381908
Short name T2502
Test name
Test status
Simulation time 550274591 ps
CPU time 1.57 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207524 kb
Host smart-da9397a5-5e0e-4824-a5ac-9e60fb053c52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822381908 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.usbdev_tx_rx_disruption.3822381908
Directory /workspace/221.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/222.usbdev_tx_rx_disruption.1772869048
Short name T1190
Test name
Test status
Simulation time 469109003 ps
CPU time 1.37 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207560 kb
Host smart-0bb5ca1b-aade-48a0-ad62-26433e05e04d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772869048 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.usbdev_tx_rx_disruption.1772869048
Directory /workspace/222.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/223.usbdev_tx_rx_disruption.394032388
Short name T3453
Test name
Test status
Simulation time 580599355 ps
CPU time 1.64 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:56 PM PDT 24
Peak memory 207548 kb
Host smart-c69f288c-c35b-4d35-83f0-49b0d3f4407f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394032388 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 223.usbdev_tx_rx_disruption.394032388
Directory /workspace/223.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/224.usbdev_tx_rx_disruption.4042913497
Short name T1718
Test name
Test status
Simulation time 615850565 ps
CPU time 1.57 seconds
Started Aug 10 07:17:54 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 207516 kb
Host smart-2dcda6e7-162a-4d43-8a48-42b39a4d6840
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042913497 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.usbdev_tx_rx_disruption.4042913497
Directory /workspace/224.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/225.usbdev_tx_rx_disruption.1090307346
Short name T1381
Test name
Test status
Simulation time 586833660 ps
CPU time 1.8 seconds
Started Aug 10 07:17:55 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 207548 kb
Host smart-e528988a-9210-428f-a4ea-a4910ffccd46
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090307346 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.usbdev_tx_rx_disruption.1090307346
Directory /workspace/225.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/226.usbdev_tx_rx_disruption.1744058937
Short name T3630
Test name
Test status
Simulation time 486950154 ps
CPU time 1.49 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207532 kb
Host smart-7a74a883-e56a-496f-a3d6-706a33a20ee8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744058937 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.usbdev_tx_rx_disruption.1744058937
Directory /workspace/226.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/227.usbdev_tx_rx_disruption.4216717458
Short name T272
Test name
Test status
Simulation time 518950872 ps
CPU time 1.58 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207528 kb
Host smart-45bf6d21-9e98-4301-aeac-7079db2f92c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216717458 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.usbdev_tx_rx_disruption.4216717458
Directory /workspace/227.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/228.usbdev_tx_rx_disruption.518669784
Short name T2952
Test name
Test status
Simulation time 666584113 ps
CPU time 1.79 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207572 kb
Host smart-401ed17c-69d0-4177-b462-d022f12d972a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518669784 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 228.usbdev_tx_rx_disruption.518669784
Directory /workspace/228.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/229.usbdev_tx_rx_disruption.2355853858
Short name T3415
Test name
Test status
Simulation time 569518842 ps
CPU time 1.74 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207508 kb
Host smart-5c50e41e-648c-48d0-a3c7-e703010c5d2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355853858 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.usbdev_tx_rx_disruption.2355853858
Directory /workspace/229.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.3912203393
Short name T1170
Test name
Test status
Simulation time 42290541 ps
CPU time 0.68 seconds
Started Aug 10 07:10:48 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 207520 kb
Host smart-b1ad5952-e3d7-47c9-a239-d8aeeaa39239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3912203393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.3912203393
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2592875435
Short name T780
Test name
Test status
Simulation time 11958473728 ps
CPU time 14.01 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:39 PM PDT 24
Peak memory 207896 kb
Host smart-25d4a4d5-a6f4-449a-8b65-c43e5c7451f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592875435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.2592875435
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2195738612
Short name T1767
Test name
Test status
Simulation time 15304198141 ps
CPU time 22.76 seconds
Started Aug 10 07:10:28 PM PDT 24
Finished Aug 10 07:10:50 PM PDT 24
Peak memory 215968 kb
Host smart-0d99a72b-2fe4-4f45-804e-20d649d4fcd1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195738612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2195738612
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1149520156
Short name T2305
Test name
Test status
Simulation time 25026493882 ps
CPU time 28.7 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 216016 kb
Host smart-fe616526-cbbe-4bb8-b50f-a1a42d0aab08
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149520156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.1149520156
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2794211876
Short name T3512
Test name
Test status
Simulation time 177804220 ps
CPU time 0.96 seconds
Started Aug 10 07:10:28 PM PDT 24
Finished Aug 10 07:10:29 PM PDT 24
Peak memory 207520 kb
Host smart-d956c171-ad0a-4a3e-9169-d26f9f82e20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
11876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2794211876
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3411735077
Short name T2700
Test name
Test status
Simulation time 157567467 ps
CPU time 0.87 seconds
Started Aug 10 07:10:32 PM PDT 24
Finished Aug 10 07:10:33 PM PDT 24
Peak memory 207424 kb
Host smart-aa0ac8a0-ba34-44c9-814d-c98e77bed5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34117
35077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3411735077
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3146644574
Short name T1966
Test name
Test status
Simulation time 145415857 ps
CPU time 0.83 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:26 PM PDT 24
Peak memory 207516 kb
Host smart-82a1439a-b77e-4a4c-a14c-0f8105e11d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31466
44574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3146644574
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2235967655
Short name T619
Test name
Test status
Simulation time 319240415 ps
CPU time 1.08 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:10:28 PM PDT 24
Peak memory 207572 kb
Host smart-58278d8b-2e5a-4e82-af8e-1ffc7e192542
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2235967655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2235967655
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1336500812
Short name T536
Test name
Test status
Simulation time 42370245233 ps
CPU time 68.36 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:11:35 PM PDT 24
Peak memory 207840 kb
Host smart-919cd977-5183-4c09-8ef7-9ef5756a5149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13365
00812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1336500812
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.2260377646
Short name T2446
Test name
Test status
Simulation time 617602269 ps
CPU time 12.05 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:39 PM PDT 24
Peak memory 207584 kb
Host smart-820a1ba0-4555-4c8e-87bd-2183683e65f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260377646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2260377646
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.4015525366
Short name T2229
Test name
Test status
Simulation time 449212977 ps
CPU time 1.5 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:28 PM PDT 24
Peak memory 207388 kb
Host smart-bec722a6-c722-4856-8edc-5dcf757b9b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40155
25366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.4015525366
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.687479918
Short name T769
Test name
Test status
Simulation time 210838868 ps
CPU time 0.9 seconds
Started Aug 10 07:10:32 PM PDT 24
Finished Aug 10 07:10:33 PM PDT 24
Peak memory 207452 kb
Host smart-bb034de2-767a-4ecc-bd55-4b4781737d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68747
9918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.687479918
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2042786257
Short name T1688
Test name
Test status
Simulation time 90131055 ps
CPU time 0.77 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207544 kb
Host smart-75c523b4-92b2-4c21-a0e3-3dd917e893a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20427
86257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2042786257
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.320608139
Short name T2169
Test name
Test status
Simulation time 901833769 ps
CPU time 2.31 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:28 PM PDT 24
Peak memory 207652 kb
Host smart-2dcf93a1-1c3c-41f5-bb41-ce76a8a3808e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
8139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.320608139
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2689973905
Short name T3147
Test name
Test status
Simulation time 338105610 ps
CPU time 2.37 seconds
Started Aug 10 07:10:25 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207704 kb
Host smart-f962e78d-0441-4685-b07d-d394144fd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26899
73905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2689973905
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3740836887
Short name T3599
Test name
Test status
Simulation time 219794972 ps
CPU time 1.16 seconds
Started Aug 10 07:10:32 PM PDT 24
Finished Aug 10 07:10:33 PM PDT 24
Peak memory 216856 kb
Host smart-d1e39301-7994-49bd-a848-3beff59384d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3740836887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3740836887
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1329795938
Short name T126
Test name
Test status
Simulation time 143253922 ps
CPU time 0.84 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207552 kb
Host smart-fb092c83-91a4-459f-82be-be93b8252f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13297
95938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1329795938
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3159898477
Short name T3365
Test name
Test status
Simulation time 186653418 ps
CPU time 0.92 seconds
Started Aug 10 07:10:26 PM PDT 24
Finished Aug 10 07:10:27 PM PDT 24
Peak memory 207564 kb
Host smart-095efc1b-409d-458f-8d99-de6e439a9c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31598
98477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3159898477
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3360210836
Short name T1035
Test name
Test status
Simulation time 2008000879 ps
CPU time 19.86 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:47 PM PDT 24
Peak memory 218272 kb
Host smart-35f64997-db6b-4688-aa96-ec5db1402b87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3360210836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3360210836
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3957089254
Short name T1409
Test name
Test status
Simulation time 12458101379 ps
CPU time 149.95 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207712 kb
Host smart-2873215d-3da3-4a4c-818d-6a1b9bc3cff4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3957089254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3957089254
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.558021621
Short name T2616
Test name
Test status
Simulation time 189802186 ps
CPU time 0.93 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207540 kb
Host smart-12c54945-3524-4f90-801e-e24639243372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55802
1621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.558021621
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.515469685
Short name T818
Test name
Test status
Simulation time 25247832643 ps
CPU time 39.21 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207812 kb
Host smart-094cef30-f5bc-484a-9a29-286fd6fa83db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51546
9685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.515469685
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.433662960
Short name T1521
Test name
Test status
Simulation time 4486080672 ps
CPU time 6.92 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 216128 kb
Host smart-f203aae1-39b8-493a-abfe-6a4e46e60393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43366
2960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.433662960
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3492897584
Short name T1314
Test name
Test status
Simulation time 3277623228 ps
CPU time 32.33 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:11:13 PM PDT 24
Peak memory 216056 kb
Host smart-2b949e8d-2721-4e68-aa02-b520d1cad633
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3492897584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3492897584
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.4034506625
Short name T587
Test name
Test status
Simulation time 3003430718 ps
CPU time 84.39 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:12:06 PM PDT 24
Peak memory 217608 kb
Host smart-e985839e-aaa2-4f07-bc52-868df3a5e1d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4034506625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.4034506625
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.197599311
Short name T651
Test name
Test status
Simulation time 235182105 ps
CPU time 1.02 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:10:43 PM PDT 24
Peak memory 207512 kb
Host smart-f2660b4a-7266-491c-b321-84ffc692e15b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=197599311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.197599311
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2861905759
Short name T3015
Test name
Test status
Simulation time 198391982 ps
CPU time 0.93 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:43 PM PDT 24
Peak memory 207552 kb
Host smart-6066db2d-7369-47c1-a075-ede5018487d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
05759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2861905759
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.755357552
Short name T918
Test name
Test status
Simulation time 3348891682 ps
CPU time 35.36 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:11:16 PM PDT 24
Peak memory 216088 kb
Host smart-7cb5908b-2e74-4e5a-a73e-4784b14e31a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75535
7552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.755357552
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.93964673
Short name T2920
Test name
Test status
Simulation time 2104713800 ps
CPU time 20.22 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:11:02 PM PDT 24
Peak memory 216712 kb
Host smart-2a14e190-091f-4e73-bebb-d865c6b6e7ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=93964673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.93964673
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.771806571
Short name T1122
Test name
Test status
Simulation time 155361593 ps
CPU time 0.87 seconds
Started Aug 10 07:10:39 PM PDT 24
Finished Aug 10 07:10:40 PM PDT 24
Peak memory 207576 kb
Host smart-af5443ad-a664-4d8a-a2f9-3098cec872e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=771806571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.771806571
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3002982628
Short name T981
Test name
Test status
Simulation time 148203304 ps
CPU time 0.89 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:43 PM PDT 24
Peak memory 207520 kb
Host smart-8090e17f-f148-4b82-bff0-01fac2bd349e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30029
82628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3002982628
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2076726045
Short name T3611
Test name
Test status
Simulation time 194039644 ps
CPU time 0.88 seconds
Started Aug 10 07:10:39 PM PDT 24
Finished Aug 10 07:10:40 PM PDT 24
Peak memory 207536 kb
Host smart-303996fb-f942-4e51-b4b3-7d07798459af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20767
26045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2076726045
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2479367342
Short name T1413
Test name
Test status
Simulation time 165531972 ps
CPU time 0.85 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:10:50 PM PDT 24
Peak memory 207552 kb
Host smart-42da2c35-6b5a-4978-af65-ef62bebdbc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
67342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2479367342
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2018036560
Short name T2200
Test name
Test status
Simulation time 150248235 ps
CPU time 0.83 seconds
Started Aug 10 07:10:38 PM PDT 24
Finished Aug 10 07:10:39 PM PDT 24
Peak memory 207744 kb
Host smart-b556139f-dd6d-45f3-9868-171a636d2b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
36560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2018036560
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1868942827
Short name T2646
Test name
Test status
Simulation time 154078203 ps
CPU time 0.87 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207492 kb
Host smart-cb5b7bc1-73cd-4919-9844-06953d019a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
42827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1868942827
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2812867597
Short name T3369
Test name
Test status
Simulation time 174002176 ps
CPU time 0.96 seconds
Started Aug 10 07:10:39 PM PDT 24
Finished Aug 10 07:10:40 PM PDT 24
Peak memory 207564 kb
Host smart-320d9539-a2e2-4f3a-8dd6-5dc44e8df7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28128
67597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2812867597
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2408458153
Short name T1193
Test name
Test status
Simulation time 211947129 ps
CPU time 1.06 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:10:42 PM PDT 24
Peak memory 207532 kb
Host smart-814cc8e5-18ac-4eca-baae-6b36fd197ae4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2408458153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2408458153
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.943226545
Short name T2259
Test name
Test status
Simulation time 181237648 ps
CPU time 0.85 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207504 kb
Host smart-d0560957-1a6f-4ee4-a9dc-e6d8209ac182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94322
6545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.943226545
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2986733812
Short name T2388
Test name
Test status
Simulation time 67350394 ps
CPU time 0.75 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:10:42 PM PDT 24
Peak memory 207496 kb
Host smart-9950fad2-a8bb-4db0-bed8-48873674e12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
33812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2986733812
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2278344473
Short name T2050
Test name
Test status
Simulation time 8554562675 ps
CPU time 21.1 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:11:02 PM PDT 24
Peak memory 216040 kb
Host smart-d7e44234-81e6-474e-98ee-fc76deb485c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
44473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2278344473
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1880629858
Short name T1856
Test name
Test status
Simulation time 168787378 ps
CPU time 0.87 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207540 kb
Host smart-fada125b-118d-4428-b673-e4f5375fcf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18806
29858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1880629858
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.812482100
Short name T2126
Test name
Test status
Simulation time 191537594 ps
CPU time 0.97 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:10:42 PM PDT 24
Peak memory 207388 kb
Host smart-be0d1060-36aa-4e37-a55f-820e0239a60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81248
2100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.812482100
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2581021140
Short name T3609
Test name
Test status
Simulation time 272910381 ps
CPU time 0.98 seconds
Started Aug 10 07:10:38 PM PDT 24
Finished Aug 10 07:10:39 PM PDT 24
Peak memory 207540 kb
Host smart-e3fe8b9e-82b9-424f-8078-23bfb4923ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25810
21140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2581021140
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2732991460
Short name T2461
Test name
Test status
Simulation time 189695515 ps
CPU time 0.94 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207580 kb
Host smart-ba6d48d7-2f5e-4250-9a61-d2b54843533f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27329
91460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2732991460
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1860511308
Short name T3218
Test name
Test status
Simulation time 219792955 ps
CPU time 0.91 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:10:50 PM PDT 24
Peak memory 207548 kb
Host smart-6eced20c-2180-49cd-b708-6ecaad42c13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18605
11308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1860511308
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_rx_full.1037458078
Short name T50
Test name
Test status
Simulation time 264648897 ps
CPU time 1.1 seconds
Started Aug 10 07:10:39 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207572 kb
Host smart-0a5c584e-6c48-4393-a0d7-e1f2d3b4ae1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374
58078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.1037458078
Directory /workspace/23.usbdev_rx_full/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3849340788
Short name T2344
Test name
Test status
Simulation time 147573710 ps
CPU time 0.9 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207516 kb
Host smart-22f81ed4-1a02-4bc3-a606-792ea39ae6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38493
40788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3849340788
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2547019712
Short name T2443
Test name
Test status
Simulation time 150612639 ps
CPU time 0.93 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:43 PM PDT 24
Peak memory 207548 kb
Host smart-04e6b6b3-062f-4d3b-bf48-6accb1e99131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25470
19712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2547019712
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1270514590
Short name T3275
Test name
Test status
Simulation time 195481203 ps
CPU time 0.94 seconds
Started Aug 10 07:10:41 PM PDT 24
Finished Aug 10 07:10:42 PM PDT 24
Peak memory 207512 kb
Host smart-ece71ac0-0c7d-48cb-badd-d406564bc4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12705
14590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1270514590
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.699093326
Short name T2079
Test name
Test status
Simulation time 2151764700 ps
CPU time 16.2 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 216000 kb
Host smart-e267d61d-214f-4861-a7f0-e92c6208e9bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=699093326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.699093326
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3268242898
Short name T1168
Test name
Test status
Simulation time 178411861 ps
CPU time 0.87 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:43 PM PDT 24
Peak memory 207520 kb
Host smart-d4987067-0dec-434a-a5ac-d94f61fd9ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32682
42898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3268242898
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2581194638
Short name T649
Test name
Test status
Simulation time 169950357 ps
CPU time 0.96 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:10:41 PM PDT 24
Peak memory 207576 kb
Host smart-ac002c75-d13f-42a0-b14f-d518b763efd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
94638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2581194638
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2272309332
Short name T3368
Test name
Test status
Simulation time 1169562292 ps
CPU time 2.67 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:10:48 PM PDT 24
Peak memory 207784 kb
Host smart-cf88ed28-c716-48b0-908d-7bf3712fcf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22723
09332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2272309332
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1797597993
Short name T1263
Test name
Test status
Simulation time 2484179080 ps
CPU time 20.11 seconds
Started Aug 10 07:10:40 PM PDT 24
Finished Aug 10 07:11:00 PM PDT 24
Peak memory 215952 kb
Host smart-3fa29dfc-033c-4b85-b827-0583e4b4ab8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17975
97993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1797597993
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.3678304829
Short name T2742
Test name
Test status
Simulation time 1630463085 ps
CPU time 9.67 seconds
Started Aug 10 07:10:27 PM PDT 24
Finished Aug 10 07:10:37 PM PDT 24
Peak memory 207808 kb
Host smart-6e76750c-ca2c-4883-8ca5-5db3d20f4876
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678304829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.3678304829
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_tx_rx_disruption.4215504457
Short name T3083
Test name
Test status
Simulation time 592118912 ps
CPU time 1.62 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:10:45 PM PDT 24
Peak memory 207492 kb
Host smart-471e06e9-353e-470c-8e9a-df956032f939
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215504457 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.usbdev_tx_rx_disruption.4215504457
Directory /workspace/23.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/230.usbdev_tx_rx_disruption.1175111274
Short name T795
Test name
Test status
Simulation time 586415680 ps
CPU time 1.52 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207500 kb
Host smart-a031d5cd-934c-40ed-9454-2dced1bc759c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175111274 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.usbdev_tx_rx_disruption.1175111274
Directory /workspace/230.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/231.usbdev_tx_rx_disruption.1374471404
Short name T3046
Test name
Test status
Simulation time 448420660 ps
CPU time 1.39 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207480 kb
Host smart-211e0bf2-6b0b-4169-9b8f-f8c77c75e65e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374471404 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.usbdev_tx_rx_disruption.1374471404
Directory /workspace/231.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/232.usbdev_tx_rx_disruption.2058817700
Short name T2856
Test name
Test status
Simulation time 595952200 ps
CPU time 1.64 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207572 kb
Host smart-09416222-256f-4d21-b374-1ef3a0643424
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058817700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.usbdev_tx_rx_disruption.2058817700
Directory /workspace/232.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/233.usbdev_tx_rx_disruption.2985396964
Short name T2497
Test name
Test status
Simulation time 584569280 ps
CPU time 1.63 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207464 kb
Host smart-d4368070-08f0-4a34-83db-1a1bcd9b29fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985396964 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.usbdev_tx_rx_disruption.2985396964
Directory /workspace/233.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/234.usbdev_tx_rx_disruption.1113442616
Short name T269
Test name
Test status
Simulation time 613205347 ps
CPU time 1.61 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207588 kb
Host smart-3b9197a5-8e2d-4d32-8978-6341672b1bd7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113442616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.usbdev_tx_rx_disruption.1113442616
Directory /workspace/234.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/235.usbdev_tx_rx_disruption.1930473738
Short name T1823
Test name
Test status
Simulation time 504777013 ps
CPU time 1.6 seconds
Started Aug 10 07:18:01 PM PDT 24
Finished Aug 10 07:18:03 PM PDT 24
Peak memory 207596 kb
Host smart-afe40bde-b2bf-471a-8b68-a8b612823449
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930473738 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.usbdev_tx_rx_disruption.1930473738
Directory /workspace/235.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/236.usbdev_tx_rx_disruption.149540974
Short name T3548
Test name
Test status
Simulation time 603165855 ps
CPU time 1.59 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207424 kb
Host smart-69690fa0-f1ed-44e2-8016-64d5d3cd5db8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149540974 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 236.usbdev_tx_rx_disruption.149540974
Directory /workspace/236.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/237.usbdev_tx_rx_disruption.2287021153
Short name T2083
Test name
Test status
Simulation time 529025795 ps
CPU time 1.63 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207560 kb
Host smart-140046cf-3439-46d1-8d80-92a73620b221
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287021153 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.usbdev_tx_rx_disruption.2287021153
Directory /workspace/237.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/238.usbdev_tx_rx_disruption.625104004
Short name T1350
Test name
Test status
Simulation time 576479379 ps
CPU time 1.69 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207604 kb
Host smart-75664dce-94ce-4bd9-9fe7-a0b4dc437c63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625104004 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.usbdev_tx_rx_disruption.625104004
Directory /workspace/238.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/239.usbdev_tx_rx_disruption.1632834833
Short name T3325
Test name
Test status
Simulation time 521082936 ps
CPU time 1.58 seconds
Started Aug 10 07:18:01 PM PDT 24
Finished Aug 10 07:18:03 PM PDT 24
Peak memory 207536 kb
Host smart-52eb97f4-9cf8-4d88-9438-51df1a623ae1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632834833 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.usbdev_tx_rx_disruption.1632834833
Directory /workspace/239.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3413137678
Short name T2325
Test name
Test status
Simulation time 69883522 ps
CPU time 0.69 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:53 PM PDT 24
Peak memory 207484 kb
Host smart-d3888f09-0454-48f6-ac7a-d6464466b169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3413137678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3413137678
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3449827304
Short name T2785
Test name
Test status
Simulation time 3998610044 ps
CPU time 5.95 seconds
Started Aug 10 07:10:42 PM PDT 24
Finished Aug 10 07:10:48 PM PDT 24
Peak memory 216052 kb
Host smart-819becac-10c2-4ea4-ba97-2408374c7cac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449827304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.3449827304
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1150480666
Short name T1530
Test name
Test status
Simulation time 20864142470 ps
CPU time 28.11 seconds
Started Aug 10 07:10:43 PM PDT 24
Finished Aug 10 07:11:11 PM PDT 24
Peak memory 207876 kb
Host smart-f1cd808d-9fdc-4a18-bc5c-f7b4ccc8bca8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150480666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1150480666
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.622492036
Short name T2762
Test name
Test status
Simulation time 23970231663 ps
CPU time 29.04 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:11:14 PM PDT 24
Peak memory 215876 kb
Host smart-6bc77385-ce62-45ae-916a-2ae62ddbb736
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622492036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_resume.622492036
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2284232404
Short name T1285
Test name
Test status
Simulation time 197279274 ps
CPU time 0.93 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:10:46 PM PDT 24
Peak memory 207532 kb
Host smart-e3a941ae-3f3d-460b-afa9-4a1730e83820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22842
32404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2284232404
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.422344410
Short name T2665
Test name
Test status
Simulation time 149099272 ps
CPU time 0.86 seconds
Started Aug 10 07:10:48 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 207476 kb
Host smart-37fc2151-a433-44d5-a609-df944f0c3caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42234
4410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.422344410
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.4055730371
Short name T2804
Test name
Test status
Simulation time 181142178 ps
CPU time 0.94 seconds
Started Aug 10 07:10:48 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 207508 kb
Host smart-0af91af1-d111-48e9-bd6e-48fcc7191005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
30371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.4055730371
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1461302747
Short name T3585
Test name
Test status
Simulation time 719912173 ps
CPU time 1.85 seconds
Started Aug 10 07:10:48 PM PDT 24
Finished Aug 10 07:10:50 PM PDT 24
Peak memory 207500 kb
Host smart-1f7ff1e4-01ff-4a83-9178-51d6d69e0304
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1461302747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1461302747
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2645882696
Short name T3039
Test name
Test status
Simulation time 16396089122 ps
CPU time 28.3 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:11:13 PM PDT 24
Peak memory 207828 kb
Host smart-0727c57f-7019-4453-85cb-73a02cf7865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
82696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2645882696
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.276628322
Short name T767
Test name
Test status
Simulation time 1140521875 ps
CPU time 26.41 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:11:11 PM PDT 24
Peak memory 207736 kb
Host smart-4e034226-2904-42e3-9dda-39d631dfd0e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276628322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.276628322
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3186040836
Short name T2054
Test name
Test status
Simulation time 829329403 ps
CPU time 2.09 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:10:51 PM PDT 24
Peak memory 207484 kb
Host smart-58bfa21f-3d1d-4380-b0c7-5b082c1d928b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
40836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3186040836
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1420884977
Short name T1834
Test name
Test status
Simulation time 206078727 ps
CPU time 0.85 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:10:46 PM PDT 24
Peak memory 207492 kb
Host smart-3d8460e9-7fab-49ba-abf3-8fd243d47b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
84977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1420884977
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.84905597
Short name T1808
Test name
Test status
Simulation time 42971235 ps
CPU time 0.73 seconds
Started Aug 10 07:10:48 PM PDT 24
Finished Aug 10 07:10:49 PM PDT 24
Peak memory 207472 kb
Host smart-261066de-2311-454e-8481-073b67efc9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84905
597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.84905597
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.616295966
Short name T1478
Test name
Test status
Simulation time 842195846 ps
CPU time 2.13 seconds
Started Aug 10 07:10:46 PM PDT 24
Finished Aug 10 07:10:48 PM PDT 24
Peak memory 207632 kb
Host smart-aca88a92-0698-4733-8fa2-004bf74b92f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61629
5966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.616295966
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3245254155
Short name T3219
Test name
Test status
Simulation time 251918806 ps
CPU time 1.71 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:10:46 PM PDT 24
Peak memory 207712 kb
Host smart-c15a97f1-b8c6-429e-b6eb-3162f6122e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
54155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3245254155
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1892176085
Short name T3001
Test name
Test status
Simulation time 204943277 ps
CPU time 1.05 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:10:50 PM PDT 24
Peak memory 215876 kb
Host smart-328bd68d-8d7a-4269-9be7-2783b2c6e95c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1892176085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1892176085
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1489686992
Short name T3034
Test name
Test status
Simulation time 162192686 ps
CPU time 0.93 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:10:45 PM PDT 24
Peak memory 207384 kb
Host smart-b74d7bb5-a33c-4ff3-9d8b-87ed2918b376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14896
86992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1489686992
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1262107332
Short name T2981
Test name
Test status
Simulation time 182070232 ps
CPU time 0.88 seconds
Started Aug 10 07:10:46 PM PDT 24
Finished Aug 10 07:10:47 PM PDT 24
Peak memory 207508 kb
Host smart-8762c898-6144-4f1a-b520-105570df1278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
07332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1262107332
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1016536279
Short name T2634
Test name
Test status
Simulation time 3112069371 ps
CPU time 86.19 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:12:10 PM PDT 24
Peak memory 218540 kb
Host smart-d4ef5f7c-1332-4f40-90be-921cf41993d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1016536279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1016536279
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1124939676
Short name T2457
Test name
Test status
Simulation time 6264260920 ps
CPU time 72.37 seconds
Started Aug 10 07:10:43 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207764 kb
Host smart-bb90e65e-1f5c-44be-828f-a49bb5ec49e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1124939676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1124939676
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.203779102
Short name T1128
Test name
Test status
Simulation time 186013999 ps
CPU time 0.9 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:10:45 PM PDT 24
Peak memory 207424 kb
Host smart-93caec2c-7826-421d-9e51-e9158220e234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20377
9102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.203779102
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1163361402
Short name T2940
Test name
Test status
Simulation time 14144222215 ps
CPU time 18.49 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:11:03 PM PDT 24
Peak memory 207900 kb
Host smart-6bdcaf60-f60b-4375-8f11-b46ba9550832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
61402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1163361402
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2731848814
Short name T2406
Test name
Test status
Simulation time 10810212060 ps
CPU time 13.98 seconds
Started Aug 10 07:10:47 PM PDT 24
Finished Aug 10 07:11:01 PM PDT 24
Peak memory 207832 kb
Host smart-e8bd4053-83cb-479c-8d2d-f0f8c44f9f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318
48814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2731848814
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.430883154
Short name T186
Test name
Test status
Simulation time 2717766993 ps
CPU time 20.97 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 224252 kb
Host smart-9c3ac451-13c7-4139-b9c9-efef0405626b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=430883154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.430883154
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3055666019
Short name T2533
Test name
Test status
Simulation time 3123320346 ps
CPU time 24.94 seconds
Started Aug 10 07:10:49 PM PDT 24
Finished Aug 10 07:11:14 PM PDT 24
Peak memory 216036 kb
Host smart-cb734dd6-66e4-4b06-9a52-0e64584be2fb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3055666019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3055666019
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2486875291
Short name T890
Test name
Test status
Simulation time 269298225 ps
CPU time 0.99 seconds
Started Aug 10 07:10:44 PM PDT 24
Finished Aug 10 07:10:45 PM PDT 24
Peak memory 207600 kb
Host smart-9cdf13a3-d9e0-42c9-a946-3ce9ec2fd9d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2486875291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2486875291
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1846193263
Short name T2340
Test name
Test status
Simulation time 189810924 ps
CPU time 0.91 seconds
Started Aug 10 07:10:45 PM PDT 24
Finished Aug 10 07:10:46 PM PDT 24
Peak memory 207568 kb
Host smart-d7f7a30e-59a4-4264-b236-e60f4eb9e1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18461
93263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1846193263
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.2106684914
Short name T2777
Test name
Test status
Simulation time 2735958666 ps
CPU time 20.54 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:11:15 PM PDT 24
Peak memory 218132 kb
Host smart-aeb72a38-b4a6-49ab-ac26-5755b607448f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21066
84914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.2106684914
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3444930553
Short name T588
Test name
Test status
Simulation time 2842057054 ps
CPU time 78.1 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:12:14 PM PDT 24
Peak memory 216112 kb
Host smart-29db04f5-7176-4270-af7e-e19faed56f0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3444930553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3444930553
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.467943831
Short name T1805
Test name
Test status
Simulation time 145948173 ps
CPU time 0.85 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207604 kb
Host smart-1fcf9c12-573b-42d4-adba-5a8214bb15c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=467943831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.467943831
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2970063643
Short name T1889
Test name
Test status
Simulation time 140639891 ps
CPU time 0.83 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 207400 kb
Host smart-2ce60020-a966-4490-8f81-33901a2c3dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29700
63643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2970063643
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.222676101
Short name T140
Test name
Test status
Simulation time 252004208 ps
CPU time 0.98 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207528 kb
Host smart-42c41472-16b4-4c06-8b8d-3784f946ee98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
6101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.222676101
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2221363029
Short name T971
Test name
Test status
Simulation time 162490379 ps
CPU time 0.89 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207552 kb
Host smart-6e0ea41f-d83d-438d-8b85-c692b7ade04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22213
63029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2221363029
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3966409297
Short name T2569
Test name
Test status
Simulation time 193088163 ps
CPU time 0.9 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207544 kb
Host smart-b1535a0f-19a8-4bf8-9427-43f533e1d1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
09297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3966409297
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1335187425
Short name T2045
Test name
Test status
Simulation time 201190870 ps
CPU time 0.94 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 207500 kb
Host smart-7f891c26-d1e0-4a27-822a-b67564d4ce40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
87425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1335187425
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3009180276
Short name T948
Test name
Test status
Simulation time 145878237 ps
CPU time 0.83 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207512 kb
Host smart-a7f0a934-c6f7-4477-bc41-4bbdd0e9f790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
80276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3009180276
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.4202184938
Short name T1652
Test name
Test status
Simulation time 262881531 ps
CPU time 1.06 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:10:57 PM PDT 24
Peak memory 207568 kb
Host smart-774a2aab-abf5-4e32-8e2d-db4995b6552e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4202184938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.4202184938
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.499538636
Short name T2699
Test name
Test status
Simulation time 147269342 ps
CPU time 0.78 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207500 kb
Host smart-297ae501-cbe3-454e-a587-ca92ab8c527a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49953
8636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.499538636
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.509992607
Short name T3551
Test name
Test status
Simulation time 59935814 ps
CPU time 0.75 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207408 kb
Host smart-a8398d72-0860-4d08-bb53-cfd7861705d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50999
2607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.509992607
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.85798771
Short name T1373
Test name
Test status
Simulation time 8391699047 ps
CPU time 21.16 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:11:15 PM PDT 24
Peak memory 216028 kb
Host smart-8f76662e-83d6-40f7-9ede-98194459a2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85798
771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.85798771
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.33723935
Short name T376
Test name
Test status
Simulation time 145273037 ps
CPU time 0.88 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:10:57 PM PDT 24
Peak memory 207608 kb
Host smart-0255cef6-a0ca-44e3-9c87-75c351b64458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33723
935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.33723935
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1428031864
Short name T2166
Test name
Test status
Simulation time 216743992 ps
CPU time 0.97 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207488 kb
Host smart-65e08fe8-8599-451e-9273-1aa2e3ba2e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
31864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1428031864
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2048226156
Short name T2496
Test name
Test status
Simulation time 248453341 ps
CPU time 0.98 seconds
Started Aug 10 07:10:57 PM PDT 24
Finished Aug 10 07:10:58 PM PDT 24
Peak memory 207508 kb
Host smart-825279c1-ef34-4ce5-be10-18f05b17f656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
26156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2048226156
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.830528427
Short name T575
Test name
Test status
Simulation time 164235219 ps
CPU time 0.9 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207576 kb
Host smart-3eb0baae-9fc0-42b9-8951-aea1d20b0526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83052
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.830528427
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2367521273
Short name T1702
Test name
Test status
Simulation time 142480947 ps
CPU time 0.79 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207540 kb
Host smart-df98d772-3d77-47f1-bb95-dea62414569c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
21273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2367521273
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_rx_full.2196025002
Short name T352
Test name
Test status
Simulation time 244395446 ps
CPU time 1.09 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:10:57 PM PDT 24
Peak memory 207524 kb
Host smart-d5ed847e-ac68-4311-85c6-b44bc71308a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
25002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.2196025002
Directory /workspace/24.usbdev_rx_full/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3828259005
Short name T1017
Test name
Test status
Simulation time 160682605 ps
CPU time 0.87 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 207516 kb
Host smart-8b09a9cc-9069-4865-8cca-6caff5fd8099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38282
59005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3828259005
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3248505823
Short name T3460
Test name
Test status
Simulation time 159979198 ps
CPU time 0.81 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207512 kb
Host smart-2bb9c193-8261-4703-9b61-ed128fdeb485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
05823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3248505823
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.509765952
Short name T3492
Test name
Test status
Simulation time 248193253 ps
CPU time 1.04 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207528 kb
Host smart-73fa9148-0b0b-4fff-96c2-3eeb760d49e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50976
5952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.509765952
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4253348174
Short name T2959
Test name
Test status
Simulation time 3151753533 ps
CPU time 24.05 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:11:20 PM PDT 24
Peak memory 215936 kb
Host smart-0548d248-207c-4fe3-b93d-a30eb956f640
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4253348174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4253348174
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2225232525
Short name T1579
Test name
Test status
Simulation time 247631252 ps
CPU time 0.93 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 207492 kb
Host smart-9e6b2f9d-c4c6-4da3-9a6b-ce351a101f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22252
32525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2225232525
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.284326129
Short name T3042
Test name
Test status
Simulation time 190820269 ps
CPU time 0.9 seconds
Started Aug 10 07:10:54 PM PDT 24
Finished Aug 10 07:10:55 PM PDT 24
Peak memory 207416 kb
Host smart-59101895-8223-4cc8-8030-8a9abeac679a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
6129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.284326129
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1769113535
Short name T2101
Test name
Test status
Simulation time 856653377 ps
CPU time 2.01 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:57 PM PDT 24
Peak memory 207772 kb
Host smart-51c9284e-81dc-4a54-b129-ede9e1918382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17691
13535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1769113535
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.265914642
Short name T3142
Test name
Test status
Simulation time 3992202953 ps
CPU time 118.78 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:12:52 PM PDT 24
Peak memory 217416 kb
Host smart-c059fb8b-3f8a-483d-8cd9-344fe9a8abe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
4642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.265914642
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.443034471
Short name T1133
Test name
Test status
Simulation time 5272176322 ps
CPU time 41.97 seconds
Started Aug 10 07:10:46 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207852 kb
Host smart-0ad50fa5-3b6b-468c-b012-73d03da514bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443034471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host
_handshake.443034471
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_tx_rx_disruption.3762598031
Short name T3614
Test name
Test status
Simulation time 455183101 ps
CPU time 1.49 seconds
Started Aug 10 07:10:53 PM PDT 24
Finished Aug 10 07:10:54 PM PDT 24
Peak memory 207572 kb
Host smart-375232db-1472-499b-afc2-563f73febe17
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762598031 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.usbdev_tx_rx_disruption.3762598031
Directory /workspace/24.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/240.usbdev_tx_rx_disruption.2858094875
Short name T699
Test name
Test status
Simulation time 634207151 ps
CPU time 1.86 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207404 kb
Host smart-b1173352-aa6d-4ea4-ac69-6c8ee1862102
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858094875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.usbdev_tx_rx_disruption.2858094875
Directory /workspace/240.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/241.usbdev_tx_rx_disruption.715383871
Short name T607
Test name
Test status
Simulation time 487514284 ps
CPU time 1.58 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207508 kb
Host smart-c9f56a6e-75ba-4ccc-b010-a2f4527de722
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715383871 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 241.usbdev_tx_rx_disruption.715383871
Directory /workspace/241.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/242.usbdev_tx_rx_disruption.505715144
Short name T3373
Test name
Test status
Simulation time 496833236 ps
CPU time 1.45 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207508 kb
Host smart-5f415b27-9221-4df7-bf3d-e1518026c2d3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505715144 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 242.usbdev_tx_rx_disruption.505715144
Directory /workspace/242.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/243.usbdev_tx_rx_disruption.3584329788
Short name T1962
Test name
Test status
Simulation time 648504048 ps
CPU time 1.84 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:09 PM PDT 24
Peak memory 207336 kb
Host smart-8f567cb8-dd1a-4fa0-a7b7-8e075d915445
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584329788 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.usbdev_tx_rx_disruption.3584329788
Directory /workspace/243.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/244.usbdev_tx_rx_disruption.3162765301
Short name T3474
Test name
Test status
Simulation time 643356635 ps
CPU time 1.68 seconds
Started Aug 10 07:18:00 PM PDT 24
Finished Aug 10 07:18:02 PM PDT 24
Peak memory 207596 kb
Host smart-a402269c-6f42-493a-8b08-13876977f506
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162765301 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.usbdev_tx_rx_disruption.3162765301
Directory /workspace/244.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/245.usbdev_tx_rx_disruption.1384860634
Short name T261
Test name
Test status
Simulation time 440580047 ps
CPU time 1.44 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:11 PM PDT 24
Peak memory 207604 kb
Host smart-1caa2a72-0248-403b-8f53-805f67d3f5ba
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384860634 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.usbdev_tx_rx_disruption.1384860634
Directory /workspace/245.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/246.usbdev_tx_rx_disruption.3906325107
Short name T2392
Test name
Test status
Simulation time 639863404 ps
CPU time 1.68 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207600 kb
Host smart-4208342f-df16-4468-9b3c-27b5103c25f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906325107 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.usbdev_tx_rx_disruption.3906325107
Directory /workspace/246.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/247.usbdev_tx_rx_disruption.2313973754
Short name T3177
Test name
Test status
Simulation time 572679991 ps
CPU time 1.56 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207588 kb
Host smart-439677e1-4ca7-41e9-bff5-5e4b881ff43a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313973754 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.usbdev_tx_rx_disruption.2313973754
Directory /workspace/247.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/248.usbdev_tx_rx_disruption.3447371923
Short name T198
Test name
Test status
Simulation time 571531581 ps
CPU time 1.54 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207572 kb
Host smart-9de4841a-b660-4646-a997-1e18488f25c8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447371923 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.usbdev_tx_rx_disruption.3447371923
Directory /workspace/248.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/249.usbdev_tx_rx_disruption.314375578
Short name T2890
Test name
Test status
Simulation time 484950213 ps
CPU time 1.53 seconds
Started Aug 10 07:18:08 PM PDT 24
Finished Aug 10 07:18:09 PM PDT 24
Peak memory 207604 kb
Host smart-ab3b9c59-274b-4c85-8d6c-1f2a32462b3a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314375578 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 249.usbdev_tx_rx_disruption.314375578
Directory /workspace/249.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1024583409
Short name T3096
Test name
Test status
Simulation time 44042923 ps
CPU time 0.68 seconds
Started Aug 10 07:11:15 PM PDT 24
Finished Aug 10 07:11:16 PM PDT 24
Peak memory 207616 kb
Host smart-eeda3faf-c7d6-40cb-968d-30365c00fc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1024583409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1024583409
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.981865598
Short name T3312
Test name
Test status
Simulation time 3518436274 ps
CPU time 5.19 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:11:00 PM PDT 24
Peak memory 216012 kb
Host smart-3749b538-ee75-48f9-a07a-4e0606f6653b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981865598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_ao
n_wake_disconnect.981865598
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3763691436
Short name T1820
Test name
Test status
Simulation time 19310923985 ps
CPU time 23.08 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207848 kb
Host smart-5d81e714-8480-4a4d-a48d-2b7b40d49ba9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763691436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3763691436
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2860488424
Short name T1564
Test name
Test status
Simulation time 30065096778 ps
CPU time 34.93 seconds
Started Aug 10 07:10:52 PM PDT 24
Finished Aug 10 07:11:27 PM PDT 24
Peak memory 207872 kb
Host smart-ea95e402-3b1b-4107-95b8-22970e267174
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860488424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.2860488424
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2754223647
Short name T1923
Test name
Test status
Simulation time 158972622 ps
CPU time 0.84 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207640 kb
Host smart-f98c0845-006b-4c1d-a1d7-7ca57aa4bb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27542
23647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2754223647
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2272988504
Short name T3003
Test name
Test status
Simulation time 152934985 ps
CPU time 0.81 seconds
Started Aug 10 07:10:55 PM PDT 24
Finished Aug 10 07:10:56 PM PDT 24
Peak memory 207508 kb
Host smart-8c77fbfa-36ee-4365-8d48-16ac25fb4473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
88504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2272988504
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2305846271
Short name T2649
Test name
Test status
Simulation time 380473659 ps
CPU time 1.35 seconds
Started Aug 10 07:10:56 PM PDT 24
Finished Aug 10 07:10:57 PM PDT 24
Peak memory 207548 kb
Host smart-8ea13ae9-f192-4696-a9fc-fe9d0d76be7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23058
46271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2305846271
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4041481116
Short name T2855
Test name
Test status
Simulation time 361411850 ps
CPU time 1.19 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 207548 kb
Host smart-376c6f6d-47e3-4e02-a6fa-c6cc678cc590
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4041481116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4041481116
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.110116490
Short name T1776
Test name
Test status
Simulation time 13062319791 ps
CPU time 22.74 seconds
Started Aug 10 07:11:08 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207828 kb
Host smart-ccc92606-8aa3-44ee-bee5-6b72b1b11b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
6490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.110116490
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.806772555
Short name T1159
Test name
Test status
Simulation time 3719362188 ps
CPU time 25.72 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207800 kb
Host smart-1cb22bc5-ebc5-4ce5-8245-9fcc5eaa3b05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806772555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.806772555
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1149769036
Short name T2234
Test name
Test status
Simulation time 597637583 ps
CPU time 1.51 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207384 kb
Host smart-c74d96b7-0d27-487d-afd0-f736a05a13ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
69036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1149769036
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4128077310
Short name T547
Test name
Test status
Simulation time 180103562 ps
CPU time 0.86 seconds
Started Aug 10 07:11:07 PM PDT 24
Finished Aug 10 07:11:08 PM PDT 24
Peak memory 207576 kb
Host smart-d8ceb5db-155d-4830-b0eb-e4c56bfb73f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41280
77310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4128077310
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2617555028
Short name T1079
Test name
Test status
Simulation time 68411856 ps
CPU time 0.77 seconds
Started Aug 10 07:11:08 PM PDT 24
Finished Aug 10 07:11:09 PM PDT 24
Peak memory 207532 kb
Host smart-53c3cc80-f5ac-4111-8166-45ca0223997b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26175
55028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2617555028
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3576816854
Short name T2626
Test name
Test status
Simulation time 839819677 ps
CPU time 2.47 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207716 kb
Host smart-bf0003e9-9519-407e-8011-f365ca0d1426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768
16854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3576816854
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_types.3282336164
Short name T2463
Test name
Test status
Simulation time 648135937 ps
CPU time 1.71 seconds
Started Aug 10 07:11:07 PM PDT 24
Finished Aug 10 07:11:09 PM PDT 24
Peak memory 207620 kb
Host smart-39d575d8-8e27-48f5-8a62-6cb3b86ddc01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3282336164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.3282336164
Directory /workspace/25.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3333354509
Short name T2022
Test name
Test status
Simulation time 280283279 ps
CPU time 2.27 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207696 kb
Host smart-79761837-fe89-4242-a38e-b1794d27d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33333
54509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3333354509
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1465522824
Short name T2611
Test name
Test status
Simulation time 205859813 ps
CPU time 1.14 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 215924 kb
Host smart-0ee55d97-8282-400b-8d41-5d7b686aa62a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1465522824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1465522824
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3947678091
Short name T2921
Test name
Test status
Simulation time 195706407 ps
CPU time 0.9 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:04 PM PDT 24
Peak memory 207432 kb
Host smart-11494939-47e2-4eef-a702-b0c1025eeaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39476
78091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3947678091
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1182590990
Short name T3004
Test name
Test status
Simulation time 236993818 ps
CPU time 1.16 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207464 kb
Host smart-fbb0be45-0f70-4b04-bb71-69657f374148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825
90990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1182590990
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1176691547
Short name T220
Test name
Test status
Simulation time 4664184968 ps
CPU time 139.31 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:13:24 PM PDT 24
Peak memory 217784 kb
Host smart-00fbc324-b14b-4593-99a1-0f626f6a2863
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1176691547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1176691547
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.3464786642
Short name T811
Test name
Test status
Simulation time 9984004078 ps
CPU time 126.23 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207832 kb
Host smart-df837db3-7ec8-4579-a8a8-3eb19446e9d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3464786642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3464786642
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3654557830
Short name T2504
Test name
Test status
Simulation time 256489059 ps
CPU time 1.03 seconds
Started Aug 10 07:11:08 PM PDT 24
Finished Aug 10 07:11:09 PM PDT 24
Peak memory 207564 kb
Host smart-4a472d80-a10a-4b1c-bc73-a0a46ee078df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36545
57830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3654557830
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.316084080
Short name T1771
Test name
Test status
Simulation time 4464380108 ps
CPU time 6.16 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:10 PM PDT 24
Peak memory 207740 kb
Host smart-9f92b1d8-4396-4efd-ad46-54027300027d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
4080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.316084080
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.1561821439
Short name T2212
Test name
Test status
Simulation time 4937970547 ps
CPU time 146.72 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 218524 kb
Host smart-fd75cf05-2602-4544-9908-dbd64b47bc08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1561821439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.1561821439
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3504502348
Short name T2594
Test name
Test status
Simulation time 2379895502 ps
CPU time 23.07 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:26 PM PDT 24
Peak memory 217616 kb
Host smart-a7791231-ee1a-48c4-8446-65a759cbc7cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3504502348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3504502348
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2761090226
Short name T2954
Test name
Test status
Simulation time 270283964 ps
CPU time 1.03 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207568 kb
Host smart-e29fbcf1-55f8-4851-8c74-36e8a68017ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2761090226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2761090226
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2118177025
Short name T1556
Test name
Test status
Simulation time 189232861 ps
CPU time 0.98 seconds
Started Aug 10 07:11:06 PM PDT 24
Finished Aug 10 07:11:07 PM PDT 24
Peak memory 207532 kb
Host smart-500c49cf-0c86-40b0-8d6d-51b6a0044c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21181
77025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2118177025
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2398826795
Short name T2918
Test name
Test status
Simulation time 1914487371 ps
CPU time 55.46 seconds
Started Aug 10 07:11:07 PM PDT 24
Finished Aug 10 07:12:03 PM PDT 24
Peak memory 217440 kb
Host smart-d1f548d3-d5ea-4e7c-8f27-3c4897086413
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2398826795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2398826795
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.4160319788
Short name T1335
Test name
Test status
Simulation time 159508169 ps
CPU time 0.84 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:04 PM PDT 24
Peak memory 207556 kb
Host smart-b0ee5c8a-cd1f-4a47-b079-f745761147f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4160319788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.4160319788
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3334476670
Short name T1955
Test name
Test status
Simulation time 162458030 ps
CPU time 0.83 seconds
Started Aug 10 07:11:07 PM PDT 24
Finished Aug 10 07:11:08 PM PDT 24
Peak memory 207552 kb
Host smart-793a465a-b7a6-40fd-a880-896c7e00e123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
76670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3334476670
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.621997344
Short name T3061
Test name
Test status
Simulation time 210026249 ps
CPU time 0.97 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:04 PM PDT 24
Peak memory 207500 kb
Host smart-b821c80b-b8a3-4732-abe0-d4c1961990d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62199
7344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.621997344
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1375518658
Short name T2114
Test name
Test status
Simulation time 172954748 ps
CPU time 0.88 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207544 kb
Host smart-35d18984-79e2-482d-9565-1e4b6899d00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13755
18658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1375518658
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3109476707
Short name T2545
Test name
Test status
Simulation time 221452120 ps
CPU time 0.92 seconds
Started Aug 10 07:11:06 PM PDT 24
Finished Aug 10 07:11:07 PM PDT 24
Peak memory 207532 kb
Host smart-fd827c6c-e515-4dec-90ab-4b7e26ea75d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
76707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3109476707
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.592106147
Short name T1588
Test name
Test status
Simulation time 152865548 ps
CPU time 0.83 seconds
Started Aug 10 07:11:04 PM PDT 24
Finished Aug 10 07:11:05 PM PDT 24
Peak memory 207576 kb
Host smart-2982ac10-183f-4d9a-86bd-987baf4fb856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59210
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.592106147
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3062715200
Short name T1242
Test name
Test status
Simulation time 219601228 ps
CPU time 0.97 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207600 kb
Host smart-81b3c2fd-16ef-40b5-a145-9cf1cd113c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30627
15200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3062715200
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2764870112
Short name T3230
Test name
Test status
Simulation time 262648968 ps
CPU time 1.07 seconds
Started Aug 10 07:11:05 PM PDT 24
Finished Aug 10 07:11:06 PM PDT 24
Peak memory 207548 kb
Host smart-140c5b93-a393-4e42-9b9e-309b7d7b9f77
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2764870112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2764870112
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.724994137
Short name T2540
Test name
Test status
Simulation time 164515681 ps
CPU time 0.83 seconds
Started Aug 10 07:11:07 PM PDT 24
Finished Aug 10 07:11:08 PM PDT 24
Peak memory 207536 kb
Host smart-d04dc05f-f94d-4d6c-8327-e4147b637ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72499
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.724994137
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3759706273
Short name T3421
Test name
Test status
Simulation time 8074352338 ps
CPU time 20.29 seconds
Started Aug 10 07:11:17 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 216112 kb
Host smart-86f4892e-e4ff-4d9d-be31-ec0a00925d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
06273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3759706273
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3371457175
Short name T2793
Test name
Test status
Simulation time 168319700 ps
CPU time 0.91 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207416 kb
Host smart-a81b512e-7080-4538-90ef-0d7a21791c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
57175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3371457175
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1062408957
Short name T672
Test name
Test status
Simulation time 219996518 ps
CPU time 0.98 seconds
Started Aug 10 07:11:15 PM PDT 24
Finished Aug 10 07:11:16 PM PDT 24
Peak memory 207728 kb
Host smart-315e8548-6eb1-4dd2-a1d5-b250cad92ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10624
08957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1062408957
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3102755431
Short name T2717
Test name
Test status
Simulation time 164241395 ps
CPU time 0.85 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207552 kb
Host smart-e8c7aea2-be48-4d2a-bd41-37876ec684a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31027
55431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3102755431
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.762120224
Short name T3559
Test name
Test status
Simulation time 198928067 ps
CPU time 0.92 seconds
Started Aug 10 07:11:17 PM PDT 24
Finished Aug 10 07:11:18 PM PDT 24
Peak memory 207540 kb
Host smart-8f1ab791-0c28-4656-9444-906bc7c961a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76212
0224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.762120224
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1424241210
Short name T2930
Test name
Test status
Simulation time 206531815 ps
CPU time 0.9 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207608 kb
Host smart-dd729b05-675a-4d95-a27d-c00254da7a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
41210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1424241210
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_rx_full.2154939883
Short name T1060
Test name
Test status
Simulation time 499108549 ps
CPU time 1.41 seconds
Started Aug 10 07:11:15 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207480 kb
Host smart-1e1cd752-968d-41fb-934c-b53cf95032a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
39883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.2154939883
Directory /workspace/25.usbdev_rx_full/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1490176162
Short name T958
Test name
Test status
Simulation time 156446160 ps
CPU time 0.84 seconds
Started Aug 10 07:11:15 PM PDT 24
Finished Aug 10 07:11:15 PM PDT 24
Peak memory 207528 kb
Host smart-a6083042-0fe1-42ea-9589-73f5e99e099b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14901
76162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1490176162
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1626293769
Short name T2994
Test name
Test status
Simulation time 151713846 ps
CPU time 0.85 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207424 kb
Host smart-7972c074-887c-4642-bb39-3e3e37a79dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262
93769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1626293769
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.833055699
Short name T1172
Test name
Test status
Simulation time 198209991 ps
CPU time 0.94 seconds
Started Aug 10 07:11:18 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207608 kb
Host smart-f1fed4f3-c870-4c44-bdda-9b30487ded24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83305
5699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.833055699
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3458235371
Short name T2025
Test name
Test status
Simulation time 2335653081 ps
CPU time 64.7 seconds
Started Aug 10 07:11:17 PM PDT 24
Finished Aug 10 07:12:21 PM PDT 24
Peak memory 217688 kb
Host smart-f48bd02a-1f93-47a2-837f-a0fa1a1341de
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3458235371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3458235371
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3226006923
Short name T3414
Test name
Test status
Simulation time 158286835 ps
CPU time 0.9 seconds
Started Aug 10 07:11:18 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207444 kb
Host smart-4b326663-d66b-43ef-a879-0b63ce6d4d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
06923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3226006923
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2880339553
Short name T1916
Test name
Test status
Simulation time 178467402 ps
CPU time 0.91 seconds
Started Aug 10 07:11:18 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207564 kb
Host smart-3a70a685-6c0e-4fec-ab0d-f9b36f9a09dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803
39553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2880339553
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.2315592736
Short name T983
Test name
Test status
Simulation time 1023550708 ps
CPU time 2.46 seconds
Started Aug 10 07:11:17 PM PDT 24
Finished Aug 10 07:11:20 PM PDT 24
Peak memory 207756 kb
Host smart-60587db7-8b51-482c-acf4-c9b0f41ec1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23155
92736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.2315592736
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2380932777
Short name T1232
Test name
Test status
Simulation time 3086730679 ps
CPU time 30.54 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:47 PM PDT 24
Peak memory 217532 kb
Host smart-9e49b314-218e-4125-b354-482605e652e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23809
32777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2380932777
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.734333488
Short name T2483
Test name
Test status
Simulation time 1317394086 ps
CPU time 31.08 seconds
Started Aug 10 07:11:03 PM PDT 24
Finished Aug 10 07:11:34 PM PDT 24
Peak memory 207720 kb
Host smart-823117e6-c3e5-4a36-8240-8e9dfcaadccd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734333488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_host
_handshake.734333488
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_tx_rx_disruption.3320662014
Short name T209
Test name
Test status
Simulation time 482877094 ps
CPU time 1.55 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:17 PM PDT 24
Peak memory 207604 kb
Host smart-49b7db2f-b20a-4b80-a471-591836641b6f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320662014 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.usbdev_tx_rx_disruption.3320662014
Directory /workspace/25.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/250.usbdev_tx_rx_disruption.2288530945
Short name T3231
Test name
Test status
Simulation time 603549651 ps
CPU time 1.71 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207512 kb
Host smart-a819cc37-0619-4b7b-a41a-55cde2c87e6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288530945 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.usbdev_tx_rx_disruption.2288530945
Directory /workspace/250.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/251.usbdev_tx_rx_disruption.365486268
Short name T1665
Test name
Test status
Simulation time 599524140 ps
CPU time 1.66 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207568 kb
Host smart-01105c98-b145-4a75-8995-2004de926240
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365486268 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 251.usbdev_tx_rx_disruption.365486268
Directory /workspace/251.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/252.usbdev_tx_rx_disruption.1568384225
Short name T2550
Test name
Test status
Simulation time 484506887 ps
CPU time 1.45 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207608 kb
Host smart-84f4db3f-f46b-41d2-ab27-995d381a7606
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568384225 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.usbdev_tx_rx_disruption.1568384225
Directory /workspace/252.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/253.usbdev_tx_rx_disruption.4086232976
Short name T2138
Test name
Test status
Simulation time 594172813 ps
CPU time 1.7 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207508 kb
Host smart-b03e2406-b6ce-42ca-baa1-9c66cc7934e3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086232976 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.usbdev_tx_rx_disruption.4086232976
Directory /workspace/253.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/254.usbdev_tx_rx_disruption.970948649
Short name T1632
Test name
Test status
Simulation time 673847700 ps
CPU time 1.9 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207512 kb
Host smart-2d0bf189-7ae9-4c24-bbe2-29eaad150b15
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970948649 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 254.usbdev_tx_rx_disruption.970948649
Directory /workspace/254.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/255.usbdev_tx_rx_disruption.2682803946
Short name T3355
Test name
Test status
Simulation time 474687654 ps
CPU time 1.56 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207608 kb
Host smart-f366cc11-03dc-41fc-b2de-b17a69be87e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682803946 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.usbdev_tx_rx_disruption.2682803946
Directory /workspace/255.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/256.usbdev_tx_rx_disruption.2526204935
Short name T2886
Test name
Test status
Simulation time 571721224 ps
CPU time 1.68 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:03 PM PDT 24
Peak memory 207600 kb
Host smart-9747ac7d-6fd1-4ccb-992e-b3733d211882
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526204935 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.usbdev_tx_rx_disruption.2526204935
Directory /workspace/256.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/257.usbdev_tx_rx_disruption.2016307898
Short name T3517
Test name
Test status
Simulation time 633869847 ps
CPU time 1.85 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207520 kb
Host smart-1cc531c3-ee1c-4e09-9b39-d9084fae09a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016307898 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.usbdev_tx_rx_disruption.2016307898
Directory /workspace/257.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/258.usbdev_tx_rx_disruption.453585279
Short name T1517
Test name
Test status
Simulation time 451899514 ps
CPU time 1.38 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207444 kb
Host smart-7082be43-5071-4830-992a-b99462426dea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453585279 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 258.usbdev_tx_rx_disruption.453585279
Directory /workspace/258.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/259.usbdev_tx_rx_disruption.3161901020
Short name T3443
Test name
Test status
Simulation time 641341784 ps
CPU time 1.8 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:03 PM PDT 24
Peak memory 207456 kb
Host smart-8b822005-e030-4a7c-9792-320a0eeeb15b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161901020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.usbdev_tx_rx_disruption.3161901020
Directory /workspace/259.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.354746862
Short name T3444
Test name
Test status
Simulation time 60636690 ps
CPU time 0.69 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:38 PM PDT 24
Peak memory 207552 kb
Host smart-502d8c0b-e50a-4ef3-b0c3-63e8fba8de8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=354746862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.354746862
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3698614701
Short name T1622
Test name
Test status
Simulation time 10406789774 ps
CPU time 12.79 seconds
Started Aug 10 07:11:18 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207712 kb
Host smart-80dd9383-dc47-4bf4-aca0-82318af28f47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698614701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.3698614701
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2191725007
Short name T718
Test name
Test status
Simulation time 14197487785 ps
CPU time 19.69 seconds
Started Aug 10 07:11:17 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 215968 kb
Host smart-81cf329d-f59b-4338-b709-80ae567ef451
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191725007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2191725007
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1409032300
Short name T2510
Test name
Test status
Simulation time 28439287290 ps
CPU time 34.41 seconds
Started Aug 10 07:11:16 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 207784 kb
Host smart-09ac1ceb-9bfb-4134-9bf1-2e52584deaad
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409032300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.1409032300
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.644116290
Short name T1643
Test name
Test status
Simulation time 181911835 ps
CPU time 0.91 seconds
Started Aug 10 07:11:18 PM PDT 24
Finished Aug 10 07:11:19 PM PDT 24
Peak memory 207608 kb
Host smart-c32f5dd6-a34d-495d-bd38-5bc2229077a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64411
6290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.644116290
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2791242596
Short name T2992
Test name
Test status
Simulation time 158615556 ps
CPU time 0.86 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:11:27 PM PDT 24
Peak memory 207584 kb
Host smart-5d471e41-23c0-4c19-b630-db93e6588e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
42596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2791242596
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.709406197
Short name T641
Test name
Test status
Simulation time 472656214 ps
CPU time 1.69 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207476 kb
Host smart-875b7689-c2f6-4e64-9d98-b13a3444d63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70940
6197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.709406197
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3742158898
Short name T3575
Test name
Test status
Simulation time 1120916513 ps
CPU time 2.99 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207784 kb
Host smart-83021e62-364e-437d-a630-e20cd7326037
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3742158898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3742158898
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2209697281
Short name T3145
Test name
Test status
Simulation time 42030267915 ps
CPU time 69.97 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207848 kb
Host smart-7cc199fa-adc2-476c-bbfd-d65f66246804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22096
97281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2209697281
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.2506477095
Short name T98
Test name
Test status
Simulation time 7742333492 ps
CPU time 51.01 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:12:21 PM PDT 24
Peak memory 207764 kb
Host smart-484f4490-ff82-464a-b764-f1d61e9c076e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506477095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.2506477095
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1143013540
Short name T1270
Test name
Test status
Simulation time 981078292 ps
CPU time 2.16 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:32 PM PDT 24
Peak memory 207476 kb
Host smart-5d1a2576-88b8-48b1-aa2e-583e8524b64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
13540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1143013540
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.545181749
Short name T2393
Test name
Test status
Simulation time 150984079 ps
CPU time 0.88 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207476 kb
Host smart-bac9ea62-0551-4605-afb2-bb19f1cee93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54518
1749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.545181749
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3057565679
Short name T1597
Test name
Test status
Simulation time 28575611 ps
CPU time 0.68 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207488 kb
Host smart-d7d6b683-5efc-43ad-ae65-ae6d24eab20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30575
65679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3057565679
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3396377780
Short name T23
Test name
Test status
Simulation time 842030362 ps
CPU time 2.52 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207712 kb
Host smart-466633ec-202e-4077-b27d-2f1abe204829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
77780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3396377780
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_types.3293643695
Short name T2219
Test name
Test status
Simulation time 189841590 ps
CPU time 0.89 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207520 kb
Host smart-4ce99efe-152b-419b-b3b8-d050f5aa654f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3293643695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.3293643695
Directory /workspace/26.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2134865973
Short name T2987
Test name
Test status
Simulation time 230863672 ps
CPU time 2.5 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207660 kb
Host smart-3b5513ea-6c5e-4949-97c9-f5f47f676dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
65973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2134865973
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3015222997
Short name T3224
Test name
Test status
Simulation time 208662070 ps
CPU time 1.07 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 215896 kb
Host smart-4bdece30-c04d-4409-b674-c5769e6b77ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3015222997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3015222997
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2120727888
Short name T851
Test name
Test status
Simulation time 149309673 ps
CPU time 0.83 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207516 kb
Host smart-dca08135-fa41-4063-b49a-1347e417189b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21207
27888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2120727888
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2925802954
Short name T571
Test name
Test status
Simulation time 181002137 ps
CPU time 0.88 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:11:27 PM PDT 24
Peak memory 207544 kb
Host smart-b4c8322b-24d0-4853-ad04-ecd6a97d4a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29258
02954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2925802954
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.911204473
Short name T1846
Test name
Test status
Simulation time 4838925797 ps
CPU time 47.14 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:12:14 PM PDT 24
Peak memory 218428 kb
Host smart-433c3372-00ef-48fa-ad5e-dbe60a92c923
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=911204473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.911204473
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.111105093
Short name T3476
Test name
Test status
Simulation time 6476444410 ps
CPU time 84.88 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:12:55 PM PDT 24
Peak memory 207776 kb
Host smart-2d3c7de3-3033-4246-a509-6b4e6d2f8a8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=111105093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.111105093
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3709704827
Short name T753
Test name
Test status
Simulation time 171180560 ps
CPU time 0.88 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207528 kb
Host smart-3d32e246-8e1d-4193-8bab-d6a46c6b426c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37097
04827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3709704827
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3928822193
Short name T1402
Test name
Test status
Simulation time 30971861538 ps
CPU time 47.99 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207812 kb
Host smart-0d001015-e1f0-43e0-b5bb-fc5e94c6cd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
22193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3928822193
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2176671715
Short name T1320
Test name
Test status
Simulation time 11236372428 ps
CPU time 16.84 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:44 PM PDT 24
Peak memory 207820 kb
Host smart-09104845-3586-4a47-bd60-1be338a3b86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766
71715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2176671715
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1477516745
Short name T3570
Test name
Test status
Simulation time 2630733855 ps
CPU time 76.52 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:12:45 PM PDT 24
Peak memory 224112 kb
Host smart-3842070e-75e6-4223-a7f2-92aef55b6f60
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1477516745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1477516745
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.789435938
Short name T6
Test name
Test status
Simulation time 2320157771 ps
CPU time 22.99 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 217684 kb
Host smart-55fc4b24-a8c9-4113-ac21-16cfc238bb3c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=789435938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.789435938
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.510399210
Short name T3554
Test name
Test status
Simulation time 250636145 ps
CPU time 0.97 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207512 kb
Host smart-9304c5e7-0949-48d8-bd53-a52085e755e1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=510399210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.510399210
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1252159162
Short name T842
Test name
Test status
Simulation time 191996705 ps
CPU time 0.92 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207412 kb
Host smart-95b5347c-f721-4e89-9bb1-bb05fde6bc54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
59162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1252159162
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.4050594813
Short name T3352
Test name
Test status
Simulation time 3955563876 ps
CPU time 116.88 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:13:27 PM PDT 24
Peak memory 217696 kb
Host smart-2fbe68b6-7616-4e90-91ca-934460640b6a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4050594813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.4050594813
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2655554856
Short name T3194
Test name
Test status
Simulation time 152356254 ps
CPU time 0.9 seconds
Started Aug 10 07:11:31 PM PDT 24
Finished Aug 10 07:11:32 PM PDT 24
Peak memory 207476 kb
Host smart-0df9e3a7-f163-4d31-98b6-8f6afa7e4ae5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2655554856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2655554856
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2528982570
Short name T1383
Test name
Test status
Simulation time 145538503 ps
CPU time 0.84 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207396 kb
Host smart-bf38f930-b40a-47fe-b767-d3d32f49fc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
82570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2528982570
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2410593716
Short name T139
Test name
Test status
Simulation time 196527631 ps
CPU time 0.95 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207404 kb
Host smart-c77d73d8-7926-41d3-9d47-56985b324db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105
93716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2410593716
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2847863259
Short name T3251
Test name
Test status
Simulation time 237669032 ps
CPU time 1.02 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207572 kb
Host smart-51c3b4b4-c98b-457a-8adf-621695c27e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
63259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2847863259
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1203526260
Short name T3234
Test name
Test status
Simulation time 163646120 ps
CPU time 0.85 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207540 kb
Host smart-a7472b30-4dcf-46a3-b18c-e35be637392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12035
26260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1203526260
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.340859096
Short name T2120
Test name
Test status
Simulation time 199485111 ps
CPU time 0.91 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207500 kb
Host smart-c482b5cc-8b35-4350-8163-9a4249dc5804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34085
9096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.340859096
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4226024832
Short name T206
Test name
Test status
Simulation time 192770473 ps
CPU time 0.88 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207744 kb
Host smart-753f541c-e359-464e-8e65-b051527672a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
24832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4226024832
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.898930912
Short name T1126
Test name
Test status
Simulation time 236951971 ps
CPU time 1.03 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207420 kb
Host smart-ce665636-7963-4782-abb5-119794bb01a0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=898930912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.898930912
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2661700246
Short name T1001
Test name
Test status
Simulation time 163998088 ps
CPU time 0.85 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207520 kb
Host smart-2b7193b7-bea8-4566-bc9f-b14adc878d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
00246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2661700246
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2435466802
Short name T2680
Test name
Test status
Simulation time 50665205 ps
CPU time 0.69 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 206752 kb
Host smart-4255612d-217d-4aea-a0ff-70d5ac04607d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24354
66802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2435466802
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.341348374
Short name T2069
Test name
Test status
Simulation time 7883340839 ps
CPU time 19.76 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:11:46 PM PDT 24
Peak memory 216064 kb
Host smart-3746c2e3-ff8a-4879-8139-21cd0b6cbef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34134
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.341348374
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3415801999
Short name T1155
Test name
Test status
Simulation time 174997335 ps
CPU time 0.87 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207512 kb
Host smart-4df12820-493e-4960-9932-070baf3b03be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34158
01999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3415801999
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2587503434
Short name T1832
Test name
Test status
Simulation time 281310621 ps
CPU time 1.05 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207528 kb
Host smart-afd16aba-2183-4af5-b705-8180e3d64255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25875
03434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2587503434
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.360240889
Short name T1732
Test name
Test status
Simulation time 224396133 ps
CPU time 1.01 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207508 kb
Host smart-f0b34cfe-53ac-4378-a89b-b77ac10686f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
0889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.360240889
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.2117320770
Short name T2972
Test name
Test status
Simulation time 145835307 ps
CPU time 0.89 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207552 kb
Host smart-7461207a-0e2d-4ddf-8253-4b4ef3b8f47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21173
20770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.2117320770
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.638122281
Short name T2161
Test name
Test status
Simulation time 134806494 ps
CPU time 0.83 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:29 PM PDT 24
Peak memory 207548 kb
Host smart-12e55f15-5e2e-4c43-a9c9-c5756513e89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63812
2281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.638122281
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_rx_full.3530296300
Short name T355
Test name
Test status
Simulation time 278525649 ps
CPU time 1.11 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207552 kb
Host smart-03dbcab2-0150-4652-a84c-614baba10519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
96300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.3530296300
Directory /workspace/26.usbdev_rx_full/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3416659245
Short name T1565
Test name
Test status
Simulation time 167484353 ps
CPU time 0.86 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:11:27 PM PDT 24
Peak memory 207492 kb
Host smart-f10d0517-31f7-4aef-a9d2-91fa313e1907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34166
59245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3416659245
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1144016713
Short name T2351
Test name
Test status
Simulation time 161187197 ps
CPU time 0.84 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207520 kb
Host smart-c6a78181-51ef-4623-bb6d-f2d43a10eadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11440
16713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1144016713
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2281133409
Short name T3330
Test name
Test status
Simulation time 224967614 ps
CPU time 0.98 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207568 kb
Host smart-e47a6757-f600-44b8-94df-b0b8220cc36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
33409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2281133409
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1936584298
Short name T2182
Test name
Test status
Simulation time 3696040401 ps
CPU time 111.34 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:13:20 PM PDT 24
Peak memory 217788 kb
Host smart-1a6ea367-d1c9-4331-bef6-dc1fad7c4ece
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1936584298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1936584298
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.239241523
Short name T747
Test name
Test status
Simulation time 210587298 ps
CPU time 0.95 seconds
Started Aug 10 07:11:29 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 207552 kb
Host smart-845cf9df-3d35-44f2-99a2-13936a515822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23924
1523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.239241523
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1144803753
Short name T562
Test name
Test status
Simulation time 164070773 ps
CPU time 0.84 seconds
Started Aug 10 07:11:27 PM PDT 24
Finished Aug 10 07:11:28 PM PDT 24
Peak memory 207488 kb
Host smart-6606e3a5-f0c9-4596-9aea-78e29f07c785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
03753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1144803753
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.2562476189
Short name T3289
Test name
Test status
Simulation time 1263662454 ps
CPU time 2.92 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:31 PM PDT 24
Peak memory 207676 kb
Host smart-dd9bf5a7-1cc6-437a-b414-dd8b65040b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25624
76189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.2562476189
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.836124556
Short name T1096
Test name
Test status
Simulation time 1854264186 ps
CPU time 14.1 seconds
Started Aug 10 07:11:30 PM PDT 24
Finished Aug 10 07:11:44 PM PDT 24
Peak memory 215956 kb
Host smart-f4ace7aa-819f-4b15-a33c-98e9bdffbb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83612
4556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.836124556
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.1671462149
Short name T1520
Test name
Test status
Simulation time 8390704347 ps
CPU time 57.16 seconds
Started Aug 10 07:11:26 PM PDT 24
Finished Aug 10 07:12:24 PM PDT 24
Peak memory 207876 kb
Host smart-373d731f-f2e6-4a88-900b-a33652ce2d31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671462149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.1671462149
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_tx_rx_disruption.2182538970
Short name T1534
Test name
Test status
Simulation time 597180179 ps
CPU time 1.59 seconds
Started Aug 10 07:11:28 PM PDT 24
Finished Aug 10 07:11:30 PM PDT 24
Peak memory 206876 kb
Host smart-51fb2219-4d65-4251-b726-a8b5c805d368
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182538970 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.usbdev_tx_rx_disruption.2182538970
Directory /workspace/26.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/260.usbdev_tx_rx_disruption.1278998305
Short name T1888
Test name
Test status
Simulation time 484730985 ps
CPU time 1.53 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207512 kb
Host smart-f3509eb1-b2be-4323-a58d-61c2221482e7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278998305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.usbdev_tx_rx_disruption.1278998305
Directory /workspace/260.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/261.usbdev_tx_rx_disruption.959468103
Short name T2726
Test name
Test status
Simulation time 599847217 ps
CPU time 1.59 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207540 kb
Host smart-8e7b38ff-8c86-46c8-b1b6-0faf98b71bc2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959468103 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 261.usbdev_tx_rx_disruption.959468103
Directory /workspace/261.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/262.usbdev_tx_rx_disruption.352518248
Short name T3313
Test name
Test status
Simulation time 461757658 ps
CPU time 1.5 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:03 PM PDT 24
Peak memory 207532 kb
Host smart-e476afb3-0f21-43cb-bac4-d4c32335a95e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352518248 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 262.usbdev_tx_rx_disruption.352518248
Directory /workspace/262.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/263.usbdev_tx_rx_disruption.478647472
Short name T1081
Test name
Test status
Simulation time 618624876 ps
CPU time 1.75 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207564 kb
Host smart-79db42f3-5ee4-4bde-bd98-ed8661074b53
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478647472 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 263.usbdev_tx_rx_disruption.478647472
Directory /workspace/263.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/264.usbdev_tx_rx_disruption.2622031989
Short name T2033
Test name
Test status
Simulation time 534272619 ps
CPU time 1.64 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207444 kb
Host smart-87a23f12-e952-42ba-8109-c65863689d2d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622031989 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.usbdev_tx_rx_disruption.2622031989
Directory /workspace/264.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/265.usbdev_tx_rx_disruption.3937932163
Short name T1726
Test name
Test status
Simulation time 685696774 ps
CPU time 1.84 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207480 kb
Host smart-1237a131-2140-4d25-b3fc-1c10b4d21040
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937932163 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.usbdev_tx_rx_disruption.3937932163
Directory /workspace/265.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/266.usbdev_tx_rx_disruption.1950485289
Short name T789
Test name
Test status
Simulation time 527666152 ps
CPU time 1.8 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207420 kb
Host smart-5f25b70e-350d-4fb2-8535-6bacc95c1d9b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950485289 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.usbdev_tx_rx_disruption.1950485289
Directory /workspace/266.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/267.usbdev_tx_rx_disruption.1484526069
Short name T1137
Test name
Test status
Simulation time 517616875 ps
CPU time 1.6 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207556 kb
Host smart-f8fa40c8-e8e1-4c62-96ab-a7927967fc08
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484526069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.usbdev_tx_rx_disruption.1484526069
Directory /workspace/267.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/269.usbdev_tx_rx_disruption.2422050606
Short name T814
Test name
Test status
Simulation time 484793107 ps
CPU time 1.5 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207604 kb
Host smart-b4da1646-cb1e-494d-8efd-69d5d3263efc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422050606 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.usbdev_tx_rx_disruption.2422050606
Directory /workspace/269.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3039518748
Short name T984
Test name
Test status
Simulation time 60050672 ps
CPU time 0.66 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:51 PM PDT 24
Peak memory 207572 kb
Host smart-47b96aa3-0a49-4bcd-a19e-ba66c3ba2040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3039518748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3039518748
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1949007447
Short name T2678
Test name
Test status
Simulation time 4436137620 ps
CPU time 6.42 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:43 PM PDT 24
Peak memory 215980 kb
Host smart-86964b3c-1242-481b-a202-ce3406720a06
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949007447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.1949007447
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1190963716
Short name T3573
Test name
Test status
Simulation time 21175194185 ps
CPU time 25.75 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:12:02 PM PDT 24
Peak memory 207876 kb
Host smart-cb80be19-1784-4f85-a194-358880617fb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190963716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1190963716
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3847855767
Short name T1934
Test name
Test status
Simulation time 28365337924 ps
CPU time 33.78 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:12:11 PM PDT 24
Peak memory 207780 kb
Host smart-3120a08e-b660-4b3a-a524-f97edbf3c6cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847855767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.3847855767
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2144534331
Short name T2445
Test name
Test status
Simulation time 170626017 ps
CPU time 0.9 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207444 kb
Host smart-58c25244-ed09-4168-b568-bfc74ccc564c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21445
34331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2144534331
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2269746159
Short name T950
Test name
Test status
Simulation time 153054869 ps
CPU time 0.83 seconds
Started Aug 10 07:11:42 PM PDT 24
Finished Aug 10 07:11:43 PM PDT 24
Peak memory 207508 kb
Host smart-9e5eaed5-d557-48cc-b733-3fc3a4a39c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22697
46159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2269746159
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.898543292
Short name T1774
Test name
Test status
Simulation time 349851591 ps
CPU time 1.32 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:11:38 PM PDT 24
Peak memory 207496 kb
Host smart-d1ca7096-c10a-41e3-87cf-2acb65244721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89854
3292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.898543292
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3373914979
Short name T360
Test name
Test status
Simulation time 1370248256 ps
CPU time 3.41 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:44 PM PDT 24
Peak memory 207756 kb
Host smart-b126b213-195b-43d2-a098-9a020ffc268c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3373914979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3373914979
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3652592981
Short name T2969
Test name
Test status
Simulation time 16823447704 ps
CPU time 27.59 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:12:03 PM PDT 24
Peak memory 207812 kb
Host smart-46032873-b910-4b33-bb77-0aebd280187d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36525
92981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3652592981
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.1838563859
Short name T2403
Test name
Test status
Simulation time 3607888263 ps
CPU time 23.35 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:12:04 PM PDT 24
Peak memory 207892 kb
Host smart-ae62b387-472d-4556-8f98-d8994a9fc33e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838563859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.1838563859
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2549341416
Short name T2888
Test name
Test status
Simulation time 1031180381 ps
CPU time 2.25 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207616 kb
Host smart-0a47fa31-886a-47b5-9e0e-7fb67b5d4782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25493
41416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2549341416
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1057281976
Short name T2831
Test name
Test status
Simulation time 227093627 ps
CPU time 0.96 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207496 kb
Host smart-d3dd9cf5-924c-42ee-ac18-4116bebfa93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10572
81976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1057281976
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2801568526
Short name T632
Test name
Test status
Simulation time 51073010 ps
CPU time 0.72 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 207468 kb
Host smart-3543e090-3d82-4525-b688-d9b97b2dfe52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28015
68526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2801568526
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1819086111
Short name T599
Test name
Test status
Simulation time 798305164 ps
CPU time 2.22 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:40 PM PDT 24
Peak memory 207704 kb
Host smart-6a69a28f-cfda-4aea-84cf-680fc4c015a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18190
86111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1819086111
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_types.2797742761
Short name T424
Test name
Test status
Simulation time 549991374 ps
CPU time 1.41 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:40 PM PDT 24
Peak memory 207488 kb
Host smart-1fd87459-e76d-409c-b549-919497306838
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2797742761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.2797742761
Directory /workspace/27.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3273217161
Short name T900
Test name
Test status
Simulation time 191593248 ps
CPU time 2.41 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:42 PM PDT 24
Peak memory 207724 kb
Host smart-af559a63-9948-42c9-9b9e-0a97dc5af9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732
17161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3273217161
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2259545196
Short name T2364
Test name
Test status
Simulation time 160689132 ps
CPU time 0.92 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 207432 kb
Host smart-a3f3d11b-aaa2-4ed0-b428-60673b1191e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2259545196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2259545196
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2264693067
Short name T2846
Test name
Test status
Simulation time 175501043 ps
CPU time 0.83 seconds
Started Aug 10 07:11:43 PM PDT 24
Finished Aug 10 07:11:44 PM PDT 24
Peak memory 207512 kb
Host smart-995eac72-80a5-4bc6-b576-65c1a469dd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
93067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2264693067
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2186975468
Short name T1986
Test name
Test status
Simulation time 268228789 ps
CPU time 1.02 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207416 kb
Host smart-4937df51-3225-420b-bab7-c080f480425e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21869
75468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2186975468
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.1502354651
Short name T2784
Test name
Test status
Simulation time 3291083921 ps
CPU time 93.77 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:13:12 PM PDT 24
Peak memory 218356 kb
Host smart-49d43d6f-e8ad-4a3b-a04a-a48abbdd7f87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1502354651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.1502354651
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.2866995326
Short name T3213
Test name
Test status
Simulation time 4489797854 ps
CPU time 32.23 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:12:11 PM PDT 24
Peak memory 207820 kb
Host smart-5c791a1b-dabb-49af-8baf-038a6294249e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2866995326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.2866995326
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3481140094
Short name T2426
Test name
Test status
Simulation time 252540270 ps
CPU time 1.02 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:38 PM PDT 24
Peak memory 207528 kb
Host smart-d79f8c74-d281-4eb4-9b81-bbe5622e18c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811
40094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3481140094
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.117547507
Short name T2246
Test name
Test status
Simulation time 32288993675 ps
CPU time 48.88 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207804 kb
Host smart-e82c7d0f-39b3-44ef-b7ea-9fa1b051e020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11754
7507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.117547507
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2932176357
Short name T1536
Test name
Test status
Simulation time 4349632201 ps
CPU time 6.68 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:45 PM PDT 24
Peak memory 207776 kb
Host smart-d5b9dfda-c42f-4568-b9b5-e58bd274df91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29321
76357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2932176357
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.674329330
Short name T1528
Test name
Test status
Simulation time 3244171351 ps
CPU time 95.91 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:13:14 PM PDT 24
Peak memory 218536 kb
Host smart-98c32cd4-4cda-4d28-a51b-78ef7bae6f11
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=674329330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.674329330
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2875081034
Short name T2170
Test name
Test status
Simulation time 2263893841 ps
CPU time 64.4 seconds
Started Aug 10 07:11:42 PM PDT 24
Finished Aug 10 07:12:47 PM PDT 24
Peak memory 216060 kb
Host smart-cead4052-f534-4fc5-8690-2dd0246176db
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2875081034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2875081034
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3586468527
Short name T812
Test name
Test status
Simulation time 315136058 ps
CPU time 1.04 seconds
Started Aug 10 07:11:42 PM PDT 24
Finished Aug 10 07:11:43 PM PDT 24
Peak memory 207536 kb
Host smart-3ceaba15-4ce9-49a8-8136-1b2d94bad693
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3586468527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3586468527
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1207931710
Short name T2768
Test name
Test status
Simulation time 202114116 ps
CPU time 0.97 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 207580 kb
Host smart-e0955522-d8bc-47f1-8b87-d60db1c1a3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12079
31710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1207931710
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2952499522
Short name T1809
Test name
Test status
Simulation time 2255867495 ps
CPU time 69.2 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:12:45 PM PDT 24
Peak memory 217156 kb
Host smart-36fdf6dd-42bc-491d-9662-ca463b9822bc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2952499522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2952499522
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3169746879
Short name T1557
Test name
Test status
Simulation time 168165927 ps
CPU time 0.89 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:41 PM PDT 24
Peak memory 207504 kb
Host smart-eb85ade6-e5ad-4458-93ee-4205afcf45c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3169746879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3169746879
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4240319911
Short name T2506
Test name
Test status
Simulation time 150661821 ps
CPU time 0.83 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:41 PM PDT 24
Peak memory 207540 kb
Host smart-448efd31-1e77-43eb-80f8-a7506dc6ff12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
19911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4240319911
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.583549867
Short name T142
Test name
Test status
Simulation time 214022595 ps
CPU time 1.03 seconds
Started Aug 10 07:11:43 PM PDT 24
Finished Aug 10 07:11:44 PM PDT 24
Peak memory 207544 kb
Host smart-f8c26a45-6fcd-4b93-b01e-16182ac4032d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58354
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.583549867
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.4161459318
Short name T2514
Test name
Test status
Simulation time 185868770 ps
CPU time 1.01 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:41 PM PDT 24
Peak memory 207392 kb
Host smart-08f9b288-2818-4539-9092-9970c45d6978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41614
59318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.4161459318
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2860341508
Short name T921
Test name
Test status
Simulation time 166751812 ps
CPU time 0.89 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:41 PM PDT 24
Peak memory 207588 kb
Host smart-0dada832-e5c4-438c-b93b-0ea879097b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
41508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2860341508
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.513307023
Short name T745
Test name
Test status
Simulation time 181243179 ps
CPU time 0.88 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:38 PM PDT 24
Peak memory 207524 kb
Host smart-c857bd49-14ce-461c-96f2-a1eab1a6ff14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51330
7023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.513307023
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1069822209
Short name T3628
Test name
Test status
Simulation time 157833525 ps
CPU time 0.85 seconds
Started Aug 10 07:11:36 PM PDT 24
Finished Aug 10 07:11:37 PM PDT 24
Peak memory 207544 kb
Host smart-7d7fc491-0ce9-421c-9e45-ce9ac3755847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698
22209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1069822209
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2748245068
Short name T2989
Test name
Test status
Simulation time 222362204 ps
CPU time 1.09 seconds
Started Aug 10 07:11:39 PM PDT 24
Finished Aug 10 07:11:40 PM PDT 24
Peak memory 207604 kb
Host smart-289731fc-ca44-4627-877b-43d6ed748710
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2748245068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2748245068
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2266348756
Short name T1592
Test name
Test status
Simulation time 151193624 ps
CPU time 0.94 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:11:41 PM PDT 24
Peak memory 207568 kb
Host smart-0c1b40c0-1d0d-4612-a0f4-dc48d4a1c2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
48756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2266348756
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1375336889
Short name T42
Test name
Test status
Simulation time 87631971 ps
CPU time 0.74 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207524 kb
Host smart-09757631-f79e-4966-baa8-c8debb73cf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
36889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1375336889
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.4237165752
Short name T315
Test name
Test status
Simulation time 14256741639 ps
CPU time 40.01 seconds
Started Aug 10 07:11:40 PM PDT 24
Finished Aug 10 07:12:20 PM PDT 24
Peak memory 216032 kb
Host smart-ad3b5006-a7e9-4e2f-87f4-99dc4d2e5b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42371
65752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.4237165752
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.4062842517
Short name T1163
Test name
Test status
Simulation time 203627936 ps
CPU time 0.93 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207420 kb
Host smart-8de93d85-deb3-415f-8645-3ee00d7dd661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
42517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.4062842517
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.339544659
Short name T1937
Test name
Test status
Simulation time 269824072 ps
CPU time 1.03 seconds
Started Aug 10 07:11:38 PM PDT 24
Finished Aug 10 07:11:39 PM PDT 24
Peak memory 207540 kb
Host smart-14613c85-db73-47d3-9aca-e649c8651a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33954
4659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.339544659
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.501795840
Short name T2905
Test name
Test status
Simulation time 196523143 ps
CPU time 0.98 seconds
Started Aug 10 07:11:45 PM PDT 24
Finished Aug 10 07:11:46 PM PDT 24
Peak memory 207540 kb
Host smart-1649454e-3377-4e2a-a8f6-88550ea4f1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50179
5840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.501795840
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3720272535
Short name T545
Test name
Test status
Simulation time 180134994 ps
CPU time 0.92 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 207496 kb
Host smart-2529f8e7-2aab-4c17-8272-98c045204062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37202
72535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3720272535
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2633984595
Short name T1030
Test name
Test status
Simulation time 141435565 ps
CPU time 0.86 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207384 kb
Host smart-d831542b-f194-4c75-b4f4-5652e2d53a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
84595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2633984595
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_rx_full.2146775014
Short name T724
Test name
Test status
Simulation time 253999981 ps
CPU time 1.06 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 207532 kb
Host smart-54660c8d-5176-4a0b-b3bb-05ca09b16fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21467
75014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.2146775014
Directory /workspace/27.usbdev_rx_full/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3540781420
Short name T2094
Test name
Test status
Simulation time 160044756 ps
CPU time 0.84 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207628 kb
Host smart-250b4cdc-9248-4811-bbc8-1971dddde58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35407
81420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3540781420
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.200999953
Short name T2268
Test name
Test status
Simulation time 175109597 ps
CPU time 0.89 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 207600 kb
Host smart-afcb9a6b-e098-4e04-9218-724ce0bdf1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099
9953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.200999953
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.836589963
Short name T836
Test name
Test status
Simulation time 190770526 ps
CPU time 0.93 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207496 kb
Host smart-fb833a6e-66c1-4095-9fe6-51ff36216ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83658
9963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.836589963
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.4043351894
Short name T3063
Test name
Test status
Simulation time 2677000112 ps
CPU time 78.61 seconds
Started Aug 10 07:11:47 PM PDT 24
Finished Aug 10 07:13:06 PM PDT 24
Peak memory 217972 kb
Host smart-82a84474-06c4-42a1-aad6-504ae69c6c8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4043351894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4043351894
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.380974504
Short name T1378
Test name
Test status
Simulation time 168808855 ps
CPU time 0.86 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207532 kb
Host smart-1925968a-1543-441d-90f1-a880ce8b27e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38097
4504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.380974504
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2976575381
Short name T2370
Test name
Test status
Simulation time 172776465 ps
CPU time 0.9 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207604 kb
Host smart-982c1a69-5828-45e4-bdc2-735488d0b89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765
75381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2976575381
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.2785048854
Short name T1105
Test name
Test status
Simulation time 1393131731 ps
CPU time 3.22 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:52 PM PDT 24
Peak memory 207672 kb
Host smart-10b83ba2-0b1f-4221-a0a9-bfda545e0917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850
48854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.2785048854
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.914433748
Short name T907
Test name
Test status
Simulation time 2401671531 ps
CPU time 23.16 seconds
Started Aug 10 07:11:46 PM PDT 24
Finished Aug 10 07:12:10 PM PDT 24
Peak memory 216124 kb
Host smart-e08cd3db-ec39-4424-a910-772b62469bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91443
3748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.914433748
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2481646541
Short name T2887
Test name
Test status
Simulation time 882423789 ps
CPU time 18.96 seconds
Started Aug 10 07:11:37 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207772 kb
Host smart-bacc39f6-bba2-44eb-b9e3-1080afc1a707
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481646541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.2481646541
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_tx_rx_disruption.147006242
Short name T3620
Test name
Test status
Simulation time 547976551 ps
CPU time 1.5 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:50 PM PDT 24
Peak memory 207564 kb
Host smart-a6d924b1-43eb-44f3-a891-12eed5ad9025
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147006242 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.usbdev_tx_rx_disruption.147006242
Directory /workspace/27.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/270.usbdev_tx_rx_disruption.494836062
Short name T2230
Test name
Test status
Simulation time 490392265 ps
CPU time 1.6 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207532 kb
Host smart-9a150cb4-b9c7-4744-9661-011afbd035b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494836062 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 270.usbdev_tx_rx_disruption.494836062
Directory /workspace/270.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/271.usbdev_tx_rx_disruption.2953851352
Short name T2911
Test name
Test status
Simulation time 546574617 ps
CPU time 1.6 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:09 PM PDT 24
Peak memory 207604 kb
Host smart-3ec1a091-1de2-47e5-bc80-7c8eaa67c0e2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953851352 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.usbdev_tx_rx_disruption.2953851352
Directory /workspace/271.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/272.usbdev_tx_rx_disruption.1298017587
Short name T2615
Test name
Test status
Simulation time 582550602 ps
CPU time 1.52 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207360 kb
Host smart-e895386c-6278-44fa-b226-dd69afd967bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298017587 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.usbdev_tx_rx_disruption.1298017587
Directory /workspace/272.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/273.usbdev_tx_rx_disruption.1084011407
Short name T1334
Test name
Test status
Simulation time 575259870 ps
CPU time 1.63 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207516 kb
Host smart-f21b4352-c339-43d0-8a81-6389b6c5e138
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084011407 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.usbdev_tx_rx_disruption.1084011407
Directory /workspace/273.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/274.usbdev_tx_rx_disruption.2600908732
Short name T2240
Test name
Test status
Simulation time 481760762 ps
CPU time 1.52 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207608 kb
Host smart-a9d16871-d26a-430e-b257-ee4c501e3dc2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600908732 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.usbdev_tx_rx_disruption.2600908732
Directory /workspace/274.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/275.usbdev_tx_rx_disruption.3881434842
Short name T935
Test name
Test status
Simulation time 543009782 ps
CPU time 1.71 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207568 kb
Host smart-6ab50c9f-4438-4089-82e5-83aedb34db81
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881434842 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.usbdev_tx_rx_disruption.3881434842
Directory /workspace/275.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/276.usbdev_tx_rx_disruption.4243446616
Short name T929
Test name
Test status
Simulation time 638402341 ps
CPU time 1.65 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207508 kb
Host smart-296c31ee-123c-49ce-9c17-27357409074e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243446616 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.usbdev_tx_rx_disruption.4243446616
Directory /workspace/276.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/277.usbdev_tx_rx_disruption.4222194701
Short name T1496
Test name
Test status
Simulation time 554147665 ps
CPU time 1.63 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207504 kb
Host smart-bdb132cc-1f7b-4c39-973f-ec6537850970
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222194701 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.usbdev_tx_rx_disruption.4222194701
Directory /workspace/277.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/278.usbdev_tx_rx_disruption.1074611386
Short name T1897
Test name
Test status
Simulation time 512860212 ps
CPU time 1.62 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207520 kb
Host smart-f1a6ab45-c8ca-404e-896a-d72e86a4ca0e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074611386 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.usbdev_tx_rx_disruption.1074611386
Directory /workspace/278.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/279.usbdev_tx_rx_disruption.3967094489
Short name T2809
Test name
Test status
Simulation time 484581300 ps
CPU time 1.57 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207536 kb
Host smart-b0541424-f3d9-418e-b666-62f26ad1583f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967094489 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.usbdev_tx_rx_disruption.3967094489
Directory /workspace/279.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.2831707209
Short name T1175
Test name
Test status
Simulation time 50707955 ps
CPU time 0.66 seconds
Started Aug 10 07:12:09 PM PDT 24
Finished Aug 10 07:12:09 PM PDT 24
Peak memory 207548 kb
Host smart-4ce3773d-6942-4e77-aaed-5b6718b950c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2831707209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.2831707209
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3943795881
Short name T2817
Test name
Test status
Simulation time 5504132244 ps
CPU time 7.64 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 215992 kb
Host smart-14544d46-22ea-440d-8446-47366a3a189f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943795881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.3943795881
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3936230744
Short name T12
Test name
Test status
Simulation time 21238832202 ps
CPU time 25.27 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:12:21 PM PDT 24
Peak memory 207860 kb
Host smart-383a388d-b113-4861-a8f1-5add2b3d0e51
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936230744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3936230744
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2990376039
Short name T957
Test name
Test status
Simulation time 23579169016 ps
CPU time 33.55 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:12:21 PM PDT 24
Peak memory 216072 kb
Host smart-8edf92ad-dea4-405e-a8b6-5ad95973b02c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990376039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.2990376039
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2528371122
Short name T2915
Test name
Test status
Simulation time 220208987 ps
CPU time 0.93 seconds
Started Aug 10 07:11:48 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207560 kb
Host smart-20018c07-ad92-4449-956a-dea3caf23203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25283
71122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2528371122
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1413809682
Short name T1005
Test name
Test status
Simulation time 156888847 ps
CPU time 0.84 seconds
Started Aug 10 07:11:51 PM PDT 24
Finished Aug 10 07:11:52 PM PDT 24
Peak memory 207444 kb
Host smart-f490397d-ccd5-4bbb-96a3-406f99971a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
09682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1413809682
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.4160395770
Short name T2932
Test name
Test status
Simulation time 239136578 ps
CPU time 1.06 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:51 PM PDT 24
Peak memory 207552 kb
Host smart-d23acf46-fa50-4143-abb5-ee50e09cbabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
95770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.4160395770
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2346347327
Short name T2032
Test name
Test status
Simulation time 961954076 ps
CPU time 2.68 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:53 PM PDT 24
Peak memory 207684 kb
Host smart-3eabd794-99c4-4930-86bf-fe718383f328
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2346347327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2346347327
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.4222336627
Short name T3431
Test name
Test status
Simulation time 35642450562 ps
CPU time 55.11 seconds
Started Aug 10 07:11:52 PM PDT 24
Finished Aug 10 07:12:47 PM PDT 24
Peak memory 207732 kb
Host smart-a162899b-6555-46f4-8d57-3c4ca33c5ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
36627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.4222336627
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.85222573
Short name T2751
Test name
Test status
Simulation time 1573940329 ps
CPU time 36.54 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:12:32 PM PDT 24
Peak memory 207748 kb
Host smart-b9b4d83f-cb74-442d-8cb8-a7d4e83368d0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85222573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.85222573
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.241560488
Short name T3018
Test name
Test status
Simulation time 858737969 ps
CPU time 1.94 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:58 PM PDT 24
Peak memory 207572 kb
Host smart-ca27a519-944f-4ad8-80a4-20b8dbe3948d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24156
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.241560488
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2233042823
Short name T1619
Test name
Test status
Simulation time 143562204 ps
CPU time 0.81 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:49 PM PDT 24
Peak memory 207540 kb
Host smart-96ee2d75-993a-47e6-8b36-f11cd46dbb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
42823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2233042823
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3467522474
Short name T1874
Test name
Test status
Simulation time 50723278 ps
CPU time 0.72 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:51 PM PDT 24
Peak memory 207448 kb
Host smart-2ec6f1a9-222e-4063-a6de-92eb2f369c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34675
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3467522474
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.465907958
Short name T3220
Test name
Test status
Simulation time 823104472 ps
CPU time 2.41 seconds
Started Aug 10 07:11:50 PM PDT 24
Finished Aug 10 07:11:52 PM PDT 24
Peak memory 207736 kb
Host smart-11c7270d-3009-405a-a43d-96e565b7cd41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46590
7958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.465907958
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_types.3637188874
Short name T387
Test name
Test status
Simulation time 465983941 ps
CPU time 1.35 seconds
Started Aug 10 07:11:47 PM PDT 24
Finished Aug 10 07:11:48 PM PDT 24
Peak memory 207488 kb
Host smart-abfae2df-5bdb-49a7-8309-4062ed58c161
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3637188874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.3637188874
Directory /workspace/28.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.353120475
Short name T1393
Test name
Test status
Simulation time 409311743 ps
CPU time 2.79 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:11:52 PM PDT 24
Peak memory 207736 kb
Host smart-47d2c881-94df-4ab2-92af-2b22960938a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35312
0475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.353120475
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.610974456
Short name T3359
Test name
Test status
Simulation time 196385150 ps
CPU time 1.04 seconds
Started Aug 10 07:11:47 PM PDT 24
Finished Aug 10 07:11:48 PM PDT 24
Peak memory 215888 kb
Host smart-76d894a5-7baa-47dd-b9c2-4bd4160d32ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=610974456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.610974456
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.725900201
Short name T1016
Test name
Test status
Simulation time 141620920 ps
CPU time 0.83 seconds
Started Aug 10 07:11:57 PM PDT 24
Finished Aug 10 07:11:58 PM PDT 24
Peak memory 207364 kb
Host smart-1d5fafec-bee6-4361-ab3d-981516b7defc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72590
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.725900201
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1966844475
Short name T1140
Test name
Test status
Simulation time 150732572 ps
CPU time 0.9 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207484 kb
Host smart-dcbc64cb-6e9d-4142-a0c9-f14aaf1dc913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19668
44475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1966844475
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.581235959
Short name T797
Test name
Test status
Simulation time 3198970370 ps
CPU time 89.73 seconds
Started Aug 10 07:11:47 PM PDT 24
Finished Aug 10 07:13:17 PM PDT 24
Peak memory 217620 kb
Host smart-da599335-2468-4f52-b729-ac88b9e005da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=581235959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.581235959
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.1763256586
Short name T1139
Test name
Test status
Simulation time 12723473491 ps
CPU time 147.8 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:14:23 PM PDT 24
Peak memory 207860 kb
Host smart-f9d4fa9f-b7e8-4857-9c7f-f4816802ac7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1763256586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1763256586
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1728301566
Short name T2820
Test name
Test status
Simulation time 161017711 ps
CPU time 0.9 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207608 kb
Host smart-b897b4db-43e1-4615-a201-7bd16eb36f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17283
01566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1728301566
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1881493977
Short name T881
Test name
Test status
Simulation time 13833283569 ps
CPU time 18.3 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:12:14 PM PDT 24
Peak memory 207856 kb
Host smart-3f0c17d6-4c31-4c4a-bad4-7758093ce93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18814
93977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1881493977
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1356029281
Short name T1474
Test name
Test status
Simulation time 9587071604 ps
CPU time 11.77 seconds
Started Aug 10 07:11:58 PM PDT 24
Finished Aug 10 07:12:10 PM PDT 24
Peak memory 207804 kb
Host smart-882f243b-e381-46a7-a704-3dc160557b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
29281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1356029281
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2962088984
Short name T1046
Test name
Test status
Simulation time 4182780876 ps
CPU time 41.74 seconds
Started Aug 10 07:11:54 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 219448 kb
Host smart-b8d35384-4749-4d6d-9783-554453b1a8d2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2962088984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2962088984
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1620537995
Short name T1871
Test name
Test status
Simulation time 2792559956 ps
CPU time 27.49 seconds
Started Aug 10 07:11:57 PM PDT 24
Finished Aug 10 07:12:24 PM PDT 24
Peak memory 217780 kb
Host smart-b194a089-6217-4d8e-bbc3-e8865cb93e34
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1620537995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1620537995
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2502099112
Short name T2761
Test name
Test status
Simulation time 246616672 ps
CPU time 1.01 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207596 kb
Host smart-9f731fc5-5a07-4ebf-af68-416c54de4bf6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2502099112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2502099112
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.192175658
Short name T2213
Test name
Test status
Simulation time 214050878 ps
CPU time 1 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207424 kb
Host smart-4fd1f3ba-a59d-4c15-a664-ae92eb32e251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.192175658
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2521796009
Short name T883
Test name
Test status
Simulation time 2574330319 ps
CPU time 70.75 seconds
Started Aug 10 07:11:57 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 217440 kb
Host smart-e44121ca-8ec3-4e82-bf41-926c5917b683
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2521796009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2521796009
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.156107351
Short name T2536
Test name
Test status
Simulation time 172594512 ps
CPU time 0.87 seconds
Started Aug 10 07:11:58 PM PDT 24
Finished Aug 10 07:11:59 PM PDT 24
Peak memory 207600 kb
Host smart-7d9b42b8-4638-4201-8365-a41182528fb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=156107351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.156107351
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.824730167
Short name T1332
Test name
Test status
Simulation time 148343399 ps
CPU time 0.82 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207580 kb
Host smart-cab38167-4645-4c5a-bc84-1db5c7400566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82473
0167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.824730167
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.153073916
Short name T3463
Test name
Test status
Simulation time 211038784 ps
CPU time 0.93 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207532 kb
Host smart-e9b68361-24cf-485c-9c38-5db914d36d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307
3916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.153073916
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2852779582
Short name T901
Test name
Test status
Simulation time 157950011 ps
CPU time 0.85 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207588 kb
Host smart-55f7619b-ba4e-40ff-a924-e7b94ae1a3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
79582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2852779582
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3439159932
Short name T3122
Test name
Test status
Simulation time 173805239 ps
CPU time 0.86 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207520 kb
Host smart-952c7619-4de7-4591-b0a3-aa5f405fbc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34391
59932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3439159932
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3791404369
Short name T192
Test name
Test status
Simulation time 163693596 ps
CPU time 0.87 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207540 kb
Host smart-32e39966-0f4f-4110-a274-8c9bb5727138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
04369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3791404369
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2641783614
Short name T3284
Test name
Test status
Simulation time 249658694 ps
CPU time 1.1 seconds
Started Aug 10 07:11:58 PM PDT 24
Finished Aug 10 07:11:59 PM PDT 24
Peak memory 207556 kb
Host smart-0d067ba5-db48-4112-a124-2f6883c13954
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2641783614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2641783614
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3758936017
Short name T919
Test name
Test status
Simulation time 144035854 ps
CPU time 0.85 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207516 kb
Host smart-a4d765e7-7002-4cdc-b7a7-abeebe74ceca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
36017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3758936017
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2758245000
Short name T43
Test name
Test status
Simulation time 41091664 ps
CPU time 0.69 seconds
Started Aug 10 07:11:57 PM PDT 24
Finished Aug 10 07:11:58 PM PDT 24
Peak memory 207368 kb
Host smart-b9386bcb-ed95-49b6-86a8-0120e3c7e412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
45000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2758245000
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4020993534
Short name T2076
Test name
Test status
Simulation time 13298195504 ps
CPU time 36.22 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:12:32 PM PDT 24
Peak memory 216052 kb
Host smart-e38223db-005d-4b6d-9102-6677ce7e3cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40209
93534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4020993534
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.424670622
Short name T2427
Test name
Test status
Simulation time 161250815 ps
CPU time 0.86 seconds
Started Aug 10 07:11:59 PM PDT 24
Finished Aug 10 07:12:00 PM PDT 24
Peak memory 207608 kb
Host smart-54f9358f-06a6-497d-8e87-12a732cef287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
0622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.424670622
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2630178461
Short name T1014
Test name
Test status
Simulation time 215020118 ps
CPU time 0.91 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207644 kb
Host smart-3be0652c-19c4-426c-9c7b-73203c9f3b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
78461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2630178461
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.972570126
Short name T989
Test name
Test status
Simulation time 189526431 ps
CPU time 0.88 seconds
Started Aug 10 07:12:00 PM PDT 24
Finished Aug 10 07:12:01 PM PDT 24
Peak memory 207604 kb
Host smart-95459ec2-f7de-41da-a5a7-29b86cb9baec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97257
0126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.972570126
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3108677151
Short name T2060
Test name
Test status
Simulation time 150455691 ps
CPU time 0.82 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207444 kb
Host smart-c570dff1-1f75-4e1b-a8f7-7d76bf38b17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
77151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3108677151
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3635359376
Short name T1435
Test name
Test status
Simulation time 162294656 ps
CPU time 0.86 seconds
Started Aug 10 07:11:54 PM PDT 24
Finished Aug 10 07:11:55 PM PDT 24
Peak memory 207596 kb
Host smart-03265726-6740-4536-8f4d-f78340fda536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
59376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3635359376
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_rx_full.2665921749
Short name T2297
Test name
Test status
Simulation time 317597922 ps
CPU time 1.23 seconds
Started Aug 10 07:12:00 PM PDT 24
Finished Aug 10 07:12:01 PM PDT 24
Peak memory 207552 kb
Host smart-54536b67-0380-4b9a-8520-bc719449d77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
21749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2665921749
Directory /workspace/28.usbdev_rx_full/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2038206642
Short name T3318
Test name
Test status
Simulation time 156645869 ps
CPU time 0.83 seconds
Started Aug 10 07:11:56 PM PDT 24
Finished Aug 10 07:11:57 PM PDT 24
Peak memory 207712 kb
Host smart-bd2e878f-52c0-4191-825a-b61f14f434f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382
06642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2038206642
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4175452502
Short name T2192
Test name
Test status
Simulation time 199168120 ps
CPU time 0.91 seconds
Started Aug 10 07:11:55 PM PDT 24
Finished Aug 10 07:11:56 PM PDT 24
Peak memory 207532 kb
Host smart-ebac3477-5e64-466d-a7f1-b451b412984c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41754
52502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4175452502
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2026598476
Short name T3274
Test name
Test status
Simulation time 261252127 ps
CPU time 1.02 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:05 PM PDT 24
Peak memory 207532 kb
Host smart-df25cdd6-bff1-49b3-a22b-42c618e79c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20265
98476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2026598476
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1791704212
Short name T1668
Test name
Test status
Simulation time 3289596085 ps
CPU time 94.55 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:13:38 PM PDT 24
Peak memory 217904 kb
Host smart-f8eec828-0171-4deb-9007-44f815a57960
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1791704212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1791704212
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1220975430
Short name T810
Test name
Test status
Simulation time 189507489 ps
CPU time 0.88 seconds
Started Aug 10 07:12:07 PM PDT 24
Finished Aug 10 07:12:08 PM PDT 24
Peak memory 207548 kb
Host smart-6ee1cc31-f2c4-49d9-8a7a-4fad4860f585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
75430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1220975430
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2808541718
Short name T689
Test name
Test status
Simulation time 145242739 ps
CPU time 0.82 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:05 PM PDT 24
Peak memory 207556 kb
Host smart-e67d48f9-e81d-4c40-aa7c-f90dbdd495af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
41718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2808541718
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.3689998968
Short name T2303
Test name
Test status
Simulation time 799406435 ps
CPU time 2.17 seconds
Started Aug 10 07:12:07 PM PDT 24
Finished Aug 10 07:12:09 PM PDT 24
Peak memory 207512 kb
Host smart-7516fda9-e641-4de5-8db6-4a4e865c2aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899
98968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.3689998968
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2047554746
Short name T592
Test name
Test status
Simulation time 1720991320 ps
CPU time 13.39 seconds
Started Aug 10 07:12:05 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207744 kb
Host smart-b28fa4d9-0f85-4e1d-96aa-f8ffa27891a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
54746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2047554746
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.3591881849
Short name T920
Test name
Test status
Simulation time 869682214 ps
CPU time 18.91 seconds
Started Aug 10 07:11:49 PM PDT 24
Finished Aug 10 07:12:08 PM PDT 24
Peak memory 207640 kb
Host smart-809962eb-5bdc-4c16-9f73-6acf00c58395
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591881849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.3591881849
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_tx_rx_disruption.3442286882
Short name T2260
Test name
Test status
Simulation time 629080818 ps
CPU time 1.65 seconds
Started Aug 10 07:12:05 PM PDT 24
Finished Aug 10 07:12:06 PM PDT 24
Peak memory 207456 kb
Host smart-1d27806c-04dc-47d4-8ea8-e0be7bb7d77e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442286882 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.usbdev_tx_rx_disruption.3442286882
Directory /workspace/28.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/280.usbdev_tx_rx_disruption.893337113
Short name T1450
Test name
Test status
Simulation time 532673493 ps
CPU time 1.61 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207560 kb
Host smart-56ce4d96-06de-45b0-8644-992de6492fb9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893337113 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 280.usbdev_tx_rx_disruption.893337113
Directory /workspace/280.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/281.usbdev_tx_rx_disruption.3569728146
Short name T3536
Test name
Test status
Simulation time 579804698 ps
CPU time 1.58 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207520 kb
Host smart-815fa71b-60b8-409a-ba5c-a7767ab68f8c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569728146 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.usbdev_tx_rx_disruption.3569728146
Directory /workspace/281.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/282.usbdev_tx_rx_disruption.327647576
Short name T3245
Test name
Test status
Simulation time 469406537 ps
CPU time 1.52 seconds
Started Aug 10 07:18:03 PM PDT 24
Finished Aug 10 07:18:05 PM PDT 24
Peak memory 207572 kb
Host smart-6dec5ce5-3530-46f2-9ac5-9f8e437ea312
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327647576 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 282.usbdev_tx_rx_disruption.327647576
Directory /workspace/282.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/283.usbdev_tx_rx_disruption.2352004145
Short name T203
Test name
Test status
Simulation time 577634482 ps
CPU time 1.61 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207520 kb
Host smart-3e9360a7-c249-422f-907c-cbf63b2d364f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352004145 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.usbdev_tx_rx_disruption.2352004145
Directory /workspace/283.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/284.usbdev_tx_rx_disruption.868673780
Short name T1158
Test name
Test status
Simulation time 543560706 ps
CPU time 1.73 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207528 kb
Host smart-e9de3f4a-a28c-4b9f-8af8-4e031655b537
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868673780 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 284.usbdev_tx_rx_disruption.868673780
Directory /workspace/284.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/285.usbdev_tx_rx_disruption.1829378344
Short name T2520
Test name
Test status
Simulation time 460668986 ps
CPU time 1.4 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207476 kb
Host smart-d757f827-cb4a-408d-b2b6-f8f60cda165f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829378344 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.usbdev_tx_rx_disruption.1829378344
Directory /workspace/285.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/286.usbdev_tx_rx_disruption.427693638
Short name T3584
Test name
Test status
Simulation time 535093250 ps
CPU time 1.55 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207528 kb
Host smart-01123997-4775-419f-8256-acd56f81f615
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427693638 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.usbdev_tx_rx_disruption.427693638
Directory /workspace/286.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/287.usbdev_tx_rx_disruption.3995646485
Short name T1930
Test name
Test status
Simulation time 515916907 ps
CPU time 1.53 seconds
Started Aug 10 07:18:02 PM PDT 24
Finished Aug 10 07:18:04 PM PDT 24
Peak memory 207572 kb
Host smart-eecf8e8f-1223-42c4-94be-89fc01ca3ca5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995646485 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.usbdev_tx_rx_disruption.3995646485
Directory /workspace/287.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/288.usbdev_tx_rx_disruption.230839027
Short name T3107
Test name
Test status
Simulation time 665708087 ps
CPU time 1.72 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207552 kb
Host smart-0dd2d83d-a832-4ce3-8fee-b583502ebe21
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230839027 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 288.usbdev_tx_rx_disruption.230839027
Directory /workspace/288.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/289.usbdev_tx_rx_disruption.3200503218
Short name T882
Test name
Test status
Simulation time 478113188 ps
CPU time 1.41 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207508 kb
Host smart-50813b11-1cb6-4029-9652-52602e25349e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200503218 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.usbdev_tx_rx_disruption.3200503218
Directory /workspace/289.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.307150703
Short name T3450
Test name
Test status
Simulation time 56050288 ps
CPU time 0.7 seconds
Started Aug 10 07:12:27 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207440 kb
Host smart-aaa6a41c-4dec-4ac8-9cb4-133f9fa9d046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=307150703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.307150703
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1445607686
Short name T15
Test name
Test status
Simulation time 4486893917 ps
CPU time 6.22 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:10 PM PDT 24
Peak memory 216036 kb
Host smart-2efc8f57-fd90-470b-8bb5-ed695bfd7d8e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445607686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1445607686
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3088280987
Short name T3104
Test name
Test status
Simulation time 15806087501 ps
CPU time 20.1 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:24 PM PDT 24
Peak memory 216000 kb
Host smart-1eedc1d4-c15a-482d-b3b0-5dbfcc77c984
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088280987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3088280987
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1915911483
Short name T1558
Test name
Test status
Simulation time 29017547917 ps
CPU time 35.28 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207828 kb
Host smart-a6286ea7-b2ed-44a6-bd47-fed69758b072
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915911483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.1915911483
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2774639944
Short name T3475
Test name
Test status
Simulation time 181306999 ps
CPU time 0.93 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:05 PM PDT 24
Peak memory 207508 kb
Host smart-71d085ab-03bb-46c0-b0ef-43055a73c14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27746
39944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2774639944
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1738809671
Short name T750
Test name
Test status
Simulation time 149216958 ps
CPU time 0.84 seconds
Started Aug 10 07:12:06 PM PDT 24
Finished Aug 10 07:12:06 PM PDT 24
Peak memory 207464 kb
Host smart-2c21809c-78f1-49e7-ad76-ff9c2257ce4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17388
09671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1738809671
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.773431018
Short name T1870
Test name
Test status
Simulation time 207544084 ps
CPU time 0.99 seconds
Started Aug 10 07:12:05 PM PDT 24
Finished Aug 10 07:12:06 PM PDT 24
Peak memory 207412 kb
Host smart-0a9cc8ba-4cd3-4a2b-abe6-c0bf4fccab20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77343
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.773431018
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.735257415
Short name T2771
Test name
Test status
Simulation time 1110334129 ps
CPU time 2.68 seconds
Started Aug 10 07:12:07 PM PDT 24
Finished Aug 10 07:12:10 PM PDT 24
Peak memory 207764 kb
Host smart-cca57806-a546-4a2e-8fd4-720859461e3a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=735257415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.735257415
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1718579171
Short name T537
Test name
Test status
Simulation time 42956092500 ps
CPU time 66.76 seconds
Started Aug 10 07:12:05 PM PDT 24
Finished Aug 10 07:13:12 PM PDT 24
Peak memory 207852 kb
Host smart-c9fd1e96-bb51-4e43-b2ba-368cff95ea5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17185
79171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1718579171
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.3326323981
Short name T1904
Test name
Test status
Simulation time 2480023318 ps
CPU time 21.5 seconds
Started Aug 10 07:12:05 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207772 kb
Host smart-a5d2bd0e-793d-415f-b004-e1324e1f06a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326323981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.3326323981
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.2401207566
Short name T2882
Test name
Test status
Simulation time 813550304 ps
CPU time 1.86 seconds
Started Aug 10 07:12:06 PM PDT 24
Finished Aug 10 07:12:07 PM PDT 24
Peak memory 207440 kb
Host smart-2cd360f7-25a5-4f2e-9485-f7ebff4c7784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24012
07566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.2401207566
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2983369084
Short name T2323
Test name
Test status
Simulation time 138571907 ps
CPU time 0.8 seconds
Started Aug 10 07:12:06 PM PDT 24
Finished Aug 10 07:12:07 PM PDT 24
Peak memory 207564 kb
Host smart-ff33f406-9750-4cc1-93c8-02bd6b61859d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29833
69084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2983369084
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1928318509
Short name T2735
Test name
Test status
Simulation time 85413790 ps
CPU time 0.75 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207360 kb
Host smart-a9bad7a9-688e-4387-b60f-58e0b1f4d85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19283
18509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1928318509
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1509725261
Short name T3088
Test name
Test status
Simulation time 957833937 ps
CPU time 2.49 seconds
Started Aug 10 07:12:17 PM PDT 24
Finished Aug 10 07:12:20 PM PDT 24
Peak memory 207800 kb
Host smart-017c3c47-3720-4391-973a-57dd5600da09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15097
25261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1509725261
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2862776136
Short name T1961
Test name
Test status
Simulation time 274736995 ps
CPU time 1.84 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207908 kb
Host smart-66a98b17-cea0-49ad-9319-1c8026cf724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
76136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2862776136
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3681538323
Short name T2160
Test name
Test status
Simulation time 155414753 ps
CPU time 0.84 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207556 kb
Host smart-9addfaba-a7a4-4981-b856-5beac21487aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3681538323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3681538323
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.4061341437
Short name T666
Test name
Test status
Simulation time 140919771 ps
CPU time 0.82 seconds
Started Aug 10 07:12:14 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 207508 kb
Host smart-afff5098-657f-40f7-9ffa-30a9a1cc3330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40613
41437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.4061341437
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3314562811
Short name T2778
Test name
Test status
Simulation time 188678960 ps
CPU time 0.91 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207548 kb
Host smart-dfbc76fe-543d-4b04-9ec4-7238a1c611af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
62811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3314562811
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.1652795234
Short name T2332
Test name
Test status
Simulation time 3043003861 ps
CPU time 84.62 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 218516 kb
Host smart-1cf34c41-9a65-49b9-b78d-a1a377c13467
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1652795234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.1652795234
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1503208608
Short name T1714
Test name
Test status
Simulation time 11440528512 ps
CPU time 74.4 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:13:30 PM PDT 24
Peak memory 207860 kb
Host smart-92cda4ff-e1db-42c5-b103-cab81d33c623
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1503208608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1503208608
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.225168491
Short name T1707
Test name
Test status
Simulation time 210158952 ps
CPU time 0.95 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207456 kb
Host smart-a5cb0e25-70d2-4b7e-8902-15bef8ac6561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22516
8491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.225168491
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.4134718638
Short name T2145
Test name
Test status
Simulation time 32214843351 ps
CPU time 48.34 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:13:05 PM PDT 24
Peak memory 207872 kb
Host smart-f475f9a3-ce36-4273-ab2c-336d3bbd2338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41347
18638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.4134718638
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4006194719
Short name T3361
Test name
Test status
Simulation time 8327679582 ps
CPU time 10.54 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207868 kb
Host smart-90fdcb0f-5cd9-40bd-b2ed-8b51bd7db5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
94719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4006194719
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.3148226224
Short name T1940
Test name
Test status
Simulation time 4466332693 ps
CPU time 45.94 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 218836 kb
Host smart-68b59f04-e28d-4d3c-8171-8cfb179d764a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3148226224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.3148226224
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.757331474
Short name T1333
Test name
Test status
Simulation time 2338994916 ps
CPU time 62.9 seconds
Started Aug 10 07:12:19 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 217476 kb
Host smart-1f0cf64e-db4d-44c5-973a-031e23e53133
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=757331474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.757331474
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.4086000374
Short name T3168
Test name
Test status
Simulation time 270199281 ps
CPU time 1.02 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207544 kb
Host smart-78938553-066d-49b0-abb5-b348f97d5a97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4086000374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.4086000374
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.909653006
Short name T653
Test name
Test status
Simulation time 191039934 ps
CPU time 0.94 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207512 kb
Host smart-1f1fc82a-7d9c-4179-96a0-f322bb306fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90965
3006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.909653006
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1537917179
Short name T2976
Test name
Test status
Simulation time 1708470384 ps
CPU time 17.07 seconds
Started Aug 10 07:12:19 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 224124 kb
Host smart-6a1f220d-ed37-4b63-a4fe-7990caba9ca6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1537917179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1537917179
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1581308879
Short name T3558
Test name
Test status
Simulation time 171917767 ps
CPU time 0.87 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207560 kb
Host smart-1e6f4666-f8cf-47bd-b6fd-0d69b8c2ac20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1581308879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1581308879
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1405824935
Short name T2787
Test name
Test status
Simulation time 152317552 ps
CPU time 0.83 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207528 kb
Host smart-6d94553f-d340-4390-9a10-0adf3eb757a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
24935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1405824935
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.794334703
Short name T1031
Test name
Test status
Simulation time 255082413 ps
CPU time 1 seconds
Started Aug 10 07:12:17 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207528 kb
Host smart-500e58be-a892-4f43-a292-ecc0a0ce0f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79433
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.794334703
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3630243925
Short name T2582
Test name
Test status
Simulation time 165824215 ps
CPU time 0.83 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207552 kb
Host smart-240b710c-97e1-45e6-8881-87134095b55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36302
43925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3630243925
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1211794333
Short name T2975
Test name
Test status
Simulation time 175047358 ps
CPU time 0.89 seconds
Started Aug 10 07:12:14 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 207420 kb
Host smart-d81529f4-d87e-4a9d-8a24-ad0dcc647af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
94333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1211794333
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.4042783422
Short name T1516
Test name
Test status
Simulation time 160432856 ps
CPU time 0.84 seconds
Started Aug 10 07:12:14 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 207556 kb
Host smart-11781488-17cd-4d8a-9718-bdccefb3603f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40427
83422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.4042783422
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2612121710
Short name T1070
Test name
Test status
Simulation time 204958726 ps
CPU time 0.99 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207576 kb
Host smart-8b37fa13-1755-49db-9859-9b0b2d148336
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2612121710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2612121710
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1103127082
Short name T1116
Test name
Test status
Simulation time 163683208 ps
CPU time 0.84 seconds
Started Aug 10 07:12:14 PM PDT 24
Finished Aug 10 07:12:15 PM PDT 24
Peak memory 207464 kb
Host smart-78b2d714-a7eb-4af4-9454-48dfabbc71d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
27082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1103127082
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.474738736
Short name T1878
Test name
Test status
Simulation time 92044807 ps
CPU time 0.73 seconds
Started Aug 10 07:12:19 PM PDT 24
Finished Aug 10 07:12:20 PM PDT 24
Peak memory 207516 kb
Host smart-90ba2059-814d-4b78-9f1d-12540ea15c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47473
8736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.474738736
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1418567740
Short name T1717
Test name
Test status
Simulation time 12860529096 ps
CPU time 35.19 seconds
Started Aug 10 07:12:19 PM PDT 24
Finished Aug 10 07:12:54 PM PDT 24
Peak memory 220096 kb
Host smart-1773c6b1-348c-4424-b5f3-96d0559aba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
67740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1418567740
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2765095154
Short name T3464
Test name
Test status
Simulation time 162282976 ps
CPU time 0.84 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207580 kb
Host smart-a420a4f1-2ebf-4a61-aa62-cae6f16d8e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
95154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2765095154
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1226734639
Short name T627
Test name
Test status
Simulation time 239284134 ps
CPU time 0.96 seconds
Started Aug 10 07:12:15 PM PDT 24
Finished Aug 10 07:12:16 PM PDT 24
Peak memory 207512 kb
Host smart-d44a5acd-9701-486e-9cf3-0e7914be4568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12267
34639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1226734639
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1613109357
Short name T691
Test name
Test status
Simulation time 224405771 ps
CPU time 0.96 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207508 kb
Host smart-cd34ef5a-15b0-44c5-8080-b34db9a092b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
09357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1613109357
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.4267160906
Short name T1660
Test name
Test status
Simulation time 207814930 ps
CPU time 0.92 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207508 kb
Host smart-7185be05-5a1e-4832-a99e-1725b8d4c8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42671
60906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.4267160906
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_full.11712652
Short name T3153
Test name
Test status
Simulation time 328165344 ps
CPU time 1.19 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207572 kb
Host smart-ae87c598-c574-4cbc-bf80-9470db30edb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11712
652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.11712652
Directory /workspace/29.usbdev_rx_full/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2926061815
Short name T794
Test name
Test status
Simulation time 144584792 ps
CPU time 0.84 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207504 kb
Host smart-719f7262-fd1d-4427-ad61-5be95a91744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
61815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2926061815
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2588538629
Short name T1689
Test name
Test status
Simulation time 151523662 ps
CPU time 0.86 seconds
Started Aug 10 07:12:17 PM PDT 24
Finished Aug 10 07:12:18 PM PDT 24
Peak memory 207572 kb
Host smart-ccb1b302-37a4-46bd-a048-fae55a48ecb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
38629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2588538629
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1908522799
Short name T2273
Test name
Test status
Simulation time 227572865 ps
CPU time 1.01 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:12:17 PM PDT 24
Peak memory 207644 kb
Host smart-bd176605-437f-4d68-ba2b-53abacd67681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19085
22799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1908522799
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2712150104
Short name T2729
Test name
Test status
Simulation time 3048105710 ps
CPU time 23.84 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:42 PM PDT 24
Peak memory 218112 kb
Host smart-ef6645ca-9f9a-44b7-ac87-22d14427abda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2712150104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2712150104
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1788956782
Short name T3238
Test name
Test status
Simulation time 175848223 ps
CPU time 0.92 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207572 kb
Host smart-8dd62e02-6823-4dbd-a31f-591c4dec79e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17889
56782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1788956782
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2369517122
Short name T1799
Test name
Test status
Simulation time 160813927 ps
CPU time 0.88 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207508 kb
Host smart-44f77830-adb3-4b3c-8af9-9293b722d723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23695
17122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2369517122
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.2508339058
Short name T1169
Test name
Test status
Simulation time 199414737 ps
CPU time 0.95 seconds
Started Aug 10 07:12:18 PM PDT 24
Finished Aug 10 07:12:19 PM PDT 24
Peak memory 207368 kb
Host smart-a4d8f2ff-608f-4866-96e9-ec03367e17b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083
39058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.2508339058
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1877517673
Short name T1457
Test name
Test status
Simulation time 2400476453 ps
CPU time 67.32 seconds
Started Aug 10 07:12:16 PM PDT 24
Finished Aug 10 07:13:24 PM PDT 24
Peak memory 216028 kb
Host smart-e6096333-78d2-4dc0-8679-18a1b1502858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18775
17673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1877517673
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.299863046
Short name T1369
Test name
Test status
Simulation time 2938314267 ps
CPU time 19.42 seconds
Started Aug 10 07:12:04 PM PDT 24
Finished Aug 10 07:12:24 PM PDT 24
Peak memory 207896 kb
Host smart-f60006d8-0a96-4b8d-a206-b24d9c28d377
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299863046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_host
_handshake.299863046
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_tx_rx_disruption.1956115318
Short name T174
Test name
Test status
Simulation time 479347112 ps
CPU time 1.64 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207536 kb
Host smart-9dfdd1b6-0bb0-4f68-8453-a75aab2cea9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956115318 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.usbdev_tx_rx_disruption.1956115318
Directory /workspace/29.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/290.usbdev_tx_rx_disruption.4012777039
Short name T1357
Test name
Test status
Simulation time 588381362 ps
CPU time 1.6 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207420 kb
Host smart-82cbcd00-9804-4aae-9b70-63034b3f4478
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012777039 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.usbdev_tx_rx_disruption.4012777039
Directory /workspace/290.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/291.usbdev_tx_rx_disruption.4189840912
Short name T1451
Test name
Test status
Simulation time 666291146 ps
CPU time 1.92 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207528 kb
Host smart-9fa2ea9d-2b9e-4fbe-af2e-888d8781cbe4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189840912 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.usbdev_tx_rx_disruption.4189840912
Directory /workspace/291.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/292.usbdev_tx_rx_disruption.2166971172
Short name T3360
Test name
Test status
Simulation time 500862531 ps
CPU time 1.51 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207584 kb
Host smart-ddd19b68-5493-43bc-ac86-a974ad736bd9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166971172 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.usbdev_tx_rx_disruption.2166971172
Directory /workspace/292.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/293.usbdev_tx_rx_disruption.1391197852
Short name T215
Test name
Test status
Simulation time 634334438 ps
CPU time 1.94 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207572 kb
Host smart-b804eb07-d90a-4f38-aeca-5a362fdf888f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391197852 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.usbdev_tx_rx_disruption.1391197852
Directory /workspace/293.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/294.usbdev_tx_rx_disruption.1249127247
Short name T1097
Test name
Test status
Simulation time 514427835 ps
CPU time 1.67 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207528 kb
Host smart-8b00b036-8dd3-4744-911d-fd00476e2d3f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249127247 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.usbdev_tx_rx_disruption.1249127247
Directory /workspace/294.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/295.usbdev_tx_rx_disruption.3657683540
Short name T2454
Test name
Test status
Simulation time 488037929 ps
CPU time 1.45 seconds
Started Aug 10 07:18:08 PM PDT 24
Finished Aug 10 07:18:10 PM PDT 24
Peak memory 207420 kb
Host smart-c25b0183-1ec6-43d3-9b7d-0b3dd3677e21
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657683540 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.usbdev_tx_rx_disruption.3657683540
Directory /workspace/295.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/296.usbdev_tx_rx_disruption.1950008912
Short name T1148
Test name
Test status
Simulation time 467339407 ps
CPU time 1.5 seconds
Started Aug 10 07:18:09 PM PDT 24
Finished Aug 10 07:18:10 PM PDT 24
Peak memory 207420 kb
Host smart-003ed8a2-23be-4d8d-82ca-bf9297865eea
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950008912 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.usbdev_tx_rx_disruption.1950008912
Directory /workspace/296.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/297.usbdev_tx_rx_disruption.880705802
Short name T1209
Test name
Test status
Simulation time 537719099 ps
CPU time 1.57 seconds
Started Aug 10 07:18:09 PM PDT 24
Finished Aug 10 07:18:11 PM PDT 24
Peak memory 207420 kb
Host smart-e670a6ef-ea44-4995-9a03-a9564017b808
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880705802 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 297.usbdev_tx_rx_disruption.880705802
Directory /workspace/297.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/298.usbdev_tx_rx_disruption.2217304305
Short name T1310
Test name
Test status
Simulation time 565421257 ps
CPU time 1.64 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207420 kb
Host smart-2dca06d1-e777-4cc9-9709-1ab58a2a9f5f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217304305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.usbdev_tx_rx_disruption.2217304305
Directory /workspace/298.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/299.usbdev_tx_rx_disruption.770492660
Short name T35
Test name
Test status
Simulation time 587736446 ps
CPU time 1.61 seconds
Started Aug 10 07:18:11 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207604 kb
Host smart-0428caa4-8235-4b02-b806-cdc7f5c3ccaf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770492660 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 299.usbdev_tx_rx_disruption.770492660
Directory /workspace/299.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2999025694
Short name T1086
Test name
Test status
Simulation time 39387134 ps
CPU time 0.69 seconds
Started Aug 10 07:02:12 PM PDT 24
Finished Aug 10 07:02:12 PM PDT 24
Peak memory 207500 kb
Host smart-583ae4f7-0761-44c2-9048-1d300d64d929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2999025694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2999025694
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1380133489
Short name T3089
Test name
Test status
Simulation time 9763381907 ps
CPU time 12.83 seconds
Started Aug 10 07:01:26 PM PDT 24
Finished Aug 10 07:01:39 PM PDT 24
Peak memory 207800 kb
Host smart-d58ccbee-90d1-467a-88ad-bcd0d40267c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380133489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.1380133489
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.548783884
Short name T3110
Test name
Test status
Simulation time 20540570366 ps
CPU time 23.52 seconds
Started Aug 10 07:01:24 PM PDT 24
Finished Aug 10 07:01:48 PM PDT 24
Peak memory 207804 kb
Host smart-4db6da69-e96a-45b1-97b1-7de280eef83a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=548783884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.548783884
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2333541133
Short name T2097
Test name
Test status
Simulation time 30329810481 ps
CPU time 33.76 seconds
Started Aug 10 07:01:24 PM PDT 24
Finished Aug 10 07:01:58 PM PDT 24
Peak memory 207836 kb
Host smart-c7c5a315-9be7-4258-bb40-260ab985f05d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333541133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.2333541133
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4292778258
Short name T2899
Test name
Test status
Simulation time 157351053 ps
CPU time 0.87 seconds
Started Aug 10 07:01:23 PM PDT 24
Finished Aug 10 07:01:24 PM PDT 24
Peak memory 207564 kb
Host smart-52b587ae-3de5-4369-89dd-674ea0a71377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
78258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4292778258
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.416823736
Short name T3595
Test name
Test status
Simulation time 138499064 ps
CPU time 0.85 seconds
Started Aug 10 07:01:25 PM PDT 24
Finished Aug 10 07:01:26 PM PDT 24
Peak memory 207512 kb
Host smart-c3aed074-abe5-44a2-be12-595d2ae3367f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41682
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.416823736
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2581130527
Short name T1970
Test name
Test status
Simulation time 145672155 ps
CPU time 0.85 seconds
Started Aug 10 07:01:26 PM PDT 24
Finished Aug 10 07:01:27 PM PDT 24
Peak memory 207580 kb
Host smart-1a32eed3-af86-4ee4-8537-6acf9bffa0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25811
30527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2581130527
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4109958323
Short name T2931
Test name
Test status
Simulation time 199371003 ps
CPU time 0.99 seconds
Started Aug 10 07:01:33 PM PDT 24
Finished Aug 10 07:01:35 PM PDT 24
Peak memory 207652 kb
Host smart-e1f6e79e-12ab-45bd-9172-dcdb018abe7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41099
58323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4109958323
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.28870488
Short name T1802
Test name
Test status
Simulation time 449898331 ps
CPU time 1.34 seconds
Started Aug 10 07:01:33 PM PDT 24
Finished Aug 10 07:01:35 PM PDT 24
Peak memory 207520 kb
Host smart-c2686418-2025-4dd2-ba83-7b50944e73cf
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=28870488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.28870488
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1090865901
Short name T2251
Test name
Test status
Simulation time 36565520016 ps
CPU time 55.6 seconds
Started Aug 10 07:01:34 PM PDT 24
Finished Aug 10 07:02:30 PM PDT 24
Peak memory 207880 kb
Host smart-61804f5a-036f-4bc8-9661-481ffa9d4066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10908
65901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1090865901
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2293006762
Short name T1494
Test name
Test status
Simulation time 434731335 ps
CPU time 8.04 seconds
Started Aug 10 07:01:34 PM PDT 24
Finished Aug 10 07:01:43 PM PDT 24
Peak memory 207628 kb
Host smart-6d4a3f84-43c9-419b-8960-dd37f518b5ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293006762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2293006762
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2975137903
Short name T2470
Test name
Test status
Simulation time 631085458 ps
CPU time 1.59 seconds
Started Aug 10 07:01:35 PM PDT 24
Finished Aug 10 07:01:36 PM PDT 24
Peak memory 207532 kb
Host smart-07f8465c-9fe3-4b68-ab3b-7fa90f730892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29751
37903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2975137903
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3741648729
Short name T1421
Test name
Test status
Simulation time 147544026 ps
CPU time 0.82 seconds
Started Aug 10 07:01:37 PM PDT 24
Finished Aug 10 07:01:38 PM PDT 24
Peak memory 207572 kb
Host smart-cd3c0358-eafe-4b68-b5e3-e32fb2222b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
48729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3741648729
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.848082580
Short name T1065
Test name
Test status
Simulation time 33770294 ps
CPU time 0.71 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:01:44 PM PDT 24
Peak memory 207608 kb
Host smart-dd98b31c-44f9-4570-a6e3-057c202cffa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84808
2580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.848082580
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.777064602
Short name T2655
Test name
Test status
Simulation time 1003195187 ps
CPU time 2.41 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:01:45 PM PDT 24
Peak memory 207800 kb
Host smart-406c2fc5-3b0a-4104-851d-6c6f9597172d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77706
4602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.777064602
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_types.26510302
Short name T493
Test name
Test status
Simulation time 430400573 ps
CPU time 1.39 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:01:44 PM PDT 24
Peak memory 207472 kb
Host smart-fab57a8e-a918-44bd-9904-ea15df80edd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=26510302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.26510302
Directory /workspace/3.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.56361339
Short name T2455
Test name
Test status
Simulation time 191113100 ps
CPU time 2.28 seconds
Started Aug 10 07:01:44 PM PDT 24
Finished Aug 10 07:01:47 PM PDT 24
Peak memory 207564 kb
Host smart-acf16d35-b3f8-4127-a732-7ab8305d84a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56361
339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.56361339
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3528625551
Short name T2354
Test name
Test status
Simulation time 81187550659 ps
CPU time 146.89 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:04:10 PM PDT 24
Peak memory 207832 kb
Host smart-a621eafc-56b6-4924-a1d4-8493d664f9ec
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3528625551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3528625551
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3593616006
Short name T2790
Test name
Test status
Simulation time 95121374308 ps
CPU time 141.3 seconds
Started Aug 10 07:01:44 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 207808 kb
Host smart-2c33bf49-3ab2-489d-a9dd-86629780c1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593616006 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3593616006
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.206904756
Short name T366
Test name
Test status
Simulation time 85130710011 ps
CPU time 132.41 seconds
Started Aug 10 07:01:42 PM PDT 24
Finished Aug 10 07:03:54 PM PDT 24
Peak memory 207728 kb
Host smart-afe22793-39c0-4101-aa5f-d1f85c43dd75
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=206904756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.206904756
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2778373237
Short name T3087
Test name
Test status
Simulation time 100168761541 ps
CPU time 164.51 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:04:28 PM PDT 24
Peak memory 207832 kb
Host smart-4d8393aa-3bed-4f89-b75f-2b12cfc899b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778373237 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2778373237
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.415888852
Short name T885
Test name
Test status
Simulation time 98192131618 ps
CPU time 158.82 seconds
Started Aug 10 07:01:44 PM PDT 24
Finished Aug 10 07:04:23 PM PDT 24
Peak memory 207832 kb
Host smart-59c8e52f-9369-43c0-83f3-92d0370dac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
8852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.415888852
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3852524446
Short name T1893
Test name
Test status
Simulation time 213955318 ps
CPU time 1.16 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:01:44 PM PDT 24
Peak memory 215908 kb
Host smart-d5052fc1-6d88-4615-80ff-e1c8802a3a48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3852524446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3852524446
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4071981260
Short name T1927
Test name
Test status
Simulation time 167123404 ps
CPU time 0.84 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:01:44 PM PDT 24
Peak memory 207548 kb
Host smart-99101249-0e53-4192-8450-699f4acc0a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
81260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4071981260
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.663006973
Short name T1971
Test name
Test status
Simulation time 165695417 ps
CPU time 0.91 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207400 kb
Host smart-79bd2d90-d4b4-4fce-af64-01262ddda87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66300
6973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.663006973
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2275385729
Short name T1337
Test name
Test status
Simulation time 3041006676 ps
CPU time 29.71 seconds
Started Aug 10 07:01:43 PM PDT 24
Finished Aug 10 07:02:13 PM PDT 24
Peak memory 217968 kb
Host smart-84601265-7329-46b2-b4f1-0b9b877ba335
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2275385729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2275385729
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.1212788675
Short name T3198
Test name
Test status
Simulation time 7314801602 ps
CPU time 46.69 seconds
Started Aug 10 07:01:52 PM PDT 24
Finished Aug 10 07:02:39 PM PDT 24
Peak memory 207780 kb
Host smart-069bbc3b-5c6d-40f3-ab19-e2cbe199d50a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1212788675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1212788675
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2595834084
Short name T109
Test name
Test status
Simulation time 255060516 ps
CPU time 0.95 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207568 kb
Host smart-6b27d128-6536-499d-abdd-cfa550f55daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
34084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2595834084
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.70939210
Short name T2988
Test name
Test status
Simulation time 24397389521 ps
CPU time 36.85 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 216708 kb
Host smart-05c17ae0-2c8c-4fa1-9143-dbe8567fb574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70939
210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.70939210
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2227851547
Short name T3157
Test name
Test status
Simulation time 3934874662 ps
CPU time 6.23 seconds
Started Aug 10 07:01:55 PM PDT 24
Finished Aug 10 07:02:02 PM PDT 24
Peak memory 207736 kb
Host smart-80b9fac5-9e4d-41e6-a83c-cd2f3cab8fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22278
51547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2227851547
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.430434855
Short name T2800
Test name
Test status
Simulation time 4963503162 ps
CPU time 39.61 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:02:33 PM PDT 24
Peak memory 216160 kb
Host smart-b49f3efd-36f0-4765-8886-9d92259ee8ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=430434855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.430434855
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1502891960
Short name T2043
Test name
Test status
Simulation time 1787585234 ps
CPU time 18.62 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:02:12 PM PDT 24
Peak memory 217388 kb
Host smart-ce0f7612-ee7f-4a02-a5d4-92f4d264cf7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1502891960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1502891960
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1307680522
Short name T3000
Test name
Test status
Simulation time 238951217 ps
CPU time 0.97 seconds
Started Aug 10 07:01:52 PM PDT 24
Finished Aug 10 07:01:53 PM PDT 24
Peak memory 207568 kb
Host smart-2bc80120-29e1-4cef-9fc5-df8dcae525ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1307680522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1307680522
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1492761919
Short name T1928
Test name
Test status
Simulation time 190829519 ps
CPU time 1.02 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207552 kb
Host smart-71d3289f-b49c-4030-89b7-85ed1bea6132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
61919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1492761919
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.87877808
Short name T2449
Test name
Test status
Simulation time 1740038425 ps
CPU time 13.42 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:02:06 PM PDT 24
Peak memory 224124 kb
Host smart-2db9c651-b78f-457c-8e53-06b12d4a2fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87877
808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.87877808
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3842974588
Short name T2218
Test name
Test status
Simulation time 2410656488 ps
CPU time 64.74 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:02:58 PM PDT 24
Peak memory 216064 kb
Host smart-9cc61a75-e31a-4406-9847-9f9e836b3732
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3842974588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3842974588
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2229320027
Short name T3308
Test name
Test status
Simulation time 1957885767 ps
CPU time 20.07 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:02:14 PM PDT 24
Peak memory 216424 kb
Host smart-048833e4-727f-4797-bf25-8bdf5e8c7e10
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2229320027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2229320027
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.37784068
Short name T1212
Test name
Test status
Simulation time 143927201 ps
CPU time 0.85 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207552 kb
Host smart-3dae2062-081c-45c2-9ccc-d1ddb2d8b888
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=37784068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.37784068
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2859164424
Short name T3009
Test name
Test status
Simulation time 149150782 ps
CPU time 0.84 seconds
Started Aug 10 07:01:52 PM PDT 24
Finished Aug 10 07:01:53 PM PDT 24
Peak memory 207572 kb
Host smart-ac7e1708-4e73-41fe-b472-70bbd7d3618b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28591
64424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2859164424
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2761359532
Short name T154
Test name
Test status
Simulation time 173893921 ps
CPU time 0.86 seconds
Started Aug 10 07:01:52 PM PDT 24
Finished Aug 10 07:01:53 PM PDT 24
Peak memory 207404 kb
Host smart-d1c45b54-5034-48db-bb8e-afc685e6890d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27613
59532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2761359532
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2130613652
Short name T642
Test name
Test status
Simulation time 175540138 ps
CPU time 0.85 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:01:54 PM PDT 24
Peak memory 207524 kb
Host smart-864f0a9a-2552-469f-84e4-280905e8a913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21306
13652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2130613652
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2191601463
Short name T3288
Test name
Test status
Simulation time 213566695 ps
CPU time 0.9 seconds
Started Aug 10 07:01:53 PM PDT 24
Finished Aug 10 07:01:54 PM PDT 24
Peak memory 207512 kb
Host smart-81dd2502-3e57-4366-9584-53621a443db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
01463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2191601463
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1054526113
Short name T3139
Test name
Test status
Simulation time 155508474 ps
CPU time 0.83 seconds
Started Aug 10 07:01:54 PM PDT 24
Finished Aug 10 07:01:55 PM PDT 24
Peak memory 207508 kb
Host smart-a88e0bac-824a-4e13-bbee-b16e09cae66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10545
26113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1054526113
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.505880331
Short name T3447
Test name
Test status
Simulation time 195539832 ps
CPU time 0.92 seconds
Started Aug 10 07:01:50 PM PDT 24
Finished Aug 10 07:01:51 PM PDT 24
Peak memory 207532 kb
Host smart-3d5f43c0-5837-4489-90d7-af8ba2714573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50588
0331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.505880331
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.638782326
Short name T644
Test name
Test status
Simulation time 248016253 ps
CPU time 1 seconds
Started Aug 10 07:01:55 PM PDT 24
Finished Aug 10 07:01:56 PM PDT 24
Peak memory 207460 kb
Host smart-8ac4b406-b3fa-4e0d-ac09-6d6f19197990
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=638782326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.638782326
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2113886306
Short name T1092
Test name
Test status
Simulation time 230626030 ps
CPU time 1 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207540 kb
Host smart-502ecec4-3aca-46b2-93e2-e6780aba5a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21138
86306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2113886306
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1373465398
Short name T939
Test name
Test status
Simulation time 167170938 ps
CPU time 0.83 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207384 kb
Host smart-3335f949-befb-4939-a34d-e8724cfe7f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
65398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1373465398
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1607886651
Short name T696
Test name
Test status
Simulation time 31471081 ps
CPU time 0.67 seconds
Started Aug 10 07:02:04 PM PDT 24
Finished Aug 10 07:02:05 PM PDT 24
Peak memory 207516 kb
Host smart-cd208219-42ce-4679-8c9c-9a978d5444ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16078
86651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1607886651
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3285621349
Short name T320
Test name
Test status
Simulation time 8806923560 ps
CPU time 22.4 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:25 PM PDT 24
Peak memory 221060 kb
Host smart-0b562f9a-52a3-4fd8-8c1f-2bd1b8f11a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
21349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3285621349
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1635130384
Short name T690
Test name
Test status
Simulation time 206420929 ps
CPU time 0.92 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207600 kb
Host smart-9176fe92-336c-4bbd-aa6e-e2c00801d098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16351
30384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1635130384
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1075376544
Short name T936
Test name
Test status
Simulation time 283893392 ps
CPU time 1.13 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207524 kb
Host smart-337f7bd1-ea9f-48be-bdd7-575c10b1265b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753
76544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1075376544
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2366853837
Short name T630
Test name
Test status
Simulation time 5365069503 ps
CPU time 66.07 seconds
Started Aug 10 07:02:04 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 219188 kb
Host smart-41b6602b-71c6-4bb0-ada5-1dcf73fcf48c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366853837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2366853837
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3483429762
Short name T199
Test name
Test status
Simulation time 7697190459 ps
CPU time 140.12 seconds
Started Aug 10 07:02:04 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 218936 kb
Host smart-b13f5447-ca36-4037-97c7-c3235ebac680
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3483429762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3483429762
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3624860928
Short name T3442
Test name
Test status
Simulation time 4980546165 ps
CPU time 17 seconds
Started Aug 10 07:02:04 PM PDT 24
Finished Aug 10 07:02:21 PM PDT 24
Peak memory 219712 kb
Host smart-a06e17bc-c54a-4b9d-998a-18e1d5842906
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624860928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3624860928
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2034610971
Short name T2565
Test name
Test status
Simulation time 189549153 ps
CPU time 0.95 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207532 kb
Host smart-9b498ba9-4de9-4d45-9f1f-081fbf89c43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
10971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2034610971
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3551993094
Short name T3108
Test name
Test status
Simulation time 168364601 ps
CPU time 0.85 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207528 kb
Host smart-99e4e2ad-845b-4cac-bd0e-ba7c944bddf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
93094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3551993094
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_resume_link_active.1893859962
Short name T2788
Test name
Test status
Simulation time 20174006717 ps
CPU time 24.97 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:28 PM PDT 24
Peak memory 207580 kb
Host smart-f0d48f6f-d94c-479c-8456-3b9f32ffe67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18938
59962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_resume_link_active.1893859962
Directory /workspace/3.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.128880334
Short name T1759
Test name
Test status
Simulation time 162581038 ps
CPU time 0.83 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207480 kb
Host smart-c4bbee73-b134-44be-b57c-315db2be679e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12888
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.128880334
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_full.975130122
Short name T2371
Test name
Test status
Simulation time 358123533 ps
CPU time 1.3 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:06 PM PDT 24
Peak memory 207420 kb
Host smart-950550b3-9c78-47ad-b9f4-0309dfe0cebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97513
0122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.975130122
Directory /workspace/3.usbdev_rx_full/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1563305833
Short name T84
Test name
Test status
Simulation time 158925376 ps
CPU time 0.87 seconds
Started Aug 10 07:02:02 PM PDT 24
Finished Aug 10 07:02:03 PM PDT 24
Peak memory 207544 kb
Host smart-3b5546a8-a72a-4810-9435-cd6b54b63c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
05833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1563305833
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3062389179
Short name T253
Test name
Test status
Simulation time 423451825 ps
CPU time 1.21 seconds
Started Aug 10 07:02:15 PM PDT 24
Finished Aug 10 07:02:16 PM PDT 24
Peak memory 223448 kb
Host smart-69d80fc4-76a6-422e-9c2b-4d0ad35b162f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3062389179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3062389179
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3673834366
Short name T55
Test name
Test status
Simulation time 398648117 ps
CPU time 1.4 seconds
Started Aug 10 07:02:03 PM PDT 24
Finished Aug 10 07:02:04 PM PDT 24
Peak memory 207500 kb
Host smart-81a9d547-b8c4-4476-9ae2-5114f224c40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
34366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3673834366
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1519477107
Short name T2607
Test name
Test status
Simulation time 306578614 ps
CPU time 1.14 seconds
Started Aug 10 07:02:14 PM PDT 24
Finished Aug 10 07:02:15 PM PDT 24
Peak memory 207512 kb
Host smart-3e5b8bb3-52bf-4b0c-ac57-8981c553730e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
77107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1519477107
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2770353892
Short name T2541
Test name
Test status
Simulation time 153463442 ps
CPU time 0.85 seconds
Started Aug 10 07:02:15 PM PDT 24
Finished Aug 10 07:02:16 PM PDT 24
Peak memory 207512 kb
Host smart-c8eae97c-c4a4-435b-b224-6cf0db39926e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
53892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2770353892
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.290762662
Short name T697
Test name
Test status
Simulation time 166980424 ps
CPU time 0.83 seconds
Started Aug 10 07:02:12 PM PDT 24
Finished Aug 10 07:02:13 PM PDT 24
Peak memory 207564 kb
Host smart-0b647835-dcce-40ac-a1b5-3263f670d4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29076
2662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.290762662
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1174986786
Short name T1498
Test name
Test status
Simulation time 232996710 ps
CPU time 1.03 seconds
Started Aug 10 07:02:13 PM PDT 24
Finished Aug 10 07:02:14 PM PDT 24
Peak memory 207544 kb
Host smart-00b7565a-8ac6-40ac-844b-4cc0e2443832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11749
86786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1174986786
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2276567376
Short name T1543
Test name
Test status
Simulation time 3105418209 ps
CPU time 87.66 seconds
Started Aug 10 07:02:15 PM PDT 24
Finished Aug 10 07:03:43 PM PDT 24
Peak memory 224240 kb
Host smart-67cc9d7a-4022-4f12-b2ca-b4412e526611
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2276567376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2276567376
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1741617788
Short name T2580
Test name
Test status
Simulation time 171655581 ps
CPU time 0.85 seconds
Started Aug 10 07:02:15 PM PDT 24
Finished Aug 10 07:02:16 PM PDT 24
Peak memory 207516 kb
Host smart-89b7aa03-cc24-4cc6-8247-861ff9cf5573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
17788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1741617788
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1680837366
Short name T1951
Test name
Test status
Simulation time 185883308 ps
CPU time 0.89 seconds
Started Aug 10 07:02:16 PM PDT 24
Finished Aug 10 07:02:17 PM PDT 24
Peak memory 207572 kb
Host smart-5626d84b-3dce-4dbe-9957-2c13c2892742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1680837366
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2188066683
Short name T1430
Test name
Test status
Simulation time 794388746 ps
CPU time 2.11 seconds
Started Aug 10 07:02:12 PM PDT 24
Finished Aug 10 07:02:15 PM PDT 24
Peak memory 207800 kb
Host smart-ea547797-545c-494f-b346-c767e7ac971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
66683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2188066683
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.4076501879
Short name T581
Test name
Test status
Simulation time 1410221701 ps
CPU time 10.77 seconds
Started Aug 10 07:02:15 PM PDT 24
Finished Aug 10 07:02:26 PM PDT 24
Peak memory 217516 kb
Host smart-0977d9b1-2058-4838-8252-02428e4a0d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765
01879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.4076501879
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.134096712
Short name T1485
Test name
Test status
Simulation time 1544903840 ps
CPU time 10.52 seconds
Started Aug 10 07:01:35 PM PDT 24
Finished Aug 10 07:01:45 PM PDT 24
Peak memory 207688 kb
Host smart-85425eb2-3648-45dd-a9d9-fea2970a72c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134096712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host_
handshake.134096712
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_tx_rx_disruption.2982951256
Short name T2522
Test name
Test status
Simulation time 508676401 ps
CPU time 1.57 seconds
Started Aug 10 07:02:14 PM PDT 24
Finished Aug 10 07:02:15 PM PDT 24
Peak memory 207524 kb
Host smart-8220587d-0d0a-4804-ae77-4f0ee18e7195
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982951256 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.usbdev_tx_rx_disruption.2982951256
Directory /workspace/3.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2556213182
Short name T809
Test name
Test status
Simulation time 58453401 ps
CPU time 0.67 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207524 kb
Host smart-c55af7e4-2fd7-4eea-9360-fccb7e7cbbe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2556213182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2556213182
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.794885552
Short name T1895
Test name
Test status
Simulation time 10157804614 ps
CPU time 11.9 seconds
Started Aug 10 07:12:31 PM PDT 24
Finished Aug 10 07:12:43 PM PDT 24
Peak memory 207480 kb
Host smart-c57b9202-d377-427b-bf7f-fc95912d58ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794885552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_disconnect.794885552
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2455623076
Short name T1698
Test name
Test status
Simulation time 18329365581 ps
CPU time 20.42 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:45 PM PDT 24
Peak memory 207764 kb
Host smart-3db6e58b-c932-4d10-9fe3-82eaa7a8c19e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455623076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2455623076
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.647149828
Short name T3322
Test name
Test status
Simulation time 24686517943 ps
CPU time 27.1 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:53 PM PDT 24
Peak memory 216060 kb
Host smart-79717c37-a0a6-4f3c-aba5-37b0224cc5a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647149828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.647149828
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2296277717
Short name T3035
Test name
Test status
Simulation time 229965039 ps
CPU time 0.96 seconds
Started Aug 10 07:12:27 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207512 kb
Host smart-2bd9c0f1-3ced-4326-b109-78454707d53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22962
77717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2296277717
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3732549923
Short name T86
Test name
Test status
Simulation time 162006939 ps
CPU time 0.84 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207608 kb
Host smart-cbfeab53-8fd8-4e34-95ce-be5c42593aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
49923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3732549923
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1579446171
Short name T2073
Test name
Test status
Simulation time 223264078 ps
CPU time 1.13 seconds
Started Aug 10 07:12:29 PM PDT 24
Finished Aug 10 07:12:31 PM PDT 24
Peak memory 207552 kb
Host smart-ce56580f-25bc-4119-9860-a7551e82601c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15794
46171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1579446171
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1476059315
Short name T2949
Test name
Test status
Simulation time 656784059 ps
CPU time 1.92 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207488 kb
Host smart-46bd3c13-ce0b-4ad3-bf5f-6ad6d7a504f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1476059315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1476059315
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2103505404
Short name T1298
Test name
Test status
Simulation time 28323617934 ps
CPU time 47.85 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:13:12 PM PDT 24
Peak memory 207816 kb
Host smart-50187cdc-2f7d-4e3b-a25d-a133d7001c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21035
05404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2103505404
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3882653626
Short name T965
Test name
Test status
Simulation time 1681662978 ps
CPU time 39.34 seconds
Started Aug 10 07:12:29 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207768 kb
Host smart-3a57e326-5fe7-4dcc-bfbf-d4b2f384d2c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882653626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3882653626
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1396107894
Short name T1308
Test name
Test status
Simulation time 518691024 ps
CPU time 1.53 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207484 kb
Host smart-9a88bb23-5236-4dea-a0aa-da27d3c53ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
07894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1396107894
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3722196022
Short name T2978
Test name
Test status
Simulation time 137284171 ps
CPU time 0.82 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:27 PM PDT 24
Peak memory 207512 kb
Host smart-9c965139-12c4-4971-9c66-9ebe591fa1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221
96022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3722196022
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4188153035
Short name T1444
Test name
Test status
Simulation time 74646907 ps
CPU time 0.73 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207412 kb
Host smart-99a4d93d-ca45-4af2-8962-a0fbe2c93461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
53035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4188153035
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1693894365
Short name T897
Test name
Test status
Simulation time 710015684 ps
CPU time 2.28 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207724 kb
Host smart-e67c48d6-6aed-457e-a035-e0cbdcf28d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16938
94365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1693894365
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_types.485499295
Short name T515
Test name
Test status
Simulation time 411967014 ps
CPU time 1.29 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:25 PM PDT 24
Peak memory 207548 kb
Host smart-368f1954-95f7-4db8-a768-75b3011ee667
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=485499295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.485499295
Directory /workspace/30.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3844346524
Short name T2776
Test name
Test status
Simulation time 344172786 ps
CPU time 2.47 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207688 kb
Host smart-33482f7a-52d8-4e4f-b32d-3cdc8f217447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
46524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3844346524
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1800555179
Short name T1162
Test name
Test status
Simulation time 146580841 ps
CPU time 0.84 seconds
Started Aug 10 07:12:27 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207556 kb
Host smart-65af1907-a29f-442a-9b82-6322888e3f55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1800555179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1800555179
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.416695139
Short name T1741
Test name
Test status
Simulation time 196972551 ps
CPU time 0.89 seconds
Started Aug 10 07:12:29 PM PDT 24
Finished Aug 10 07:12:30 PM PDT 24
Peak memory 207384 kb
Host smart-fc922cf4-0578-4a9e-8b35-5b8b1093a427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41669
5139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.416695139
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2001125596
Short name T1908
Test name
Test status
Simulation time 320295516 ps
CPU time 1.2 seconds
Started Aug 10 07:12:27 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207560 kb
Host smart-d5c94b05-4645-4d1d-b449-e25faa1bb7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
25596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2001125596
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2586427393
Short name T1110
Test name
Test status
Simulation time 2532788660 ps
CPU time 19.41 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:46 PM PDT 24
Peak memory 218232 kb
Host smart-171afa53-5899-42d8-8a79-dd998ba20fad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2586427393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2586427393
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2319024557
Short name T2493
Test name
Test status
Simulation time 6451310711 ps
CPU time 41.99 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207700 kb
Host smart-3ff582e1-3af5-4bf6-bb64-fa35551d1a7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2319024557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2319024557
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4228529435
Short name T2551
Test name
Test status
Simulation time 164868968 ps
CPU time 0.89 seconds
Started Aug 10 07:12:23 PM PDT 24
Finished Aug 10 07:12:24 PM PDT 24
Peak memory 207568 kb
Host smart-e6d58443-2bad-4cc0-b4c5-341b27d10634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42285
29435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4228529435
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2482893672
Short name T3051
Test name
Test status
Simulation time 33782038416 ps
CPU time 54.81 seconds
Started Aug 10 07:12:29 PM PDT 24
Finished Aug 10 07:13:24 PM PDT 24
Peak memory 207848 kb
Host smart-3cf06ef4-9b8d-437b-887b-33b261291445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
93672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2482893672
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1684059228
Short name T59
Test name
Test status
Simulation time 4953659987 ps
CPU time 7.03 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:31 PM PDT 24
Peak memory 216064 kb
Host smart-1aa03676-54c1-4147-a422-a86080beb423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16840
59228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1684059228
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3759911491
Short name T940
Test name
Test status
Simulation time 2393672233 ps
CPU time 23.86 seconds
Started Aug 10 07:12:31 PM PDT 24
Finished Aug 10 07:12:55 PM PDT 24
Peak memory 215724 kb
Host smart-a5dee33f-3fb8-45c2-886b-0f3930e1711e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3759911491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3759911491
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1564046835
Short name T2808
Test name
Test status
Simulation time 1783233770 ps
CPU time 13.68 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 224176 kb
Host smart-08ac1b02-6475-4c17-a3d5-138ae9a59e0b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1564046835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1564046835
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2667656914
Short name T2795
Test name
Test status
Simulation time 238846391 ps
CPU time 0.97 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207512 kb
Host smart-41ed5f8a-eb3e-47bc-8316-02a39b02bb6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2667656914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2667656914
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1378611857
Short name T1653
Test name
Test status
Simulation time 212943820 ps
CPU time 1.04 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207608 kb
Host smart-ab9f3e53-697f-4b66-91ab-f61d78766d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13786
11857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1378611857
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1663180064
Short name T966
Test name
Test status
Simulation time 2872968601 ps
CPU time 28.74 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:54 PM PDT 24
Peak memory 217928 kb
Host smart-96a1568c-0287-436a-ad2e-635275549284
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1663180064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1663180064
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3250634842
Short name T2262
Test name
Test status
Simulation time 159136725 ps
CPU time 0.84 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:12:29 PM PDT 24
Peak memory 207600 kb
Host smart-bb795033-db73-4636-ae97-1436b026a8c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3250634842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3250634842
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2156113279
Short name T3446
Test name
Test status
Simulation time 141780113 ps
CPU time 0.8 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:25 PM PDT 24
Peak memory 207580 kb
Host smart-42906bc5-2fb5-4c8c-9eef-efc1adb99c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
13279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2156113279
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2819198368
Short name T161
Test name
Test status
Simulation time 203779523 ps
CPU time 1 seconds
Started Aug 10 07:12:27 PM PDT 24
Finished Aug 10 07:12:28 PM PDT 24
Peak memory 207608 kb
Host smart-69beebd9-d100-4e97-8bf9-a0c5ba4167e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28191
98368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2819198368
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.4004269756
Short name T1222
Test name
Test status
Simulation time 216763691 ps
CPU time 0.99 seconds
Started Aug 10 07:12:30 PM PDT 24
Finished Aug 10 07:12:31 PM PDT 24
Peak memory 207552 kb
Host smart-70f7b4eb-4bbc-466f-aa23-43f3ab614cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
69756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.4004269756
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1260225322
Short name T1531
Test name
Test status
Simulation time 183251907 ps
CPU time 0.93 seconds
Started Aug 10 07:12:25 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207532 kb
Host smart-f899fae1-4e85-474a-a6be-433c0d470374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12602
25322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1260225322
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.426404575
Short name T2892
Test name
Test status
Simulation time 187669603 ps
CPU time 0.93 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:27 PM PDT 24
Peak memory 207540 kb
Host smart-ea4e89b4-ba81-4cb3-be2f-c019f89ed6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42640
4575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.426404575
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3100011283
Short name T1248
Test name
Test status
Simulation time 149791306 ps
CPU time 0.82 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:25 PM PDT 24
Peak memory 207540 kb
Host smart-9a0cb74c-8273-47bf-8dbf-4258d00c813c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
11283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3100011283
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1621685044
Short name T1424
Test name
Test status
Simulation time 220921811 ps
CPU time 1.07 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:26 PM PDT 24
Peak memory 207416 kb
Host smart-2f7101d1-fd2e-4bd5-8d4b-ff7b3845721b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1621685044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1621685044
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2585457902
Short name T2282
Test name
Test status
Simulation time 137344903 ps
CPU time 0.8 seconds
Started Aug 10 07:12:26 PM PDT 24
Finished Aug 10 07:12:27 PM PDT 24
Peak memory 207544 kb
Host smart-2001c24e-aca2-4382-972f-b4f4d5e7db49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
57902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2585457902
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1426715483
Short name T1
Test name
Test status
Simulation time 79006252 ps
CPU time 0.73 seconds
Started Aug 10 07:12:24 PM PDT 24
Finished Aug 10 07:12:25 PM PDT 24
Peak memory 207508 kb
Host smart-56eaea90-be97-4b37-82a0-daef7c76fa1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
15483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1426715483
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2831114115
Short name T341
Test name
Test status
Simulation time 17043003356 ps
CPU time 48.16 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 216100 kb
Host smart-f5c42171-650c-491d-b3f3-9984b3151bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28311
14115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2831114115
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1527699348
Short name T2189
Test name
Test status
Simulation time 196419876 ps
CPU time 0.87 seconds
Started Aug 10 07:12:34 PM PDT 24
Finished Aug 10 07:12:35 PM PDT 24
Peak memory 207548 kb
Host smart-66a96d05-456d-4156-a47c-7f5865b7a8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
99348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1527699348
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2448265679
Short name T1647
Test name
Test status
Simulation time 260800490 ps
CPU time 1.12 seconds
Started Aug 10 07:12:34 PM PDT 24
Finished Aug 10 07:12:35 PM PDT 24
Peak memory 207556 kb
Host smart-93bf808b-9430-48f9-a8d5-8b3432993503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24482
65679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2448265679
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2918272930
Short name T2945
Test name
Test status
Simulation time 169022484 ps
CPU time 0.86 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207404 kb
Host smart-9fd15adb-88e3-4cc8-8aeb-a6dbfb1dd6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
72930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2918272930
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1824692635
Short name T1138
Test name
Test status
Simulation time 171842292 ps
CPU time 0.88 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:38 PM PDT 24
Peak memory 207580 kb
Host smart-70c7cbb2-888c-4d64-acf9-d3e150fc74c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18246
92635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1824692635
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3294361324
Short name T3012
Test name
Test status
Simulation time 178162761 ps
CPU time 0.92 seconds
Started Aug 10 07:12:39 PM PDT 24
Finished Aug 10 07:12:40 PM PDT 24
Peak memory 207508 kb
Host smart-a0053f88-6d3a-4d16-989b-d1a4857452ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943
61324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3294361324
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_rx_full.3964746666
Short name T2687
Test name
Test status
Simulation time 426447987 ps
CPU time 1.48 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207456 kb
Host smart-e4c3e8b4-2ded-42aa-9229-07eb5e6c6b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39647
46666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.3964746666
Directory /workspace/30.usbdev_rx_full/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1872468377
Short name T1791
Test name
Test status
Simulation time 146754172 ps
CPU time 0.81 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207576 kb
Host smart-7002ad03-4b4a-47a9-aa50-1514c5825c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18724
68377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1872468377
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1376483459
Short name T37
Test name
Test status
Simulation time 156535607 ps
CPU time 0.83 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207572 kb
Host smart-ee85f0a3-90fe-4fe3-8513-94755716a60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764
83459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1376483459
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2299065263
Short name T3547
Test name
Test status
Simulation time 212808719 ps
CPU time 0.98 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:38 PM PDT 24
Peak memory 207476 kb
Host smart-c36aab49-c282-43fa-a582-615474c01017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990
65263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2299065263
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2052247621
Short name T2331
Test name
Test status
Simulation time 2171014540 ps
CPU time 63.03 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:13:38 PM PDT 24
Peak memory 217568 kb
Host smart-03302be8-4146-432b-b29a-0364ee4ca527
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2052247621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2052247621
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.721537042
Short name T1974
Test name
Test status
Simulation time 206060111 ps
CPU time 0.94 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207416 kb
Host smart-133159fd-88c4-47c3-9fa2-e25886990112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72153
7042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.721537042
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1485395557
Short name T1135
Test name
Test status
Simulation time 191116162 ps
CPU time 0.91 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207524 kb
Host smart-e7ff0408-531a-4078-9c97-417e762a6fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
95557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1485395557
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1404940655
Short name T2404
Test name
Test status
Simulation time 386457133 ps
CPU time 1.29 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207572 kb
Host smart-87f1305d-45fe-46a7-8103-b5770277d7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14049
40655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1404940655
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.110396666
Short name T894
Test name
Test status
Simulation time 2054591978 ps
CPU time 59.25 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:13:37 PM PDT 24
Peak memory 217304 kb
Host smart-2343e2ef-b458-4ac4-85eb-79c215a0ab99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11039
6666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.110396666
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1043466489
Short name T2608
Test name
Test status
Simulation time 3779633828 ps
CPU time 25.86 seconds
Started Aug 10 07:12:28 PM PDT 24
Finished Aug 10 07:12:54 PM PDT 24
Peak memory 207716 kb
Host smart-ecef0620-46e3-468e-8cbe-4bca013eabe9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043466489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos
t_handshake.1043466489
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_tx_rx_disruption.760019837
Short name T46
Test name
Test status
Simulation time 550757043 ps
CPU time 1.68 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207556 kb
Host smart-4d09d160-1702-4028-8386-813878288de0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760019837 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.usbdev_tx_rx_disruption.760019837
Directory /workspace/30.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/300.usbdev_tx_rx_disruption.2645777440
Short name T2217
Test name
Test status
Simulation time 507583146 ps
CPU time 1.42 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207548 kb
Host smart-42d0449c-a3c3-445d-b328-71c0a0fa1c35
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645777440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 300.usbdev_tx_rx_disruption.2645777440
Directory /workspace/300.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/301.usbdev_tx_rx_disruption.526119080
Short name T2749
Test name
Test status
Simulation time 672274061 ps
CPU time 1.84 seconds
Started Aug 10 07:18:11 PM PDT 24
Finished Aug 10 07:18:13 PM PDT 24
Peak memory 207600 kb
Host smart-6cebf20f-243c-4e3d-89bb-7b5c1ccf7b7b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526119080 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 301.usbdev_tx_rx_disruption.526119080
Directory /workspace/301.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/302.usbdev_tx_rx_disruption.2323851674
Short name T1178
Test name
Test status
Simulation time 483194063 ps
CPU time 1.44 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207500 kb
Host smart-190cbb07-bf10-452e-98e1-50c1ecdabdbf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323851674 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 302.usbdev_tx_rx_disruption.2323851674
Directory /workspace/302.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/303.usbdev_tx_rx_disruption.3434801960
Short name T2091
Test name
Test status
Simulation time 484129224 ps
CPU time 1.52 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207532 kb
Host smart-975b8e14-a11c-4e7b-8896-82962735495e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434801960 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 303.usbdev_tx_rx_disruption.3434801960
Directory /workspace/303.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/304.usbdev_tx_rx_disruption.688932557
Short name T636
Test name
Test status
Simulation time 524256259 ps
CPU time 1.65 seconds
Started Aug 10 07:18:04 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207556 kb
Host smart-1c2bec06-325b-459b-bed8-806a875df41d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688932557 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 304.usbdev_tx_rx_disruption.688932557
Directory /workspace/304.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/305.usbdev_tx_rx_disruption.2591859252
Short name T2425
Test name
Test status
Simulation time 651107247 ps
CPU time 1.74 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:09 PM PDT 24
Peak memory 207508 kb
Host smart-c3c1ab1e-19e3-4dcb-b276-cbad6a90f154
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591859252 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 305.usbdev_tx_rx_disruption.2591859252
Directory /workspace/305.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/306.usbdev_tx_rx_disruption.237496913
Short name T3156
Test name
Test status
Simulation time 598612388 ps
CPU time 1.54 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207524 kb
Host smart-70c8064e-6830-4873-85a6-6adf48afda28
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237496913 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 306.usbdev_tx_rx_disruption.237496913
Directory /workspace/306.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/307.usbdev_tx_rx_disruption.3687759239
Short name T2704
Test name
Test status
Simulation time 478651557 ps
CPU time 1.46 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:06 PM PDT 24
Peak memory 207420 kb
Host smart-05258618-19bf-4534-afd6-e3bb9fcde3ac
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687759239 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 307.usbdev_tx_rx_disruption.3687759239
Directory /workspace/307.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/308.usbdev_tx_rx_disruption.4266089569
Short name T2407
Test name
Test status
Simulation time 438224038 ps
CPU time 1.42 seconds
Started Aug 10 07:18:05 PM PDT 24
Finished Aug 10 07:18:07 PM PDT 24
Peak memory 207500 kb
Host smart-e9e5a01a-4617-4518-9eaf-64f477454196
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266089569 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 308.usbdev_tx_rx_disruption.4266089569
Directory /workspace/308.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/309.usbdev_tx_rx_disruption.2022088106
Short name T657
Test name
Test status
Simulation time 529084885 ps
CPU time 1.46 seconds
Started Aug 10 07:18:07 PM PDT 24
Finished Aug 10 07:18:09 PM PDT 24
Peak memory 207604 kb
Host smart-5250c891-a8bc-4b4b-b035-c932ce0878bd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022088106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 309.usbdev_tx_rx_disruption.2022088106
Directory /workspace/309.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2445102018
Short name T2423
Test name
Test status
Simulation time 44626338 ps
CPU time 0.64 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207592 kb
Host smart-503e9f4a-4035-4c22-bf87-3ca24ba8054a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2445102018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2445102018
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3440924616
Short name T1008
Test name
Test status
Simulation time 11362917163 ps
CPU time 15.48 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:51 PM PDT 24
Peak memory 207852 kb
Host smart-b54b4b66-7929-47b7-b785-f9c7930b9335
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440924616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.3440924616
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2831838500
Short name T1587
Test name
Test status
Simulation time 18496031159 ps
CPU time 21.03 seconds
Started Aug 10 07:12:34 PM PDT 24
Finished Aug 10 07:12:55 PM PDT 24
Peak memory 207852 kb
Host smart-de88dac6-00cc-4065-8c53-39c48f3bab1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831838500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2831838500
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2685734178
Short name T13
Test name
Test status
Simulation time 24966673873 ps
CPU time 29.11 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:13:07 PM PDT 24
Peak memory 215876 kb
Host smart-34a32ac6-2f74-44a8-a402-e65700e48017
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685734178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.2685734178
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3646450417
Short name T2156
Test name
Test status
Simulation time 148536929 ps
CPU time 0.84 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207552 kb
Host smart-479fb6df-e37c-4dd8-9aaf-0c16bd9f9fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36464
50417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3646450417
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2816335983
Short name T1739
Test name
Test status
Simulation time 158577308 ps
CPU time 0.83 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207532 kb
Host smart-8e5ba892-aad7-4024-bde1-a281298bcdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
35983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2816335983
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2771022310
Short name T1656
Test name
Test status
Simulation time 575933172 ps
CPU time 1.69 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:37 PM PDT 24
Peak memory 207548 kb
Host smart-e76206d2-e5de-4758-8c58-e0bd626ec983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
22310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2771022310
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4019388251
Short name T1817
Test name
Test status
Simulation time 366426112 ps
CPU time 1.27 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207456 kb
Host smart-73e07e98-5591-4a32-8008-843342fd7bbc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4019388251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4019388251
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.25187865
Short name T2270
Test name
Test status
Simulation time 40679445296 ps
CPU time 63.51 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:13:38 PM PDT 24
Peak memory 207764 kb
Host smart-b6a1fe2c-8187-4241-a518-8914618b0e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25187
865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.25187865
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.3981012327
Short name T1827
Test name
Test status
Simulation time 3215903722 ps
CPU time 21.81 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:58 PM PDT 24
Peak memory 207812 kb
Host smart-a26a1a5b-c8c2-4448-994c-366f127f3a43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981012327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.3981012327
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2419088798
Short name T1264
Test name
Test status
Simulation time 910146053 ps
CPU time 2.18 seconds
Started Aug 10 07:12:33 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207712 kb
Host smart-46582267-3ef4-411a-9774-5290fa922a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
88798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2419088798
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1267669615
Short name T2439
Test name
Test status
Simulation time 153899518 ps
CPU time 0.85 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207496 kb
Host smart-51ba66b1-316e-45bc-85f8-b486d9c58a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12676
69615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1267669615
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2867003848
Short name T1244
Test name
Test status
Simulation time 54697649 ps
CPU time 0.71 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207572 kb
Host smart-d0d05bff-ae60-4bca-a27a-d87d8903e85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28670
03848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2867003848
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2803987245
Short name T1710
Test name
Test status
Simulation time 808238954 ps
CPU time 2.14 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:38 PM PDT 24
Peak memory 207720 kb
Host smart-213abccb-7384-4c34-9e3c-6af98ea8f2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
87245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2803987245
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_types.44883716
Short name T2280
Test name
Test status
Simulation time 389618059 ps
CPU time 1.25 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207528 kb
Host smart-bf843508-73b2-41c4-9656-51fd747c59ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=44883716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.44883716
Directory /workspace/31.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3383012885
Short name T3508
Test name
Test status
Simulation time 189471699 ps
CPU time 1.5 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207672 kb
Host smart-f99b9c6c-412b-4695-86a3-948bb9175d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
12885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3383012885
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.10684412
Short name T551
Test name
Test status
Simulation time 159713119 ps
CPU time 0.87 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207580 kb
Host smart-de6ac31a-4553-454d-af64-cebdda6ac369
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=10684412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.10684412
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.208829270
Short name T2638
Test name
Test status
Simulation time 187083138 ps
CPU time 0.92 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207508 kb
Host smart-40f34f9f-0321-43dc-b951-25b22f99faf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
9270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.208829270
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3214315817
Short name T2714
Test name
Test status
Simulation time 245638728 ps
CPU time 1.12 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207552 kb
Host smart-f8ffdc8f-210d-4b1e-b38e-4b3d5688a933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
15817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3214315817
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.2521979778
Short name T2958
Test name
Test status
Simulation time 2625331457 ps
CPU time 25.58 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 217548 kb
Host smart-4f2a66eb-813a-489a-b782-ef485899acdf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2521979778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2521979778
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.457928649
Short name T693
Test name
Test status
Simulation time 4020507017 ps
CPU time 27.68 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:13:05 PM PDT 24
Peak memory 207848 kb
Host smart-92a8680b-72a2-46e1-982d-482e30aaae65
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=457928649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.457928649
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1878161946
Short name T3480
Test name
Test status
Simulation time 200022791 ps
CPU time 0.94 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:38 PM PDT 24
Peak memory 207604 kb
Host smart-da9f11ca-94b4-43ae-99c8-52f8906e5624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
61946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1878161946
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3048989299
Short name T3226
Test name
Test status
Simulation time 8720877276 ps
CPU time 11.92 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 216244 kb
Host smart-209bc3d1-5439-40ea-bcc2-b18fbe6cc7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
89299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3048989299
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1101910030
Short name T34
Test name
Test status
Simulation time 8833772573 ps
CPU time 12.2 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:47 PM PDT 24
Peak memory 207772 kb
Host smart-7f1a907e-2236-4c9f-a506-cd568639158c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019
10030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1101910030
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2127848976
Short name T1166
Test name
Test status
Simulation time 3975826751 ps
CPU time 37.68 seconds
Started Aug 10 07:12:39 PM PDT 24
Finished Aug 10 07:13:16 PM PDT 24
Peak memory 224256 kb
Host smart-50d2e788-194e-4cb6-ae9d-4bcc77c9022c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2127848976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2127848976
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2809826864
Short name T1306
Test name
Test status
Simulation time 3614709013 ps
CPU time 108.21 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 217508 kb
Host smart-0734621c-6c62-4cc7-a7e4-96aabb57321b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2809826864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2809826864
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.187812681
Short name T2780
Test name
Test status
Simulation time 304773196 ps
CPU time 1.04 seconds
Started Aug 10 07:12:35 PM PDT 24
Finished Aug 10 07:12:36 PM PDT 24
Peak memory 207588 kb
Host smart-1ac645e3-4918-428e-b145-dc19776141a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=187812681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.187812681
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2889223644
Short name T995
Test name
Test status
Simulation time 189141254 ps
CPU time 0.98 seconds
Started Aug 10 07:12:38 PM PDT 24
Finished Aug 10 07:12:39 PM PDT 24
Peak memory 207544 kb
Host smart-ff397f2d-5b86-41b8-8f49-e1dce546d0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892
23644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2889223644
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3980343917
Short name T538
Test name
Test status
Simulation time 3015987886 ps
CPU time 88.81 seconds
Started Aug 10 07:12:36 PM PDT 24
Finished Aug 10 07:14:05 PM PDT 24
Peak memory 217600 kb
Host smart-776ca595-5602-488b-a0bb-e5c8580e03f2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3980343917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3980343917
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3708136254
Short name T732
Test name
Test status
Simulation time 155221176 ps
CPU time 0.84 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207524 kb
Host smart-841e40a5-a144-4faf-b2ff-0d14d85baae0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3708136254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3708136254
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4156223077
Short name T2627
Test name
Test status
Simulation time 149650005 ps
CPU time 0.81 seconds
Started Aug 10 07:12:49 PM PDT 24
Finished Aug 10 07:12:49 PM PDT 24
Peak memory 207600 kb
Host smart-0c249f3b-bc31-4922-9cb4-8c85a03b64fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41562
23077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4156223077
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.863974977
Short name T159
Test name
Test status
Simulation time 173471755 ps
CPU time 0.87 seconds
Started Aug 10 07:12:45 PM PDT 24
Finished Aug 10 07:12:46 PM PDT 24
Peak memory 207556 kb
Host smart-ee618882-4737-40a1-98a8-0edb5ec90ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86397
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.863974977
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1998764588
Short name T2216
Test name
Test status
Simulation time 192208529 ps
CPU time 0.96 seconds
Started Aug 10 07:12:46 PM PDT 24
Finished Aug 10 07:12:47 PM PDT 24
Peak memory 207428 kb
Host smart-82960d2a-4dbc-43b9-a3a0-87c3e6952c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19987
64588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1998764588
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3756536395
Short name T2226
Test name
Test status
Simulation time 178288549 ps
CPU time 0.89 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207444 kb
Host smart-4f26b1d1-608e-4e14-aceb-32d5674c932a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
36395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3756536395
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3017740569
Short name T3505
Test name
Test status
Simulation time 166572259 ps
CPU time 0.86 seconds
Started Aug 10 07:12:48 PM PDT 24
Finished Aug 10 07:12:49 PM PDT 24
Peak memory 207412 kb
Host smart-944e3a1b-2c15-4e79-a451-ee091375e35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
40569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3017740569
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.448659194
Short name T1023
Test name
Test status
Simulation time 156844642 ps
CPU time 0.88 seconds
Started Aug 10 07:12:46 PM PDT 24
Finished Aug 10 07:12:47 PM PDT 24
Peak memory 207588 kb
Host smart-e6ca54e9-6795-42b6-83d5-96a79fdb3ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44865
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.448659194
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3738066038
Short name T3094
Test name
Test status
Simulation time 212909726 ps
CPU time 1 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207664 kb
Host smart-e4f4d165-3a48-4e4f-bf00-ccbcd05f1721
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3738066038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3738066038
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2140615689
Short name T665
Test name
Test status
Simulation time 163447254 ps
CPU time 0.82 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207536 kb
Host smart-5bd6072f-d85a-4c57-843a-ac9255109254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21406
15689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2140615689
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.144917087
Short name T1630
Test name
Test status
Simulation time 19874891289 ps
CPU time 58.18 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:13:45 PM PDT 24
Peak memory 216000 kb
Host smart-839ff647-e2fa-4ddd-b07f-d70ffdbab112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
7087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.144917087
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.816167360
Short name T1119
Test name
Test status
Simulation time 186519750 ps
CPU time 0.93 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207524 kb
Host smart-4fbda5da-847f-4882-a41c-11745ff28cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81616
7360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.816167360
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3236024124
Short name T1646
Test name
Test status
Simulation time 242136872 ps
CPU time 1.03 seconds
Started Aug 10 07:12:50 PM PDT 24
Finished Aug 10 07:12:51 PM PDT 24
Peak memory 207500 kb
Host smart-ef873fc6-2a07-46fd-84b4-a83363d72a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
24124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3236024124
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2375534535
Short name T2142
Test name
Test status
Simulation time 223105374 ps
CPU time 0.98 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207548 kb
Host smart-b1c92fb8-75ca-49f2-a7d0-91c62da3f0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23755
34535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2375534535
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3650617376
Short name T620
Test name
Test status
Simulation time 174536432 ps
CPU time 0.88 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207548 kb
Host smart-fb7e469c-b6f6-4425-9077-daeab8fc7c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506
17376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3650617376
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.311611880
Short name T1386
Test name
Test status
Simulation time 177392375 ps
CPU time 0.89 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207552 kb
Host smart-ccc745d7-41e5-4cfe-a8a9-3be920990093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31161
1880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.311611880
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_rx_full.3691818998
Short name T3148
Test name
Test status
Simulation time 364561904 ps
CPU time 1.46 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:49 PM PDT 24
Peak memory 207564 kb
Host smart-da5e7bd5-ccc7-4d29-997e-2d498d109b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
18998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.3691818998
Directory /workspace/31.usbdev_rx_full/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.356742989
Short name T2816
Test name
Test status
Simulation time 181979765 ps
CPU time 0.92 seconds
Started Aug 10 07:12:49 PM PDT 24
Finished Aug 10 07:12:50 PM PDT 24
Peak memory 207532 kb
Host smart-21032b03-3acd-4395-8a82-41a3cb0599e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35674
2989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.356742989
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2889571398
Short name T2528
Test name
Test status
Simulation time 148231420 ps
CPU time 0.86 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207536 kb
Host smart-0d32fa9b-b84f-4f74-abaa-edce44729175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
71398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2889571398
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.556398419
Short name T1050
Test name
Test status
Simulation time 210325459 ps
CPU time 0.95 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207584 kb
Host smart-d6f5381e-3c82-4ae4-a38f-49255b7fbebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55639
8419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.556398419
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.218659126
Short name T202
Test name
Test status
Simulation time 3312879737 ps
CPU time 93.71 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 217776 kb
Host smart-41dfdefd-5a5c-4033-bff4-5fdc8f6d923d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=218659126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.218659126
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3812864347
Short name T2413
Test name
Test status
Simulation time 199638886 ps
CPU time 0.92 seconds
Started Aug 10 07:12:48 PM PDT 24
Finished Aug 10 07:12:49 PM PDT 24
Peak memory 207484 kb
Host smart-86ef8400-c07d-45bb-b82e-e060137e1413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
64347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3812864347
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.481140333
Short name T2456
Test name
Test status
Simulation time 193145886 ps
CPU time 0.87 seconds
Started Aug 10 07:12:47 PM PDT 24
Finished Aug 10 07:12:48 PM PDT 24
Peak memory 207564 kb
Host smart-4353ffa3-74f8-436d-aef5-2dd157bb4fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48114
0333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.481140333
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2032788475
Short name T2490
Test name
Test status
Simulation time 519894037 ps
CPU time 1.57 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207372 kb
Host smart-221a9274-42c2-4244-8aa2-a154c660474e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20327
88475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2032788475
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3297671411
Short name T2645
Test name
Test status
Simulation time 1994289912 ps
CPU time 15.2 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:13:13 PM PDT 24
Peak memory 217396 kb
Host smart-9b816d42-99f9-415d-a9e3-04fe1727435d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32976
71411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3297671411
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.1043309036
Short name T1631
Test name
Test status
Simulation time 2878051002 ps
CPU time 18.79 seconds
Started Aug 10 07:12:37 PM PDT 24
Finished Aug 10 07:12:55 PM PDT 24
Peak memory 207756 kb
Host smart-482b89e2-e42e-4c85-989d-cf3a724ac4b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043309036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.1043309036
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_tx_rx_disruption.2801222677
Short name T2727
Test name
Test status
Simulation time 574907454 ps
CPU time 1.55 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207556 kb
Host smart-d0b30eb6-54af-434f-8d97-b2ce521ba8e1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801222677 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.usbdev_tx_rx_disruption.2801222677
Directory /workspace/31.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/310.usbdev_tx_rx_disruption.1339545826
Short name T3577
Test name
Test status
Simulation time 472967331 ps
CPU time 1.43 seconds
Started Aug 10 07:18:11 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207392 kb
Host smart-ad19ca44-b2ae-49d5-83f1-2fc6aa762a44
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339545826 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 310.usbdev_tx_rx_disruption.1339545826
Directory /workspace/310.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/311.usbdev_tx_rx_disruption.574673584
Short name T1371
Test name
Test status
Simulation time 538050195 ps
CPU time 1.51 seconds
Started Aug 10 07:18:11 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207384 kb
Host smart-f0955b22-d17d-4de0-85a6-5eb2cc212415
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574673584 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 311.usbdev_tx_rx_disruption.574673584
Directory /workspace/311.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/312.usbdev_tx_rx_disruption.2933288951
Short name T2509
Test name
Test status
Simulation time 578180712 ps
CPU time 1.71 seconds
Started Aug 10 07:18:11 PM PDT 24
Finished Aug 10 07:18:13 PM PDT 24
Peak memory 207604 kb
Host smart-4e177c01-3d96-46e2-8970-8e6b8ceaa360
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933288951 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 312.usbdev_tx_rx_disruption.2933288951
Directory /workspace/312.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/313.usbdev_tx_rx_disruption.1722960543
Short name T3416
Test name
Test status
Simulation time 552850441 ps
CPU time 1.64 seconds
Started Aug 10 07:18:08 PM PDT 24
Finished Aug 10 07:18:10 PM PDT 24
Peak memory 207584 kb
Host smart-2f67b829-2d11-4896-b09a-37bd147385d7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722960543 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 313.usbdev_tx_rx_disruption.1722960543
Directory /workspace/313.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/314.usbdev_tx_rx_disruption.3725244801
Short name T662
Test name
Test status
Simulation time 459431302 ps
CPU time 1.43 seconds
Started Aug 10 07:18:09 PM PDT 24
Finished Aug 10 07:18:11 PM PDT 24
Peak memory 207608 kb
Host smart-7db0ad4b-1658-4c8b-877c-e628fccb75fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725244801 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 314.usbdev_tx_rx_disruption.3725244801
Directory /workspace/314.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/315.usbdev_tx_rx_disruption.3753115628
Short name T2924
Test name
Test status
Simulation time 575020009 ps
CPU time 1.5 seconds
Started Aug 10 07:18:09 PM PDT 24
Finished Aug 10 07:18:10 PM PDT 24
Peak memory 207604 kb
Host smart-f4605c78-e1b2-4d31-bc2d-cccabbe5d8eb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753115628 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 315.usbdev_tx_rx_disruption.3753115628
Directory /workspace/315.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/316.usbdev_tx_rx_disruption.2516120335
Short name T1691
Test name
Test status
Simulation time 457144220 ps
CPU time 1.54 seconds
Started Aug 10 07:18:06 PM PDT 24
Finished Aug 10 07:18:08 PM PDT 24
Peak memory 207548 kb
Host smart-c8c7b573-7e2a-48a0-810c-3eec1631c885
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516120335 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 316.usbdev_tx_rx_disruption.2516120335
Directory /workspace/316.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/317.usbdev_tx_rx_disruption.1366405310
Short name T2292
Test name
Test status
Simulation time 709816539 ps
CPU time 1.74 seconds
Started Aug 10 07:18:10 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 207608 kb
Host smart-988fabb7-58be-44a5-9a65-49d95ba858d5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366405310 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 317.usbdev_tx_rx_disruption.1366405310
Directory /workspace/317.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/318.usbdev_tx_rx_disruption.2842614089
Short name T1069
Test name
Test status
Simulation time 660073380 ps
CPU time 1.73 seconds
Started Aug 10 07:18:09 PM PDT 24
Finished Aug 10 07:18:11 PM PDT 24
Peak memory 207608 kb
Host smart-f737bc91-49ed-4ac9-9562-cc6356f4e23a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842614089 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 318.usbdev_tx_rx_disruption.2842614089
Directory /workspace/318.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/319.usbdev_tx_rx_disruption.1251487134
Short name T2243
Test name
Test status
Simulation time 473663058 ps
CPU time 1.45 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207592 kb
Host smart-7bea92b1-7ad9-4bb8-b2ee-cfc440227455
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251487134 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 319.usbdev_tx_rx_disruption.1251487134
Directory /workspace/319.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.4138955510
Short name T1978
Test name
Test status
Simulation time 44130859 ps
CPU time 0.74 seconds
Started Aug 10 07:13:09 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207560 kb
Host smart-aa32bb2c-36c7-4a01-9af8-928e89da7d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4138955510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.4138955510
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2612928302
Short name T1960
Test name
Test status
Simulation time 6308957092 ps
CPU time 8.64 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:06 PM PDT 24
Peak memory 216012 kb
Host smart-99f34656-6527-48fd-9ad3-7a33ade18b9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612928302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.2612928302
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2059459551
Short name T3307
Test name
Test status
Simulation time 21231304602 ps
CPU time 25.63 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:23 PM PDT 24
Peak memory 207840 kb
Host smart-2f3c80aa-232f-4ea8-a92d-d73414dd76e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059459551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2059459551
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.4197381321
Short name T1387
Test name
Test status
Simulation time 25882254152 ps
CPU time 40.01 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:37 PM PDT 24
Peak memory 216012 kb
Host smart-c51ed4f5-400f-49fb-8fdc-d095d2f8cd75
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197381321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.4197381321
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3294232183
Short name T2667
Test name
Test status
Simulation time 171768369 ps
CPU time 0.87 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207544 kb
Host smart-885da9e5-97d5-4a1c-b893-87594079a9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
32183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3294232183
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.543192839
Short name T1405
Test name
Test status
Simulation time 152414874 ps
CPU time 0.81 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:12:58 PM PDT 24
Peak memory 207460 kb
Host smart-f786c01d-4aa0-4b8a-bf9d-f0518d9eb1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54319
2839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.543192839
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3608036024
Short name T3381
Test name
Test status
Simulation time 282687574 ps
CPU time 1.12 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207508 kb
Host smart-038b34fa-174c-4456-90c6-08f664b61ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
36024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3608036024
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.1347763600
Short name T564
Test name
Test status
Simulation time 4326248191 ps
CPU time 40.48 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:40 PM PDT 24
Peak memory 207948 kb
Host smart-e2dab5b3-b867-45f0-8250-e2c7a23e0199
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347763600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.1347763600
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2254802647
Short name T127
Test name
Test status
Simulation time 844580528 ps
CPU time 2.04 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:03 PM PDT 24
Peak memory 207560 kb
Host smart-fb67100e-16e1-46b7-bf72-bfc70e3cc781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
02647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2254802647
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2921048730
Short name T2798
Test name
Test status
Simulation time 154196373 ps
CPU time 0.81 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207544 kb
Host smart-c0778e5b-c63b-470b-9622-ae9fab5cc379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29210
48730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2921048730
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2377756710
Short name T2558
Test name
Test status
Simulation time 37946985 ps
CPU time 0.73 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:12:59 PM PDT 24
Peak memory 207532 kb
Host smart-72e9dc91-17bf-4d46-9304-da4e8795170c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23777
56710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2377756710
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.72157988
Short name T2874
Test name
Test status
Simulation time 793061607 ps
CPU time 2.22 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207756 kb
Host smart-2d56bd98-3ac4-4f49-b05d-2bcdc313a9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72157
988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.72157988
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_types.3225063350
Short name T480
Test name
Test status
Simulation time 438521726 ps
CPU time 1.39 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207440 kb
Host smart-c7fda417-d9d8-4976-92fd-1d81bd71d3eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3225063350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.3225063350
Directory /workspace/32.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2653031743
Short name T576
Test name
Test status
Simulation time 182563228 ps
CPU time 2.23 seconds
Started Aug 10 07:13:00 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207636 kb
Host smart-09f11bef-1fc9-4b53-87c6-78b80ea7e0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
31743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2653031743
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4038723912
Short name T3485
Test name
Test status
Simulation time 173677358 ps
CPU time 0.93 seconds
Started Aug 10 07:12:55 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207556 kb
Host smart-fae78683-5019-4994-b3d6-80cdc83cfa8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4038723912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4038723912
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3185097262
Short name T858
Test name
Test status
Simulation time 144457255 ps
CPU time 0.85 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207704 kb
Host smart-cb8af0a9-9d4d-451f-9af8-918a81d1ea86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
97262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3185097262
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3046783374
Short name T590
Test name
Test status
Simulation time 303188757 ps
CPU time 1.09 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:00 PM PDT 24
Peak memory 207400 kb
Host smart-194b5a93-967a-4640-b3ee-64578dc60475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467
83374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3046783374
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.2304153308
Short name T3419
Test name
Test status
Simulation time 2676694821 ps
CPU time 26.62 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:13:25 PM PDT 24
Peak memory 224364 kb
Host smart-dec13cb6-d7c1-4ee9-9001-1261cce8a2d1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2304153308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.2304153308
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.9365955
Short name T3102
Test name
Test status
Simulation time 8963732580 ps
CPU time 58.36 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 207764 kb
Host smart-98bf4274-f4a7-4014-a561-48fe38b120a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=9365955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.9365955
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2757718135
Short name T1362
Test name
Test status
Simulation time 174827960 ps
CPU time 0.93 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:00 PM PDT 24
Peak memory 207516 kb
Host smart-de1c2c2d-ce1a-47b9-a4d8-e782af62b89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27577
18135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2757718135
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.4039682712
Short name T45
Test name
Test status
Simulation time 28821999381 ps
CPU time 41.53 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:39 PM PDT 24
Peak memory 207824 kb
Host smart-eb574da2-cdce-4e90-91e0-d74738ff3ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
82712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.4039682712
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3508531243
Short name T790
Test name
Test status
Simulation time 10364540475 ps
CPU time 13.43 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207804 kb
Host smart-59d25af2-4f0a-41e5-bef5-6e8defef109a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
31243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3508531243
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3782293350
Short name T3399
Test name
Test status
Simulation time 3807392760 ps
CPU time 31.89 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:29 PM PDT 24
Peak memory 219448 kb
Host smart-82800705-366a-4b82-baa8-6848f591414d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3782293350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3782293350
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3683076517
Short name T2070
Test name
Test status
Simulation time 1703993741 ps
CPU time 17.03 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:13:14 PM PDT 24
Peak memory 216688 kb
Host smart-b7b32226-ed6a-4184-9a7a-07420c88a3ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3683076517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3683076517
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.320678732
Short name T3128
Test name
Test status
Simulation time 298639609 ps
CPU time 1.03 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:12:59 PM PDT 24
Peak memory 207568 kb
Host smart-a3cdad44-b7cb-4482-a394-acbb12706a97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=320678732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.320678732
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1793730343
Short name T1359
Test name
Test status
Simulation time 192835131 ps
CPU time 1 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:58 PM PDT 24
Peak memory 207504 kb
Host smart-cb946a21-809e-42df-a017-751978bc2d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
30343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1793730343
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3258773740
Short name T886
Test name
Test status
Simulation time 2350357388 ps
CPU time 63.92 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:14:02 PM PDT 24
Peak memory 217744 kb
Host smart-75a9be08-d1f1-4d5d-844c-0467e64fcb39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3258773740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3258773740
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3603907953
Short name T2172
Test name
Test status
Simulation time 201468488 ps
CPU time 0.94 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207548 kb
Host smart-6978c33b-ce2d-4f84-bbc7-dcf0bd13699a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3603907953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3603907953
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.726774036
Short name T3404
Test name
Test status
Simulation time 141964068 ps
CPU time 0.81 seconds
Started Aug 10 07:12:55 PM PDT 24
Finished Aug 10 07:12:56 PM PDT 24
Peak memory 207580 kb
Host smart-b806f452-3dde-4735-a745-4e51107ec586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72677
4036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.726774036
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3895592987
Short name T1879
Test name
Test status
Simulation time 161231637 ps
CPU time 0.83 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:12:59 PM PDT 24
Peak memory 207468 kb
Host smart-a46d73fd-c6e1-4184-afbe-405af280ffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
92987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3895592987
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1955393170
Short name T626
Test name
Test status
Simulation time 212774458 ps
CPU time 0.91 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:00 PM PDT 24
Peak memory 207572 kb
Host smart-ebec65d6-bdc0-488d-858b-1ab8ea9544c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19553
93170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1955393170
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1775205561
Short name T1121
Test name
Test status
Simulation time 148058071 ps
CPU time 0.87 seconds
Started Aug 10 07:13:00 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207480 kb
Host smart-b94e7796-a93e-4f39-9bdd-f5ac14330893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17752
05561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1775205561
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1080816688
Short name T3506
Test name
Test status
Simulation time 166839515 ps
CPU time 0.85 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:12:58 PM PDT 24
Peak memory 207564 kb
Host smart-649303c0-a4e8-4c4b-bfb0-4f792f7abb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
16688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1080816688
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3364936203
Short name T2451
Test name
Test status
Simulation time 234379189 ps
CPU time 0.97 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207412 kb
Host smart-34eddf54-c306-47e2-bf26-0eacda242871
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3364936203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3364936203
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.4236324565
Short name T1054
Test name
Test status
Simulation time 176118639 ps
CPU time 0.83 seconds
Started Aug 10 07:13:00 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207496 kb
Host smart-ac5b7b48-2b37-416b-a93b-a2939c798f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
24565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.4236324565
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1068657294
Short name T1693
Test name
Test status
Simulation time 68530491 ps
CPU time 0.71 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:12:59 PM PDT 24
Peak memory 207480 kb
Host smart-391d9416-7133-45d6-bad7-b3047b295ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686
57294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1068657294
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.811815617
Short name T96
Test name
Test status
Simulation time 22405648317 ps
CPU time 57.4 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 216020 kb
Host smart-bc520aaf-cc32-4c52-86e4-acbd5782b40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81181
5617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.811815617
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3820258665
Short name T3391
Test name
Test status
Simulation time 152784591 ps
CPU time 0.85 seconds
Started Aug 10 07:12:57 PM PDT 24
Finished Aug 10 07:12:58 PM PDT 24
Peak memory 207548 kb
Host smart-d36ec4a0-7253-4237-98ec-7fcc3501215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
58665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3820258665
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1071336973
Short name T760
Test name
Test status
Simulation time 194179373 ps
CPU time 1.02 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207576 kb
Host smart-7aebe5c2-6ae2-4f07-ac48-dd7508a36c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10713
36973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1071336973
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3128823237
Short name T2584
Test name
Test status
Simulation time 230142471 ps
CPU time 0.94 seconds
Started Aug 10 07:12:56 PM PDT 24
Finished Aug 10 07:12:57 PM PDT 24
Peak memory 207588 kb
Host smart-91acef66-a403-4852-88ae-da7fea691278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31288
23237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3128823237
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2424154266
Short name T262
Test name
Test status
Simulation time 160918382 ps
CPU time 0.88 seconds
Started Aug 10 07:12:59 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207536 kb
Host smart-2c8402a6-189c-46aa-8b76-ae624471d58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24241
54266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2424154266
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2608019504
Short name T2410
Test name
Test status
Simulation time 156419075 ps
CPU time 0.85 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207420 kb
Host smart-bdc3b9af-d286-419e-ad97-f6636497c514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26080
19504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2608019504
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_rx_full.2296394123
Short name T643
Test name
Test status
Simulation time 279353817 ps
CPU time 1.12 seconds
Started Aug 10 07:13:01 PM PDT 24
Finished Aug 10 07:13:02 PM PDT 24
Peak memory 207456 kb
Host smart-52f8c424-02b6-4c2f-a383-50ea9b82cb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22963
94123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.2296394123
Directory /workspace/32.usbdev_rx_full/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1857304985
Short name T2018
Test name
Test status
Simulation time 228297996 ps
CPU time 0.93 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:12:59 PM PDT 24
Peak memory 207464 kb
Host smart-98ff92e1-bc08-4f1b-9cb4-d53b38b56d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18573
04985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1857304985
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3652763708
Short name T482
Test name
Test status
Simulation time 189883172 ps
CPU time 0.91 seconds
Started Aug 10 07:13:00 PM PDT 24
Finished Aug 10 07:13:01 PM PDT 24
Peak memory 207560 kb
Host smart-18ecfcc3-a15d-4a3e-818d-307ccca54c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
63708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3652763708
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3892455644
Short name T1300
Test name
Test status
Simulation time 208393447 ps
CPU time 0.97 seconds
Started Aug 10 07:13:15 PM PDT 24
Finished Aug 10 07:13:16 PM PDT 24
Peak memory 207584 kb
Host smart-d8a9f52a-9667-44a4-bcb9-a36e6560f763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38924
55644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3892455644
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2603631710
Short name T727
Test name
Test status
Simulation time 3172279137 ps
CPU time 24.3 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:34 PM PDT 24
Peak memory 224224 kb
Host smart-6799eee3-c855-4200-b6c2-982ad03c4871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2603631710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2603631710
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1279378278
Short name T1470
Test name
Test status
Simulation time 212955552 ps
CPU time 0.9 seconds
Started Aug 10 07:13:06 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207576 kb
Host smart-ab23cb4f-66fd-4e14-8789-42e3abcf6490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
78278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1279378278
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2611788758
Short name T3429
Test name
Test status
Simulation time 211463436 ps
CPU time 0.9 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207656 kb
Host smart-9d883351-aae7-4c09-a513-00701f077941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26117
88758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2611788758
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3050033943
Short name T552
Test name
Test status
Simulation time 930266954 ps
CPU time 2.46 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:13 PM PDT 24
Peak memory 207544 kb
Host smart-2da0e2de-9348-4c91-b4b1-fde7a12536a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
33943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3050033943
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3444077982
Short name T1713
Test name
Test status
Simulation time 3930510873 ps
CPU time 28.75 seconds
Started Aug 10 07:13:09 PM PDT 24
Finished Aug 10 07:13:38 PM PDT 24
Peak memory 207876 kb
Host smart-55464538-6ee0-4d9b-88c0-13e902d9a06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34440
77982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3444077982
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.328159345
Short name T2477
Test name
Test status
Simulation time 284166065 ps
CPU time 4.37 seconds
Started Aug 10 07:12:58 PM PDT 24
Finished Aug 10 07:13:03 PM PDT 24
Peak memory 207728 kb
Host smart-ac245de5-3ac2-4626-8ea4-933487ede19a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328159345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_host
_handshake.328159345
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_tx_rx_disruption.1297408325
Short name T1672
Test name
Test status
Simulation time 636479660 ps
CPU time 1.97 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207560 kb
Host smart-4f8062f1-76d2-4858-a2da-39a8dfb57ea8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297408325 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.usbdev_tx_rx_disruption.1297408325
Directory /workspace/32.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/320.usbdev_tx_rx_disruption.2955903700
Short name T913
Test name
Test status
Simulation time 477264624 ps
CPU time 1.46 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207596 kb
Host smart-1cc9c5ea-1945-4e9b-b74d-083c0c6b151d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955903700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 320.usbdev_tx_rx_disruption.2955903700
Directory /workspace/320.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/321.usbdev_tx_rx_disruption.2843259254
Short name T2187
Test name
Test status
Simulation time 444630676 ps
CPU time 1.4 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207556 kb
Host smart-c77d6516-73d8-427f-9730-d48be31ffbdb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843259254 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 321.usbdev_tx_rx_disruption.2843259254
Directory /workspace/321.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/322.usbdev_tx_rx_disruption.2669487101
Short name T3076
Test name
Test status
Simulation time 590236036 ps
CPU time 1.5 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207284 kb
Host smart-619942f2-7f93-4a89-b289-981615c8ab71
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669487101 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 322.usbdev_tx_rx_disruption.2669487101
Directory /workspace/322.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/323.usbdev_tx_rx_disruption.4014545496
Short name T1959
Test name
Test status
Simulation time 507895247 ps
CPU time 1.61 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207520 kb
Host smart-5dde15af-b45c-4f0f-8941-e6f3a130931f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014545496 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 323.usbdev_tx_rx_disruption.4014545496
Directory /workspace/323.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/324.usbdev_tx_rx_disruption.3829337434
Short name T1728
Test name
Test status
Simulation time 675891023 ps
CPU time 1.8 seconds
Started Aug 10 07:18:21 PM PDT 24
Finished Aug 10 07:18:23 PM PDT 24
Peak memory 207480 kb
Host smart-cc21993c-7b8d-43ec-bfe7-9948677208cc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829337434 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 324.usbdev_tx_rx_disruption.3829337434
Directory /workspace/324.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/325.usbdev_tx_rx_disruption.4172630771
Short name T2164
Test name
Test status
Simulation time 451385252 ps
CPU time 1.46 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207760 kb
Host smart-1f686bfa-6247-4f69-8989-a9aa826fa96b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172630771 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 325.usbdev_tx_rx_disruption.4172630771
Directory /workspace/325.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/326.usbdev_tx_rx_disruption.1015754108
Short name T123
Test name
Test status
Simulation time 681478380 ps
CPU time 1.96 seconds
Started Aug 10 07:18:14 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207528 kb
Host smart-cd492996-2081-46f1-a77f-796f234c3493
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015754108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 326.usbdev_tx_rx_disruption.1015754108
Directory /workspace/326.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/327.usbdev_tx_rx_disruption.76537158
Short name T2308
Test name
Test status
Simulation time 615789775 ps
CPU time 1.63 seconds
Started Aug 10 07:18:22 PM PDT 24
Finished Aug 10 07:18:23 PM PDT 24
Peak memory 207480 kb
Host smart-fcd2675b-89fb-4fc2-b15d-402ec568fed7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76537158 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 327.usbdev_tx_rx_disruption.76537158
Directory /workspace/327.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/328.usbdev_tx_rx_disruption.4134041349
Short name T2327
Test name
Test status
Simulation time 467766818 ps
CPU time 1.45 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207568 kb
Host smart-9d31c059-547f-428e-8abd-44946a630366
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134041349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 328.usbdev_tx_rx_disruption.4134041349
Directory /workspace/328.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/329.usbdev_tx_rx_disruption.3214283526
Short name T214
Test name
Test status
Simulation time 658119809 ps
CPU time 1.98 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207580 kb
Host smart-3d8d1ffb-5e97-46db-99b2-9f72390819fb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214283526 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 329.usbdev_tx_rx_disruption.3214283526
Directory /workspace/329.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3293534926
Short name T234
Test name
Test status
Simulation time 42025431 ps
CPU time 0.7 seconds
Started Aug 10 07:13:27 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207592 kb
Host smart-82e9aeb5-23dc-47ba-8cb2-33c0b7ec348e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3293534926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3293534926
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.735398835
Short name T2339
Test name
Test status
Simulation time 11175092822 ps
CPU time 15.7 seconds
Started Aug 10 07:13:15 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 207852 kb
Host smart-5c8683fb-a66e-416f-88a1-ea292d9b1eec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735398835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_disconnect.735398835
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1690166273
Short name T2523
Test name
Test status
Simulation time 13765072397 ps
CPU time 16.21 seconds
Started Aug 10 07:13:15 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 216040 kb
Host smart-e3779c91-5780-4131-b6bc-db1fa5a1e595
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690166273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1690166273
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2510770730
Short name T3070
Test name
Test status
Simulation time 30563781065 ps
CPU time 36.33 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207896 kb
Host smart-72831789-3d62-49d5-bd7d-ca10d63d11c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510770730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.2510770730
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1567854042
Short name T1804
Test name
Test status
Simulation time 174994987 ps
CPU time 0.94 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207560 kb
Host smart-2ba7c355-df01-440b-ab0c-0a798c1f52c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
54042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1567854042
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2083271949
Short name T1697
Test name
Test status
Simulation time 147931940 ps
CPU time 0.84 seconds
Started Aug 10 07:13:09 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207432 kb
Host smart-419732c9-b453-4d8f-93e9-217de01f7a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20832
71949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2083271949
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.4106874733
Short name T2640
Test name
Test status
Simulation time 256754371 ps
CPU time 0.99 seconds
Started Aug 10 07:13:06 PM PDT 24
Finished Aug 10 07:13:07 PM PDT 24
Peak memory 207532 kb
Host smart-ae1c41e3-6ea2-4332-a6da-8fcd9a11d716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068
74733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.4106874733
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.650122490
Short name T358
Test name
Test status
Simulation time 1236137016 ps
CPU time 2.92 seconds
Started Aug 10 07:13:14 PM PDT 24
Finished Aug 10 07:13:17 PM PDT 24
Peak memory 207796 kb
Host smart-f938a83d-842f-4b0a-a2cb-b27eccfcc3e6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=650122490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.650122490
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.972601176
Short name T1933
Test name
Test status
Simulation time 21077537151 ps
CPU time 36.49 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:47 PM PDT 24
Peak memory 207860 kb
Host smart-be67f212-a851-45b0-9020-35ae4f4eac47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97260
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.972601176
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.3691290289
Short name T3466
Test name
Test status
Simulation time 479448290 ps
CPU time 8.03 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:13:16 PM PDT 24
Peak memory 207740 kb
Host smart-1d35326d-e934-4c62-b56c-38615130387c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691290289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3691290289
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3543186514
Short name T3327
Test name
Test status
Simulation time 846115887 ps
CPU time 2.01 seconds
Started Aug 10 07:13:06 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 207560 kb
Host smart-03ef653d-36a2-408a-8c72-529409eb58a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35431
86514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3543186514
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_enable.3547903826
Short name T1194
Test name
Test status
Simulation time 70442870 ps
CPU time 0.75 seconds
Started Aug 10 07:13:15 PM PDT 24
Finished Aug 10 07:13:16 PM PDT 24
Peak memory 207540 kb
Host smart-351ad734-0469-418d-a3de-33945293c31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
03826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3547903826
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2106928085
Short name T1376
Test name
Test status
Simulation time 885008222 ps
CPU time 2.26 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 207772 kb
Host smart-1aa8c2e3-1ff0-4347-b255-33ad4a348309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
28085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2106928085
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_types.1358424141
Short name T3511
Test name
Test status
Simulation time 147545796 ps
CPU time 0.82 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207380 kb
Host smart-3101a60a-bf2e-4227-a16a-9b446ab0076e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1358424141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.1358424141
Directory /workspace/33.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2598870370
Short name T2552
Test name
Test status
Simulation time 284292886 ps
CPU time 2.44 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 207728 kb
Host smart-fa200808-8f6e-41ee-ab88-fa006c4d4570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25988
70370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2598870370
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1778459712
Short name T1757
Test name
Test status
Simulation time 190101464 ps
CPU time 0.99 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 215908 kb
Host smart-20943259-ce2b-46dd-b94f-735f730e7eac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1778459712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1778459712
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.215574992
Short name T2294
Test name
Test status
Simulation time 143674419 ps
CPU time 0.79 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207512 kb
Host smart-c46b704f-e069-411e-968b-49e1c5df67d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
4992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.215574992
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3500447649
Short name T3335
Test name
Test status
Simulation time 209708707 ps
CPU time 0.97 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207492 kb
Host smart-209b43ea-7331-4f39-88b6-b41081b8dc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004
47649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3500447649
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1935550743
Short name T1059
Test name
Test status
Simulation time 3233961807 ps
CPU time 27.11 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:13:35 PM PDT 24
Peak memory 224216 kb
Host smart-b13b37c9-ac83-4b6f-a3c1-a806192b5e1c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1935550743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1935550743
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1998351736
Short name T1173
Test name
Test status
Simulation time 5530489946 ps
CPU time 36.28 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207824 kb
Host smart-4bd5fce1-251d-415d-85f0-b58846671e02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1998351736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1998351736
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3126016151
Short name T1015
Test name
Test status
Simulation time 231636368 ps
CPU time 0.97 seconds
Started Aug 10 07:13:06 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207576 kb
Host smart-1999fcaa-9247-440f-89f3-798a390572bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31260
16151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3126016151
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.970936125
Short name T2632
Test name
Test status
Simulation time 31261737221 ps
CPU time 44.24 seconds
Started Aug 10 07:13:06 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207884 kb
Host smart-af8e0571-607a-4717-bbdc-2cb24c42d637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97093
6125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.970936125
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3006266462
Short name T3301
Test name
Test status
Simulation time 9499964988 ps
CPU time 12.32 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:13:20 PM PDT 24
Peak memory 207904 kb
Host smart-6a897484-d1bf-4a8d-b404-bff380a025df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062
66462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3006266462
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1043611893
Short name T1048
Test name
Test status
Simulation time 4907776880 ps
CPU time 145.2 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:15:33 PM PDT 24
Peak memory 224240 kb
Host smart-ebbf638e-8fbd-4f1c-a997-37b7c5b825bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1043611893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1043611893
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3188629864
Short name T3014
Test name
Test status
Simulation time 3695316638 ps
CPU time 108.08 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 217340 kb
Host smart-66ea4404-5898-422e-a3c1-40c4863a1117
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3188629864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3188629864
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2677336175
Short name T3334
Test name
Test status
Simulation time 295385081 ps
CPU time 1.1 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207596 kb
Host smart-9b94b33f-44fe-46b4-9b7e-3736b70f61dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2677336175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2677336175
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1300385526
Short name T3374
Test name
Test status
Simulation time 192075162 ps
CPU time 0.94 seconds
Started Aug 10 07:13:08 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 207596 kb
Host smart-328fe197-0321-405a-9eee-06136a9a4d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13003
85526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1300385526
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1359887441
Short name T3241
Test name
Test status
Simulation time 2692034486 ps
CPU time 20.86 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207912 kb
Host smart-2d2855e0-221d-4f79-9516-900fb10c012b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1359887441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1359887441
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2163359335
Short name T671
Test name
Test status
Simulation time 177634717 ps
CPU time 0.86 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207560 kb
Host smart-1f8dc63e-6c4e-4348-9ca0-352b0bee97b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2163359335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2163359335
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3453233790
Short name T259
Test name
Test status
Simulation time 148468495 ps
CPU time 0.85 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207604 kb
Host smart-4e3ac2be-61e3-4d31-b5f0-5437db19fa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
33790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3453233790
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2610479390
Short name T135
Test name
Test status
Simulation time 216201684 ps
CPU time 1.01 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:09 PM PDT 24
Peak memory 207572 kb
Host smart-dd317936-dd1e-4635-b86b-f4cfd83bcece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26104
79390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2610479390
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1992922727
Short name T2049
Test name
Test status
Simulation time 188535776 ps
CPU time 0.86 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:08 PM PDT 24
Peak memory 207512 kb
Host smart-ef230bec-40a5-42e6-b675-256d6c851761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
22727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1992922727
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3212352101
Short name T2320
Test name
Test status
Simulation time 170762769 ps
CPU time 0.88 seconds
Started Aug 10 07:13:10 PM PDT 24
Finished Aug 10 07:13:11 PM PDT 24
Peak memory 207604 kb
Host smart-0bbed9d1-fb4c-4b0f-9229-a92b3ce18deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32123
52101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3212352101
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1096557044
Short name T1853
Test name
Test status
Simulation time 193911200 ps
CPU time 0.88 seconds
Started Aug 10 07:13:09 PM PDT 24
Finished Aug 10 07:13:10 PM PDT 24
Peak memory 207500 kb
Host smart-af712f8a-d2f6-4dde-8498-8f94634d0978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10965
57044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1096557044
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3936653742
Short name T177
Test name
Test status
Simulation time 148318283 ps
CPU time 0.86 seconds
Started Aug 10 07:13:23 PM PDT 24
Finished Aug 10 07:13:24 PM PDT 24
Peak memory 207596 kb
Host smart-dd0e1508-49f0-449b-ba04-272da4779d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
53742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3936653742
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2231756207
Short name T231
Test name
Test status
Simulation time 220773064 ps
CPU time 1.05 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 207600 kb
Host smart-7414101b-4ba8-40e3-b89c-db6f428b6092
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2231756207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2231756207
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2142322903
Short name T685
Test name
Test status
Simulation time 148220235 ps
CPU time 0.89 seconds
Started Aug 10 07:13:17 PM PDT 24
Finished Aug 10 07:13:18 PM PDT 24
Peak memory 207444 kb
Host smart-9769c5aa-0a5e-4ca5-8eb8-dfc6b1c4d1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
22903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2142322903
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3047002791
Short name T544
Test name
Test status
Simulation time 33422597 ps
CPU time 0.65 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 207572 kb
Host smart-2f1473b9-dd3f-4231-ab1c-5de109339f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30470
02791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3047002791
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1126396024
Short name T3598
Test name
Test status
Simulation time 17246458139 ps
CPU time 40.57 seconds
Started Aug 10 07:13:27 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 216020 kb
Host smart-1a745c3e-be64-4954-98ca-bf5e8479cd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11263
96024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1126396024
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1898450775
Short name T762
Test name
Test status
Simulation time 178529989 ps
CPU time 0.88 seconds
Started Aug 10 07:13:25 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 207568 kb
Host smart-6fea0334-abab-4a33-b721-54f617fad7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18984
50775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1898450775
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2843631027
Short name T3125
Test name
Test status
Simulation time 237118409 ps
CPU time 0.97 seconds
Started Aug 10 07:13:22 PM PDT 24
Finished Aug 10 07:13:23 PM PDT 24
Peak memory 207540 kb
Host smart-9dab407b-b23a-41c2-ba3d-028fc1970d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28436
31027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2843631027
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2876951668
Short name T2424
Test name
Test status
Simulation time 183780085 ps
CPU time 0.92 seconds
Started Aug 10 07:13:25 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 207584 kb
Host smart-886a6c49-1c32-4c9d-9873-458ab16f80db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
51668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2876951668
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3360489829
Short name T2789
Test name
Test status
Simulation time 192518376 ps
CPU time 0.93 seconds
Started Aug 10 07:13:23 PM PDT 24
Finished Aug 10 07:13:24 PM PDT 24
Peak memory 207580 kb
Host smart-9e855602-3fbf-4bba-871d-da90702488ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33604
89829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3360489829
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1485301481
Short name T2174
Test name
Test status
Simulation time 138550192 ps
CPU time 0.85 seconds
Started Aug 10 07:13:18 PM PDT 24
Finished Aug 10 07:13:19 PM PDT 24
Peak memory 207500 kb
Host smart-1d161ad6-1244-4ccd-9b1d-ae325b0751a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
01481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1485301481
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1932382251
Short name T2633
Test name
Test status
Simulation time 163770024 ps
CPU time 0.83 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:25 PM PDT 24
Peak memory 207576 kb
Host smart-d0656220-1439-45cf-9413-c61ddc9e065a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19323
82251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1932382251
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2839599534
Short name T1403
Test name
Test status
Simulation time 159005099 ps
CPU time 0.95 seconds
Started Aug 10 07:13:17 PM PDT 24
Finished Aug 10 07:13:18 PM PDT 24
Peak memory 207536 kb
Host smart-10ccce6f-8c7a-4c49-aa42-648e3d3aa578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28395
99534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2839599534
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1273253138
Short name T1913
Test name
Test status
Simulation time 205839633 ps
CPU time 0.97 seconds
Started Aug 10 07:13:27 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207468 kb
Host smart-66f36cd4-8691-4ad4-98e2-1217a32bab30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
53138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1273253138
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2963232721
Short name T3106
Test name
Test status
Simulation time 2235243326 ps
CPU time 61.38 seconds
Started Aug 10 07:13:19 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 224260 kb
Host smart-0da959c4-8fab-4506-94ce-18c1ebeb1559
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2963232721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2963232721
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3455244298
Short name T1346
Test name
Test status
Simulation time 163720987 ps
CPU time 0.86 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 207532 kb
Host smart-f0dd520b-3261-43b1-bb86-df89533d593d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34552
44298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3455244298
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.663633758
Short name T602
Test name
Test status
Simulation time 172470486 ps
CPU time 0.88 seconds
Started Aug 10 07:13:22 PM PDT 24
Finished Aug 10 07:13:23 PM PDT 24
Peak memory 207516 kb
Host smart-1b07c6b2-3d53-40f5-900a-af439b794719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66363
3758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.663633758
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3125319392
Short name T3401
Test name
Test status
Simulation time 830625724 ps
CPU time 2.17 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 207680 kb
Host smart-0910e362-aca5-4069-ae17-87c065e9cea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31253
19392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3125319392
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.2432122597
Short name T1075
Test name
Test status
Simulation time 2365343279 ps
CPU time 23.29 seconds
Started Aug 10 07:13:17 PM PDT 24
Finished Aug 10 07:13:40 PM PDT 24
Peak memory 217044 kb
Host smart-b12c14e8-c9fb-4378-9cfe-52776dfbbbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
22597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2432122597
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2282935475
Short name T654
Test name
Test status
Simulation time 1185295175 ps
CPU time 24.97 seconds
Started Aug 10 07:13:07 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207572 kb
Host smart-360090ee-2785-430d-a72b-f7cdf2179741
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282935475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2282935475
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/330.usbdev_tx_rx_disruption.2904356947
Short name T1677
Test name
Test status
Simulation time 514183896 ps
CPU time 1.58 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207584 kb
Host smart-e1222258-e601-4fdb-915f-a4af5ac13980
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904356947 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 330.usbdev_tx_rx_disruption.2904356947
Directory /workspace/330.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/331.usbdev_tx_rx_disruption.1148277969
Short name T1473
Test name
Test status
Simulation time 626871217 ps
CPU time 1.81 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207480 kb
Host smart-df0ed37f-2de0-42f4-afd3-90b6ea2c3f90
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148277969 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 331.usbdev_tx_rx_disruption.1148277969
Directory /workspace/331.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/332.usbdev_tx_rx_disruption.3049713724
Short name T2369
Test name
Test status
Simulation time 512430541 ps
CPU time 1.5 seconds
Started Aug 10 07:18:13 PM PDT 24
Finished Aug 10 07:18:15 PM PDT 24
Peak memory 207548 kb
Host smart-3a62b996-4935-4c07-9d03-498f0ffbc861
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049713724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 332.usbdev_tx_rx_disruption.3049713724
Directory /workspace/332.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/333.usbdev_tx_rx_disruption.386847345
Short name T176
Test name
Test status
Simulation time 472641939 ps
CPU time 1.45 seconds
Started Aug 10 07:18:14 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207536 kb
Host smart-d8efd0a4-e408-4bdf-8c75-f567c17cee4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386847345 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 333.usbdev_tx_rx_disruption.386847345
Directory /workspace/333.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/334.usbdev_tx_rx_disruption.2427064248
Short name T3540
Test name
Test status
Simulation time 683448018 ps
CPU time 1.81 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207440 kb
Host smart-e48c95b1-6cbd-4698-9324-24f135e1765d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427064248 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 334.usbdev_tx_rx_disruption.2427064248
Directory /workspace/334.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/335.usbdev_tx_rx_disruption.3559120297
Short name T1939
Test name
Test status
Simulation time 489077791 ps
CPU time 1.6 seconds
Started Aug 10 07:18:21 PM PDT 24
Finished Aug 10 07:18:23 PM PDT 24
Peak memory 207480 kb
Host smart-90fdaa32-ff95-4102-b674-8175e523ca68
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559120297 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 335.usbdev_tx_rx_disruption.3559120297
Directory /workspace/335.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/336.usbdev_tx_rx_disruption.1915939886
Short name T808
Test name
Test status
Simulation time 515317258 ps
CPU time 1.53 seconds
Started Aug 10 07:18:21 PM PDT 24
Finished Aug 10 07:18:23 PM PDT 24
Peak memory 207480 kb
Host smart-7d6c6f55-e9c4-473e-a736-e86b11d45875
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915939886 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 336.usbdev_tx_rx_disruption.1915939886
Directory /workspace/336.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/337.usbdev_tx_rx_disruption.991598316
Short name T1325
Test name
Test status
Simulation time 589409763 ps
CPU time 1.6 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207560 kb
Host smart-0cbd8cb2-6e6e-430d-834d-965db9a524bc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991598316 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 337.usbdev_tx_rx_disruption.991598316
Directory /workspace/337.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/338.usbdev_tx_rx_disruption.3894871438
Short name T1754
Test name
Test status
Simulation time 566262640 ps
CPU time 1.69 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207572 kb
Host smart-a4879fa5-f7f4-4c0f-b935-0a338625db0b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894871438 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 338.usbdev_tx_rx_disruption.3894871438
Directory /workspace/338.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/339.usbdev_tx_rx_disruption.769549794
Short name T1184
Test name
Test status
Simulation time 562195231 ps
CPU time 1.67 seconds
Started Aug 10 07:18:18 PM PDT 24
Finished Aug 10 07:18:20 PM PDT 24
Peak memory 207664 kb
Host smart-c377c353-accd-43d8-86e6-122717280d15
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769549794 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 339.usbdev_tx_rx_disruption.769549794
Directory /workspace/339.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3876646303
Short name T3455
Test name
Test status
Simulation time 72186452 ps
CPU time 0.72 seconds
Started Aug 10 07:13:44 PM PDT 24
Finished Aug 10 07:13:45 PM PDT 24
Peak memory 207484 kb
Host smart-8e0ef55b-c40b-4b49-84ac-b7b5b6c15c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3876646303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3876646303
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1241255537
Short name T829
Test name
Test status
Simulation time 6748828966 ps
CPU time 8.38 seconds
Started Aug 10 07:13:22 PM PDT 24
Finished Aug 10 07:13:30 PM PDT 24
Peak memory 216008 kb
Host smart-f729d8c7-35f3-4ac8-89f7-d84cb95b4127
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241255537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.1241255537
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3817576853
Short name T1275
Test name
Test status
Simulation time 29398334219 ps
CPU time 34.36 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:58 PM PDT 24
Peak memory 207784 kb
Host smart-b886df55-5c56-4add-8fc8-baf84f654b04
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817576853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.3817576853
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.538100918
Short name T3363
Test name
Test status
Simulation time 145599390 ps
CPU time 0.89 seconds
Started Aug 10 07:13:26 PM PDT 24
Finished Aug 10 07:13:27 PM PDT 24
Peak memory 207504 kb
Host smart-c60bff42-a27a-4d7b-bed5-6126c2e7c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53810
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.538100918
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3237052317
Short name T3074
Test name
Test status
Simulation time 167874214 ps
CPU time 0.84 seconds
Started Aug 10 07:13:19 PM PDT 24
Finished Aug 10 07:13:20 PM PDT 24
Peak memory 207496 kb
Host smart-036aa67c-2aa7-4f80-aefc-2de10f680a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
52317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3237052317
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2620676090
Short name T1736
Test name
Test status
Simulation time 554743196 ps
CPU time 1.81 seconds
Started Aug 10 07:13:17 PM PDT 24
Finished Aug 10 07:13:19 PM PDT 24
Peak memory 207536 kb
Host smart-019ee53f-8196-4b1d-9651-b27a823cd21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26206
76090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2620676090
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.4059920236
Short name T2666
Test name
Test status
Simulation time 1360838739 ps
CPU time 3.41 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207704 kb
Host smart-4c1b913d-e0a0-47d3-8200-3544ce61cf28
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4059920236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.4059920236
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2056906542
Short name T3137
Test name
Test status
Simulation time 47728591062 ps
CPU time 79.71 seconds
Started Aug 10 07:13:26 PM PDT 24
Finished Aug 10 07:14:46 PM PDT 24
Peak memory 207760 kb
Host smart-5d1c4932-7b86-4cc0-ad2a-4fb6651bc9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569
06542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2056906542
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.2586195801
Short name T891
Test name
Test status
Simulation time 3432323773 ps
CPU time 30.03 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207772 kb
Host smart-0a15110d-6d54-48d7-954e-01a02b6db9f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586195801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.2586195801
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.427024137
Short name T377
Test name
Test status
Simulation time 765270888 ps
CPU time 1.88 seconds
Started Aug 10 07:13:25 PM PDT 24
Finished Aug 10 07:13:27 PM PDT 24
Peak memory 207476 kb
Host smart-62cb3d01-db59-492b-b945-0777d6b86b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.427024137
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3461149956
Short name T1903
Test name
Test status
Simulation time 161596131 ps
CPU time 0.85 seconds
Started Aug 10 07:13:27 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207516 kb
Host smart-15c506e8-4a8d-47dd-b8ee-9385ec1d8a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
49956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3461149956
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.145211098
Short name T2005
Test name
Test status
Simulation time 75519110 ps
CPU time 0.75 seconds
Started Aug 10 07:13:25 PM PDT 24
Finished Aug 10 07:13:26 PM PDT 24
Peak memory 207492 kb
Host smart-77f2dac5-0d94-4edc-86f2-cca2a2f094ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14521
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.145211098
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1031354165
Short name T1906
Test name
Test status
Simulation time 877353413 ps
CPU time 2.44 seconds
Started Aug 10 07:13:26 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207580 kb
Host smart-2aaad7eb-476a-4d44-948f-01081c32c544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313
54165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1031354165
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_types.2215259810
Short name T385
Test name
Test status
Simulation time 695457773 ps
CPU time 1.77 seconds
Started Aug 10 07:13:26 PM PDT 24
Finished Aug 10 07:13:28 PM PDT 24
Peak memory 207468 kb
Host smart-0feabd2e-4df1-4d9b-baa3-f3ac1d590ebc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2215259810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.2215259810
Directory /workspace/34.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.121413197
Short name T2214
Test name
Test status
Simulation time 482441822 ps
CPU time 3.1 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:27 PM PDT 24
Peak memory 207676 kb
Host smart-22025cad-cfa4-4932-b803-9f5ba4bdc21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12141
3197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.121413197
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3996019419
Short name T1911
Test name
Test status
Simulation time 219241917 ps
CPU time 1.08 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 215972 kb
Host smart-f08c63e3-dcd8-4a15-b0b2-ad65efc964fc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3996019419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3996019419
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2541777072
Short name T2961
Test name
Test status
Simulation time 143865010 ps
CPU time 0.83 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 207572 kb
Host smart-139f886c-72d1-4a40-ad12-f630a7b1c6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25417
77072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2541777072
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2758564029
Short name T3526
Test name
Test status
Simulation time 206288018 ps
CPU time 0.92 seconds
Started Aug 10 07:13:21 PM PDT 24
Finished Aug 10 07:13:22 PM PDT 24
Peak memory 207604 kb
Host smart-d88c2606-0375-411e-bd44-7f48b99d5fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27585
64029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2758564029
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.602640561
Short name T3113
Test name
Test status
Simulation time 4061328100 ps
CPU time 38.75 seconds
Started Aug 10 07:13:18 PM PDT 24
Finished Aug 10 07:13:57 PM PDT 24
Peak memory 224284 kb
Host smart-47df17ef-105f-4f5d-8cc4-fc1f2e5b702b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=602640561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.602640561
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3641302553
Short name T2772
Test name
Test status
Simulation time 6863275425 ps
CPU time 44.61 seconds
Started Aug 10 07:13:19 PM PDT 24
Finished Aug 10 07:14:04 PM PDT 24
Peak memory 207676 kb
Host smart-3706cc8c-c835-4630-9d31-b7c3b2088bbd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3641302553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3641302553
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3671177669
Short name T2453
Test name
Test status
Simulation time 150987120 ps
CPU time 0.88 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207596 kb
Host smart-d1acdaf5-a986-40fe-b3f8-248b2c112cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36711
77669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3671177669
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1264277881
Short name T924
Test name
Test status
Simulation time 31251543652 ps
CPU time 46.61 seconds
Started Aug 10 07:13:33 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207900 kb
Host smart-09d3750c-dff0-4cee-a5f5-277f73bfed92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12642
77881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1264277881
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.4078304141
Short name T1909
Test name
Test status
Simulation time 9158277115 ps
CPU time 12.09 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207876 kb
Host smart-3d7d280b-e4cf-4f08-8472-a4050388aafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40783
04141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.4078304141
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4272203752
Short name T2387
Test name
Test status
Simulation time 5285380652 ps
CPU time 161.79 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 224248 kb
Host smart-9a8e4084-39e9-4547-917a-2b0baa673514
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4272203752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4272203752
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3012289201
Short name T1952
Test name
Test status
Simulation time 2596285011 ps
CPU time 26.74 seconds
Started Aug 10 07:13:29 PM PDT 24
Finished Aug 10 07:13:56 PM PDT 24
Peak memory 217588 kb
Host smart-12bb6f48-15ac-4468-9190-5f73e9206a72
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3012289201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3012289201
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1452951503
Short name T1180
Test name
Test status
Simulation time 268781958 ps
CPU time 1.02 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207564 kb
Host smart-b99327ad-b379-432b-8563-6142ba55256e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1452951503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1452951503
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2736314981
Short name T32
Test name
Test status
Simulation time 212709102 ps
CPU time 0.94 seconds
Started Aug 10 07:13:29 PM PDT 24
Finished Aug 10 07:13:30 PM PDT 24
Peak memory 207524 kb
Host smart-deac6d69-49a7-4581-a14c-4641869da4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
14981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2736314981
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3781635961
Short name T1107
Test name
Test status
Simulation time 1648945028 ps
CPU time 13.05 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207808 kb
Host smart-70ba1fdf-ccec-43c8-8b31-001234722619
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3781635961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3781635961
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2426265431
Short name T1195
Test name
Test status
Simulation time 171472187 ps
CPU time 0.82 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207592 kb
Host smart-96e29ed5-9512-4eeb-bebc-9a571a3601b4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2426265431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2426265431
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2298731452
Short name T1411
Test name
Test status
Simulation time 161383231 ps
CPU time 0.87 seconds
Started Aug 10 07:13:29 PM PDT 24
Finished Aug 10 07:13:30 PM PDT 24
Peak memory 207500 kb
Host smart-ff066f86-8f28-4e03-a25f-a2bec9cbb364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
31452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2298731452
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1977467010
Short name T156
Test name
Test status
Simulation time 217833783 ps
CPU time 1.06 seconds
Started Aug 10 07:13:33 PM PDT 24
Finished Aug 10 07:13:34 PM PDT 24
Peak memory 207544 kb
Host smart-56cb009f-9c63-43e1-8ebf-8285d846e11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774
67010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1977467010
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2690296608
Short name T1609
Test name
Test status
Simulation time 150105908 ps
CPU time 0.86 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207532 kb
Host smart-20b44642-5c75-4022-b4b0-82f3789ec431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
96608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2690296608
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4223549392
Short name T2501
Test name
Test status
Simulation time 191248702 ps
CPU time 0.92 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207560 kb
Host smart-c25c5cae-718f-47cf-a89e-81f7e8ae2d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
49392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4223549392
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2265882287
Short name T2117
Test name
Test status
Simulation time 172076223 ps
CPU time 0.85 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 207572 kb
Host smart-e5a65138-1cd7-4927-9b9b-086095da0b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22658
82287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2265882287
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1537041867
Short name T3472
Test name
Test status
Simulation time 188347528 ps
CPU time 0.88 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207740 kb
Host smart-2e3c36ed-71dd-4528-ad71-94e953846c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370
41867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1537041867
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.566659731
Short name T2342
Test name
Test status
Simulation time 228030474 ps
CPU time 1.02 seconds
Started Aug 10 07:13:33 PM PDT 24
Finished Aug 10 07:13:34 PM PDT 24
Peak memory 207576 kb
Host smart-c18998c4-0257-4a88-be16-32281333f20f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=566659731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.566659731
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1072414977
Short name T902
Test name
Test status
Simulation time 173488601 ps
CPU time 0.87 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 207528 kb
Host smart-b249288f-d03f-4970-ac35-ef83cd73ce86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
14977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1072414977
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.62424947
Short name T3160
Test name
Test status
Simulation time 31392361 ps
CPU time 0.68 seconds
Started Aug 10 07:13:29 PM PDT 24
Finished Aug 10 07:13:30 PM PDT 24
Peak memory 207428 kb
Host smart-0f2d45ac-9b51-4503-ad77-fa194bd8b4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62424
947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.62424947
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1766737909
Short name T3408
Test name
Test status
Simulation time 18478604145 ps
CPU time 47.81 seconds
Started Aug 10 07:13:33 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 216040 kb
Host smart-0ae9df33-cc16-43de-9524-455917c54c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
37909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1766737909
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2658179022
Short name T1277
Test name
Test status
Simulation time 157413930 ps
CPU time 0.83 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207544 kb
Host smart-f3f58b4b-7056-48f6-ac47-672a07adf6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26581
79022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2658179022
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2190253700
Short name T568
Test name
Test status
Simulation time 197506834 ps
CPU time 0.99 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207736 kb
Host smart-5138a597-0dd4-41fd-a452-21a329288a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
53700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2190253700
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3475691896
Short name T2492
Test name
Test status
Simulation time 164048660 ps
CPU time 0.9 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207572 kb
Host smart-880299eb-cf1d-456c-98f6-9f860386e93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
91896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3475691896
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3929343289
Short name T2013
Test name
Test status
Simulation time 148610451 ps
CPU time 0.82 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 207496 kb
Host smart-e0b26050-2d2f-46e3-909a-7df22e2c4e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39293
43289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3929343289
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3549239976
Short name T3457
Test name
Test status
Simulation time 148200087 ps
CPU time 0.83 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207544 kb
Host smart-a375c4f2-eed9-4880-b2ef-8d740e95c9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35492
39976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3549239976
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_rx_full.1665308114
Short name T51
Test name
Test status
Simulation time 253084678 ps
CPU time 1.07 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207520 kb
Host smart-d1b461e1-0a3e-42e0-b5d0-52fae803837f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16653
08114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.1665308114
Directory /workspace/34.usbdev_rx_full/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3431907931
Short name T1563
Test name
Test status
Simulation time 150388481 ps
CPU time 0.8 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207576 kb
Host smart-47ea0c27-a33b-4d01-9881-849d6cd666ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34319
07931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3431907931
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2904097407
Short name T739
Test name
Test status
Simulation time 164367077 ps
CPU time 0.86 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:32 PM PDT 24
Peak memory 207556 kb
Host smart-6ec5e0b2-bdba-41c2-94b3-374cf47e99b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29040
97407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2904097407
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1318416025
Short name T2242
Test name
Test status
Simulation time 268616415 ps
CPU time 1.04 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207532 kb
Host smart-217f938c-1ad6-4d89-abeb-ccd3992e7f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13184
16025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1318416025
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1176159742
Short name T1072
Test name
Test status
Simulation time 3336775531 ps
CPU time 93.75 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:15:05 PM PDT 24
Peak memory 217664 kb
Host smart-f5f347f5-4b95-4ac1-9e69-14fb0adf73d8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1176159742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1176159742
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3121111601
Short name T674
Test name
Test status
Simulation time 206006215 ps
CPU time 0.89 seconds
Started Aug 10 07:13:30 PM PDT 24
Finished Aug 10 07:13:31 PM PDT 24
Peak memory 207544 kb
Host smart-0a6db8bb-52c4-49bc-982d-49e963659b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
11601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3121111601
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2281373757
Short name T2350
Test name
Test status
Simulation time 170126400 ps
CPU time 0.89 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:13:33 PM PDT 24
Peak memory 207560 kb
Host smart-372453ef-0387-4124-9c5d-b625cd5bcd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
73757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2281373757
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.345538240
Short name T992
Test name
Test status
Simulation time 1361423219 ps
CPU time 3.34 seconds
Started Aug 10 07:13:31 PM PDT 24
Finished Aug 10 07:13:34 PM PDT 24
Peak memory 207772 kb
Host smart-da6a966b-3b97-40ee-ab82-7dd4945a91e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34553
8240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.345538240
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2159921562
Short name T2147
Test name
Test status
Simulation time 2298857721 ps
CPU time 62.84 seconds
Started Aug 10 07:13:32 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 216072 kb
Host smart-9dbeb675-615d-4689-a3fa-5b9b494c4617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21599
21562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2159921562
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1284332768
Short name T1022
Test name
Test status
Simulation time 4349014853 ps
CPU time 26.85 seconds
Started Aug 10 07:13:24 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207940 kb
Host smart-e1de6da0-2d3e-4a11-bc2f-a11a7f0ccddb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284332768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.1284332768
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_tx_rx_disruption.2110769617
Short name T1602
Test name
Test status
Simulation time 620719327 ps
CPU time 1.71 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207528 kb
Host smart-c55d753b-f22c-450d-bf28-7f917e92d940
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110769617 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.usbdev_tx_rx_disruption.2110769617
Directory /workspace/34.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/340.usbdev_tx_rx_disruption.1473003217
Short name T3121
Test name
Test status
Simulation time 472686172 ps
CPU time 1.54 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207516 kb
Host smart-88fcfdb7-0a85-49fd-86b1-36863f5f8b1b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473003217 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 340.usbdev_tx_rx_disruption.1473003217
Directory /workspace/340.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/341.usbdev_tx_rx_disruption.1192538106
Short name T2836
Test name
Test status
Simulation time 454596424 ps
CPU time 1.48 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207608 kb
Host smart-9e3eca1f-b994-40a5-8eed-e31ecf4b7455
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192538106 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 341.usbdev_tx_rx_disruption.1192538106
Directory /workspace/341.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/342.usbdev_tx_rx_disruption.2993849875
Short name T2648
Test name
Test status
Simulation time 477079414 ps
CPU time 1.63 seconds
Started Aug 10 07:18:18 PM PDT 24
Finished Aug 10 07:18:20 PM PDT 24
Peak memory 207664 kb
Host smart-164a054c-3c94-4ffe-8110-c34fd79db4e9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993849875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 342.usbdev_tx_rx_disruption.2993849875
Directory /workspace/342.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/343.usbdev_tx_rx_disruption.2533783500
Short name T122
Test name
Test status
Simulation time 503558378 ps
CPU time 1.58 seconds
Started Aug 10 07:18:22 PM PDT 24
Finished Aug 10 07:18:24 PM PDT 24
Peak memory 207480 kb
Host smart-cdf7b4c0-e64b-4f1f-a1f5-5fca94c487da
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533783500 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 343.usbdev_tx_rx_disruption.2533783500
Directory /workspace/343.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/344.usbdev_tx_rx_disruption.1658645964
Short name T2235
Test name
Test status
Simulation time 516089171 ps
CPU time 1.59 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207560 kb
Host smart-45ed68c5-ff41-46ab-8fff-ac7786bc011b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658645964 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 344.usbdev_tx_rx_disruption.1658645964
Directory /workspace/344.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/345.usbdev_tx_rx_disruption.3531900647
Short name T2002
Test name
Test status
Simulation time 637161999 ps
CPU time 1.66 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207452 kb
Host smart-140656dc-07b2-4306-bbb9-dd59f8097b31
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531900647 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 345.usbdev_tx_rx_disruption.3531900647
Directory /workspace/345.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/346.usbdev_tx_rx_disruption.303136259
Short name T271
Test name
Test status
Simulation time 604158586 ps
CPU time 1.68 seconds
Started Aug 10 07:18:14 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207492 kb
Host smart-2807792f-7a8d-4ba4-834e-d45db156c84d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303136259 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 346.usbdev_tx_rx_disruption.303136259
Directory /workspace/346.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/347.usbdev_tx_rx_disruption.3187286327
Short name T3347
Test name
Test status
Simulation time 469680463 ps
CPU time 1.39 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207248 kb
Host smart-68b7b7ce-1487-4927-8f94-eb1fb4337571
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187286327 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 347.usbdev_tx_rx_disruption.3187286327
Directory /workspace/347.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/349.usbdev_tx_rx_disruption.3241295061
Short name T558
Test name
Test status
Simulation time 505095789 ps
CPU time 1.63 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207528 kb
Host smart-079eb2c7-6e32-4942-a5bc-61961291ca74
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241295061 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 349.usbdev_tx_rx_disruption.3241295061
Directory /workspace/349.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.334939504
Short name T233
Test name
Test status
Simulation time 35969290 ps
CPU time 0.66 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207616 kb
Host smart-298bad23-1d8c-41eb-bf8c-dd7d60499924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=334939504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.334939504
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1168144522
Short name T2118
Test name
Test status
Simulation time 11545703479 ps
CPU time 14.04 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 208048 kb
Host smart-d59d97df-f5ab-4d63-93b6-66056b6162c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168144522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.1168144522
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1515924000
Short name T2475
Test name
Test status
Simulation time 14533694307 ps
CPU time 17.1 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:57 PM PDT 24
Peak memory 216044 kb
Host smart-88fe3b48-109a-48e3-bbce-1faa08b66c53
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515924000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1515924000
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3489665991
Short name T1368
Test name
Test status
Simulation time 28424882601 ps
CPU time 31.66 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:14:13 PM PDT 24
Peak memory 207864 kb
Host smart-5bd19ed8-ea68-41ff-b599-eecd6b4b7fd3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489665991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.3489665991
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1548084944
Short name T3402
Test name
Test status
Simulation time 230271128 ps
CPU time 0.94 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207524 kb
Host smart-8a86cc89-2dc0-4af2-868a-003a33afd51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
84944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1548084944
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.594667416
Short name T2486
Test name
Test status
Simulation time 224371875 ps
CPU time 0.97 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207548 kb
Host smart-18c3f35f-369e-4ecd-8b23-053c660fa595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59466
7416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.594667416
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3927614322
Short name T2642
Test name
Test status
Simulation time 510839077 ps
CPU time 1.65 seconds
Started Aug 10 07:13:44 PM PDT 24
Finished Aug 10 07:13:46 PM PDT 24
Peak memory 207464 kb
Host smart-83d28aaf-2d52-4991-8506-343c54d6362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39276
14322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3927614322
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.546144947
Short name T2574
Test name
Test status
Simulation time 767084920 ps
CPU time 2.06 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207752 kb
Host smart-407decbf-6600-4b70-9eac-86a3d72d629a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=546144947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.546144947
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.188130346
Short name T1755
Test name
Test status
Simulation time 13423291222 ps
CPU time 23.13 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:14:05 PM PDT 24
Peak memory 207716 kb
Host smart-d89d9edf-a89d-44b6-84a8-05c123860fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18813
0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.188130346
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.1390979247
Short name T1439
Test name
Test status
Simulation time 473047432 ps
CPU time 8.18 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207708 kb
Host smart-067a1248-bd52-49a0-9d99-d0299d40885f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390979247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1390979247
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.603973784
Short name T2277
Test name
Test status
Simulation time 863089404 ps
CPU time 1.87 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207528 kb
Host smart-f334fd46-3641-4eeb-a54b-eb248a40cb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60397
3784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.603973784
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.54898667
Short name T726
Test name
Test status
Simulation time 143956865 ps
CPU time 0.89 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207476 kb
Host smart-1884a63c-3392-4e64-9d57-9667fe47c7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54898
667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.54898667
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.616710616
Short name T3257
Test name
Test status
Simulation time 37757406 ps
CPU time 0.69 seconds
Started Aug 10 07:13:45 PM PDT 24
Finished Aug 10 07:13:46 PM PDT 24
Peak memory 207384 kb
Host smart-225fdcd8-3e03-41ca-a581-5028e469c587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61671
0616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.616710616
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3792801930
Short name T3315
Test name
Test status
Simulation time 760170631 ps
CPU time 2 seconds
Started Aug 10 07:13:46 PM PDT 24
Finished Aug 10 07:13:48 PM PDT 24
Peak memory 207592 kb
Host smart-7582514e-39d2-4d7b-9a67-7f4f0ec5f716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
01930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3792801930
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_types.1190031400
Short name T460
Test name
Test status
Simulation time 786269532 ps
CPU time 1.85 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207572 kb
Host smart-d5dca369-e935-4b2e-b560-8d3278025a1c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1190031400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.1190031400
Directory /workspace/35.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1760184947
Short name T1221
Test name
Test status
Simulation time 229159255 ps
CPU time 1.71 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207756 kb
Host smart-8805c0bf-7b8f-4ec6-900c-940508921669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
84947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1760184947
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1692496179
Short name T611
Test name
Test status
Simulation time 265000818 ps
CPU time 1.19 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 215860 kb
Host smart-1c6c002f-2fda-4da6-b0cb-ba145b39a93b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1692496179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1692496179
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1928205964
Short name T2314
Test name
Test status
Simulation time 189307086 ps
CPU time 0.84 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207500 kb
Host smart-edfdf66c-1fe0-45a8-b2ce-68624136081e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
05964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1928205964
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2760408573
Short name T888
Test name
Test status
Simulation time 244851483 ps
CPU time 0.99 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:45 PM PDT 24
Peak memory 207536 kb
Host smart-3b59650b-47ca-4cd2-8bcb-62d3c65455fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27604
08573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2760408573
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1897111605
Short name T1287
Test name
Test status
Simulation time 2781452752 ps
CPU time 28.16 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:14:10 PM PDT 24
Peak memory 224232 kb
Host smart-8a2287fb-b4da-4b02-81ef-a669905625c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1897111605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1897111605
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.418872573
Short name T3134
Test name
Test status
Simulation time 7015048391 ps
CPU time 44.75 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:14:28 PM PDT 24
Peak memory 207696 kb
Host smart-a258dccc-7067-4a6e-8c74-e8a67daac410
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=418872573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.418872573
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2596812675
Short name T3340
Test name
Test status
Simulation time 169913874 ps
CPU time 0.88 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207504 kb
Host smart-3593ada0-cd1f-4e81-8d07-9365f24f50bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
12675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2596812675
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.3819386815
Short name T1215
Test name
Test status
Simulation time 11691636767 ps
CPU time 15.34 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:58 PM PDT 24
Peak memory 207868 kb
Host smart-de5a07bb-1b8c-4f2e-99a4-92688d0463d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
86815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3819386815
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2551310891
Short name T1661
Test name
Test status
Simulation time 8557778702 ps
CPU time 11.13 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:53 PM PDT 24
Peak memory 207836 kb
Host smart-5dec2aef-55fa-47ca-b1f7-b08545c6bdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25513
10891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2551310891
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1210001856
Short name T2311
Test name
Test status
Simulation time 4004537683 ps
CPU time 30.91 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:14:13 PM PDT 24
Peak memory 219768 kb
Host smart-bf14346c-1666-48a5-b39c-d2beb8b4fd0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1210001856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1210001856
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2048065591
Short name T1991
Test name
Test status
Simulation time 2993119606 ps
CPU time 28.22 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:14:12 PM PDT 24
Peak memory 217928 kb
Host smart-67ac842e-fba2-4784-a969-90f66c08fdae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2048065591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2048065591
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1649789380
Short name T1581
Test name
Test status
Simulation time 244649898 ps
CPU time 1.01 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207560 kb
Host smart-8bfc58da-bf8a-439f-86e3-403204d4ec81
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1649789380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1649789380
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3068876929
Short name T2411
Test name
Test status
Simulation time 221032450 ps
CPU time 0.96 seconds
Started Aug 10 07:13:39 PM PDT 24
Finished Aug 10 07:13:40 PM PDT 24
Peak memory 207544 kb
Host smart-54bec49a-09ef-4732-bba6-dfb997f4c9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
76929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3068876929
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.17939176
Short name T3366
Test name
Test status
Simulation time 1730330544 ps
CPU time 16.11 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:57 PM PDT 24
Peak memory 215884 kb
Host smart-b71e6d8d-7f32-46bb-b91c-9bc7e92bebe8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=17939176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.17939176
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2358578571
Short name T616
Test name
Test status
Simulation time 176833703 ps
CPU time 0.87 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207560 kb
Host smart-6c7e1f9e-4f78-4517-8844-064dc1fbc0f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2358578571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2358578571
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.243323885
Short name T2434
Test name
Test status
Simulation time 142093743 ps
CPU time 0.85 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207468 kb
Host smart-6cdc877f-b816-4831-b5ef-24759455f9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24332
3885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.243323885
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.595320595
Short name T153
Test name
Test status
Simulation time 220615104 ps
CPU time 0.98 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207596 kb
Host smart-bdb8eb3a-005f-4f02-aef0-ebfadc73b7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59532
0595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.595320595
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3121545764
Short name T2685
Test name
Test status
Simulation time 147521300 ps
CPU time 0.89 seconds
Started Aug 10 07:13:39 PM PDT 24
Finished Aug 10 07:13:40 PM PDT 24
Peak memory 207500 kb
Host smart-c4f5346a-62d4-4543-b301-d1db1ebadd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31215
45764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3121545764
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3079223418
Short name T970
Test name
Test status
Simulation time 177496185 ps
CPU time 0.88 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207540 kb
Host smart-5e0f448b-1c52-4a07-ae4c-b6a86005f136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792
23418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3079223418
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1353758992
Short name T2438
Test name
Test status
Simulation time 180714432 ps
CPU time 0.89 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207580 kb
Host smart-fbc680ba-98bf-4e84-8833-b0fba22f1ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
58992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1353758992
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1478495104
Short name T2128
Test name
Test status
Simulation time 167470326 ps
CPU time 0.85 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207556 kb
Host smart-879f0135-4205-45cf-82d4-fbf973ddaedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14784
95104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1478495104
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3944615211
Short name T3488
Test name
Test status
Simulation time 200216185 ps
CPU time 0.99 seconds
Started Aug 10 07:13:39 PM PDT 24
Finished Aug 10 07:13:40 PM PDT 24
Peak memory 207460 kb
Host smart-85350667-d317-4a47-a898-db4cf17a6c6d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3944615211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3944615211
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2153476129
Short name T2586
Test name
Test status
Simulation time 144032297 ps
CPU time 0.81 seconds
Started Aug 10 07:13:46 PM PDT 24
Finished Aug 10 07:13:47 PM PDT 24
Peak memory 207384 kb
Host smart-1e25e87e-4643-48cc-a9d6-12436ac5545b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21534
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2153476129
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1307028993
Short name T3321
Test name
Test status
Simulation time 39055537 ps
CPU time 0.71 seconds
Started Aug 10 07:13:43 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207444 kb
Host smart-056cc8ee-85cc-49ff-9301-1ff9e25512ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
28993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1307028993
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3569984537
Short name T3502
Test name
Test status
Simulation time 18554861181 ps
CPU time 45.35 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 216008 kb
Host smart-50f7c2d0-a34f-4f12-b570-2458c26e3817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
84537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3569984537
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4008758045
Short name T2313
Test name
Test status
Simulation time 205708515 ps
CPU time 0.96 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207516 kb
Host smart-2eb4c470-9b4c-468e-9cfb-53e2d14c50f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40087
58045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4008758045
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3512436676
Short name T840
Test name
Test status
Simulation time 223798985 ps
CPU time 0.97 seconds
Started Aug 10 07:13:40 PM PDT 24
Finished Aug 10 07:13:41 PM PDT 24
Peak memory 207516 kb
Host smart-91e3f450-85be-453b-97a0-fd126e24c85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35124
36676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3512436676
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.517407155
Short name T736
Test name
Test status
Simulation time 241350632 ps
CPU time 0.98 seconds
Started Aug 10 07:13:47 PM PDT 24
Finished Aug 10 07:13:48 PM PDT 24
Peak memory 207464 kb
Host smart-9d3a8294-a6e4-4293-b88d-85f64c357a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51740
7155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.517407155
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.4019376312
Short name T647
Test name
Test status
Simulation time 179523600 ps
CPU time 0.96 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207544 kb
Host smart-818f6945-66a9-4d03-8eb6-2da79d48101a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40193
76312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.4019376312
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2551778819
Short name T77
Test name
Test status
Simulation time 207675498 ps
CPU time 0.95 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207576 kb
Host smart-36e337b0-a1cb-4bc4-88d3-e64ea14d2a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25517
78819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2551778819
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_rx_full.2165794696
Short name T349
Test name
Test status
Simulation time 252973790 ps
CPU time 1.18 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207024 kb
Host smart-1ca3b566-c184-4a24-bc0b-4a0c01cb57dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21657
94696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.2165794696
Directory /workspace/35.usbdev_rx_full/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.383379396
Short name T1443
Test name
Test status
Simulation time 158411910 ps
CPU time 0.88 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:13:42 PM PDT 24
Peak memory 207528 kb
Host smart-7ef4088a-0081-48b4-ba0f-3e3822cb570b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
9396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.383379396
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1395697509
Short name T1670
Test name
Test status
Simulation time 155287541 ps
CPU time 0.8 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207572 kb
Host smart-6f93053e-c9cd-40de-849f-ed8424ba5571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13956
97509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1395697509
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1159227744
Short name T2999
Test name
Test status
Simulation time 210247511 ps
CPU time 1.03 seconds
Started Aug 10 07:13:46 PM PDT 24
Finished Aug 10 07:13:47 PM PDT 24
Peak memory 207416 kb
Host smart-5858e244-1f7d-4e1a-8c17-d24dec4c49e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11592
27744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1159227744
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2401374506
Short name T2015
Test name
Test status
Simulation time 2227196477 ps
CPU time 17.45 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:14:00 PM PDT 24
Peak memory 223760 kb
Host smart-dfbc670e-f870-4d05-afa0-009d096a281c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2401374506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2401374506
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1696426279
Short name T652
Test name
Test status
Simulation time 154275219 ps
CPU time 0.86 seconds
Started Aug 10 07:13:44 PM PDT 24
Finished Aug 10 07:13:45 PM PDT 24
Peak memory 207476 kb
Host smart-7fd5989d-993b-4b58-9ace-d9a3dead5275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16964
26279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1696426279
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2365259929
Short name T3170
Test name
Test status
Simulation time 157253642 ps
CPU time 0.84 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:43 PM PDT 24
Peak memory 207572 kb
Host smart-ac23f923-306b-4d35-9767-e42baa44eb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23652
59929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2365259929
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2419044787
Short name T1639
Test name
Test status
Simulation time 1366499829 ps
CPU time 3.54 seconds
Started Aug 10 07:13:47 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207644 kb
Host smart-8ef7225d-ca68-477e-b546-02c9a6488f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
44787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2419044787
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3007873825
Short name T2125
Test name
Test status
Simulation time 3176952227 ps
CPU time 90.22 seconds
Started Aug 10 07:13:41 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 217280 kb
Host smart-295935ef-1178-400c-bc15-36f69dc5363d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
73825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3007873825
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.2303271068
Short name T909
Test name
Test status
Simulation time 2626779073 ps
CPU time 17.85 seconds
Started Aug 10 07:13:44 PM PDT 24
Finished Aug 10 07:14:02 PM PDT 24
Peak memory 207792 kb
Host smart-650528e1-2626-41ea-bfbc-db690a6f1818
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303271068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.2303271068
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_tx_rx_disruption.1243154216
Short name T2948
Test name
Test status
Simulation time 588203802 ps
CPU time 1.84 seconds
Started Aug 10 07:13:42 PM PDT 24
Finished Aug 10 07:13:44 PM PDT 24
Peak memory 207416 kb
Host smart-bd82ab83-709f-4565-8449-91186f240ee3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243154216 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.usbdev_tx_rx_disruption.1243154216
Directory /workspace/35.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/350.usbdev_tx_rx_disruption.2166371293
Short name T180
Test name
Test status
Simulation time 622325340 ps
CPU time 1.64 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207548 kb
Host smart-4554cbe7-ca78-4b53-9d43-5d0da0f83a52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166371293 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 350.usbdev_tx_rx_disruption.2166371293
Directory /workspace/350.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/351.usbdev_tx_rx_disruption.1926675102
Short name T2797
Test name
Test status
Simulation time 474847189 ps
CPU time 1.46 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207596 kb
Host smart-62b92875-1dbd-4f78-9e69-5a0c042b609e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926675102 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 351.usbdev_tx_rx_disruption.1926675102
Directory /workspace/351.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/352.usbdev_tx_rx_disruption.204008622
Short name T1615
Test name
Test status
Simulation time 506644597 ps
CPU time 1.59 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207572 kb
Host smart-a7cbf2c0-ba5f-4544-8874-9fe53f49ba90
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204008622 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 352.usbdev_tx_rx_disruption.204008622
Directory /workspace/352.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/353.usbdev_tx_rx_disruption.2290389034
Short name T2017
Test name
Test status
Simulation time 545019859 ps
CPU time 1.79 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207568 kb
Host smart-ed164d3b-c45a-4564-9481-199694c55075
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290389034 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 353.usbdev_tx_rx_disruption.2290389034
Directory /workspace/353.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/354.usbdev_tx_rx_disruption.363215815
Short name T1210
Test name
Test status
Simulation time 594437392 ps
CPU time 1.53 seconds
Started Aug 10 07:18:14 PM PDT 24
Finished Aug 10 07:18:15 PM PDT 24
Peak memory 207536 kb
Host smart-f1cb0c31-1447-4a9a-8d56-a32d4219f7c9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363215815 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 354.usbdev_tx_rx_disruption.363215815
Directory /workspace/354.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/355.usbdev_tx_rx_disruption.2682438108
Short name T2561
Test name
Test status
Simulation time 515966554 ps
CPU time 1.68 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207768 kb
Host smart-ec4c1402-b7a3-4831-9d8a-d843dda3e747
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682438108 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 355.usbdev_tx_rx_disruption.2682438108
Directory /workspace/355.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/356.usbdev_tx_rx_disruption.153021375
Short name T3024
Test name
Test status
Simulation time 588379624 ps
CPU time 1.65 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207496 kb
Host smart-6645e13e-b323-4199-a069-4ff64afa6e9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153021375 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 356.usbdev_tx_rx_disruption.153021375
Directory /workspace/356.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/357.usbdev_tx_rx_disruption.757747359
Short name T1634
Test name
Test status
Simulation time 543199513 ps
CPU time 1.56 seconds
Started Aug 10 07:18:22 PM PDT 24
Finished Aug 10 07:18:23 PM PDT 24
Peak memory 207476 kb
Host smart-02ff9179-9734-4971-8361-1cd4e982ee17
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757747359 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 357.usbdev_tx_rx_disruption.757747359
Directory /workspace/357.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/358.usbdev_tx_rx_disruption.979049272
Short name T1179
Test name
Test status
Simulation time 526488900 ps
CPU time 1.55 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207512 kb
Host smart-013aa7dd-4fef-4c1e-9294-bc15d106ce48
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979049272 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 358.usbdev_tx_rx_disruption.979049272
Directory /workspace/358.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/359.usbdev_tx_rx_disruption.3898590493
Short name T2567
Test name
Test status
Simulation time 552275556 ps
CPU time 1.59 seconds
Started Aug 10 07:18:18 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207544 kb
Host smart-908cd251-0e41-44cc-9eb6-59a479d4fc73
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898590493 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 359.usbdev_tx_rx_disruption.3898590493
Directory /workspace/359.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3980180098
Short name T3615
Test name
Test status
Simulation time 50049775 ps
CPU time 0.77 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207440 kb
Host smart-a0445f6f-2b3d-42fb-b47f-3d0f856751df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3980180098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3980180098
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3270064251
Short name T758
Test name
Test status
Simulation time 9777936902 ps
CPU time 12.28 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:01 PM PDT 24
Peak memory 207904 kb
Host smart-cbb86d94-ba3c-483d-ba6c-0f9c5ac38116
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270064251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.3270064251
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1035725617
Short name T857
Test name
Test status
Simulation time 16238096756 ps
CPU time 18.48 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 216004 kb
Host smart-df24f874-a539-4499-bcd0-fc494f69c2c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035725617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1035725617
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3019889182
Short name T2963
Test name
Test status
Simulation time 30714879811 ps
CPU time 35.84 seconds
Started Aug 10 07:13:53 PM PDT 24
Finished Aug 10 07:14:28 PM PDT 24
Peak memory 207748 kb
Host smart-6bf283f0-47dd-4bd2-9e84-acc02430fa25
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019889182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.3019889182
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2545870687
Short name T530
Test name
Test status
Simulation time 235166503 ps
CPU time 0.98 seconds
Started Aug 10 07:13:54 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 207464 kb
Host smart-3cd1f75d-1ec9-41e7-ab80-dfd18b62abe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25458
70687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2545870687
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3898706985
Short name T982
Test name
Test status
Simulation time 160691796 ps
CPU time 0.88 seconds
Started Aug 10 07:13:48 PM PDT 24
Finished Aug 10 07:13:49 PM PDT 24
Peak memory 207568 kb
Host smart-f12292b5-e2ca-4a77-94b3-cdb293d4ae8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987
06985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3898706985
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3260654908
Short name T1990
Test name
Test status
Simulation time 233489908 ps
CPU time 1.03 seconds
Started Aug 10 07:13:48 PM PDT 24
Finished Aug 10 07:13:49 PM PDT 24
Peak memory 207580 kb
Host smart-630c736d-79b9-4786-8b3c-c8f83e650b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
54908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3260654908
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3605392270
Short name T2110
Test name
Test status
Simulation time 730579098 ps
CPU time 2.17 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:13:52 PM PDT 24
Peak memory 207400 kb
Host smart-181c4cde-008a-474f-a0b0-b02fc7699e7c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3605392270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3605392270
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.292038664
Short name T719
Test name
Test status
Simulation time 446687851 ps
CPU time 8.36 seconds
Started Aug 10 07:13:51 PM PDT 24
Finished Aug 10 07:13:59 PM PDT 24
Peak memory 207744 kb
Host smart-708d6cd7-07f9-4d42-b707-8460c42f6db4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292038664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.292038664
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3787754433
Short name T3531
Test name
Test status
Simulation time 946281916 ps
CPU time 2.26 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207520 kb
Host smart-3d8c7261-44fc-4ad4-8a74-43f57478ce4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37877
54433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3787754433
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.887298136
Short name T17
Test name
Test status
Simulation time 137123433 ps
CPU time 0.77 seconds
Started Aug 10 07:13:48 PM PDT 24
Finished Aug 10 07:13:49 PM PDT 24
Peak memory 207572 kb
Host smart-3f725281-764d-4e4e-b96f-1f8abc0246a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88729
8136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.887298136
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4095994135
Short name T2384
Test name
Test status
Simulation time 101284878 ps
CPU time 0.74 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207500 kb
Host smart-ab81620d-1963-46bc-9119-f2133d9eaa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40959
94135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4095994135
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.223549538
Short name T3367
Test name
Test status
Simulation time 983292856 ps
CPU time 2.63 seconds
Started Aug 10 07:13:51 PM PDT 24
Finished Aug 10 07:13:54 PM PDT 24
Peak memory 207740 kb
Host smart-7bd2e8d8-7041-4fc5-92cc-149ece021163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22354
9538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.223549538
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_types.1771434781
Short name T2222
Test name
Test status
Simulation time 287222659 ps
CPU time 1.13 seconds
Started Aug 10 07:13:52 PM PDT 24
Finished Aug 10 07:13:53 PM PDT 24
Peak memory 207540 kb
Host smart-1f37ff20-424e-41cb-a554-7adcd6fe22e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1771434781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.1771434781
Directory /workspace/36.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1606499808
Short name T1637
Test name
Test status
Simulation time 349750607 ps
CPU time 2.12 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:13:52 PM PDT 24
Peak memory 207616 kb
Host smart-23a22ac6-7df0-439f-ade8-6168ceda13fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16064
99808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1606499808
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2475621910
Short name T1548
Test name
Test status
Simulation time 216048354 ps
CPU time 1.03 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 215960 kb
Host smart-a01d1ea0-0fbd-4c75-be51-1df87dcc7ba5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2475621910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2475621910
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4136661025
Short name T1984
Test name
Test status
Simulation time 137353740 ps
CPU time 0.81 seconds
Started Aug 10 07:13:54 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 207552 kb
Host smart-32914dff-3eeb-4f09-9128-ab9230bb4d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41366
61025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4136661025
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2135870875
Short name T1273
Test name
Test status
Simulation time 193478386 ps
CPU time 0.93 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207532 kb
Host smart-ff3b8577-b7dc-47a9-8916-1803a943243f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
70875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2135870875
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.4200363022
Short name T1730
Test name
Test status
Simulation time 4657900303 ps
CPU time 36.92 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 218084 kb
Host smart-ba27e996-4103-41b7-8f1c-2574c42ce2cb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4200363022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4200363022
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2918608190
Short name T1257
Test name
Test status
Simulation time 6624583655 ps
CPU time 43.75 seconds
Started Aug 10 07:13:52 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207700 kb
Host smart-daa0134d-0e49-4589-a2f8-81d5674bea6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2918608190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2918608190
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3484938553
Short name T1519
Test name
Test status
Simulation time 181027573 ps
CPU time 0.89 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207496 kb
Host smart-c74a86e5-0553-4e83-8d0f-b7110c38d172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34849
38553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3484938553
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2004384536
Short name T72
Test name
Test status
Simulation time 14093516041 ps
CPU time 18.82 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207868 kb
Host smart-1969c1ce-1e81-4688-8ce5-b2750e35cfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
84536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2004384536
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1837822327
Short name T2675
Test name
Test status
Simulation time 9913133415 ps
CPU time 11.88 seconds
Started Aug 10 07:13:51 PM PDT 24
Finished Aug 10 07:14:03 PM PDT 24
Peak memory 207860 kb
Host smart-8548c477-0478-419a-8ba0-73de0ff9979a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
22327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1837822327
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2668012795
Short name T1533
Test name
Test status
Simulation time 5658913899 ps
CPU time 172.46 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:16:43 PM PDT 24
Peak memory 224000 kb
Host smart-c04b3c52-8176-4c81-aec7-23bee4158552
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2668012795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2668012795
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3734851876
Short name T2041
Test name
Test status
Simulation time 3175443126 ps
CPU time 30.57 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 216100 kb
Host smart-027166b9-c399-4d5a-8c8e-f7c59264abf4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734851876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3734851876
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1419780697
Short name T1742
Test name
Test status
Simulation time 254730943 ps
CPU time 1.09 seconds
Started Aug 10 07:13:52 PM PDT 24
Finished Aug 10 07:13:53 PM PDT 24
Peak memory 207576 kb
Host smart-568e67f3-e0fa-4795-948c-3872977207a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1419780697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1419780697
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.392340769
Short name T2618
Test name
Test status
Simulation time 213434048 ps
CPU time 0.96 seconds
Started Aug 10 07:13:52 PM PDT 24
Finished Aug 10 07:13:53 PM PDT 24
Peak memory 207420 kb
Host smart-7b2dcb8b-5565-43e2-b6b3-120fe19a6223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
0769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.392340769
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1442657165
Short name T3618
Test name
Test status
Simulation time 2960341030 ps
CPU time 84.25 seconds
Started Aug 10 07:13:52 PM PDT 24
Finished Aug 10 07:15:17 PM PDT 24
Peak memory 216000 kb
Host smart-dc03c0c1-2a52-439e-81a5-b12ad682868a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1442657165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1442657165
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1343663731
Short name T765
Test name
Test status
Simulation time 199172980 ps
CPU time 0.87 seconds
Started Aug 10 07:13:51 PM PDT 24
Finished Aug 10 07:13:52 PM PDT 24
Peak memory 207564 kb
Host smart-68ed13c6-a092-445d-b94d-1cf01de3a9f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1343663731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1343663731
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4128597168
Short name T917
Test name
Test status
Simulation time 188072898 ps
CPU time 0.82 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207528 kb
Host smart-ba182827-9392-4c90-9462-248956021ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
97168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4128597168
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1592302232
Short name T3243
Test name
Test status
Simulation time 209117296 ps
CPU time 0.98 seconds
Started Aug 10 07:13:54 PM PDT 24
Finished Aug 10 07:13:55 PM PDT 24
Peak memory 207464 kb
Host smart-477f57a1-14ac-4128-b6d9-012c121fd1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15923
02232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1592302232
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3567411195
Short name T967
Test name
Test status
Simulation time 184430196 ps
CPU time 0.93 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207564 kb
Host smart-8cd19715-366f-4b8c-af10-9bfa768ccbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35674
11195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3567411195
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.177151192
Short name T1696
Test name
Test status
Simulation time 180416244 ps
CPU time 0.89 seconds
Started Aug 10 07:13:51 PM PDT 24
Finished Aug 10 07:13:52 PM PDT 24
Peak memory 207420 kb
Host smart-739210cb-f079-4a5e-a925-10f54c6c2774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17715
1192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.177151192
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2387964860
Short name T2971
Test name
Test status
Simulation time 208116092 ps
CPU time 0.91 seconds
Started Aug 10 07:13:47 PM PDT 24
Finished Aug 10 07:13:48 PM PDT 24
Peak memory 207504 kb
Host smart-06f4d974-cfa6-403a-88d7-443237fdb90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23879
64860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2387964860
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.126172011
Short name T216
Test name
Test status
Simulation time 152121818 ps
CPU time 0.89 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207496 kb
Host smart-d47636ce-e753-4eaf-bc3e-7ab90a8bb4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12617
2011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.126172011
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3846730727
Short name T3604
Test name
Test status
Simulation time 236689529 ps
CPU time 0.98 seconds
Started Aug 10 07:13:49 PM PDT 24
Finished Aug 10 07:13:50 PM PDT 24
Peak memory 207548 kb
Host smart-b8030bcf-0be7-4b8d-8099-97ce68181dfc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3846730727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3846730727
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3874038947
Short name T903
Test name
Test status
Simulation time 153083421 ps
CPU time 0.87 seconds
Started Aug 10 07:13:50 PM PDT 24
Finished Aug 10 07:13:51 PM PDT 24
Peak memory 207476 kb
Host smart-9d13d8b6-c3c4-4665-980c-e6676d2ee5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
38947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3874038947
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.855514192
Short name T3541
Test name
Test status
Simulation time 41395222 ps
CPU time 0.69 seconds
Started Aug 10 07:13:57 PM PDT 24
Finished Aug 10 07:13:58 PM PDT 24
Peak memory 207368 kb
Host smart-de106032-0af3-442a-9153-7c56c725e4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85551
4192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.855514192
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3880542937
Short name T1484
Test name
Test status
Simulation time 12729453347 ps
CPU time 31.79 seconds
Started Aug 10 07:13:59 PM PDT 24
Finished Aug 10 07:14:31 PM PDT 24
Peak memory 216032 kb
Host smart-d9f06f7b-e971-4103-92b9-f4b2c8359183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38805
42937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3880542937
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3592367810
Short name T1087
Test name
Test status
Simulation time 255942802 ps
CPU time 1.07 seconds
Started Aug 10 07:14:01 PM PDT 24
Finished Aug 10 07:14:02 PM PDT 24
Peak memory 207572 kb
Host smart-afae2a40-03bd-49bb-910b-ff0609b78055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
67810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3592367810
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.342695831
Short name T2499
Test name
Test status
Simulation time 198388983 ps
CPU time 0.95 seconds
Started Aug 10 07:13:58 PM PDT 24
Finished Aug 10 07:13:59 PM PDT 24
Peak memory 207532 kb
Host smart-dbab8476-a5f1-4313-931e-b547eac0b580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34269
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.342695831
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2356407225
Short name T1852
Test name
Test status
Simulation time 216733626 ps
CPU time 1 seconds
Started Aug 10 07:13:56 PM PDT 24
Finished Aug 10 07:13:57 PM PDT 24
Peak memory 207572 kb
Host smart-b5ca10b0-19ab-4e24-a8ff-0e2b4b8b1758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23564
07225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2356407225
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2799413660
Short name T3007
Test name
Test status
Simulation time 163315135 ps
CPU time 0.84 seconds
Started Aug 10 07:13:57 PM PDT 24
Finished Aug 10 07:13:58 PM PDT 24
Peak memory 207536 kb
Host smart-7f09fc74-3dad-4a8b-aaf2-2ad85e3d73e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
13660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2799413660
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1501203613
Short name T3579
Test name
Test status
Simulation time 153322788 ps
CPU time 0.82 seconds
Started Aug 10 07:13:55 PM PDT 24
Finished Aug 10 07:13:56 PM PDT 24
Peak memory 207460 kb
Host smart-25fc752f-c7ee-41f1-aced-a9c9f9136df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15012
03613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1501203613
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_rx_full.1511013913
Short name T1083
Test name
Test status
Simulation time 241851572 ps
CPU time 1.05 seconds
Started Aug 10 07:13:58 PM PDT 24
Finished Aug 10 07:14:00 PM PDT 24
Peak memory 207480 kb
Host smart-920f06c7-dfc6-40cf-bec7-414487c91654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15110
13913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.1511013913
Directory /workspace/36.usbdev_rx_full/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1089599737
Short name T871
Test name
Test status
Simulation time 155306481 ps
CPU time 0.9 seconds
Started Aug 10 07:13:56 PM PDT 24
Finished Aug 10 07:13:57 PM PDT 24
Peak memory 207492 kb
Host smart-03d3f26e-6dad-405e-90dd-d737b9d247da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10895
99737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1089599737
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.4021869588
Short name T2330
Test name
Test status
Simulation time 156998268 ps
CPU time 0.88 seconds
Started Aug 10 07:13:59 PM PDT 24
Finished Aug 10 07:14:00 PM PDT 24
Peak memory 207536 kb
Host smart-6f7ab3e0-c4ae-4d8e-886c-55b0cd123774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
69588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.4021869588
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.464525435
Short name T2906
Test name
Test status
Simulation time 261594651 ps
CPU time 1.06 seconds
Started Aug 10 07:14:01 PM PDT 24
Finished Aug 10 07:14:02 PM PDT 24
Peak memory 207576 kb
Host smart-27c43d39-b613-4755-9e0d-31713c7e18f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46452
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.464525435
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1688516835
Short name T2487
Test name
Test status
Simulation time 2195219940 ps
CPU time 16.83 seconds
Started Aug 10 07:13:58 PM PDT 24
Finished Aug 10 07:14:15 PM PDT 24
Peak memory 217952 kb
Host smart-8f76e286-8526-4228-9ab4-44647af330f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1688516835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1688516835
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.31733989
Short name T3075
Test name
Test status
Simulation time 169361161 ps
CPU time 0.86 seconds
Started Aug 10 07:13:59 PM PDT 24
Finished Aug 10 07:14:00 PM PDT 24
Peak memory 207516 kb
Host smart-9716fb22-23a8-4b80-894a-6ac1c1744583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.31733989
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2545002376
Short name T1309
Test name
Test status
Simulation time 191394381 ps
CPU time 0.89 seconds
Started Aug 10 07:13:58 PM PDT 24
Finished Aug 10 07:13:59 PM PDT 24
Peak memory 207588 kb
Host smart-e193b307-fd6b-4ac9-af4a-9e4ef64712a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450
02376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2545002376
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2575138216
Short name T3436
Test name
Test status
Simulation time 1053787594 ps
CPU time 2.38 seconds
Started Aug 10 07:14:00 PM PDT 24
Finished Aug 10 07:14:03 PM PDT 24
Peak memory 207716 kb
Host smart-8cd1ee2f-f4e0-4518-8273-9b8e1095d1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
38216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2575138216
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3904810618
Short name T704
Test name
Test status
Simulation time 2411974788 ps
CPU time 18.21 seconds
Started Aug 10 07:13:59 PM PDT 24
Finished Aug 10 07:14:17 PM PDT 24
Peak memory 216096 kb
Host smart-2aa672ca-9c37-4de0-b889-1889bd23e0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39048
10618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3904810618
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.1263617456
Short name T845
Test name
Test status
Simulation time 3602088878 ps
CPU time 23.95 seconds
Started Aug 10 07:13:48 PM PDT 24
Finished Aug 10 07:14:12 PM PDT 24
Peak memory 207904 kb
Host smart-522b89f4-0e91-4569-bc7a-ae0a73c9bc92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263617456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.1263617456
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_tx_rx_disruption.3038414079
Short name T3331
Test name
Test status
Simulation time 615509865 ps
CPU time 1.69 seconds
Started Aug 10 07:13:57 PM PDT 24
Finished Aug 10 07:13:59 PM PDT 24
Peak memory 207528 kb
Host smart-6abb74f4-2575-46c3-8669-c49ffdebad6d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038414079 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.usbdev_tx_rx_disruption.3038414079
Directory /workspace/36.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/360.usbdev_tx_rx_disruption.268490504
Short name T945
Test name
Test status
Simulation time 579438740 ps
CPU time 1.66 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207556 kb
Host smart-0f2014e2-2a3d-4c17-9ed7-531a16740d0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268490504 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 360.usbdev_tx_rx_disruption.268490504
Directory /workspace/360.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/361.usbdev_tx_rx_disruption.3278303440
Short name T2058
Test name
Test status
Simulation time 486296363 ps
CPU time 1.61 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:18 PM PDT 24
Peak memory 207560 kb
Host smart-4fdea572-6dfb-4954-a826-c4d81fcda41b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278303440 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 361.usbdev_tx_rx_disruption.3278303440
Directory /workspace/361.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/362.usbdev_tx_rx_disruption.2275371767
Short name T2322
Test name
Test status
Simulation time 419390390 ps
CPU time 1.4 seconds
Started Aug 10 07:18:18 PM PDT 24
Finished Aug 10 07:18:20 PM PDT 24
Peak memory 207544 kb
Host smart-53ad4c58-a9a3-40d1-9fe8-405a712f1272
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275371767 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 362.usbdev_tx_rx_disruption.2275371767
Directory /workspace/362.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/363.usbdev_tx_rx_disruption.2144092907
Short name T1625
Test name
Test status
Simulation time 502002195 ps
CPU time 1.49 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:16 PM PDT 24
Peak memory 207580 kb
Host smart-545ba9e4-2901-44af-a8f6-5c2665690283
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144092907 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 363.usbdev_tx_rx_disruption.2144092907
Directory /workspace/363.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/364.usbdev_tx_rx_disruption.830678075
Short name T1207
Test name
Test status
Simulation time 626644418 ps
CPU time 1.58 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207580 kb
Host smart-42e2d148-a7dd-4d5a-9373-6c12dc030d47
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830678075 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 364.usbdev_tx_rx_disruption.830678075
Directory /workspace/364.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/365.usbdev_tx_rx_disruption.1449649484
Short name T2000
Test name
Test status
Simulation time 490454522 ps
CPU time 1.48 seconds
Started Aug 10 07:18:18 PM PDT 24
Finished Aug 10 07:18:20 PM PDT 24
Peak memory 207664 kb
Host smart-74fe6f89-ea95-4ad8-987d-9cdafc633b39
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449649484 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 365.usbdev_tx_rx_disruption.1449649484
Directory /workspace/365.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/366.usbdev_tx_rx_disruption.1775760682
Short name T1251
Test name
Test status
Simulation time 465181928 ps
CPU time 1.4 seconds
Started Aug 10 07:18:16 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207524 kb
Host smart-af62dd20-1d32-40eb-a6a1-b0d6713447c4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775760682 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 366.usbdev_tx_rx_disruption.1775760682
Directory /workspace/366.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/367.usbdev_tx_rx_disruption.3443403723
Short name T3131
Test name
Test status
Simulation time 531146255 ps
CPU time 1.59 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207504 kb
Host smart-99040aaf-e7dc-4164-8ded-f2371c72cdf4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443403723 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 367.usbdev_tx_rx_disruption.3443403723
Directory /workspace/367.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/368.usbdev_tx_rx_disruption.2448375075
Short name T1463
Test name
Test status
Simulation time 594885968 ps
CPU time 1.66 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207456 kb
Host smart-0cc932bd-e677-49a7-918f-ef26b1d0808c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448375075 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 368.usbdev_tx_rx_disruption.2448375075
Directory /workspace/368.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/369.usbdev_tx_rx_disruption.3839864349
Short name T1898
Test name
Test status
Simulation time 591059402 ps
CPU time 1.78 seconds
Started Aug 10 07:18:15 PM PDT 24
Finished Aug 10 07:18:17 PM PDT 24
Peak memory 207424 kb
Host smart-3b0b2368-18f0-42a4-94e9-587630303029
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839864349 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 369.usbdev_tx_rx_disruption.3839864349
Directory /workspace/369.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2191246850
Short name T928
Test name
Test status
Simulation time 44944463 ps
CPU time 0.72 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:17 PM PDT 24
Peak memory 207600 kb
Host smart-7ed31611-5aa4-4a0d-94b6-33134b885e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2191246850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2191246850
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2964158598
Short name T3100
Test name
Test status
Simulation time 4302923479 ps
CPU time 5.87 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:13 PM PDT 24
Peak memory 215984 kb
Host smart-d316be06-25de-486c-a59d-272633a9282c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964158598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2964158598
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2992914439
Short name T1019
Test name
Test status
Simulation time 15358894687 ps
CPU time 17.89 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:24 PM PDT 24
Peak memory 216044 kb
Host smart-f33cae50-b5ee-4732-8695-06417ba43ea1
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992914439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2992914439
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2987989695
Short name T1482
Test name
Test status
Simulation time 24143431503 ps
CPU time 29.66 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 216052 kb
Host smart-11192fd2-5b70-4384-b693-db71e52f81ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987989695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_resume.2987989695
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1965929910
Short name T678
Test name
Test status
Simulation time 218602120 ps
CPU time 0.97 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:07 PM PDT 24
Peak memory 207572 kb
Host smart-636a0d63-d209-487e-a2d8-7323ec34c50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19659
29910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1965929910
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.821530227
Short name T1111
Test name
Test status
Simulation time 138650086 ps
CPU time 0.82 seconds
Started Aug 10 07:14:10 PM PDT 24
Finished Aug 10 07:14:11 PM PDT 24
Peak memory 207476 kb
Host smart-32087271-f5a2-4510-82aa-76f89b857b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82153
0227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.821530227
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.300914110
Short name T3527
Test name
Test status
Simulation time 568217773 ps
CPU time 1.94 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:09 PM PDT 24
Peak memory 207536 kb
Host smart-bd49f6d5-3544-437e-87a6-6d88c5843abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
4110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.300914110
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2268241685
Short name T221
Test name
Test status
Simulation time 533317195 ps
CPU time 1.5 seconds
Started Aug 10 07:14:05 PM PDT 24
Finished Aug 10 07:14:07 PM PDT 24
Peak memory 207516 kb
Host smart-086d5f6a-9b9e-470e-b81e-35cde7d26ed6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2268241685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2268241685
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3230932269
Short name T1727
Test name
Test status
Simulation time 40163379979 ps
CPU time 59.31 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:15:06 PM PDT 24
Peak memory 207828 kb
Host smart-0d70c58f-6919-408b-bc7c-eb92ce87f057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32309
32269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3230932269
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.4021513150
Short name T201
Test name
Test status
Simulation time 711033384 ps
CPU time 15.12 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:23 PM PDT 24
Peak memory 207704 kb
Host smart-cc31f106-7b35-4542-898d-f43d376adae5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021513150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.4021513150
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3239875654
Short name T2659
Test name
Test status
Simulation time 949416382 ps
CPU time 2.1 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207560 kb
Host smart-a3ba0c7c-1599-4f38-8fc8-f8ac18976bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
75654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3239875654
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3733750707
Short name T3097
Test name
Test status
Simulation time 147750084 ps
CPU time 0.86 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207504 kb
Host smart-fae75097-0b87-4582-a7b4-996b53680bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337
50707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3733750707
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1300310648
Short name T1295
Test name
Test status
Simulation time 51824511 ps
CPU time 0.74 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207520 kb
Host smart-bb41b9d0-4687-45f0-bdc9-d17bde334825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13003
10648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1300310648
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1467779854
Short name T2137
Test name
Test status
Simulation time 722900777 ps
CPU time 2.08 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207716 kb
Host smart-3d641ae9-88cd-4d1d-8bfb-31be500db3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14677
79854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1467779854
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_types.2310321746
Short name T3309
Test name
Test status
Simulation time 234781739 ps
CPU time 1.01 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:07 PM PDT 24
Peak memory 207524 kb
Host smart-988b867a-ecff-4da1-ba1d-4c4737275411
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2310321746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.2310321746
Directory /workspace/37.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3966311533
Short name T2196
Test name
Test status
Simulation time 186182765 ps
CPU time 2.35 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:09 PM PDT 24
Peak memory 207736 kb
Host smart-60408961-54d8-43f5-a7be-7147886ac8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
11533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3966311533
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3089768725
Short name T723
Test name
Test status
Simulation time 215678290 ps
CPU time 1.13 seconds
Started Aug 10 07:14:09 PM PDT 24
Finished Aug 10 07:14:10 PM PDT 24
Peak memory 215976 kb
Host smart-00870ec8-f7ef-4610-bd4f-426cffabb43e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3089768725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3089768725
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1929383732
Short name T2811
Test name
Test status
Simulation time 190985027 ps
CPU time 0.91 seconds
Started Aug 10 07:14:12 PM PDT 24
Finished Aug 10 07:14:13 PM PDT 24
Peak memory 207548 kb
Host smart-3ff8c140-1a58-4a83-b11b-baf7e8832e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
83732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1929383732
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1574198045
Short name T715
Test name
Test status
Simulation time 192121245 ps
CPU time 0.91 seconds
Started Aug 10 07:14:10 PM PDT 24
Finished Aug 10 07:14:11 PM PDT 24
Peak memory 207564 kb
Host smart-dca6bd65-3e34-4aaa-ab27-15cf28eea0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
98045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1574198045
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1298571335
Short name T1130
Test name
Test status
Simulation time 4837572292 ps
CPU time 48.48 seconds
Started Aug 10 07:14:12 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 218652 kb
Host smart-8dcdd1aa-ea75-4398-a60f-c01d26d5b429
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1298571335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1298571335
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.2026664506
Short name T3296
Test name
Test status
Simulation time 13262550856 ps
CPU time 94.74 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207772 kb
Host smart-49160c42-6e4c-4d90-89fd-2997102ce0dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2026664506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.2026664506
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.4013318142
Short name T1611
Test name
Test status
Simulation time 249501434 ps
CPU time 1.03 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:09 PM PDT 24
Peak memory 207604 kb
Host smart-8b73d164-ddd5-42d0-804d-1324c72b0187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40133
18142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.4013318142
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.18222020
Short name T2947
Test name
Test status
Simulation time 25536343846 ps
CPU time 40.9 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:49 PM PDT 24
Peak memory 216004 kb
Host smart-26ce2d8e-5c08-40c8-936a-69d6e278e35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18222
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.18222020
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2569906492
Short name T3396
Test name
Test status
Simulation time 8455695197 ps
CPU time 12.09 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207576 kb
Host smart-d128af9c-7ef0-42f0-a4bf-d7b2b410cb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25699
06492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2569906492
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.137491401
Short name T3304
Test name
Test status
Simulation time 5243043280 ps
CPU time 55.12 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 219280 kb
Host smart-3bf20422-ba79-4968-b220-f2f067529814
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=137491401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.137491401
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4067867835
Short name T1269
Test name
Test status
Simulation time 2709254441 ps
CPU time 75.53 seconds
Started Aug 10 07:14:11 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 217332 kb
Host smart-d925c9ff-e6d1-4bf1-9c95-0d0250934c0e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4067867835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4067867835
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.955060518
Short name T2115
Test name
Test status
Simulation time 247130141 ps
CPU time 1.02 seconds
Started Aug 10 07:14:09 PM PDT 24
Finished Aug 10 07:14:10 PM PDT 24
Peak memory 207600 kb
Host smart-9c482c34-1ae5-46e9-b65f-e9e0a14f883c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=955060518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.955060518
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1180438335
Short name T1529
Test name
Test status
Simulation time 226809389 ps
CPU time 0.99 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:10 PM PDT 24
Peak memory 207608 kb
Host smart-6cd6d796-c4b2-4dc8-8915-2ad4b5cd1bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804
38335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1180438335
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3897582337
Short name T687
Test name
Test status
Simulation time 3745242231 ps
CPU time 28.89 seconds
Started Aug 10 07:14:10 PM PDT 24
Finished Aug 10 07:14:39 PM PDT 24
Peak memory 216024 kb
Host smart-f71e4c89-b328-4495-9e86-7ddd6f236b9e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3897582337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3897582337
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.558967952
Short name T1583
Test name
Test status
Simulation time 162530761 ps
CPU time 0.85 seconds
Started Aug 10 07:14:10 PM PDT 24
Finished Aug 10 07:14:11 PM PDT 24
Peak memory 207596 kb
Host smart-71578bbf-af57-45a0-8a02-6831b45eb7fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=558967952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.558967952
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4197452541
Short name T1610
Test name
Test status
Simulation time 145045960 ps
CPU time 0.82 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207580 kb
Host smart-e94c02c4-e677-43b9-b7f3-37f338b413d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
52541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4197452541
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.998252451
Short name T1479
Test name
Test status
Simulation time 229334072 ps
CPU time 0.95 seconds
Started Aug 10 07:14:09 PM PDT 24
Finished Aug 10 07:14:10 PM PDT 24
Peak memory 207604 kb
Host smart-66dcbc8c-5306-4b3d-8f56-c63b2326e385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99825
2451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.998252451
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.696124000
Short name T700
Test name
Test status
Simulation time 166249200 ps
CPU time 0.84 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207528 kb
Host smart-dfff3f42-e63c-4de9-abe4-e7313381edc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69612
4000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.696124000
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.623452400
Short name T2712
Test name
Test status
Simulation time 217086910 ps
CPU time 0.91 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:08 PM PDT 24
Peak memory 207552 kb
Host smart-5e2c4a0c-e3f3-4065-9b54-669d1eed2a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62345
2400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.623452400
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1213194753
Short name T2923
Test name
Test status
Simulation time 168945204 ps
CPU time 0.89 seconds
Started Aug 10 07:14:06 PM PDT 24
Finished Aug 10 07:14:07 PM PDT 24
Peak memory 207596 kb
Host smart-f8c18ebc-7caa-4fd7-8d92-c6ba39e1931c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
94753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1213194753
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.4226700160
Short name T1115
Test name
Test status
Simulation time 158315848 ps
CPU time 0.9 seconds
Started Aug 10 07:14:10 PM PDT 24
Finished Aug 10 07:14:11 PM PDT 24
Peak memory 207592 kb
Host smart-52e6d59a-a9b3-446b-87fb-9bb48dd542ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
00160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.4226700160
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1033071266
Short name T2014
Test name
Test status
Simulation time 318868138 ps
CPU time 1.15 seconds
Started Aug 10 07:14:08 PM PDT 24
Finished Aug 10 07:14:09 PM PDT 24
Peak memory 207536 kb
Host smart-28159d07-0a18-470e-9c98-eb5b5c485f4f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1033071266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1033071266
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4292891021
Short name T2754
Test name
Test status
Simulation time 146139938 ps
CPU time 0.81 seconds
Started Aug 10 07:14:19 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207512 kb
Host smart-94a7c9a9-4208-44b9-833e-c468f8a9d63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42928
91021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4292891021
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1586636438
Short name T3116
Test name
Test status
Simulation time 44243885 ps
CPU time 0.68 seconds
Started Aug 10 07:14:21 PM PDT 24
Finished Aug 10 07:14:22 PM PDT 24
Peak memory 207548 kb
Host smart-6d8df6b8-0a8f-4f83-9537-bc7f5c4d77e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
36438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1586636438
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2165529559
Short name T1317
Test name
Test status
Simulation time 11459139848 ps
CPU time 28.89 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:46 PM PDT 24
Peak memory 216060 kb
Host smart-807c522b-0eec-4114-9391-703388b88485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
29559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2165529559
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3830657596
Short name T2677
Test name
Test status
Simulation time 166300635 ps
CPU time 0.89 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 207576 kb
Host smart-ddc05b36-9365-485d-a100-b97ad4ef3bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
57596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3830657596
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1642349374
Short name T1226
Test name
Test status
Simulation time 181748382 ps
CPU time 0.95 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207484 kb
Host smart-105136d9-6b7d-4005-b6cf-2e498ee2a414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16423
49374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1642349374
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.902606612
Short name T1149
Test name
Test status
Simulation time 178450773 ps
CPU time 0.91 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 207540 kb
Host smart-1e905cb3-44f4-4a41-bb44-280451b8fd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90260
6612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.902606612
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3580619595
Short name T2420
Test name
Test status
Simulation time 156469001 ps
CPU time 0.87 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207544 kb
Host smart-9134d0ab-7c6a-45a8-828d-bb1897d497a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
19595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3580619595
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.707044239
Short name T2867
Test name
Test status
Simulation time 176503762 ps
CPU time 0.9 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:17 PM PDT 24
Peak memory 207536 kb
Host smart-14f83069-ede8-4d5a-a964-392eaa11826c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70704
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.707044239
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_rx_full.3837827383
Short name T2399
Test name
Test status
Simulation time 398077198 ps
CPU time 1.49 seconds
Started Aug 10 07:14:19 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 207520 kb
Host smart-a9e2c32d-7409-4d7f-9ecf-4e4bdafcd2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
27383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3837827383
Directory /workspace/37.usbdev_rx_full/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2248599300
Short name T2347
Test name
Test status
Simulation time 190832749 ps
CPU time 0.86 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:17 PM PDT 24
Peak memory 207544 kb
Host smart-4d8af77c-13e2-41d5-9249-7c8ec66d1159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
99300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2248599300
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2341433184
Short name T1336
Test name
Test status
Simulation time 170238948 ps
CPU time 0.89 seconds
Started Aug 10 07:14:20 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 207540 kb
Host smart-7b58132c-bcb2-48d7-a85b-88fcd6d04a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23414
33184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2341433184
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2485507576
Short name T2812
Test name
Test status
Simulation time 229037037 ps
CPU time 1.05 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207504 kb
Host smart-9d5d324c-67dc-4352-86ae-cdcb19fcd3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24855
07576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2485507576
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2792769840
Short name T711
Test name
Test status
Simulation time 2800826357 ps
CPU time 28.21 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:45 PM PDT 24
Peak memory 216980 kb
Host smart-fb9891f2-e443-4f07-a6a6-037d5e6af7db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2792769840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2792769840
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.255047922
Short name T756
Test name
Test status
Simulation time 171132049 ps
CPU time 0.91 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 207744 kb
Host smart-569e707f-8658-4380-b2b7-781c11b6efc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
7922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.255047922
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1164539134
Short name T656
Test name
Test status
Simulation time 224875970 ps
CPU time 0.92 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207460 kb
Host smart-2807f229-a32e-4441-bb0c-d7ef121093e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
39134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1164539134
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2941372717
Short name T3250
Test name
Test status
Simulation time 1244816813 ps
CPU time 3.14 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207804 kb
Host smart-2e7208be-09ed-4905-a4a0-99c556aabb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29413
72717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2941372717
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.4039699999
Short name T2008
Test name
Test status
Simulation time 3455896961 ps
CPU time 96.11 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 217480 kb
Host smart-484a09b3-6d26-408d-a571-41ae5ca242e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
99999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.4039699999
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.1908485804
Short name T2579
Test name
Test status
Simulation time 1442671980 ps
CPU time 31.97 seconds
Started Aug 10 07:14:07 PM PDT 24
Finished Aug 10 07:14:39 PM PDT 24
Peak memory 207816 kb
Host smart-b844d2e0-512c-4fb3-81d6-76990bc1e3fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908485804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.1908485804
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_tx_rx_disruption.2597511069
Short name T2860
Test name
Test status
Simulation time 478737284 ps
CPU time 1.5 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207500 kb
Host smart-54b4a574-b882-493e-b79e-dc42556f05a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597511069 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.usbdev_tx_rx_disruption.2597511069
Directory /workspace/37.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/370.usbdev_tx_rx_disruption.1848315059
Short name T2372
Test name
Test status
Simulation time 519974904 ps
CPU time 1.63 seconds
Started Aug 10 07:18:17 PM PDT 24
Finished Aug 10 07:18:19 PM PDT 24
Peak memory 207580 kb
Host smart-d2fba513-3e0b-4785-9f35-aca1be213f9c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848315059 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 370.usbdev_tx_rx_disruption.1848315059
Directory /workspace/370.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/371.usbdev_tx_rx_disruption.3521714888
Short name T601
Test name
Test status
Simulation time 455215375 ps
CPU time 1.72 seconds
Started Aug 10 07:18:28 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207420 kb
Host smart-adbbe2ee-06eb-4705-b2ea-1e19f03c07ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521714888 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 371.usbdev_tx_rx_disruption.3521714888
Directory /workspace/371.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/372.usbdev_tx_rx_disruption.1555226901
Short name T2100
Test name
Test status
Simulation time 469558371 ps
CPU time 1.59 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207548 kb
Host smart-f2a69f5f-bc4f-4eae-ac86-cd75c8b8ac9e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555226901 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 372.usbdev_tx_rx_disruption.1555226901
Directory /workspace/372.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/373.usbdev_tx_rx_disruption.3493473165
Short name T1367
Test name
Test status
Simulation time 609462001 ps
CPU time 1.74 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207528 kb
Host smart-58464905-183e-47bb-8065-767abf263fa5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493473165 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 373.usbdev_tx_rx_disruption.3493473165
Directory /workspace/373.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/374.usbdev_tx_rx_disruption.4072573782
Short name T3441
Test name
Test status
Simulation time 500539061 ps
CPU time 1.46 seconds
Started Aug 10 07:18:25 PM PDT 24
Finished Aug 10 07:18:27 PM PDT 24
Peak memory 207424 kb
Host smart-5b734c06-c262-4a3a-b392-0bfb08781f92
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072573782 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 374.usbdev_tx_rx_disruption.4072573782
Directory /workspace/374.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/375.usbdev_tx_rx_disruption.195582926
Short name T2432
Test name
Test status
Simulation time 654751427 ps
CPU time 1.89 seconds
Started Aug 10 07:18:30 PM PDT 24
Finished Aug 10 07:18:32 PM PDT 24
Peak memory 207580 kb
Host smart-447de310-31aa-435d-b99e-701f014db2f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195582926 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 375.usbdev_tx_rx_disruption.195582926
Directory /workspace/375.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/376.usbdev_tx_rx_disruption.2031766116
Short name T2639
Test name
Test status
Simulation time 472959643 ps
CPU time 1.47 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207560 kb
Host smart-138710f5-9c4d-4cf3-a932-33d01f9c7232
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031766116 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 376.usbdev_tx_rx_disruption.2031766116
Directory /workspace/376.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/377.usbdev_tx_rx_disruption.2856828564
Short name T1379
Test name
Test status
Simulation time 627241808 ps
CPU time 1.81 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207484 kb
Host smart-99de056b-5188-45ad-aac9-ef9e3d3076c5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856828564 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 377.usbdev_tx_rx_disruption.2856828564
Directory /workspace/377.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/378.usbdev_tx_rx_disruption.3756240361
Short name T1892
Test name
Test status
Simulation time 509059988 ps
CPU time 1.58 seconds
Started Aug 10 07:18:29 PM PDT 24
Finished Aug 10 07:18:31 PM PDT 24
Peak memory 207668 kb
Host smart-1fb192f0-61c8-4d33-b728-35845c8c7c75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756240361 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 378.usbdev_tx_rx_disruption.3756240361
Directory /workspace/378.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/379.usbdev_tx_rx_disruption.1408174811
Short name T978
Test name
Test status
Simulation time 506300784 ps
CPU time 1.61 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207552 kb
Host smart-2485a39f-2936-4496-99ca-03a7c3c16d19
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408174811 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 379.usbdev_tx_rx_disruption.1408174811
Directory /workspace/379.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.1338513763
Short name T1800
Test name
Test status
Simulation time 59077648 ps
CPU time 0.67 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:14:29 PM PDT 24
Peak memory 207584 kb
Host smart-a707a0d0-4f1a-42d4-9da2-dd8a6ff84872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1338513763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.1338513763
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2966790210
Short name T1537
Test name
Test status
Simulation time 6591867482 ps
CPU time 8.94 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 216024 kb
Host smart-8724d233-ff97-41f5-a75e-92780141ab3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966790210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2966790210
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.274821471
Short name T1867
Test name
Test status
Simulation time 19687018790 ps
CPU time 24.36 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:41 PM PDT 24
Peak memory 207792 kb
Host smart-58564234-403e-4b2f-85f1-b3c525326f81
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=274821471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.274821471
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2700098968
Short name T1427
Test name
Test status
Simulation time 30630332275 ps
CPU time 42.83 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207788 kb
Host smart-42835b13-7f13-4ef2-9a13-ee0b3a45386b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700098968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.2700098968
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4089008202
Short name T2253
Test name
Test status
Simulation time 184522510 ps
CPU time 0.91 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 207588 kb
Host smart-ac4ed3cb-c5a7-4de7-b8cc-5dc18935f5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890
08202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4089008202
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3136520771
Short name T3186
Test name
Test status
Simulation time 166502216 ps
CPU time 0.87 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207468 kb
Host smart-717bc0f5-3fff-40a0-980a-5cf5fb8024a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
20771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3136520771
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.1401365695
Short name T2513
Test name
Test status
Simulation time 540268245 ps
CPU time 1.88 seconds
Started Aug 10 07:14:19 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 207532 kb
Host smart-0f895b29-e2a2-40f6-b80a-156ab2a49516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14013
65695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.1401365695
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1484565462
Short name T1657
Test name
Test status
Simulation time 359642543 ps
CPU time 1.27 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207732 kb
Host smart-7a132396-d3b7-48e0-bb02-c1af7e6c4225
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1484565462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1484565462
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.2426918360
Short name T1926
Test name
Test status
Simulation time 46585849615 ps
CPU time 88.26 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:15:47 PM PDT 24
Peak memory 207812 kb
Host smart-483a7fc3-2adb-4c44-bb8b-8e0218ab5119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
18360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2426918360
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.3316275756
Short name T729
Test name
Test status
Simulation time 1291768287 ps
CPU time 28.15 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:46 PM PDT 24
Peak memory 207676 kb
Host smart-ece1ed31-2875-4806-af99-60426460ac45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316275756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.3316275756
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.3951066190
Short name T2850
Test name
Test status
Simulation time 423037784 ps
CPU time 1.37 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207528 kb
Host smart-276c964c-e5d2-4cd5-b56c-2389ca3541cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39510
66190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.3951066190
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.4085923038
Short name T2211
Test name
Test status
Simulation time 158138479 ps
CPU time 0.84 seconds
Started Aug 10 07:14:20 PM PDT 24
Finished Aug 10 07:14:21 PM PDT 24
Peak memory 207508 kb
Host smart-36ff5bb7-16c1-42f2-b69f-fc57bae70cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40859
23038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.4085923038
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3397140726
Short name T1025
Test name
Test status
Simulation time 44034626 ps
CPU time 0.69 seconds
Started Aug 10 07:14:15 PM PDT 24
Finished Aug 10 07:14:15 PM PDT 24
Peak memory 207380 kb
Host smart-33373219-8bb5-45b0-8f6a-21bd58d9ec6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
40726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3397140726
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3597958287
Short name T2447
Test name
Test status
Simulation time 958799207 ps
CPU time 2.38 seconds
Started Aug 10 07:14:16 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 207688 kb
Host smart-9622699d-4edd-4591-8c58-47a9d101eabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35979
58287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3597958287
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_types.1104409808
Short name T3383
Test name
Test status
Simulation time 574667268 ps
CPU time 1.63 seconds
Started Aug 10 07:14:21 PM PDT 24
Finished Aug 10 07:14:23 PM PDT 24
Peak memory 207568 kb
Host smart-8d39b022-5048-4cec-9386-f1a39bffa9bc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1104409808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.1104409808
Directory /workspace/38.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1271152606
Short name T2864
Test name
Test status
Simulation time 295672031 ps
CPU time 2 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:20 PM PDT 24
Peak memory 207672 kb
Host smart-ad16f0e3-c73d-42d8-8e16-475d90ba165c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
52606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1271152606
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2132315986
Short name T2557
Test name
Test status
Simulation time 218027391 ps
CPU time 1.16 seconds
Started Aug 10 07:14:18 PM PDT 24
Finished Aug 10 07:14:19 PM PDT 24
Peak memory 215976 kb
Host smart-5fd3f2f5-7760-4e5d-830e-a464847855d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2132315986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2132315986
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1940579805
Short name T1219
Test name
Test status
Simulation time 214408345 ps
CPU time 0.97 seconds
Started Aug 10 07:14:38 PM PDT 24
Finished Aug 10 07:14:39 PM PDT 24
Peak memory 207516 kb
Host smart-5fb07458-8f22-4bac-9c56-7079f10cf9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19405
79805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1940579805
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1038439710
Short name T2087
Test name
Test status
Simulation time 227605674 ps
CPU time 0.97 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207540 kb
Host smart-b4fe7490-6590-46d2-9955-3a8b123b30da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10384
39710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1038439710
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1471633401
Short name T219
Test name
Test status
Simulation time 2950086920 ps
CPU time 23.31 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:40 PM PDT 24
Peak memory 224168 kb
Host smart-fe3a1b05-4bae-4480-a8b2-a5e6d27f332f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1471633401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1471633401
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1695820588
Short name T1043
Test name
Test status
Simulation time 5127241106 ps
CPU time 39.34 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:15:07 PM PDT 24
Peak memory 207676 kb
Host smart-12338df1-ea28-4b8f-87b5-ed4d573fa97a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1695820588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1695820588
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3672032610
Short name T1849
Test name
Test status
Simulation time 245090373 ps
CPU time 1.01 seconds
Started Aug 10 07:14:38 PM PDT 24
Finished Aug 10 07:14:39 PM PDT 24
Peak memory 207536 kb
Host smart-53779eaa-16b1-4892-8982-c8973e0ffcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36720
32610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3672032610
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3077695650
Short name T1018
Test name
Test status
Simulation time 25324733809 ps
CPU time 38.79 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:15:04 PM PDT 24
Peak memory 207836 kb
Host smart-696dee97-bcac-429b-ba7e-dfa594499d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
95650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3077695650
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.577511455
Short name T2914
Test name
Test status
Simulation time 8652003611 ps
CPU time 11.34 seconds
Started Aug 10 07:14:27 PM PDT 24
Finished Aug 10 07:14:38 PM PDT 24
Peak memory 207828 kb
Host smart-420c0d76-8be3-4f84-b34e-645ec8437e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57751
1455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.577511455
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1978637578
Short name T1721
Test name
Test status
Simulation time 5015416310 ps
CPU time 135.12 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 216088 kb
Host smart-7a1ffaae-1473-4eed-9d94-ba89f3b57144
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1978637578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1978637578
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3203700843
Short name T2099
Test name
Test status
Simulation time 2010613813 ps
CPU time 56.57 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:15:22 PM PDT 24
Peak memory 217376 kb
Host smart-8a0d1dab-d558-4ff0-be5e-0925b5dd0172
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3203700843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3203700843
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2549063091
Short name T934
Test name
Test status
Simulation time 253036119 ps
CPU time 1 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 207600 kb
Host smart-5a8f85d2-2936-43c7-beb7-1316ac7b9ffc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2549063091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2549063091
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3920810723
Short name T1685
Test name
Test status
Simulation time 205232987 ps
CPU time 1.04 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 207512 kb
Host smart-13e5d197-15d8-4c68-afd4-d86b6ef2cbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
10723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3920810723
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1011198873
Short name T2233
Test name
Test status
Simulation time 3982408875 ps
CPU time 120.08 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:16:26 PM PDT 24
Peak memory 217480 kb
Host smart-3ae73eb8-e86a-4252-b164-b1207e929395
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1011198873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1011198873
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2093439259
Short name T1147
Test name
Test status
Simulation time 163642659 ps
CPU time 0.89 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207544 kb
Host smart-60ccfd96-d672-44a9-87a4-a371d7e9d137
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2093439259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2093439259
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1745103353
Short name T1775
Test name
Test status
Simulation time 178430903 ps
CPU time 0.87 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 207600 kb
Host smart-13d45804-a586-4245-9275-c791b5b0f0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451
03353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1745103353
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.935832245
Short name T155
Test name
Test status
Simulation time 219864586 ps
CPU time 0.97 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:14:31 PM PDT 24
Peak memory 207604 kb
Host smart-66681264-781d-40fb-89cb-68dc49ba8b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93583
2245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.935832245
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1841550080
Short name T1674
Test name
Test status
Simulation time 176791296 ps
CPU time 0.89 seconds
Started Aug 10 07:14:32 PM PDT 24
Finished Aug 10 07:14:33 PM PDT 24
Peak memory 207560 kb
Host smart-bdfbe7f1-4c01-4bbd-86e6-d228c604d9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18415
50080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1841550080
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1506018280
Short name T546
Test name
Test status
Simulation time 176089644 ps
CPU time 0.85 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207512 kb
Host smart-bfc6bb6a-033f-4811-baff-ed58704329de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15060
18280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1506018280
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2835435870
Short name T1230
Test name
Test status
Simulation time 145963143 ps
CPU time 0.84 seconds
Started Aug 10 07:14:31 PM PDT 24
Finished Aug 10 07:14:32 PM PDT 24
Peak memory 207564 kb
Host smart-cb1cd6a0-301c-418d-ad97-d6332e394f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
35870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2835435870
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1879146974
Short name T189
Test name
Test status
Simulation time 169912126 ps
CPU time 0.9 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 207436 kb
Host smart-f9597a1f-30dd-41e6-96ca-7999b6d6582e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18791
46974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1879146974
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.671756096
Short name T2755
Test name
Test status
Simulation time 235062534 ps
CPU time 1.05 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207520 kb
Host smart-99a2fed3-b174-418b-8788-4913bd339d62
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=671756096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.671756096
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3201171352
Short name T237
Test name
Test status
Simulation time 184866801 ps
CPU time 0.91 seconds
Started Aug 10 07:14:37 PM PDT 24
Finished Aug 10 07:14:38 PM PDT 24
Peak memory 207528 kb
Host smart-d85e20b0-6747-4dd6-9d9b-79e1cc2551be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
71352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3201171352
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3441658688
Short name T1481
Test name
Test status
Simulation time 80768865 ps
CPU time 0.74 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:14:30 PM PDT 24
Peak memory 207568 kb
Host smart-2336e701-b7de-46fb-b8ef-eab6e3619043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34416
58688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3441658688
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.219957350
Short name T258
Test name
Test status
Simulation time 181060016 ps
CPU time 0.97 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 207572 kb
Host smart-50b38f6e-c427-4806-ac22-56d1966756a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
7350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.219957350
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3379607251
Short name T1504
Test name
Test status
Simulation time 229920885 ps
CPU time 1 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207492 kb
Host smart-75302ac1-e84e-4e56-b3e2-543c58dc36ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
07251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3379607251
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3317244675
Short name T1779
Test name
Test status
Simulation time 200598277 ps
CPU time 0.98 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:14:30 PM PDT 24
Peak memory 207548 kb
Host smart-c6903bd4-d1ff-4f3d-8ef1-d61128828400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33172
44675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3317244675
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1513019156
Short name T1880
Test name
Test status
Simulation time 176688013 ps
CPU time 0.96 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207480 kb
Host smart-0873c994-cd60-49fb-85a4-6a842ccf2d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
19156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1513019156
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1838445984
Short name T2938
Test name
Test status
Simulation time 189657880 ps
CPU time 0.95 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 207580 kb
Host smart-4ab648b9-6f30-4e67-85f1-febbe5e0342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
45984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1838445984
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_rx_full.1827074780
Short name T1576
Test name
Test status
Simulation time 405762142 ps
CPU time 1.4 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:26 PM PDT 24
Peak memory 207476 kb
Host smart-50510c0d-850c-47df-b8cb-ca3b4130cd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18270
74780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.1827074780
Directory /workspace/38.usbdev_rx_full/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2929925179
Short name T2016
Test name
Test status
Simulation time 150148412 ps
CPU time 0.83 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 207540 kb
Host smart-5dfead8f-bb83-4258-91ea-0d9637c99bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
25179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2929925179
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4044144384
Short name T3550
Test name
Test status
Simulation time 145814375 ps
CPU time 0.85 seconds
Started Aug 10 07:14:37 PM PDT 24
Finished Aug 10 07:14:38 PM PDT 24
Peak memory 207560 kb
Host smart-c0cd3695-9627-4159-a394-a3e9c0588233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
44384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4044144384
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2354972383
Short name T1985
Test name
Test status
Simulation time 250104023 ps
CPU time 1.09 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:14:29 PM PDT 24
Peak memory 207556 kb
Host smart-4ae7ff66-1bd3-4724-be3c-9c3801657267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23549
72383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2354972383
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1440503746
Short name T2636
Test name
Test status
Simulation time 3553570033 ps
CPU time 36.72 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 217920 kb
Host smart-b808c997-a36c-4ba6-9385-8e648cdf2e48
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1440503746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1440503746
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1245756125
Short name T2571
Test name
Test status
Simulation time 158510850 ps
CPU time 0.89 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:14:29 PM PDT 24
Peak memory 207572 kb
Host smart-fababd6a-54b7-4a75-955f-848afb5487c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12457
56125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1245756125
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1602458256
Short name T2184
Test name
Test status
Simulation time 169183827 ps
CPU time 0.88 seconds
Started Aug 10 07:14:24 PM PDT 24
Finished Aug 10 07:14:25 PM PDT 24
Peak memory 207556 kb
Host smart-4f4c7a2e-eff9-4314-bbf8-f287dd11b2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
58256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1602458256
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2908159455
Short name T2848
Test name
Test status
Simulation time 789333376 ps
CPU time 2.03 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:29 PM PDT 24
Peak memory 207376 kb
Host smart-b7e6d7e2-52dc-4c5a-8b31-3bc18574f91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
59455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2908159455
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3401310073
Short name T208
Test name
Test status
Simulation time 2592525316 ps
CPU time 25.23 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:50 PM PDT 24
Peak memory 216088 kb
Host smart-3c21b455-5403-47eb-8517-56d40a3f755f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
10073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3401310073
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.3233260856
Short name T3539
Test name
Test status
Simulation time 198834442 ps
CPU time 0.91 seconds
Started Aug 10 07:14:17 PM PDT 24
Finished Aug 10 07:14:18 PM PDT 24
Peak memory 207544 kb
Host smart-05f33a35-d79a-4908-8b53-ff66f3b035f3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233260856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.3233260856
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_tx_rx_disruption.3262749604
Short name T2585
Test name
Test status
Simulation time 647308511 ps
CPU time 1.59 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:28 PM PDT 24
Peak memory 207604 kb
Host smart-dc595cd2-ea6a-40af-98ae-fe645a6ff131
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262749604 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.usbdev_tx_rx_disruption.3262749604
Directory /workspace/38.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/380.usbdev_tx_rx_disruption.384107302
Short name T107
Test name
Test status
Simulation time 581951076 ps
CPU time 1.63 seconds
Started Aug 10 07:18:25 PM PDT 24
Finished Aug 10 07:18:26 PM PDT 24
Peak memory 207540 kb
Host smart-664cf820-8515-48c0-b21f-5395b1bc8569
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384107302 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 380.usbdev_tx_rx_disruption.384107302
Directory /workspace/380.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/381.usbdev_tx_rx_disruption.770472469
Short name T2951
Test name
Test status
Simulation time 616244547 ps
CPU time 1.75 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207480 kb
Host smart-2620305f-1118-47b0-b2ae-16cda5624ce2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770472469 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 381.usbdev_tx_rx_disruption.770472469
Directory /workspace/381.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/382.usbdev_tx_rx_disruption.3797350122
Short name T2610
Test name
Test status
Simulation time 459892993 ps
CPU time 1.53 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207468 kb
Host smart-48140532-2021-451e-893f-727d16458716
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797350122 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 382.usbdev_tx_rx_disruption.3797350122
Directory /workspace/382.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/383.usbdev_tx_rx_disruption.842871473
Short name T1250
Test name
Test status
Simulation time 476095811 ps
CPU time 1.6 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:33 PM PDT 24
Peak memory 207572 kb
Host smart-95a68e49-0367-43f5-b493-df7646039c9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842871473 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 383.usbdev_tx_rx_disruption.842871473
Directory /workspace/383.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/384.usbdev_tx_rx_disruption.1536976279
Short name T171
Test name
Test status
Simulation time 624691519 ps
CPU time 1.81 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207420 kb
Host smart-26b27c03-1c1a-4fd5-bf36-75e4d05975dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536976279 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 384.usbdev_tx_rx_disruption.1536976279
Directory /workspace/384.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/385.usbdev_tx_rx_disruption.2335724416
Short name T741
Test name
Test status
Simulation time 578833913 ps
CPU time 1.61 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207532 kb
Host smart-7cfc6ed8-2f2e-4434-b903-6cbf91c1a3db
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335724416 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 385.usbdev_tx_rx_disruption.2335724416
Directory /workspace/385.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/386.usbdev_tx_rx_disruption.2950583264
Short name T3566
Test name
Test status
Simulation time 514872068 ps
CPU time 1.56 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207564 kb
Host smart-af6e017b-6942-4c2d-bae5-02d43eeecd60
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950583264 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 386.usbdev_tx_rx_disruption.2950583264
Directory /workspace/386.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/387.usbdev_tx_rx_disruption.2290242
Short name T191
Test name
Test status
Simulation time 462823559 ps
CPU time 1.4 seconds
Started Aug 10 07:18:25 PM PDT 24
Finished Aug 10 07:18:27 PM PDT 24
Peak memory 207584 kb
Host smart-fe7655f5-7a83-4770-a5bd-a9bf9ef19363
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290242 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 387.usbdev_tx_rx_disruption.2290242
Directory /workspace/387.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/388.usbdev_tx_rx_disruption.1945606029
Short name T2824
Test name
Test status
Simulation time 585509302 ps
CPU time 1.61 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207564 kb
Host smart-d90fa0a3-92b3-4f24-b78d-590a1b43d321
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945606029 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 388.usbdev_tx_rx_disruption.1945606029
Directory /workspace/388.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/389.usbdev_tx_rx_disruption.2434882523
Short name T267
Test name
Test status
Simulation time 644774894 ps
CPU time 1.76 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207564 kb
Host smart-1b4f6e45-e3b5-46f7-9f2a-61ca10a17266
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434882523 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 389.usbdev_tx_rx_disruption.2434882523
Directory /workspace/389.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.146667165
Short name T2429
Test name
Test status
Simulation time 65389424 ps
CPU time 0.67 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207560 kb
Host smart-4cb75489-9cbd-4689-8369-e28fedb5a606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=146667165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.146667165
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.363632533
Short name T1769
Test name
Test status
Simulation time 10199569790 ps
CPU time 12.54 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:14:40 PM PDT 24
Peak memory 207772 kb
Host smart-d558431e-8e82-4902-ad9c-3b7e32c35009
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363632533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_disconnect.363632533
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2753994873
Short name T3341
Test name
Test status
Simulation time 14748338934 ps
CPU time 17.5 seconds
Started Aug 10 07:14:29 PM PDT 24
Finished Aug 10 07:14:47 PM PDT 24
Peak memory 216024 kb
Host smart-ac25c0a4-46f7-4d76-a086-80607a81b69f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753994873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2753994873
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.478798808
Short name T1857
Test name
Test status
Simulation time 30869585274 ps
CPU time 35.29 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207812 kb
Host smart-9ef08c43-9bcb-4901-94d5-3d679e825f7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478798808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_resume.478798808
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1299476236
Short name T1271
Test name
Test status
Simulation time 175575243 ps
CPU time 0.96 seconds
Started Aug 10 07:14:30 PM PDT 24
Finished Aug 10 07:14:31 PM PDT 24
Peak memory 207604 kb
Host smart-9bfee99d-a92e-4803-8667-f73caa8a1ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
76236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1299476236
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1942445248
Short name T3405
Test name
Test status
Simulation time 144013724 ps
CPU time 0.85 seconds
Started Aug 10 07:14:31 PM PDT 24
Finished Aug 10 07:14:32 PM PDT 24
Peak memory 207572 kb
Host smart-42e09c60-93b6-441b-9702-1ebae8fcf3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19424
45248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1942445248
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1698635206
Short name T2152
Test name
Test status
Simulation time 385408663 ps
CPU time 1.45 seconds
Started Aug 10 07:14:27 PM PDT 24
Finished Aug 10 07:14:28 PM PDT 24
Peak memory 207508 kb
Host smart-37f33010-4d8b-493a-9a5b-2ca6ed349407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16986
35206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1698635206
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_device_address.32628169
Short name T2870
Test name
Test status
Simulation time 44164537187 ps
CPU time 69.71 seconds
Started Aug 10 07:14:30 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207900 kb
Host smart-e12cdceb-d49e-467a-8af2-ac9b119ddeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628
169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.32628169
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.749819626
Short name T622
Test name
Test status
Simulation time 814088763 ps
CPU time 15.59 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207724 kb
Host smart-94e71517-55f3-4bbc-b035-e08223694768
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749819626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.749819626
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.258034144
Short name T473
Test name
Test status
Simulation time 619992412 ps
CPU time 1.83 seconds
Started Aug 10 07:14:25 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 207556 kb
Host smart-5d78da5f-b63f-450e-85bf-2f466ad801c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25803
4144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.258034144
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3871714911
Short name T1801
Test name
Test status
Simulation time 141123836 ps
CPU time 0.83 seconds
Started Aug 10 07:14:38 PM PDT 24
Finished Aug 10 07:14:39 PM PDT 24
Peak memory 207528 kb
Host smart-86ad861c-f7de-462c-8265-56bce30d370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
14911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3871714911
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2196081079
Short name T1907
Test name
Test status
Simulation time 53930378 ps
CPU time 0.72 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:27 PM PDT 24
Peak memory 207540 kb
Host smart-433749cb-3c21-4604-b5a2-5fdcb3d9eae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
81079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2196081079
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3651589436
Short name T1854
Test name
Test status
Simulation time 813683458 ps
CPU time 2.18 seconds
Started Aug 10 07:14:27 PM PDT 24
Finished Aug 10 07:14:29 PM PDT 24
Peak memory 207696 kb
Host smart-3104207c-453a-4771-b93f-00c727652e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
89436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3651589436
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_types.2584653269
Short name T3576
Test name
Test status
Simulation time 471111232 ps
CPU time 1.33 seconds
Started Aug 10 07:14:26 PM PDT 24
Finished Aug 10 07:14:28 PM PDT 24
Peak memory 207568 kb
Host smart-1440808f-438b-454c-bd1d-c587b88df86e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2584653269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2584653269
Directory /workspace/39.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3028093720
Short name T1694
Test name
Test status
Simulation time 216158341 ps
CPU time 1.66 seconds
Started Aug 10 07:14:28 PM PDT 24
Finished Aug 10 07:14:30 PM PDT 24
Peak memory 207728 kb
Host smart-58dba8bf-a526-46e3-9a23-d2615859ec69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30280
93720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3028093720
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.451950151
Short name T2167
Test name
Test status
Simulation time 248043601 ps
CPU time 1.19 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 215968 kb
Host smart-bc4082c0-6970-4c8a-ae19-e19a1458b167
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=451950151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.451950151
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.799693807
Short name T3228
Test name
Test status
Simulation time 149285644 ps
CPU time 0.82 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:37 PM PDT 24
Peak memory 207464 kb
Host smart-977c4f26-1a75-444d-a402-df5e939f0970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79969
3807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.799693807
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.234019128
Short name T2464
Test name
Test status
Simulation time 209877718 ps
CPU time 0.97 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:37 PM PDT 24
Peak memory 207512 kb
Host smart-52713193-fb7f-4747-87be-35171eb532cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401
9128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.234019128
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3264956882
Short name T819
Test name
Test status
Simulation time 4230702301 ps
CPU time 30.61 seconds
Started Aug 10 07:14:38 PM PDT 24
Finished Aug 10 07:15:08 PM PDT 24
Peak memory 216160 kb
Host smart-8d2d3819-0f15-4e34-bb99-d00325cd95fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3264956882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3264956882
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.1308585344
Short name T2956
Test name
Test status
Simulation time 5667879800 ps
CPU time 65.83 seconds
Started Aug 10 07:14:44 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207824 kb
Host smart-56b30dc9-5b94-4ea3-ad39-1939f715853d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1308585344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1308585344
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.90703037
Short name T3524
Test name
Test status
Simulation time 230372149 ps
CPU time 0.95 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207536 kb
Host smart-a32a38df-302b-48c2-a25b-b380cbde0f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90703
037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.90703037
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.123686158
Short name T831
Test name
Test status
Simulation time 33161674049 ps
CPU time 48.99 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207904 kb
Host smart-9a488b7d-33d4-4857-a614-14d12e3769c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12368
6158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.123686158
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.496891637
Short name T2614
Test name
Test status
Simulation time 9059262558 ps
CPU time 11.12 seconds
Started Aug 10 07:14:32 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 207892 kb
Host smart-4b7ed95f-ff22-4ae2-b786-b0d4c78b4eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49689
1637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.496891637
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.615539645
Short name T1773
Test name
Test status
Simulation time 3532867169 ps
CPU time 32.99 seconds
Started Aug 10 07:14:32 PM PDT 24
Finished Aug 10 07:15:05 PM PDT 24
Peak memory 219284 kb
Host smart-8992f7fc-3acd-4950-8f69-a74f73e5c0d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=615539645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.615539645
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3175536468
Short name T2191
Test name
Test status
Simulation time 2737154827 ps
CPU time 21.51 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:15:04 PM PDT 24
Peak memory 218024 kb
Host smart-b95329f8-31a1-4018-9fa5-76ccce377ada
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3175536468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3175536468
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4120634182
Short name T2360
Test name
Test status
Simulation time 284598238 ps
CPU time 1.07 seconds
Started Aug 10 07:14:32 PM PDT 24
Finished Aug 10 07:14:33 PM PDT 24
Peak memory 207560 kb
Host smart-a741c03c-34fc-4420-9561-04662e5113ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4120634182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4120634182
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.649548438
Short name T3017
Test name
Test status
Simulation time 233596251 ps
CPU time 0.98 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207592 kb
Host smart-d222ca42-f480-44cc-a4ae-a50559a5db33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64954
8438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.649548438
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.4260400379
Short name T1410
Test name
Test status
Simulation time 2556860854 ps
CPU time 19.08 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 216096 kb
Host smart-58c5d6d4-2d69-4f18-966d-4b2f2207d660
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4260400379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.4260400379
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.452623652
Short name T1712
Test name
Test status
Simulation time 158181636 ps
CPU time 0.92 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207528 kb
Host smart-3f1a951f-e9dc-40dc-ac6c-078ae2f8ac3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=452623652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.452623652
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1849400226
Short name T833
Test name
Test status
Simulation time 192851448 ps
CPU time 0.92 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207540 kb
Host smart-47cb8ea5-b5d3-4795-8a04-8b16e9c93c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
00226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1849400226
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.917928878
Short name T157
Test name
Test status
Simulation time 214922290 ps
CPU time 0.97 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207548 kb
Host smart-3c7f57e5-70c1-4a99-9132-8dae151f7252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91792
8878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.917928878
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2406252601
Short name T640
Test name
Test status
Simulation time 165589470 ps
CPU time 0.87 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207416 kb
Host smart-19b95bf3-4aa8-4393-ada0-7817d9170329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
52601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2406252601
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.748401867
Short name T2593
Test name
Test status
Simulation time 186896148 ps
CPU time 0.87 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207540 kb
Host smart-445d499e-be95-4f2d-a974-661cbb1441be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74840
1867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.748401867
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1641482467
Short name T3237
Test name
Test status
Simulation time 175156760 ps
CPU time 0.87 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207548 kb
Host smart-b9476cca-0065-408e-9290-8e47f57c0c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16414
82467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1641482467
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1901179612
Short name T1171
Test name
Test status
Simulation time 152860305 ps
CPU time 0.88 seconds
Started Aug 10 07:14:39 PM PDT 24
Finished Aug 10 07:14:40 PM PDT 24
Peak memory 207560 kb
Host smart-4040ce48-f055-4216-b7cd-b1fb8ecdb09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19011
79612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1901179612
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1101124361
Short name T1876
Test name
Test status
Simulation time 233323689 ps
CPU time 0.98 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207544 kb
Host smart-2745558e-fa98-424e-9c2b-d23373fe4803
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1101124361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1101124361
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3766958761
Short name T2389
Test name
Test status
Simulation time 162329474 ps
CPU time 0.86 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207488 kb
Host smart-495a89ea-7712-4269-a859-dfe4a8d6f699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37669
58761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3766958761
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.774996662
Short name T40
Test name
Test status
Simulation time 81823235 ps
CPU time 0.85 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207504 kb
Host smart-28fd98b1-147c-41e9-91f6-ec3484965e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77499
6662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.774996662
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3522061700
Short name T3346
Test name
Test status
Simulation time 13364196237 ps
CPU time 32.6 seconds
Started Aug 10 07:14:39 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 220468 kb
Host smart-95e73098-08c5-45f4-b198-ca1b6e37b0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35220
61700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3522061700
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.995459702
Short name T1398
Test name
Test status
Simulation time 188098276 ps
CPU time 0.94 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207572 kb
Host smart-36ef2cec-f76f-4fea-9e33-595844211a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99545
9702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.995459702
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2560776270
Short name T2894
Test name
Test status
Simulation time 188182464 ps
CPU time 0.89 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207392 kb
Host smart-468b1837-44d2-45ad-99e1-dee28699609c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
76270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2560776270
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1831376683
Short name T3011
Test name
Test status
Simulation time 189817471 ps
CPU time 0.89 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:37 PM PDT 24
Peak memory 207552 kb
Host smart-bc825334-8c4a-4316-91ed-e5302d08fb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
76683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1831376683
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2399098069
Short name T2293
Test name
Test status
Simulation time 208273269 ps
CPU time 0.96 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:37 PM PDT 24
Peak memory 207580 kb
Host smart-a75c728d-4503-412a-9dd6-69c4b1ccf65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
98069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2399098069
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2324330201
Short name T2622
Test name
Test status
Simulation time 149070850 ps
CPU time 0.86 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207516 kb
Host smart-5e6ebf7b-fe30-46c8-af31-f0fecf60ce44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23243
30201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2324330201
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_rx_full.2894272111
Short name T3504
Test name
Test status
Simulation time 387318645 ps
CPU time 1.21 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:37 PM PDT 24
Peak memory 207512 kb
Host smart-24a0d3de-08b0-4bd9-923d-53afec41dcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
72111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2894272111
Directory /workspace/39.usbdev_rx_full/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2958977404
Short name T3140
Test name
Test status
Simulation time 164245589 ps
CPU time 0.88 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207520 kb
Host smart-8f03de5d-1a26-4667-8c7d-50b408e24c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29589
77404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2958977404
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1039955196
Short name T1567
Test name
Test status
Simulation time 181185714 ps
CPU time 0.88 seconds
Started Aug 10 07:14:44 PM PDT 24
Finished Aug 10 07:14:45 PM PDT 24
Peak memory 207572 kb
Host smart-a33732e4-425d-4126-ac9b-745797b7cf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
55196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1039955196
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1557517102
Short name T3052
Test name
Test status
Simulation time 231009296 ps
CPU time 1.03 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207560 kb
Host smart-92103c87-260e-4019-83fc-84e86f6c525f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
17102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1557517102
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3158891757
Short name T2185
Test name
Test status
Simulation time 1946392203 ps
CPU time 53.83 seconds
Started Aug 10 07:14:44 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 216004 kb
Host smart-aa1d70e5-e886-4d72-828f-5d119dc45fb1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3158891757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3158891757
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3215123487
Short name T1414
Test name
Test status
Simulation time 150633087 ps
CPU time 0.84 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207648 kb
Host smart-e4a6e65f-07dd-4d2b-be24-3f9e29568731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32151
23487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3215123487
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1063027686
Short name T2974
Test name
Test status
Simulation time 252103265 ps
CPU time 1.02 seconds
Started Aug 10 07:14:44 PM PDT 24
Finished Aug 10 07:14:45 PM PDT 24
Peak memory 207572 kb
Host smart-5bb2a161-8693-4bc3-92d7-5c4d027d1c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
27686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1063027686
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1206851961
Short name T1432
Test name
Test status
Simulation time 218832353 ps
CPU time 0.92 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:35 PM PDT 24
Peak memory 207504 kb
Host smart-9bc4cd75-652a-459d-bd0b-f3be9e9682d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12068
51961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1206851961
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.750226541
Short name T1822
Test name
Test status
Simulation time 2060260001 ps
CPU time 21.02 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:55 PM PDT 24
Peak memory 215932 kb
Host smart-e0c969e7-e0e8-44dc-b88f-0ba3cca42e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75022
6541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.750226541
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1315679566
Short name T2942
Test name
Test status
Simulation time 178798201 ps
CPU time 0.87 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:36 PM PDT 24
Peak memory 207536 kb
Host smart-7a07ac11-966f-48c3-9ca8-a7a1c655989e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315679566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos
t_handshake.1315679566
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_tx_rx_disruption.2145727325
Short name T1785
Test name
Test status
Simulation time 514764112 ps
CPU time 1.8 seconds
Started Aug 10 07:14:36 PM PDT 24
Finished Aug 10 07:14:38 PM PDT 24
Peak memory 207576 kb
Host smart-a3e542ed-b3ff-406f-b051-bb139c470050
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145727325 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.usbdev_tx_rx_disruption.2145727325
Directory /workspace/39.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/390.usbdev_tx_rx_disruption.3212277004
Short name T3059
Test name
Test status
Simulation time 590631393 ps
CPU time 1.62 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207528 kb
Host smart-248c682f-6877-4526-a073-7795a5ea8b05
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212277004 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 390.usbdev_tx_rx_disruption.3212277004
Directory /workspace/390.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/391.usbdev_tx_rx_disruption.818082612
Short name T3124
Test name
Test status
Simulation time 457017082 ps
CPU time 1.41 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207564 kb
Host smart-6bc787fd-d2a8-43c4-bcef-a49389637e9a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818082612 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 391.usbdev_tx_rx_disruption.818082612
Directory /workspace/391.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/392.usbdev_tx_rx_disruption.1793414251
Short name T80
Test name
Test status
Simulation time 455938444 ps
CPU time 1.52 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207564 kb
Host smart-be523978-e84a-45da-84f3-3d20774086cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793414251 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 392.usbdev_tx_rx_disruption.1793414251
Directory /workspace/392.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/393.usbdev_tx_rx_disruption.1720434949
Short name T1549
Test name
Test status
Simulation time 648825168 ps
CPU time 1.74 seconds
Started Aug 10 07:18:31 PM PDT 24
Finished Aug 10 07:18:33 PM PDT 24
Peak memory 207584 kb
Host smart-110eee52-7a72-4e93-83e8-1ccdb75ae5f8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720434949 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 393.usbdev_tx_rx_disruption.1720434949
Directory /workspace/393.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/394.usbdev_tx_rx_disruption.662667735
Short name T1616
Test name
Test status
Simulation time 505488663 ps
CPU time 1.54 seconds
Started Aug 10 07:18:28 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207420 kb
Host smart-c39e149d-5b32-44ae-9f93-8f2360975fa6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662667735 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 394.usbdev_tx_rx_disruption.662667735
Directory /workspace/394.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/395.usbdev_tx_rx_disruption.2635450019
Short name T1426
Test name
Test status
Simulation time 588639130 ps
CPU time 1.63 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207532 kb
Host smart-b8fa4712-a2fd-426f-af30-0e2e1f6d3063
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635450019 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 395.usbdev_tx_rx_disruption.2635450019
Directory /workspace/395.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/396.usbdev_tx_rx_disruption.3179788769
Short name T1011
Test name
Test status
Simulation time 446107178 ps
CPU time 1.45 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207420 kb
Host smart-b9bb3b9c-0239-420d-9804-984d48058bbc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179788769 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 396.usbdev_tx_rx_disruption.3179788769
Directory /workspace/396.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/397.usbdev_tx_rx_disruption.1313037953
Short name T121
Test name
Test status
Simulation time 606355138 ps
CPU time 1.61 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207552 kb
Host smart-02f99c10-186d-4dce-bf32-e96e50aa3acc
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313037953 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 397.usbdev_tx_rx_disruption.1313037953
Directory /workspace/397.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/398.usbdev_tx_rx_disruption.479472033
Short name T2819
Test name
Test status
Simulation time 503524467 ps
CPU time 1.48 seconds
Started Aug 10 07:18:29 PM PDT 24
Finished Aug 10 07:18:31 PM PDT 24
Peak memory 207668 kb
Host smart-a0e5b747-274f-41d4-8316-2f5ae44fd0fe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479472033 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 398.usbdev_tx_rx_disruption.479472033
Directory /workspace/398.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/399.usbdev_tx_rx_disruption.1895079063
Short name T621
Test name
Test status
Simulation time 518966517 ps
CPU time 1.63 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207600 kb
Host smart-05714e68-63ab-47b9-9e1a-687432454926
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895079063 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 399.usbdev_tx_rx_disruption.1895079063
Directory /workspace/399.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2903289668
Short name T2245
Test name
Test status
Simulation time 34965748 ps
CPU time 0.67 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 207544 kb
Host smart-e374779f-327b-4bc4-9794-bf4413c591a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2903289668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2903289668
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3033822346
Short name T1987
Test name
Test status
Simulation time 6427575489 ps
CPU time 10.3 seconds
Started Aug 10 07:02:14 PM PDT 24
Finished Aug 10 07:02:24 PM PDT 24
Peak memory 215996 kb
Host smart-57ff4b03-c7b5-409c-be3a-b559687929ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033822346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.3033822346
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2477169000
Short name T2982
Test name
Test status
Simulation time 13322294942 ps
CPU time 14.41 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:43 PM PDT 24
Peak memory 216012 kb
Host smart-4e66957a-7752-4177-af64-96a2ba102f8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477169000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2477169000
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1459573203
Short name T10
Test name
Test status
Simulation time 26269941150 ps
CPU time 37.94 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:03:07 PM PDT 24
Peak memory 215900 kb
Host smart-bb222c50-dabc-4210-ae27-4360ceead399
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459573203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.1459573203
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.511615630
Short name T3478
Test name
Test status
Simulation time 192659699 ps
CPU time 0.92 seconds
Started Aug 10 07:02:27 PM PDT 24
Finished Aug 10 07:02:28 PM PDT 24
Peak memory 207396 kb
Host smart-9cd53fe4-e621-43bb-a24a-dc4345219130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51161
5630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.511615630
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.543486847
Short name T57
Test name
Test status
Simulation time 157875729 ps
CPU time 0.87 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:29 PM PDT 24
Peak memory 207532 kb
Host smart-e47ab8a9-f188-4fff-b543-7d93d5c7059f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54348
6847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.543486847
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.562710668
Short name T64
Test name
Test status
Simulation time 180411156 ps
CPU time 0.85 seconds
Started Aug 10 07:02:30 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 207536 kb
Host smart-661bd789-3b0f-48d7-9262-5928a8ae1837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56271
0668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.562710668
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1204985205
Short name T87
Test name
Test status
Simulation time 214409226 ps
CPU time 0.95 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:02:30 PM PDT 24
Peak memory 207604 kb
Host smart-1dbf2f26-9015-405d-9578-05148876054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12049
85205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1204985205
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2209373043
Short name T603
Test name
Test status
Simulation time 554877097 ps
CPU time 1.78 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 207504 kb
Host smart-8978b6de-a0cc-4140-ac1f-7009273f0b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22093
73043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2209373043
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.206400324
Short name T112
Test name
Test status
Simulation time 503457322 ps
CPU time 1.48 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:02:30 PM PDT 24
Peak memory 207472 kb
Host smart-94c030f6-2018-4e4b-a3fe-5e568491fe22
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=206400324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.206400324
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.4138787767
Short name T393
Test name
Test status
Simulation time 14173179054 ps
CPU time 22.76 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207792 kb
Host smart-b0e76d54-b2ed-4f8d-90d7-7f517b75338c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387
87767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.4138787767
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.1258172886
Short name T1841
Test name
Test status
Simulation time 584473507 ps
CPU time 11.26 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:40 PM PDT 24
Peak memory 207772 kb
Host smart-02fcc225-88ac-4d0c-8fc9-3ae6df88323d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258172886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1258172886
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2492347780
Short name T3567
Test name
Test status
Simulation time 604041014 ps
CPU time 1.91 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 207508 kb
Host smart-19c56469-b44e-41dc-b2d6-1c103e8cb9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24923
47780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2492347780
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2126913800
Short name T2024
Test name
Test status
Simulation time 141372305 ps
CPU time 0.84 seconds
Started Aug 10 07:02:29 PM PDT 24
Finished Aug 10 07:02:30 PM PDT 24
Peak memory 207508 kb
Host smart-2d27f810-7678-420c-8305-70903949c44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21269
13800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2126913800
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1490627408
Short name T1566
Test name
Test status
Simulation time 116980231 ps
CPU time 0.8 seconds
Started Aug 10 07:02:30 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 207384 kb
Host smart-e3d92ad4-5bac-40c7-b958-b5f6868fd7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14906
27408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1490627408
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1365568533
Short name T580
Test name
Test status
Simulation time 940383826 ps
CPU time 2.45 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:31 PM PDT 24
Peak memory 207740 kb
Host smart-568113b0-72c9-4a7a-a29d-72dc5e4bbf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
68533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1365568533
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_types.336876425
Short name T416
Test name
Test status
Simulation time 673483631 ps
CPU time 1.65 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:30 PM PDT 24
Peak memory 207524 kb
Host smart-dd43cc93-9f3a-465a-833b-a89bd1d32254
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=336876425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.336876425
Directory /workspace/4.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1692840157
Short name T1650
Test name
Test status
Simulation time 268591254 ps
CPU time 2.13 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:02:42 PM PDT 24
Peak memory 207760 kb
Host smart-6afc4791-6843-4115-b981-b7a096e99c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
40157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1692840157
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2993530512
Short name T3499
Test name
Test status
Simulation time 116193020695 ps
CPU time 214.5 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 207852 kb
Host smart-c4d0e808-f957-4b0d-bc29-b5f18cdba8f3
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2993530512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2993530512
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1300571168
Short name T2484
Test name
Test status
Simulation time 115374049443 ps
CPU time 167.62 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:05:27 PM PDT 24
Peak memory 207924 kb
Host smart-00401dfa-7fd6-49f1-a36b-47e3715620bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300571168 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1300571168
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3365918028
Short name T2842
Test name
Test status
Simulation time 106160001093 ps
CPU time 149.9 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207828 kb
Host smart-d7cd2ff0-e3f9-41eb-8443-e7cc696dbc14
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3365918028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3365918028
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.955648365
Short name T369
Test name
Test status
Simulation time 101313319866 ps
CPU time 157.32 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:05:17 PM PDT 24
Peak memory 207816 kb
Host smart-c262278f-6ac2-49f2-88d6-fd18412a496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955648365 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.955648365
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2060079310
Short name T2693
Test name
Test status
Simulation time 94148094903 ps
CPU time 142.52 seconds
Started Aug 10 07:02:43 PM PDT 24
Finished Aug 10 07:05:06 PM PDT 24
Peak memory 207772 kb
Host smart-a967b03a-a9dc-43f4-b89e-2ffb83cf5107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
79310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2060079310
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3197445884
Short name T600
Test name
Test status
Simulation time 155795192 ps
CPU time 0.87 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:02:41 PM PDT 24
Peak memory 207416 kb
Host smart-16779d57-fbfb-446d-81de-1ffdd51181d3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3197445884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3197445884
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2898297434
Short name T1731
Test name
Test status
Simulation time 130860498 ps
CPU time 0.78 seconds
Started Aug 10 07:02:41 PM PDT 24
Finished Aug 10 07:02:42 PM PDT 24
Peak memory 207576 kb
Host smart-7657d9f2-28e1-4dd5-8dc7-f48830644a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
97434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2898297434
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2042391237
Short name T3068
Test name
Test status
Simulation time 201012667 ps
CPU time 0.94 seconds
Started Aug 10 07:02:41 PM PDT 24
Finished Aug 10 07:02:42 PM PDT 24
Peak memory 207508 kb
Host smart-352fe343-5a67-453f-8c9a-619794d6b8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
91237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2042391237
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3705924357
Short name T1188
Test name
Test status
Simulation time 3084402185 ps
CPU time 88.78 seconds
Started Aug 10 07:02:41 PM PDT 24
Finished Aug 10 07:04:10 PM PDT 24
Peak memory 218672 kb
Host smart-2bccdd79-2004-42a8-a78b-45761a649c49
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3705924357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3705924357
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2182687670
Short name T2732
Test name
Test status
Simulation time 12604292517 ps
CPU time 89.3 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:04:08 PM PDT 24
Peak memory 207864 kb
Host smart-34a04d88-d822-4c49-b0c6-8f92ce07d998
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2182687670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2182687670
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1230007532
Short name T947
Test name
Test status
Simulation time 224464894 ps
CPU time 0.93 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:02:40 PM PDT 24
Peak memory 207520 kb
Host smart-2d463a02-486b-4baa-b324-43f7262421a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
07532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1230007532
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1179212544
Short name T1724
Test name
Test status
Simulation time 25120586282 ps
CPU time 30.91 seconds
Started Aug 10 07:02:42 PM PDT 24
Finished Aug 10 07:03:13 PM PDT 24
Peak memory 215968 kb
Host smart-844090a7-ccd6-4276-96e6-4ddc5c5738b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11792
12544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1179212544
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.117685106
Short name T1950
Test name
Test status
Simulation time 10350047480 ps
CPU time 15.47 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:02:56 PM PDT 24
Peak memory 207844 kb
Host smart-761e91d8-9d1a-4b90-a588-f823c5f606f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11768
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.117685106
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.999422111
Short name T224
Test name
Test status
Simulation time 4769299720 ps
CPU time 140.51 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:05:00 PM PDT 24
Peak memory 224244 kb
Host smart-9148d584-0398-4351-9e5c-04eedbf20cf6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=999422111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.999422111
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2822393139
Short name T2606
Test name
Test status
Simulation time 3162317261 ps
CPU time 87.59 seconds
Started Aug 10 07:02:38 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 216140 kb
Host smart-6d4fe857-ee8b-48a5-899e-921b8a178ac3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2822393139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2822393139
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2692652187
Short name T2775
Test name
Test status
Simulation time 271149330 ps
CPU time 1.01 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:02:40 PM PDT 24
Peak memory 207552 kb
Host smart-c81011ab-b74c-4224-b608-58e415aa1b47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2692652187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2692652187
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.267723095
Short name T3222
Test name
Test status
Simulation time 184432675 ps
CPU time 0.88 seconds
Started Aug 10 07:02:40 PM PDT 24
Finished Aug 10 07:02:41 PM PDT 24
Peak memory 207540 kb
Host smart-d487b7ed-0620-4c56-a9c5-9d11022972ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26772
3095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.267723095
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.294170815
Short name T1872
Test name
Test status
Simulation time 2075029713 ps
CPU time 16.03 seconds
Started Aug 10 07:02:39 PM PDT 24
Finished Aug 10 07:02:55 PM PDT 24
Peak memory 217604 kb
Host smart-1d2dfd93-1420-47da-8dfa-3349f95cd0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
0815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.294170815
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1666116656
Short name T3596
Test name
Test status
Simulation time 1754889188 ps
CPU time 17.74 seconds
Started Aug 10 07:02:41 PM PDT 24
Finished Aug 10 07:02:59 PM PDT 24
Peak memory 217464 kb
Host smart-7e58f858-6c08-45ff-bdc8-4c282c4ac41e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1666116656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1666116656
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1660278924
Short name T2637
Test name
Test status
Simulation time 2487851657 ps
CPU time 68.11 seconds
Started Aug 10 07:02:55 PM PDT 24
Finished Aug 10 07:04:03 PM PDT 24
Peak memory 215800 kb
Host smart-f1e04bb4-fc29-48e9-83d4-1a4fce250579
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1660278924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1660278924
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.277527372
Short name T807
Test name
Test status
Simulation time 171718328 ps
CPU time 0.85 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207508 kb
Host smart-0e6cb82f-3cf6-46d9-b29d-9a31acf55970
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=277527372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.277527372
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.95722826
Short name T2134
Test name
Test status
Simulation time 176032405 ps
CPU time 0.85 seconds
Started Aug 10 07:02:54 PM PDT 24
Finished Aug 10 07:02:55 PM PDT 24
Peak memory 207560 kb
Host smart-9e255a5a-ba88-4b7c-8563-71319a21158d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95722
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.95722826
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.709912036
Short name T150
Test name
Test status
Simulation time 205044542 ps
CPU time 0.95 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207420 kb
Host smart-7a884260-1906-4fbb-a773-af86b55a7344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70991
2036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.709912036
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2067541123
Short name T2416
Test name
Test status
Simulation time 214532278 ps
CPU time 0.97 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207500 kb
Host smart-c834adfc-1cc6-44b2-88af-576bbe76b769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675
41123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2067541123
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2680971530
Short name T1599
Test name
Test status
Simulation time 175958567 ps
CPU time 0.9 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207552 kb
Host smart-a0182863-da86-4831-8d14-d6beb1a55a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26809
71530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2680971530
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3989968240
Short name T605
Test name
Test status
Simulation time 214802198 ps
CPU time 0.89 seconds
Started Aug 10 07:02:49 PM PDT 24
Finished Aug 10 07:02:50 PM PDT 24
Peak memory 207540 kb
Host smart-fba34a6d-d980-4e7b-86e2-6271eb149e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
68240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3989968240
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3749582238
Short name T1789
Test name
Test status
Simulation time 154709191 ps
CPU time 0.85 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:50 PM PDT 24
Peak memory 207656 kb
Host smart-821eea11-f66a-4712-8446-f2bf318d2b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37495
82238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3749582238
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1281697582
Short name T2072
Test name
Test status
Simulation time 239425287 ps
CPU time 0.99 seconds
Started Aug 10 07:02:49 PM PDT 24
Finished Aug 10 07:02:50 PM PDT 24
Peak memory 207572 kb
Host smart-11754525-52ec-488d-849a-b5ef34101cc9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1281697582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1281697582
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.286184545
Short name T2127
Test name
Test status
Simulation time 192441785 ps
CPU time 0.97 seconds
Started Aug 10 07:02:50 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207568 kb
Host smart-7dac4e99-7a85-49a5-98d1-2dea6977003d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
4545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.286184545
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1715429065
Short name T1157
Test name
Test status
Simulation time 149924900 ps
CPU time 0.81 seconds
Started Aug 10 07:02:49 PM PDT 24
Finished Aug 10 07:02:50 PM PDT 24
Peak memory 207468 kb
Host smart-938bbe90-ac74-4288-bf2e-b48504069512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17154
29065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1715429065
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1275336728
Short name T2326
Test name
Test status
Simulation time 43076361 ps
CPU time 0.68 seconds
Started Aug 10 07:02:49 PM PDT 24
Finished Aug 10 07:02:49 PM PDT 24
Peak memory 207528 kb
Host smart-115ba00e-51c1-4f10-b58c-c3867d91c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
36728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1275336728
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3595362764
Short name T3425
Test name
Test status
Simulation time 183601191 ps
CPU time 0.91 seconds
Started Aug 10 07:02:54 PM PDT 24
Finished Aug 10 07:02:55 PM PDT 24
Peak memory 207564 kb
Host smart-1b0b350f-8a56-4d73-bf5d-4538a85aa372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
62764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3595362764
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.931497763
Short name T2539
Test name
Test status
Simulation time 226088431 ps
CPU time 0.98 seconds
Started Aug 10 07:02:55 PM PDT 24
Finished Aug 10 07:02:56 PM PDT 24
Peak memory 207160 kb
Host smart-42191752-11c9-4700-8a84-f8045787aba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93149
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.931497763
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1170133135
Short name T1303
Test name
Test status
Simulation time 3186964793 ps
CPU time 20.12 seconds
Started Aug 10 07:03:00 PM PDT 24
Finished Aug 10 07:03:20 PM PDT 24
Peak memory 224320 kb
Host smart-d9531e97-9f50-4764-829e-b916fad1b5ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170133135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1170133135
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3476679776
Short name T638
Test name
Test status
Simulation time 3241042669 ps
CPU time 30.49 seconds
Started Aug 10 07:03:04 PM PDT 24
Finished Aug 10 07:03:34 PM PDT 24
Peak memory 218792 kb
Host smart-2dc15e49-be51-40ad-91f9-185f94c9108f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3476679776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3476679776
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1595535829
Short name T2307
Test name
Test status
Simulation time 8984553300 ps
CPU time 57.82 seconds
Started Aug 10 07:03:00 PM PDT 24
Finished Aug 10 07:03:58 PM PDT 24
Peak memory 224220 kb
Host smart-815e569e-4e11-42f8-9a2d-83579a43f50a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595535829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1595535829
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.4254941320
Short name T3151
Test name
Test status
Simulation time 223984026 ps
CPU time 1 seconds
Started Aug 10 07:02:55 PM PDT 24
Finished Aug 10 07:02:56 PM PDT 24
Peak memory 207564 kb
Host smart-47284299-9ad8-4d1e-92a5-3d7636358fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
41320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.4254941320
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.4280855932
Short name T29
Test name
Test status
Simulation time 168318320 ps
CPU time 0.91 seconds
Started Aug 10 07:03:04 PM PDT 24
Finished Aug 10 07:03:05 PM PDT 24
Peak memory 207556 kb
Host smart-861df7b5-5ca7-4b56-aee1-2e23e0d61b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
55932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.4280855932
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_resume_link_active.1800243390
Short name T3132
Test name
Test status
Simulation time 20166341410 ps
CPU time 23.13 seconds
Started Aug 10 07:03:03 PM PDT 24
Finished Aug 10 07:03:26 PM PDT 24
Peak memory 207656 kb
Host smart-c8fe02b9-3a6f-474f-af7a-194909b8f04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
43390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_resume_link_active.1800243390
Directory /workspace/4.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2335962662
Short name T2287
Test name
Test status
Simulation time 195694224 ps
CPU time 0.91 seconds
Started Aug 10 07:03:02 PM PDT 24
Finished Aug 10 07:03:03 PM PDT 24
Peak memory 207548 kb
Host smart-15684225-a4b3-40d9-971e-6ac592595214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23359
62662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2335962662
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_full.3024411925
Short name T1342
Test name
Test status
Simulation time 350121073 ps
CPU time 1.17 seconds
Started Aug 10 07:02:59 PM PDT 24
Finished Aug 10 07:03:00 PM PDT 24
Peak memory 207532 kb
Host smart-a9f45ca7-be66-463a-bbda-6ac399615def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
11925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.3024411925
Directory /workspace/4.usbdev_rx_full/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1235958367
Short name T83
Test name
Test status
Simulation time 166862318 ps
CPU time 0.89 seconds
Started Aug 10 07:03:03 PM PDT 24
Finished Aug 10 07:03:04 PM PDT 24
Peak memory 207580 kb
Host smart-d7667418-31bd-475b-9105-3c1cf2aac838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
58367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1235958367
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2684626029
Short name T3587
Test name
Test status
Simulation time 337883874 ps
CPU time 1.26 seconds
Started Aug 10 07:03:00 PM PDT 24
Finished Aug 10 07:03:01 PM PDT 24
Peak memory 207488 kb
Host smart-aa457417-8e35-49ea-97b1-cf9aebdac2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26846
26029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2684626029
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2692349913
Short name T2405
Test name
Test status
Simulation time 317104983 ps
CPU time 1.1 seconds
Started Aug 10 07:03:01 PM PDT 24
Finished Aug 10 07:03:03 PM PDT 24
Peak memory 207480 kb
Host smart-cb3540d9-8120-4112-b5c3-7743f66ed157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26923
49913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2692349913
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4198664613
Short name T3123
Test name
Test status
Simulation time 152514907 ps
CPU time 0.85 seconds
Started Aug 10 07:03:02 PM PDT 24
Finished Aug 10 07:03:02 PM PDT 24
Peak memory 207544 kb
Host smart-c2909a79-938a-4bc9-859a-3f3086b3a82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41986
64613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4198664613
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.309304559
Short name T3114
Test name
Test status
Simulation time 149461060 ps
CPU time 0.87 seconds
Started Aug 10 07:03:03 PM PDT 24
Finished Aug 10 07:03:04 PM PDT 24
Peak memory 207576 kb
Host smart-dad915f7-370d-47c6-88e8-265a739fec8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30930
4559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.309304559
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2759861704
Short name T1020
Test name
Test status
Simulation time 237721399 ps
CPU time 1.08 seconds
Started Aug 10 07:03:00 PM PDT 24
Finished Aug 10 07:03:02 PM PDT 24
Peak memory 207532 kb
Host smart-d0f83b20-e728-45f3-8d9e-2217d360be3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27598
61704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2759861704
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4114440943
Short name T3574
Test name
Test status
Simulation time 2108803516 ps
CPU time 62.46 seconds
Started Aug 10 07:03:02 PM PDT 24
Finished Aug 10 07:04:05 PM PDT 24
Peak memory 217576 kb
Host smart-5dbc1d25-c849-4896-bab0-11d2abf3937b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4114440943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4114440943
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3590700307
Short name T2512
Test name
Test status
Simulation time 181058654 ps
CPU time 0.93 seconds
Started Aug 10 07:03:01 PM PDT 24
Finished Aug 10 07:03:02 PM PDT 24
Peak memory 207480 kb
Host smart-872b6855-1868-468e-a06d-303f24764ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35907
00307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3590700307
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.4242956008
Short name T33
Test name
Test status
Simulation time 197549786 ps
CPU time 0.9 seconds
Started Aug 10 07:03:00 PM PDT 24
Finished Aug 10 07:03:01 PM PDT 24
Peak memory 207492 kb
Host smart-5b34d490-9b17-422b-a702-b781079512c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
56008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.4242956008
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3825644415
Short name T1918
Test name
Test status
Simulation time 1007563270 ps
CPU time 2.36 seconds
Started Aug 10 07:03:08 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 207632 kb
Host smart-0a5b9f67-1a84-4e6f-8824-7b63767d5ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
44415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3825644415
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.4033776406
Short name T1968
Test name
Test status
Simulation time 2699630426 ps
CPU time 27.25 seconds
Started Aug 10 07:03:03 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 216160 kb
Host smart-a4932da2-bf41-4870-9e92-faca75f47761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40337
76406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.4033776406
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2400327535
Short name T89
Test name
Test status
Simulation time 3937466370 ps
CPU time 28.98 seconds
Started Aug 10 07:03:08 PM PDT 24
Finished Aug 10 07:03:37 PM PDT 24
Peak memory 224304 kb
Host smart-b8fa23d3-3c71-42d1-a331-b8bb331778a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400327535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2400327535
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3271238980
Short name T2827
Test name
Test status
Simulation time 3597743029 ps
CPU time 22.5 seconds
Started Aug 10 07:02:28 PM PDT 24
Finished Aug 10 07:02:51 PM PDT 24
Peak memory 207848 kb
Host smart-790e2dcc-daec-4665-b757-6dce8d5947c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271238980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.3271238980
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_tx_rx_disruption.3882106757
Short name T1189
Test name
Test status
Simulation time 478000557 ps
CPU time 1.51 seconds
Started Aug 10 07:03:10 PM PDT 24
Finished Aug 10 07:03:12 PM PDT 24
Peak memory 207464 kb
Host smart-e5f3feea-9a18-41bb-bf04-b1c3ce3d2529
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882106757 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.usbdev_tx_rx_disruption.3882106757
Directory /workspace/4.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.275417800
Short name T1361
Test name
Test status
Simulation time 46623454 ps
CPU time 0.73 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207424 kb
Host smart-ac9e0557-4667-4e4a-bf38-a41ea8b33282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=275417800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.275417800
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.289001298
Short name T3138
Test name
Test status
Simulation time 12237229410 ps
CPU time 16.37 seconds
Started Aug 10 07:14:35 PM PDT 24
Finished Aug 10 07:14:51 PM PDT 24
Peak memory 207760 kb
Host smart-15abf953-a96a-44ce-954c-2ccce59359a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289001298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_ao
n_wake_disconnect.289001298
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1297388563
Short name T1551
Test name
Test status
Simulation time 20763191962 ps
CPU time 23.14 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:14:58 PM PDT 24
Peak memory 207764 kb
Host smart-7e9da931-8509-4cd8-a30a-21b51054b5ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297388563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1297388563
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2270996244
Short name T872
Test name
Test status
Simulation time 29622686733 ps
CPU time 36.2 seconds
Started Aug 10 07:14:34 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 207756 kb
Host smart-178867e0-b168-4bd2-854f-d00cccd02617
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270996244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.2270996244
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2394359393
Short name T2398
Test name
Test status
Simulation time 183446049 ps
CPU time 0.89 seconds
Started Aug 10 07:14:41 PM PDT 24
Finished Aug 10 07:14:42 PM PDT 24
Peak memory 207584 kb
Host smart-d0d2cc61-69fc-4492-a390-1984c2e52706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23943
59393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2394359393
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.683754415
Short name T869
Test name
Test status
Simulation time 146577037 ps
CPU time 0.82 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 207572 kb
Host smart-d18d04ae-4da8-4744-978b-8c0edb2ea822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68375
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.683754415
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1548744827
Short name T130
Test name
Test status
Simulation time 500791321 ps
CPU time 1.59 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207572 kb
Host smart-7f8bd40c-42a2-47a8-92c1-6deca056ffc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
44827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1548744827
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.287030830
Short name T3468
Test name
Test status
Simulation time 396305988 ps
CPU time 1.25 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 207528 kb
Host smart-dbbec733-036f-45ac-bd98-ddc71d987560
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=287030830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.287030830
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3582613517
Short name T1829
Test name
Test status
Simulation time 28489590463 ps
CPU time 43.35 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:15:26 PM PDT 24
Peak memory 207860 kb
Host smart-a26bbe4b-7348-4b9d-afa2-a01b5d2e4e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
13517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3582613517
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.941907970
Short name T3054
Test name
Test status
Simulation time 891280787 ps
CPU time 18.41 seconds
Started Aug 10 07:14:45 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207576 kb
Host smart-ed3857e4-59a3-4f8c-8f07-941775a895fb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941907970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.941907970
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3007121076
Short name T1352
Test name
Test status
Simulation time 654986539 ps
CPU time 1.81 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207484 kb
Host smart-0c6e8c24-8bbc-4445-abdf-fcfdc055285f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
21076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3007121076
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1860192132
Short name T66
Test name
Test status
Simulation time 156392346 ps
CPU time 0.84 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207472 kb
Host smart-7c021c02-3fd1-46ce-b321-5c366876f28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18601
92132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1860192132
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.725100424
Short name T604
Test name
Test status
Simulation time 37114041 ps
CPU time 0.7 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207520 kb
Host smart-892b1773-8c5b-4a86-8bbb-bb57046195d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72510
0424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.725100424
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3861194089
Short name T2428
Test name
Test status
Simulation time 1005147361 ps
CPU time 2.57 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:45 PM PDT 24
Peak memory 207760 kb
Host smart-ec0a3e8f-32c3-40a6-ba33-56b4a09f685a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
94089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3861194089
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_types.501545301
Short name T488
Test name
Test status
Simulation time 702146828 ps
CPU time 1.68 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 207404 kb
Host smart-97d51c11-c486-418d-bc81-5631528bf2b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=501545301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.501545301
Directory /workspace/40.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3719571142
Short name T1255
Test name
Test status
Simulation time 157673906 ps
CPU time 1.36 seconds
Started Aug 10 07:14:45 PM PDT 24
Finished Aug 10 07:14:46 PM PDT 24
Peak memory 207560 kb
Host smart-f775b7a6-dfd5-4169-a42d-0999c301fa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
71142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3719571142
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2049544550
Short name T3066
Test name
Test status
Simulation time 251819788 ps
CPU time 1.12 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 215904 kb
Host smart-1685eb35-4ce8-4f35-926e-07a64fdc8b81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2049544550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2049544550
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3702279618
Short name T806
Test name
Test status
Simulation time 152594685 ps
CPU time 0.82 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:43 PM PDT 24
Peak memory 207404 kb
Host smart-fc476180-2c97-4165-abc8-84ebe859b05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37022
79618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3702279618
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1632045626
Short name T3092
Test name
Test status
Simulation time 205247986 ps
CPU time 0.97 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:14:44 PM PDT 24
Peak memory 207596 kb
Host smart-7df4656f-fde4-454f-8d88-764f5540c9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
45626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1632045626
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2615145880
Short name T3246
Test name
Test status
Simulation time 4135840838 ps
CPU time 115.87 seconds
Started Aug 10 07:14:40 PM PDT 24
Finished Aug 10 07:16:36 PM PDT 24
Peak memory 218640 kb
Host smart-3eedc19e-8c2d-4089-bcce-2195e81dca06
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2615145880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2615145880
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1652604190
Short name T3136
Test name
Test status
Simulation time 5817617199 ps
CPU time 67.38 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207836 kb
Host smart-425c62b5-bcd1-40f4-af71-b49ee5af061b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1652604190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1652604190
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3997647122
Short name T1833
Test name
Test status
Simulation time 294573561 ps
CPU time 1 seconds
Started Aug 10 07:14:45 PM PDT 24
Finished Aug 10 07:14:46 PM PDT 24
Peak memory 207420 kb
Host smart-9d1d75d6-3901-45b1-893b-fb18ff3f0e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39976
47122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3997647122
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1956765538
Short name T2668
Test name
Test status
Simulation time 32041559162 ps
CPU time 55.61 seconds
Started Aug 10 07:14:45 PM PDT 24
Finished Aug 10 07:15:41 PM PDT 24
Peak memory 207716 kb
Host smart-26a5ed69-a914-4b4b-84a3-723bd9902e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
65538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1956765538
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2098963216
Short name T1896
Test name
Test status
Simulation time 9550960647 ps
CPU time 13.43 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207824 kb
Host smart-2070b3ea-cd42-4daf-a6a5-68f718c44f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
63216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2098963216
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.4121216423
Short name T3020
Test name
Test status
Simulation time 3980899650 ps
CPU time 115.66 seconds
Started Aug 10 07:14:42 PM PDT 24
Finished Aug 10 07:16:38 PM PDT 24
Peak memory 218632 kb
Host smart-351a32cb-dfbe-491f-8472-c9706697b800
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4121216423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.4121216423
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2927588400
Short name T2731
Test name
Test status
Simulation time 2403648300 ps
CPU time 17.86 seconds
Started Aug 10 07:14:41 PM PDT 24
Finished Aug 10 07:14:59 PM PDT 24
Peak memory 217832 kb
Host smart-78116162-7b7d-4160-8df1-d49e0b4254d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2927588400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2927588400
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3586231331
Short name T2737
Test name
Test status
Simulation time 257165053 ps
CPU time 1.15 seconds
Started Aug 10 07:14:41 PM PDT 24
Finished Aug 10 07:14:42 PM PDT 24
Peak memory 207508 kb
Host smart-4576dad2-a492-4c12-ad78-a97c599a3eb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3586231331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3586231331
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.11017984
Short name T1860
Test name
Test status
Simulation time 203245337 ps
CPU time 0.98 seconds
Started Aug 10 07:14:44 PM PDT 24
Finished Aug 10 07:14:45 PM PDT 24
Peak memory 207660 kb
Host smart-92716e7b-6ad8-4e3e-abf3-73e6b3c428ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.11017984
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2500318550
Short name T3269
Test name
Test status
Simulation time 2422920753 ps
CPU time 18.99 seconds
Started Aug 10 07:14:43 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 217792 kb
Host smart-26612e4d-3f80-4667-9b8f-82a50d9a81d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2500318550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2500318550
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.726400799
Short name T1604
Test name
Test status
Simulation time 172179874 ps
CPU time 0.9 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207408 kb
Host smart-a27ccf14-5927-4965-9f23-08fc44c19b17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=726400799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.726400799
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3218112675
Short name T2146
Test name
Test status
Simulation time 182332596 ps
CPU time 0.85 seconds
Started Aug 10 07:14:51 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207512 kb
Host smart-c0cd9a03-cce9-45e9-b08e-74b102376b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181
12675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3218112675
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.866465949
Short name T145
Test name
Test status
Simulation time 208254779 ps
CPU time 0.92 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207580 kb
Host smart-b52cfb49-c02c-4e32-923b-1a3f04fc5012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86646
5949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.866465949
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2081932716
Short name T3101
Test name
Test status
Simulation time 216689710 ps
CPU time 0.93 seconds
Started Aug 10 07:14:49 PM PDT 24
Finished Aug 10 07:14:50 PM PDT 24
Peak memory 207568 kb
Host smart-310a7a51-3957-41f5-8b3a-69a25e911dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20819
32716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2081932716
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.941088022
Short name T2317
Test name
Test status
Simulation time 154325719 ps
CPU time 0.86 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:14:51 PM PDT 24
Peak memory 207528 kb
Host smart-24c4b621-9edb-4771-aba2-1d42280e0d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94108
8022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.941088022
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3302821455
Short name T3295
Test name
Test status
Simulation time 209543074 ps
CPU time 0.9 seconds
Started Aug 10 07:14:51 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207500 kb
Host smart-261a0a5d-d032-4887-9589-26a53277bf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33028
21455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3302821455
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.4112888586
Short name T1061
Test name
Test status
Simulation time 161604638 ps
CPU time 0.84 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207420 kb
Host smart-ffb42fc4-d743-4408-8efe-bf5d8d66a434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
88586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.4112888586
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.4272959462
Short name T2753
Test name
Test status
Simulation time 206953440 ps
CPU time 1.02 seconds
Started Aug 10 07:14:54 PM PDT 24
Finished Aug 10 07:14:55 PM PDT 24
Peak memory 207604 kb
Host smart-1e964187-1ffd-43f4-9eab-8fafe8a63560
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4272959462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.4272959462
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2703698506
Short name T1006
Test name
Test status
Simulation time 148232630 ps
CPU time 0.8 seconds
Started Aug 10 07:14:56 PM PDT 24
Finished Aug 10 07:14:57 PM PDT 24
Peak memory 207384 kb
Host smart-ff72517b-b3d8-4b08-aef9-a7911fc27e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27036
98506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2703698506
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3091135407
Short name T3260
Test name
Test status
Simulation time 37802756 ps
CPU time 0.68 seconds
Started Aug 10 07:14:53 PM PDT 24
Finished Aug 10 07:14:54 PM PDT 24
Peak memory 207504 kb
Host smart-e7370a3a-65c1-44fe-8ce1-e8dead3fc382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
35407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3091135407
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2053587269
Short name T3239
Test name
Test status
Simulation time 21400506792 ps
CPU time 53.16 seconds
Started Aug 10 07:14:53 PM PDT 24
Finished Aug 10 07:15:47 PM PDT 24
Peak memory 216020 kb
Host smart-a018e2a4-e0ce-45a4-b1c9-150fe1726edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20535
87269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2053587269
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3736697617
Short name T375
Test name
Test status
Simulation time 172399977 ps
CPU time 0.89 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207548 kb
Host smart-023502d3-9856-41f9-9d36-1d6e1934934e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366
97617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3736697617
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4036676028
Short name T3314
Test name
Test status
Simulation time 223755063 ps
CPU time 0.97 seconds
Started Aug 10 07:14:56 PM PDT 24
Finished Aug 10 07:14:57 PM PDT 24
Peak memory 207536 kb
Host smart-08415b5f-2f25-4b37-b3f7-e507324428dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366
76028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4036676028
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.429638032
Short name T2255
Test name
Test status
Simulation time 200066304 ps
CPU time 0.95 seconds
Started Aug 10 07:14:52 PM PDT 24
Finished Aug 10 07:14:53 PM PDT 24
Peak memory 207580 kb
Host smart-91168408-1da9-4e13-bcca-537b6037e212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42963
8032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.429638032
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2001911900
Short name T996
Test name
Test status
Simulation time 171475043 ps
CPU time 0.9 seconds
Started Aug 10 07:14:54 PM PDT 24
Finished Aug 10 07:14:55 PM PDT 24
Peak memory 207608 kb
Host smart-248ab9df-113f-4d34-a454-2c9fce2d7167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
11900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2001911900
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2028293107
Short name T2035
Test name
Test status
Simulation time 140268369 ps
CPU time 0.85 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207516 kb
Host smart-46a8d74b-3dda-4202-968d-d3df4f7881ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282
93107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2028293107
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_rx_full.2708653739
Short name T3013
Test name
Test status
Simulation time 253732720 ps
CPU time 1.12 seconds
Started Aug 10 07:14:51 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207544 kb
Host smart-ae817356-56d7-427d-91ed-e23c1d2fdb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27086
53739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.2708653739
Directory /workspace/40.usbdev_rx_full/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.4290967733
Short name T668
Test name
Test status
Simulation time 196365595 ps
CPU time 0.85 seconds
Started Aug 10 07:14:52 PM PDT 24
Finished Aug 10 07:14:53 PM PDT 24
Peak memory 207452 kb
Host smart-07f5b0f3-524b-41aa-9132-b0b161bbb5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42909
67733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.4290967733
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3846985930
Short name T2849
Test name
Test status
Simulation time 151620976 ps
CPU time 0.87 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:14:51 PM PDT 24
Peak memory 207568 kb
Host smart-8a8d85d2-b986-4b2b-bd96-2146d4f9928c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
85930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3846985930
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2130128481
Short name T1009
Test name
Test status
Simulation time 208323608 ps
CPU time 0.96 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207428 kb
Host smart-9cb44c01-c165-4259-a16a-7e9afe0cae0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
28481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2130128481
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2711742205
Short name T2943
Test name
Test status
Simulation time 2067049899 ps
CPU time 16.43 seconds
Started Aug 10 07:14:52 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 217436 kb
Host smart-023bdc2f-8393-41a5-817c-3f672c486740
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2711742205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2711742205
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2260102495
Short name T606
Test name
Test status
Simulation time 142666404 ps
CPU time 0.84 seconds
Started Aug 10 07:14:51 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207560 kb
Host smart-5ec51457-5d9b-4a6c-8ea9-3a242f9a8828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22601
02495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2260102495
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.257395379
Short name T946
Test name
Test status
Simulation time 188944804 ps
CPU time 0.9 seconds
Started Aug 10 07:14:52 PM PDT 24
Finished Aug 10 07:14:53 PM PDT 24
Peak memory 207496 kb
Host smart-7f6f989a-89f7-47b0-b3dc-b7ab823212f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25739
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.257395379
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.846463507
Short name T675
Test name
Test status
Simulation time 1043899998 ps
CPU time 2.63 seconds
Started Aug 10 07:14:53 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207684 kb
Host smart-57472ea6-31ae-4b97-b81c-23d35cbddd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84646
3507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.846463507
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.821911242
Short name T1039
Test name
Test status
Simulation time 4062068521 ps
CPU time 31.56 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 216068 kb
Host smart-16b49c19-af6a-4209-a58d-fb166dad3c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82191
1242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.821911242
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.174682685
Short name T3371
Test name
Test status
Simulation time 2930433905 ps
CPU time 24.82 seconds
Started Aug 10 07:14:45 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 207732 kb
Host smart-1b35acfe-2602-48ad-a272-08214d028eac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174682685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_host
_handshake.174682685
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_tx_rx_disruption.3727509492
Short name T1806
Test name
Test status
Simulation time 445554047 ps
CPU time 1.43 seconds
Started Aug 10 07:14:52 PM PDT 24
Finished Aug 10 07:14:54 PM PDT 24
Peak memory 207600 kb
Host smart-604d0afb-8f95-42f7-b868-9fbec470d87c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727509492 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.usbdev_tx_rx_disruption.3727509492
Directory /workspace/40.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/400.usbdev_tx_rx_disruption.2217801877
Short name T631
Test name
Test status
Simulation time 587811336 ps
CPU time 1.79 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207508 kb
Host smart-72fdc715-2229-46db-ab0a-effbaabe7c79
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217801877 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 400.usbdev_tx_rx_disruption.2217801877
Directory /workspace/400.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/401.usbdev_tx_rx_disruption.2114136646
Short name T2806
Test name
Test status
Simulation time 604428071 ps
CPU time 1.72 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207516 kb
Host smart-3a238284-7755-412d-99c4-a5e0b7af604a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114136646 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 401.usbdev_tx_rx_disruption.2114136646
Directory /workspace/401.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/402.usbdev_tx_rx_disruption.108784114
Short name T534
Test name
Test status
Simulation time 509988955 ps
CPU time 1.69 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207596 kb
Host smart-c150a590-88fd-4a4f-85b8-80827b62ee9b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108784114 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 402.usbdev_tx_rx_disruption.108784114
Directory /workspace/402.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/403.usbdev_tx_rx_disruption.472334637
Short name T3073
Test name
Test status
Simulation time 569864471 ps
CPU time 1.73 seconds
Started Aug 10 07:18:30 PM PDT 24
Finished Aug 10 07:18:32 PM PDT 24
Peak memory 207520 kb
Host smart-637ffde9-bacf-4e63-9a60-62f66ec90e97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472334637 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 403.usbdev_tx_rx_disruption.472334637
Directory /workspace/403.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/404.usbdev_tx_rx_disruption.3545772656
Short name T2397
Test name
Test status
Simulation time 582909075 ps
CPU time 1.58 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207548 kb
Host smart-bb91b168-2b1a-4ddd-9830-e6513ed89d29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545772656 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 404.usbdev_tx_rx_disruption.3545772656
Directory /workspace/404.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/405.usbdev_tx_rx_disruption.376559210
Short name T3479
Test name
Test status
Simulation time 481626404 ps
CPU time 1.67 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207508 kb
Host smart-7ffe4402-f74d-42ee-8373-b44a1e3730de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376559210 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 405.usbdev_tx_rx_disruption.376559210
Directory /workspace/405.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/406.usbdev_tx_rx_disruption.975227995
Short name T2901
Test name
Test status
Simulation time 479805553 ps
CPU time 1.49 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207552 kb
Host smart-46e7f428-93de-44a4-b4e0-54d72cb09851
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975227995 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 406.usbdev_tx_rx_disruption.975227995
Directory /workspace/406.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/407.usbdev_tx_rx_disruption.1973951537
Short name T838
Test name
Test status
Simulation time 589009892 ps
CPU time 1.73 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207404 kb
Host smart-b28a9d9d-f82e-4336-b8a6-d3bdb3ca7110
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973951537 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 407.usbdev_tx_rx_disruption.1973951537
Directory /workspace/407.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/408.usbdev_tx_rx_disruption.1741231703
Short name T2598
Test name
Test status
Simulation time 576635009 ps
CPU time 1.65 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207496 kb
Host smart-257e617b-e5b2-4f8c-bbeb-b48fda20a394
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741231703 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 408.usbdev_tx_rx_disruption.1741231703
Directory /workspace/408.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/409.usbdev_tx_rx_disruption.2202517493
Short name T3606
Test name
Test status
Simulation time 568633681 ps
CPU time 1.65 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207528 kb
Host smart-6fec1628-dcd8-4ff0-ba95-f7e0282523f6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202517493 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 409.usbdev_tx_rx_disruption.2202517493
Directory /workspace/409.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1716021338
Short name T1493
Test name
Test status
Simulation time 99735916 ps
CPU time 0.72 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:14 PM PDT 24
Peak memory 207572 kb
Host smart-0f91989f-6ab8-4614-84ca-3a1e3ffacec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1716021338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1716021338
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.384616412
Short name T2803
Test name
Test status
Simulation time 11576451223 ps
CPU time 15.32 seconds
Started Aug 10 07:14:58 PM PDT 24
Finished Aug 10 07:15:13 PM PDT 24
Peak memory 207720 kb
Host smart-ad861b04-e065-4fc8-b062-d4fd66affff3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384616412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_ao
n_wake_disconnect.384616412
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.2611016519
Short name T3592
Test name
Test status
Simulation time 16057605849 ps
CPU time 22.15 seconds
Started Aug 10 07:14:54 PM PDT 24
Finished Aug 10 07:15:16 PM PDT 24
Peak memory 216040 kb
Host smart-f3ad3f27-6ec5-42b5-b662-f296cad18f25
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611016519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.2611016519
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3373063142
Short name T3433
Test name
Test status
Simulation time 30755361055 ps
CPU time 40.3 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:15:31 PM PDT 24
Peak memory 207776 kb
Host smart-8f1a7635-45ad-4619-b7f1-6e9a14185ab6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373063142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3373063142
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1478787277
Short name T3537
Test name
Test status
Simulation time 160057138 ps
CPU time 0.88 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:14:56 PM PDT 24
Peak memory 207556 kb
Host smart-741667b3-a748-4650-8aa3-62324ef57d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787
87277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1478787277
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1935834923
Short name T2433
Test name
Test status
Simulation time 208277692 ps
CPU time 0.92 seconds
Started Aug 10 07:14:56 PM PDT 24
Finished Aug 10 07:14:57 PM PDT 24
Peak memory 207384 kb
Host smart-2241e0d9-090c-4539-ac7e-8fec0aaa1166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19358
34923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1935834923
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2522973591
Short name T1476
Test name
Test status
Simulation time 375191047 ps
CPU time 1.41 seconds
Started Aug 10 07:14:49 PM PDT 24
Finished Aug 10 07:14:51 PM PDT 24
Peak memory 207504 kb
Host smart-78c059b6-4d49-4935-b1e2-cc9a31cbac34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25229
73591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2522973591
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1253866466
Short name T1980
Test name
Test status
Simulation time 730970497 ps
CPU time 2.12 seconds
Started Aug 10 07:14:50 PM PDT 24
Finished Aug 10 07:14:52 PM PDT 24
Peak memory 207760 kb
Host smart-7c795eb5-5ba3-441d-971a-ee3fd3ab639a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1253866466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1253866466
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1311309499
Short name T2232
Test name
Test status
Simulation time 14926422428 ps
CPU time 24.98 seconds
Started Aug 10 07:14:55 PM PDT 24
Finished Aug 10 07:15:20 PM PDT 24
Peak memory 207820 kb
Host smart-becbe240-b28b-4310-86ba-fd935bbe3a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13113
09499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1311309499
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.4019012195
Short name T2419
Test name
Test status
Simulation time 2004094133 ps
CPU time 17.13 seconds
Started Aug 10 07:14:58 PM PDT 24
Finished Aug 10 07:15:16 PM PDT 24
Peak memory 207664 kb
Host smart-d0af5b2e-2377-47bd-a854-8c91334969af
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019012195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.4019012195
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.895555377
Short name T2519
Test name
Test status
Simulation time 772038093 ps
CPU time 1.9 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:05 PM PDT 24
Peak memory 207488 kb
Host smart-a2a268b1-5c1a-4bc2-87ec-18356c5c0bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89555
5377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.895555377
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.413355435
Short name T743
Test name
Test status
Simulation time 151466812 ps
CPU time 0.84 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207548 kb
Host smart-9974a8c5-23e2-4ff7-b669-cc46c74dce0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41335
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.413355435
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1986390627
Short name T1417
Test name
Test status
Simulation time 96246879 ps
CPU time 0.8 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207524 kb
Host smart-cceeb381-1035-4864-a235-85e854b904f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
90627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1986390627
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.388775706
Short name T1865
Test name
Test status
Simulation time 873823405 ps
CPU time 2.64 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207772 kb
Host smart-8e010bc3-bdd8-437a-b834-3af733cde8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
5706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.388775706
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1924974825
Short name T904
Test name
Test status
Simulation time 261767728 ps
CPU time 1.7 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:05 PM PDT 24
Peak memory 207880 kb
Host smart-63c07221-a578-4701-aab3-5b3f1554ffb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
74825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1924974825
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.281790620
Short name T1261
Test name
Test status
Simulation time 192167364 ps
CPU time 1.09 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:04 PM PDT 24
Peak memory 215916 kb
Host smart-e326edef-3c78-4980-8601-ae7f72a76bed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=281790620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.281790620
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2775220287
Short name T1525
Test name
Test status
Simulation time 164486528 ps
CPU time 0.87 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:04 PM PDT 24
Peak memory 207528 kb
Host smart-30501981-34e9-4f74-bbc1-a5b88dc378a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27752
20287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2775220287
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1810564348
Short name T3465
Test name
Test status
Simulation time 165199012 ps
CPU time 0.93 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207580 kb
Host smart-b45cfd28-9fe2-4b04-9ffa-ec5d119e0d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
64348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1810564348
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.707229046
Short name T2672
Test name
Test status
Simulation time 4339450511 ps
CPU time 42.89 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:43 PM PDT 24
Peak memory 216120 kb
Host smart-885fcad4-a07b-47f9-9885-2e67936e47e6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=707229046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.707229046
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.4148476602
Short name T2872
Test name
Test status
Simulation time 12765132274 ps
CPU time 87.86 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207804 kb
Host smart-7c33f0aa-bd35-4067-847d-33170308932c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4148476602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.4148476602
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.486949206
Short name T3204
Test name
Test status
Simulation time 285428510 ps
CPU time 1.03 seconds
Started Aug 10 07:14:58 PM PDT 24
Finished Aug 10 07:14:59 PM PDT 24
Peak memory 207576 kb
Host smart-a507c390-18db-4d57-b582-a8e6fcd3ec4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48694
9206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.486949206
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.2160818735
Short name T1997
Test name
Test status
Simulation time 23511708713 ps
CPU time 27.64 seconds
Started Aug 10 07:15:04 PM PDT 24
Finished Aug 10 07:15:31 PM PDT 24
Peak memory 216064 kb
Host smart-29fd6c76-82b4-418f-8826-31e9a0e14ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
18735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.2160818735
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1333043685
Short name T1328
Test name
Test status
Simulation time 10416377336 ps
CPU time 14.01 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:17 PM PDT 24
Peak memory 207836 kb
Host smart-54ffc961-938d-4700-b88e-4626b8b82ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13330
43685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1333043685
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1886065538
Short name T2724
Test name
Test status
Simulation time 4515179796 ps
CPU time 35.76 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 216100 kb
Host smart-294391a9-e4b3-40d2-9dc9-f9614b70676b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1886065538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1886065538
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.269784261
Short name T2365
Test name
Test status
Simulation time 1658794869 ps
CPU time 45.98 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:49 PM PDT 24
Peak memory 217436 kb
Host smart-96259707-fead-4d4b-940c-1daa09ab2e57
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=269784261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.269784261
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1449088094
Short name T2402
Test name
Test status
Simulation time 257753871 ps
CPU time 1.02 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207568 kb
Host smart-27943559-d5e3-4674-acaf-f394616f6376
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1449088094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1449088094
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.904598873
Short name T1040
Test name
Test status
Simulation time 195554321 ps
CPU time 0.93 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207584 kb
Host smart-100493ae-5618-4ed0-8a85-e6ec5a451ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90459
8873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.904598873
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.188195469
Short name T2081
Test name
Test status
Simulation time 3247173300 ps
CPU time 95.58 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 217452 kb
Host smart-1ff1ec27-78d4-4509-ac03-25cf0d6a3316
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=188195469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.188195469
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3000247675
Short name T542
Test name
Test status
Simulation time 179193415 ps
CPU time 0.92 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207568 kb
Host smart-df12959a-c7ec-4807-af9f-949e1e9146ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3000247675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3000247675
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.38139849
Short name T2909
Test name
Test status
Simulation time 180269669 ps
CPU time 0.87 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207440 kb
Host smart-c7bc5872-3ccb-4dca-b342-93f8b64f900b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38139
849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.38139849
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1944954790
Short name T158
Test name
Test status
Simulation time 206843935 ps
CPU time 0.99 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207580 kb
Host smart-192dcacc-40e5-4e21-b685-315b9d74413e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19449
54790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1944954790
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1819989570
Short name T3196
Test name
Test status
Simulation time 218174909 ps
CPU time 1.03 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207540 kb
Host smart-36b96a3f-9009-4599-91d8-d60ce4e1f7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18199
89570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1819989570
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1341985652
Short name T260
Test name
Test status
Simulation time 161217566 ps
CPU time 0.9 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207548 kb
Host smart-bae09a27-1793-4806-a47b-3bdefb20c0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13419
85652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1341985652
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2756414257
Short name T3440
Test name
Test status
Simulation time 193889823 ps
CPU time 0.89 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207508 kb
Host smart-0de960fe-f06e-4a1d-8932-f11740b753f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27564
14257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2756414257
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.4055684804
Short name T3364
Test name
Test status
Simulation time 167374893 ps
CPU time 0.89 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207508 kb
Host smart-fb8d91b2-4294-492b-941d-807c11929efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40556
84804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.4055684804
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1154023651
Short name T31
Test name
Test status
Simulation time 259887219 ps
CPU time 1.16 seconds
Started Aug 10 07:14:59 PM PDT 24
Finished Aug 10 07:15:00 PM PDT 24
Peak memory 207528 kb
Host smart-0fd92c00-3f76-49eb-b053-a8db302ac8c4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1154023651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1154023651
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.580298638
Short name T2409
Test name
Test status
Simulation time 136555187 ps
CPU time 0.88 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207608 kb
Host smart-a4b9549f-bf14-45c4-8443-e746a7be615a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58029
8638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.580298638
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2624271981
Short name T3456
Test name
Test status
Simulation time 36121305 ps
CPU time 0.72 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207524 kb
Host smart-a5dda2dd-d8f1-473a-869c-ff823cb56cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
71981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2624271981
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1747462706
Short name T1507
Test name
Test status
Simulation time 14493664398 ps
CPU time 36.34 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 216228 kb
Host smart-42f1c282-1b9d-4fa9-97dc-f377b5fbe82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17474
62706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1747462706
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1068809926
Short name T1228
Test name
Test status
Simulation time 165837470 ps
CPU time 0.88 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207496 kb
Host smart-4e0c5be5-c3fd-403d-95b3-85bd2e6ed745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
09926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1068809926
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.883817679
Short name T1400
Test name
Test status
Simulation time 219308621 ps
CPU time 0.99 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207452 kb
Host smart-b3ab81c0-1158-4181-8a50-6a2bfbaf3af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88381
7679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.883817679
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.118052769
Short name T1924
Test name
Test status
Simulation time 177987773 ps
CPU time 0.89 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207488 kb
Host smart-46ea045f-74ce-457a-91da-2943db0e4fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
2769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.118052769
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1185923962
Short name T2272
Test name
Test status
Simulation time 165147336 ps
CPU time 0.87 seconds
Started Aug 10 07:15:03 PM PDT 24
Finished Aug 10 07:15:04 PM PDT 24
Peak memory 207460 kb
Host smart-1aae11b6-4f9a-4fec-8e97-d1fab08d1281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
23962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1185923962
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2302830244
Short name T1412
Test name
Test status
Simulation time 230236783 ps
CPU time 0.95 seconds
Started Aug 10 07:15:02 PM PDT 24
Finished Aug 10 07:15:03 PM PDT 24
Peak memory 207516 kb
Host smart-cb31b061-bd02-4baa-94f8-6c8036d3cd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
30244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2302830244
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_rx_full.647860868
Short name T2473
Test name
Test status
Simulation time 250656552 ps
CPU time 1.15 seconds
Started Aug 10 07:15:01 PM PDT 24
Finished Aug 10 07:15:02 PM PDT 24
Peak memory 207540 kb
Host smart-4612563c-578c-4d21-92c2-8465a1c1f2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64786
0868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.647860868
Directory /workspace/41.usbdev_rx_full/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2673616838
Short name T595
Test name
Test status
Simulation time 202154811 ps
CPU time 0.91 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207516 kb
Host smart-fd038269-864c-468b-85fa-a94421776eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26736
16838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2673616838
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2130926321
Short name T1283
Test name
Test status
Simulation time 154069160 ps
CPU time 0.82 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:01 PM PDT 24
Peak memory 207608 kb
Host smart-6265b467-a878-417b-aa5a-87f7286b2784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
26321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2130926321
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1358283865
Short name T1662
Test name
Test status
Simulation time 239279364 ps
CPU time 1.01 seconds
Started Aug 10 07:15:04 PM PDT 24
Finished Aug 10 07:15:05 PM PDT 24
Peak memory 207580 kb
Host smart-9482468b-a8d5-427a-8785-54f14f99b92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13582
83865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1358283865
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3674668156
Short name T1431
Test name
Test status
Simulation time 3767683453 ps
CPU time 28.64 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 218012 kb
Host smart-c0d51955-2b3c-47af-bbe3-0b16a91d617e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3674668156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3674668156
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2127557903
Short name T1131
Test name
Test status
Simulation time 184923772 ps
CPU time 0.86 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 207556 kb
Host smart-01137ab7-e10c-4389-91cb-c87f9ea85ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21275
57903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2127557903
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.93882278
Short name T507
Test name
Test status
Simulation time 141369411 ps
CPU time 0.82 seconds
Started Aug 10 07:15:08 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 207508 kb
Host smart-8a701ed3-f365-490c-8dec-dbba4e0516f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93882
278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.93882278
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.3100450584
Short name T3439
Test name
Test status
Simulation time 1241663560 ps
CPU time 2.76 seconds
Started Aug 10 07:15:09 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 207716 kb
Host smart-377e9284-c8b2-486e-80e5-be7561522b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31004
50584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.3100450584
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2538041334
Short name T725
Test name
Test status
Simulation time 2064763379 ps
CPU time 15.72 seconds
Started Aug 10 07:15:09 PM PDT 24
Finished Aug 10 07:15:24 PM PDT 24
Peak memory 207724 kb
Host smart-501dd7ae-1868-4068-aa92-42bba3c2ca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
41334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2538041334
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.2212778194
Short name T911
Test name
Test status
Simulation time 447040996 ps
CPU time 8.07 seconds
Started Aug 10 07:15:00 PM PDT 24
Finished Aug 10 07:15:08 PM PDT 24
Peak memory 207728 kb
Host smart-2c98d1d4-06b6-46a5-87de-92096e96a476
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212778194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.2212778194
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_tx_rx_disruption.2404779869
Short name T707
Test name
Test status
Simulation time 628888398 ps
CPU time 1.84 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:13 PM PDT 24
Peak memory 207440 kb
Host smart-3189d783-1e8f-4865-834b-869a2fb3b647
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404779869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.usbdev_tx_rx_disruption.2404779869
Directory /workspace/41.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/410.usbdev_tx_rx_disruption.3902741798
Short name T247
Test name
Test status
Simulation time 533940143 ps
CPU time 1.96 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207604 kb
Host smart-07e97a32-ae66-49d7-b7c5-14b713f92be7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902741798 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 410.usbdev_tx_rx_disruption.3902741798
Directory /workspace/410.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/411.usbdev_tx_rx_disruption.701856034
Short name T1049
Test name
Test status
Simulation time 618903809 ps
CPU time 1.73 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207564 kb
Host smart-06f41d76-20a8-422c-be7c-db4c4b390c32
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701856034 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 411.usbdev_tx_rx_disruption.701856034
Directory /workspace/411.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/412.usbdev_tx_rx_disruption.1558771447
Short name T817
Test name
Test status
Simulation time 556385655 ps
CPU time 1.62 seconds
Started Aug 10 07:18:30 PM PDT 24
Finished Aug 10 07:18:32 PM PDT 24
Peak memory 207572 kb
Host smart-a59e3ea3-4f3c-45e5-b5f9-db30daf32bec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558771447 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 412.usbdev_tx_rx_disruption.1558771447
Directory /workspace/412.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/413.usbdev_tx_rx_disruption.3444824463
Short name T3202
Test name
Test status
Simulation time 553747798 ps
CPU time 1.51 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207604 kb
Host smart-2fb39a44-6b5d-4ffc-aea1-288c75a33461
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444824463 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 413.usbdev_tx_rx_disruption.3444824463
Directory /workspace/413.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/414.usbdev_tx_rx_disruption.3069668871
Short name T2286
Test name
Test status
Simulation time 611655504 ps
CPU time 1.62 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207548 kb
Host smart-f3262c84-caa0-46b7-a1f2-ba50fa39b692
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069668871 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 414.usbdev_tx_rx_disruption.3069668871
Directory /workspace/414.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/415.usbdev_tx_rx_disruption.3489677636
Short name T1101
Test name
Test status
Simulation time 629421954 ps
CPU time 1.64 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207480 kb
Host smart-b2cdb8b1-0f89-401d-889f-0e8b777ca0c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489677636 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 415.usbdev_tx_rx_disruption.3489677636
Directory /workspace/415.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/416.usbdev_tx_rx_disruption.1516601025
Short name T3279
Test name
Test status
Simulation time 564380441 ps
CPU time 1.7 seconds
Started Aug 10 07:18:30 PM PDT 24
Finished Aug 10 07:18:31 PM PDT 24
Peak memory 207520 kb
Host smart-600afdfa-5621-4a7f-9bf1-0aad37d63838
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516601025 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 416.usbdev_tx_rx_disruption.1516601025
Directory /workspace/416.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/417.usbdev_tx_rx_disruption.2990295640
Short name T1344
Test name
Test status
Simulation time 460746375 ps
CPU time 1.43 seconds
Started Aug 10 07:18:28 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207516 kb
Host smart-23a15678-ce50-43c6-b6cb-0251a8844293
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990295640 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 417.usbdev_tx_rx_disruption.2990295640
Directory /workspace/417.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/418.usbdev_tx_rx_disruption.3297074930
Short name T2298
Test name
Test status
Simulation time 579589687 ps
CPU time 1.69 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207480 kb
Host smart-f4a6133e-da0f-4bcb-beb1-8a550bdd3da1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297074930 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 418.usbdev_tx_rx_disruption.3297074930
Directory /workspace/418.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/419.usbdev_tx_rx_disruption.3116979483
Short name T2738
Test name
Test status
Simulation time 522084656 ps
CPU time 1.61 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207552 kb
Host smart-f7bfa7f4-e6fb-4385-933a-9baac4faaf83
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116979483 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 419.usbdev_tx_rx_disruption.3116979483
Directory /workspace/419.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3247112947
Short name T2925
Test name
Test status
Simulation time 59725358 ps
CPU time 0.72 seconds
Started Aug 10 07:15:25 PM PDT 24
Finished Aug 10 07:15:26 PM PDT 24
Peak memory 207508 kb
Host smart-68fd89a8-874f-4882-9c6a-b4c10dbe9536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3247112947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3247112947
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4199127234
Short name T3056
Test name
Test status
Simulation time 9609435898 ps
CPU time 13.01 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207872 kb
Host smart-faa29717-7c61-41cb-98bf-265b4a5ba877
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199127234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.4199127234
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.742223193
Short name T3496
Test name
Test status
Simulation time 18362621771 ps
CPU time 22.72 seconds
Started Aug 10 07:15:09 PM PDT 24
Finished Aug 10 07:15:31 PM PDT 24
Peak memory 207844 kb
Host smart-e87cd82d-801a-4a4a-aeb0-94a7e6a00abb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=742223193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.742223193
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1064916286
Short name T801
Test name
Test status
Simulation time 24878619120 ps
CPU time 30.92 seconds
Started Aug 10 07:15:12 PM PDT 24
Finished Aug 10 07:15:43 PM PDT 24
Peak memory 215980 kb
Host smart-16a69854-f6b0-46a8-a165-6d0e7fe7ee07
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064916286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1064916286
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.553280517
Short name T706
Test name
Test status
Simulation time 158529402 ps
CPU time 0.84 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:14 PM PDT 24
Peak memory 207604 kb
Host smart-8eeb240b-6530-468d-9dc1-285ee6a6bfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55328
0517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.553280517
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3318841934
Short name T1502
Test name
Test status
Simulation time 172320866 ps
CPU time 0.87 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:15 PM PDT 24
Peak memory 207572 kb
Host smart-79849d28-8314-4343-9d03-4b2b5f11da46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33188
41934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3318841934
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.678995738
Short name T3258
Test name
Test status
Simulation time 247442229 ps
CPU time 1.04 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 207512 kb
Host smart-524080ac-33aa-471a-9818-0ed7d982ba80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67899
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.678995738
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1796188762
Short name T3064
Test name
Test status
Simulation time 286532173 ps
CPU time 1.18 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:15 PM PDT 24
Peak memory 207596 kb
Host smart-f73e8dc2-433c-4873-be24-7185d55a3277
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1796188762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1796188762
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.1403149230
Short name T1740
Test name
Test status
Simulation time 4958724026 ps
CPU time 35.75 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207856 kb
Host smart-dfab5f65-1838-41fe-8fc9-40aacb0b3487
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403149230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.1403149230
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.404992416
Short name T2474
Test name
Test status
Simulation time 414235372 ps
CPU time 1.27 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 207500 kb
Host smart-aab396e9-4801-4b56-bb55-ce1211c9b302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40499
2416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.404992416
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3058984954
Short name T2082
Test name
Test status
Simulation time 142202392 ps
CPU time 0.84 seconds
Started Aug 10 07:15:09 PM PDT 24
Finished Aug 10 07:15:10 PM PDT 24
Peak memory 207576 kb
Host smart-47b39e2c-80cf-4e77-8b80-8d4c0caa892e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30589
84954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3058984954
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.499456444
Short name T3467
Test name
Test status
Simulation time 39226630 ps
CPU time 0.7 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:14 PM PDT 24
Peak memory 207548 kb
Host smart-6025d822-ed2b-40e8-9f58-d16eefc6ffc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49945
6444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.499456444
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_types.4083415522
Short name T454
Test name
Test status
Simulation time 306398133 ps
CPU time 1.18 seconds
Started Aug 10 07:15:07 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 207520 kb
Host smart-186f11ba-9a9c-4a40-9989-459a2ebca1c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4083415522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.4083415522
Directory /workspace/42.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.4248590327
Short name T94
Test name
Test status
Simulation time 170944556 ps
CPU time 1.79 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:13 PM PDT 24
Peak memory 207720 kb
Host smart-6416665a-1749-4374-91ee-d2acd511d360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42485
90327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4248590327
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3580057818
Short name T1262
Test name
Test status
Simulation time 234093373 ps
CPU time 1.24 seconds
Started Aug 10 07:15:08 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 215888 kb
Host smart-e6a4510d-3dac-452f-a846-005fe119c836
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3580057818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3580057818
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3851342708
Short name T2309
Test name
Test status
Simulation time 231257044 ps
CPU time 0.89 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:10 PM PDT 24
Peak memory 207556 kb
Host smart-bc8b1247-05b7-4430-bb8a-80746f20cec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38513
42708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3851342708
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.141281609
Short name T1324
Test name
Test status
Simulation time 164345905 ps
CPU time 0.88 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:14 PM PDT 24
Peak memory 207580 kb
Host smart-4f8ca48f-74e7-4ae3-8913-30a406860095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14128
1609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.141281609
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2624229033
Short name T976
Test name
Test status
Simulation time 2806324584 ps
CPU time 81.14 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:16:32 PM PDT 24
Peak memory 224232 kb
Host smart-8d4864c2-6db7-435a-9a2f-cc5033b7e283
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2624229033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2624229033
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.898248275
Short name T3183
Test name
Test status
Simulation time 11099493107 ps
CPU time 130.29 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:17:21 PM PDT 24
Peak memory 207844 kb
Host smart-97b18f9b-0f85-420d-b01b-ce174e030461
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=898248275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.898248275
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.291544408
Short name T1953
Test name
Test status
Simulation time 280097308 ps
CPU time 1.08 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:13 PM PDT 24
Peak memory 207552 kb
Host smart-27150890-e746-45fe-abe2-6de414b9815c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29154
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.291544408
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1630287198
Short name T938
Test name
Test status
Simulation time 33664666495 ps
CPU time 55.52 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207860 kb
Host smart-c3e10ad7-bd32-460f-9816-cacd5180d7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16302
87198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1630287198
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1824331573
Short name T791
Test name
Test status
Simulation time 5374936913 ps
CPU time 7.69 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 216744 kb
Host smart-7c831466-a722-4f52-827d-7ce7b475ef05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18243
31573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1824331573
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.1130727994
Short name T3498
Test name
Test status
Simulation time 3581499492 ps
CPU time 26.04 seconds
Started Aug 10 07:15:09 PM PDT 24
Finished Aug 10 07:15:35 PM PDT 24
Peak memory 224104 kb
Host smart-9a90300c-65a9-416a-b408-fafbf6458bc6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1130727994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.1130727994
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.989959815
Short name T3500
Test name
Test status
Simulation time 4212259402 ps
CPU time 42.97 seconds
Started Aug 10 07:15:12 PM PDT 24
Finished Aug 10 07:15:55 PM PDT 24
Peak memory 217616 kb
Host smart-a36f41c4-98d9-4ef1-b82d-e13a23dd6d40
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=989959815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.989959815
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.184837476
Short name T3
Test name
Test status
Simulation time 246130979 ps
CPU time 1.01 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:16 PM PDT 24
Peak memory 207600 kb
Host smart-73c3c64e-3410-4f76-bf75-e93277b48673
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=184837476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.184837476
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2954661269
Short name T2241
Test name
Test status
Simulation time 200761129 ps
CPU time 0.98 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 207540 kb
Host smart-632ab802-61b2-4d99-898d-b9f2e2e98ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
61269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2954661269
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2734814725
Short name T2228
Test name
Test status
Simulation time 2812865813 ps
CPU time 80.46 seconds
Started Aug 10 07:15:13 PM PDT 24
Finished Aug 10 07:16:33 PM PDT 24
Peak memory 216156 kb
Host smart-b4c16431-a382-44c7-9d8f-28aac941a255
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2734814725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2734814725
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2287425303
Short name T703
Test name
Test status
Simulation time 159106106 ps
CPU time 0.88 seconds
Started Aug 10 07:15:08 PM PDT 24
Finished Aug 10 07:15:09 PM PDT 24
Peak memory 207548 kb
Host smart-004ff9b3-7a19-443f-ab38-74b6a27a32e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2287425303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2287425303
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4167925960
Short name T567
Test name
Test status
Simulation time 140661239 ps
CPU time 0.85 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:15 PM PDT 24
Peak memory 207564 kb
Host smart-a5b4d58e-a924-4f94-8356-7f0068f69264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
25960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4167925960
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1985418909
Short name T143
Test name
Test status
Simulation time 249241305 ps
CPU time 1 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 207544 kb
Host smart-79424f60-3e14-467c-af14-a11b2dd70697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19854
18909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1985418909
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1314445962
Short name T1524
Test name
Test status
Simulation time 179145775 ps
CPU time 0.9 seconds
Started Aug 10 07:15:11 PM PDT 24
Finished Aug 10 07:15:12 PM PDT 24
Peak memory 207552 kb
Host smart-1fbb953d-ecdf-4cdd-bf76-09999091f3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
45962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1314445962
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4109017082
Short name T3564
Test name
Test status
Simulation time 210759601 ps
CPU time 0.92 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:15 PM PDT 24
Peak memory 207604 kb
Host smart-47839067-e9ed-4d5e-a5df-da69aeafa6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41090
17082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4109017082
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4235644710
Short name T1868
Test name
Test status
Simulation time 179149684 ps
CPU time 0.89 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 207612 kb
Host smart-74254d7b-4183-4c4c-87e0-3ea55fe307e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42356
44710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4235644710
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.725405835
Short name T3328
Test name
Test status
Simulation time 147031684 ps
CPU time 0.84 seconds
Started Aug 10 07:15:10 PM PDT 24
Finished Aug 10 07:15:11 PM PDT 24
Peak memory 207588 kb
Host smart-1b028094-f341-4bad-a65c-a533b151ba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72540
5835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.725405835
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1971356392
Short name T1343
Test name
Test status
Simulation time 229634188 ps
CPU time 1.09 seconds
Started Aug 10 07:15:12 PM PDT 24
Finished Aug 10 07:15:13 PM PDT 24
Peak memory 207520 kb
Host smart-45540168-fc26-48f1-a00c-ac7d1d7aba6b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1971356392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1971356392
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2303599376
Short name T3534
Test name
Test status
Simulation time 194511538 ps
CPU time 0.88 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207476 kb
Host smart-03d72be3-5819-411e-a878-d27b2b973f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23035
99376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2303599376
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3407522481
Short name T2928
Test name
Test status
Simulation time 47282055 ps
CPU time 0.71 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207496 kb
Host smart-381a60f2-2e8b-4ac3-8d6c-99a07965abcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075
22481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3407522481
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3042772561
Short name T3471
Test name
Test status
Simulation time 7759862736 ps
CPU time 19.54 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 216272 kb
Host smart-19c1f0b9-86d2-4aa2-91a2-5f4fb94533b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30427
72561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3042772561
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1346198380
Short name T2635
Test name
Test status
Simulation time 167377560 ps
CPU time 0.86 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207528 kb
Host smart-efe6119f-715f-4e59-8456-72a41943d9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
98380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1346198380
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3039331549
Short name T2136
Test name
Test status
Simulation time 198870529 ps
CPU time 0.93 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:22 PM PDT 24
Peak memory 207424 kb
Host smart-4b88792d-5b27-47bb-9434-571cf4a5bc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30393
31549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3039331549
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2689615229
Short name T541
Test name
Test status
Simulation time 210375981 ps
CPU time 0.93 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:24 PM PDT 24
Peak memory 207192 kb
Host smart-3782ae98-f4dd-4a3a-82be-b320d44411e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
15229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2689615229
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2599555729
Short name T2716
Test name
Test status
Simulation time 233575205 ps
CPU time 0.96 seconds
Started Aug 10 07:15:18 PM PDT 24
Finished Aug 10 07:15:19 PM PDT 24
Peak memory 207580 kb
Host smart-68500aa7-6b01-4cfd-8f45-cbd8f991cd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
55729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2599555729
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.191694779
Short name T2359
Test name
Test status
Simulation time 142856698 ps
CPU time 0.84 seconds
Started Aug 10 07:15:17 PM PDT 24
Finished Aug 10 07:15:18 PM PDT 24
Peak memory 207460 kb
Host smart-adfb07b4-e613-4d05-b731-c757681abca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.191694779
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_rx_full.3925115271
Short name T348
Test name
Test status
Simulation time 251404134 ps
CPU time 1.1 seconds
Started Aug 10 07:15:24 PM PDT 24
Finished Aug 10 07:15:25 PM PDT 24
Peak memory 207460 kb
Host smart-d13646be-aba5-4b55-ab7a-bd8a4e0ab72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
15271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3925115271
Directory /workspace/42.usbdev_rx_full/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3970839094
Short name T1777
Test name
Test status
Simulation time 146619801 ps
CPU time 0.82 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:20 PM PDT 24
Peak memory 207512 kb
Host smart-2472ace1-e206-440d-9e16-8d24d93a3053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39708
39094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3970839094
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2360322944
Short name T3376
Test name
Test status
Simulation time 170610821 ps
CPU time 0.86 seconds
Started Aug 10 07:15:18 PM PDT 24
Finished Aug 10 07:15:19 PM PDT 24
Peak memory 207516 kb
Host smart-35043367-e8f4-4fd6-882b-f5067883b6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23603
22944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2360322944
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2620952711
Short name T2042
Test name
Test status
Simulation time 202742436 ps
CPU time 0.97 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:24 PM PDT 24
Peak memory 207232 kb
Host smart-4a099aa0-c4df-4ef7-af05-13138aa3e394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26209
52711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2620952711
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2411583040
Short name T2876
Test name
Test status
Simulation time 161511722 ps
CPU time 0.89 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207452 kb
Host smart-0e83bc3d-aea8-4210-9588-c87c77124758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
83040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2411583040
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2708653821
Short name T1094
Test name
Test status
Simulation time 152391211 ps
CPU time 0.85 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207568 kb
Host smart-0532c61b-4df4-455b-a390-c5e68ce1e263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27086
53821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2708653821
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.614331442
Short name T3082
Test name
Test status
Simulation time 467237974 ps
CPU time 1.42 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:22 PM PDT 24
Peak memory 207500 kb
Host smart-72569d74-817c-41f1-91ad-f1695ed05e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61433
1442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.614331442
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2351845614
Short name T1605
Test name
Test status
Simulation time 3292427569 ps
CPU time 25 seconds
Started Aug 10 07:15:17 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207788 kb
Host smart-35638c0e-f6d9-4d2d-a31c-8e513911e2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23518
45614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2351845614
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2330185557
Short name T2966
Test name
Test status
Simulation time 1541110010 ps
CPU time 13.77 seconds
Started Aug 10 07:15:14 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207768 kb
Host smart-2625a863-8344-4eba-8ea4-e02fdc865423
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330185557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.2330185557
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_tx_rx_disruption.1873447328
Short name T841
Test name
Test status
Simulation time 492892189 ps
CPU time 1.6 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207592 kb
Host smart-e9913bb3-ab6b-489f-aac7-53703b1bdc87
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873447328 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.usbdev_tx_rx_disruption.1873447328
Directory /workspace/42.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/420.usbdev_tx_rx_disruption.664911198
Short name T578
Test name
Test status
Simulation time 633540284 ps
CPU time 1.79 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207528 kb
Host smart-7398d627-6000-4cd5-888a-dffd1832617d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664911198 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 420.usbdev_tx_rx_disruption.664911198
Directory /workspace/420.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/421.usbdev_tx_rx_disruption.1903381746
Short name T1165
Test name
Test status
Simulation time 450835222 ps
CPU time 1.56 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207508 kb
Host smart-6e01c41c-7aee-44aa-8b0b-df493d503c5a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903381746 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 421.usbdev_tx_rx_disruption.1903381746
Directory /workspace/421.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/422.usbdev_tx_rx_disruption.1116507706
Short name T257
Test name
Test status
Simulation time 510264841 ps
CPU time 1.57 seconds
Started Aug 10 07:18:27 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207576 kb
Host smart-40db18df-4211-4885-8600-0a4fc43ad258
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116507706 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 422.usbdev_tx_rx_disruption.1116507706
Directory /workspace/422.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/423.usbdev_tx_rx_disruption.1207808306
Short name T1614
Test name
Test status
Simulation time 515704072 ps
CPU time 1.52 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207564 kb
Host smart-22c440b6-ad81-4051-a828-a81eac0e8694
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207808306 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 423.usbdev_tx_rx_disruption.1207808306
Directory /workspace/423.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/425.usbdev_tx_rx_disruption.3632836245
Short name T3077
Test name
Test status
Simulation time 476298301 ps
CPU time 1.58 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207468 kb
Host smart-c130d445-5d03-40da-bf02-8bc6a656f0f1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632836245 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 425.usbdev_tx_rx_disruption.3632836245
Directory /workspace/425.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/426.usbdev_tx_rx_disruption.2253824895
Short name T3120
Test name
Test status
Simulation time 610429825 ps
CPU time 1.76 seconds
Started Aug 10 07:18:26 PM PDT 24
Finished Aug 10 07:18:28 PM PDT 24
Peak memory 207572 kb
Host smart-9b699d44-d0bf-42e6-817c-e55fc53ae820
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253824895 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 426.usbdev_tx_rx_disruption.2253824895
Directory /workspace/426.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/427.usbdev_tx_rx_disruption.3297193929
Short name T1488
Test name
Test status
Simulation time 463159340 ps
CPU time 1.51 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207416 kb
Host smart-8b2e93d7-1244-4d06-a353-f193affbcfd6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297193929 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 427.usbdev_tx_rx_disruption.3297193929
Directory /workspace/427.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/428.usbdev_tx_rx_disruption.1531892992
Short name T3357
Test name
Test status
Simulation time 568738529 ps
CPU time 1.76 seconds
Started Aug 10 07:18:28 PM PDT 24
Finished Aug 10 07:18:30 PM PDT 24
Peak memory 207564 kb
Host smart-7dac025e-1c4b-4c7c-916c-c3aff0d0f9aa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531892992 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 428.usbdev_tx_rx_disruption.1531892992
Directory /workspace/428.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/429.usbdev_tx_rx_disruption.3870577160
Short name T1956
Test name
Test status
Simulation time 483819451 ps
CPU time 1.45 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207532 kb
Host smart-1d485df9-45a1-4507-8a8a-a8b76944d41e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870577160 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 429.usbdev_tx_rx_disruption.3870577160
Directory /workspace/429.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3137961777
Short name T998
Test name
Test status
Simulation time 38312355 ps
CPU time 0.66 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 207520 kb
Host smart-f3807c3b-638c-495b-bc39-5d9e793e78d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3137961777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3137961777
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1111179088
Short name T2647
Test name
Test status
Simulation time 9662357434 ps
CPU time 14.4 seconds
Started Aug 10 07:15:21 PM PDT 24
Finished Aug 10 07:15:36 PM PDT 24
Peak memory 207832 kb
Host smart-32a9e194-bd0c-4a55-a622-f2e648c3bf55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111179088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.1111179088
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.913675819
Short name T1826
Test name
Test status
Simulation time 18890039403 ps
CPU time 22.6 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207852 kb
Host smart-36fe3aab-d3a5-41b7-b23c-7723c5311d1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=913675819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.913675819
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3991687025
Short name T1965
Test name
Test status
Simulation time 25581344661 ps
CPU time 31.24 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 215972 kb
Host smart-76664186-7728-4640-bff2-14537cafe5ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991687025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.3991687025
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2768468922
Short name T3221
Test name
Test status
Simulation time 191248709 ps
CPU time 0.92 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:20 PM PDT 24
Peak memory 207440 kb
Host smart-ef4c29fc-6534-4b4c-8125-2612bce0e800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
68922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2768468922
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2300224719
Short name T88
Test name
Test status
Simulation time 172000852 ps
CPU time 0.84 seconds
Started Aug 10 07:15:17 PM PDT 24
Finished Aug 10 07:15:18 PM PDT 24
Peak memory 207508 kb
Host smart-5b263384-5852-41cd-8827-e0bcbe60df37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23002
24719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2300224719
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.2130160383
Short name T2554
Test name
Test status
Simulation time 162127746 ps
CPU time 0.85 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:15:22 PM PDT 24
Peak memory 207512 kb
Host smart-9f1d8386-ef29-408c-8ce9-1616194d5b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
60383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.2130160383
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1782220780
Short name T111
Test name
Test status
Simulation time 1076407774 ps
CPU time 2.69 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207708 kb
Host smart-34387447-a231-4ef7-add5-d3556932b85c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1782220780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1782220780
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.960534785
Short name T531
Test name
Test status
Simulation time 31362373451 ps
CPU time 51.92 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:16:14 PM PDT 24
Peak memory 207960 kb
Host smart-91c71ad8-80a4-4c7a-8c1b-a7fc45ad07e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96053
4785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.960534785
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.2577874888
Short name T1440
Test name
Test status
Simulation time 1230855637 ps
CPU time 26.13 seconds
Started Aug 10 07:15:21 PM PDT 24
Finished Aug 10 07:15:48 PM PDT 24
Peak memory 207716 kb
Host smart-f9ca4771-1cbc-4864-bc49-38b152bf4f7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577874888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2577874888
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3415997851
Short name T2046
Test name
Test status
Simulation time 425135506 ps
CPU time 1.28 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207548 kb
Host smart-224cc23e-baf3-409c-bdae-1e61c9fc8789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
97851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3415997851
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4092276884
Short name T3255
Test name
Test status
Simulation time 145604876 ps
CPU time 0.82 seconds
Started Aug 10 07:15:17 PM PDT 24
Finished Aug 10 07:15:18 PM PDT 24
Peak memory 207500 kb
Host smart-503de554-b203-46e7-9f0b-917dddca30ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
76884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4092276884
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3944643164
Short name T1489
Test name
Test status
Simulation time 44788612 ps
CPU time 0.72 seconds
Started Aug 10 07:15:21 PM PDT 24
Finished Aug 10 07:15:22 PM PDT 24
Peak memory 207516 kb
Host smart-83af066f-bdf1-43b7-8cb1-dab1aebf6cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
43164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3944643164
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.758185426
Short name T2629
Test name
Test status
Simulation time 839729746 ps
CPU time 2.42 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:26 PM PDT 24
Peak memory 207768 kb
Host smart-1e06ed8f-1d91-44d3-ad06-f59f1c5cf2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75818
5426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.758185426
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_types.3723483696
Short name T412
Test name
Test status
Simulation time 431887770 ps
CPU time 1.3 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207568 kb
Host smart-71d032f6-6b08-4c66-b518-2780b925d52c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3723483696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.3723483696
Directory /workspace/43.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3612468214
Short name T3583
Test name
Test status
Simulation time 226336629 ps
CPU time 1.74 seconds
Started Aug 10 07:15:19 PM PDT 24
Finished Aug 10 07:15:21 PM PDT 24
Peak memory 207716 kb
Host smart-6e60261c-fe1b-47d4-ab72-2af1876956f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
68214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3612468214
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2431908396
Short name T1982
Test name
Test status
Simulation time 230315072 ps
CPU time 1.22 seconds
Started Aug 10 07:15:18 PM PDT 24
Finished Aug 10 07:15:19 PM PDT 24
Peak memory 215916 kb
Host smart-417343fa-4b58-4972-bcc1-d8db69e26e08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2431908396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2431908396
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3070887815
Short name T1508
Test name
Test status
Simulation time 162065382 ps
CPU time 0.81 seconds
Started Aug 10 07:15:18 PM PDT 24
Finished Aug 10 07:15:19 PM PDT 24
Peak memory 207488 kb
Host smart-3f9d3704-994d-47c1-9c35-3b5976dcee0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
87815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3070887815
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1680926191
Short name T2202
Test name
Test status
Simulation time 175533426 ps
CPU time 0.92 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:24 PM PDT 24
Peak memory 207508 kb
Host smart-2b3d9f84-511d-40bc-af2d-a5bba29af031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16809
26191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1680926191
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3900468070
Short name T2203
Test name
Test status
Simulation time 2830240900 ps
CPU time 76.19 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:16:38 PM PDT 24
Peak memory 218584 kb
Host smart-5f067d2d-51ca-4f5b-badb-ff75f2da34ed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3900468070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3900468070
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.413024265
Short name T879
Test name
Test status
Simulation time 8776724722 ps
CPU time 58.08 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207788 kb
Host smart-938f9953-1fef-48b9-96bd-4f32bd503cea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=413024265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.413024265
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.662006880
Short name T961
Test name
Test status
Simulation time 245160405 ps
CPU time 1.03 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207660 kb
Host smart-f5116f1f-94d0-45f7-9945-2f43f0376230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66200
6880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.662006880
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1574864783
Short name T1859
Test name
Test status
Simulation time 29850593112 ps
CPU time 44.96 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:16:05 PM PDT 24
Peak memory 207796 kb
Host smart-fd7b9744-e197-4a83-9aad-613c15a8f801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
64783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1574864783
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.691101399
Short name T3437
Test name
Test status
Simulation time 8328102893 ps
CPU time 10.66 seconds
Started Aug 10 07:15:23 PM PDT 24
Finished Aug 10 07:15:33 PM PDT 24
Peak memory 207828 kb
Host smart-7199f6ac-9527-4ce5-80cf-820aef9d8c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69110
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.691101399
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3128816459
Short name T434
Test name
Test status
Simulation time 3564887828 ps
CPU time 37.75 seconds
Started Aug 10 07:15:28 PM PDT 24
Finished Aug 10 07:16:06 PM PDT 24
Peak memory 224208 kb
Host smart-75c9ec01-0e62-40e0-8dca-1c482777e013
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3128816459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3128816459
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2650996968
Short name T2458
Test name
Test status
Simulation time 2098725659 ps
CPU time 60.44 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:16:26 PM PDT 24
Peak memory 217244 kb
Host smart-7e20f59f-0126-4535-9b81-ba24f9c022dd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2650996968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2650996968
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3522420045
Short name T2495
Test name
Test status
Simulation time 244267317 ps
CPU time 1.02 seconds
Started Aug 10 07:15:25 PM PDT 24
Finished Aug 10 07:15:26 PM PDT 24
Peak memory 207476 kb
Host smart-fcc701d5-3c76-4f36-b530-758fccfa0c40
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3522420045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3522420045
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1569713110
Short name T2361
Test name
Test status
Simulation time 189534865 ps
CPU time 0.92 seconds
Started Aug 10 07:15:22 PM PDT 24
Finished Aug 10 07:15:23 PM PDT 24
Peak memory 207584 kb
Host smart-3429902b-7408-47e1-b85a-e7d7768f8be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
13110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1569713110
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.4100481882
Short name T3162
Test name
Test status
Simulation time 2287050789 ps
CPU time 24.12 seconds
Started Aug 10 07:15:20 PM PDT 24
Finished Aug 10 07:15:44 PM PDT 24
Peak memory 216136 kb
Host smart-f37d693b-f8de-4841-8c2c-a856125160fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4100481882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.4100481882
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2373383567
Short name T1902
Test name
Test status
Simulation time 202327585 ps
CPU time 0.94 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207568 kb
Host smart-3ede6305-d1f1-4f01-bfef-272b84804fbe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2373383567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2373383567
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3820385898
Short name T1208
Test name
Test status
Simulation time 156368750 ps
CPU time 0.83 seconds
Started Aug 10 07:15:28 PM PDT 24
Finished Aug 10 07:15:29 PM PDT 24
Peak memory 207544 kb
Host smart-12dcf802-afc4-42d3-9b25-ba8382fd0833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38203
85898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3820385898
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.988865887
Short name T132
Test name
Test status
Simulation time 195220329 ps
CPU time 0.9 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207396 kb
Host smart-315f0b86-5a5c-4b02-b3c8-d07491020727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98886
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.988865887
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3282396535
Short name T3432
Test name
Test status
Simulation time 195505252 ps
CPU time 0.93 seconds
Started Aug 10 07:15:32 PM PDT 24
Finished Aug 10 07:15:33 PM PDT 24
Peak memory 207588 kb
Host smart-a21d0f4d-b2b4-40a6-be00-bebc26e5886b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32823
96535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3282396535
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2431497565
Short name T2173
Test name
Test status
Simulation time 189984069 ps
CPU time 0.91 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207584 kb
Host smart-5cd1266a-2f73-4923-865f-e7701a47709d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24314
97565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2431497565
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3204154623
Short name T228
Test name
Test status
Simulation time 187987137 ps
CPU time 0.86 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207496 kb
Host smart-7fbb19c2-b685-4f9d-9dab-97336a5f804d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
54623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3204154623
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.316984854
Short name T2421
Test name
Test status
Simulation time 149090037 ps
CPU time 0.9 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207556 kb
Host smart-ef86b7fa-c763-4e5a-bc84-288bd3563aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31698
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.316984854
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1004358478
Short name T1910
Test name
Test status
Simulation time 246271789 ps
CPU time 1.07 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207524 kb
Host smart-d543fc75-17b8-498d-8a6a-eae57bc36d52
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1004358478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1004358478
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2301913270
Short name T834
Test name
Test status
Simulation time 171257432 ps
CPU time 0.87 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207476 kb
Host smart-4581f8c0-d7ed-4c5c-b564-e5c75bda9fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
13270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2301913270
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2657913703
Short name T1861
Test name
Test status
Simulation time 38159240 ps
CPU time 0.68 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207536 kb
Host smart-93298506-3fec-4051-ae1b-7ab01b5486d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
13703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2657913703
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.3710078414
Short name T319
Test name
Test status
Simulation time 8966172853 ps
CPU time 25.23 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:55 PM PDT 24
Peak memory 216100 kb
Host smart-97b8c66e-f45f-46f2-a4ba-66d29f939ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
78414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.3710078414
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1968297317
Short name T771
Test name
Test status
Simulation time 169774617 ps
CPU time 0.9 seconds
Started Aug 10 07:15:28 PM PDT 24
Finished Aug 10 07:15:29 PM PDT 24
Peak memory 207444 kb
Host smart-70688535-a260-43c7-8f58-47d5279fee24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
97317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1968297317
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3701926698
Short name T565
Test name
Test status
Simulation time 225145949 ps
CPU time 0.94 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207544 kb
Host smart-019ccd9b-6c3d-4112-bf98-3fe2027787f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
26698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3701926698
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2460368919
Short name T2415
Test name
Test status
Simulation time 231536597 ps
CPU time 0.99 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 207504 kb
Host smart-64195fc0-9ffc-4701-976a-a448900fc6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
68919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2460368919
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.518598203
Short name T2227
Test name
Test status
Simulation time 257031114 ps
CPU time 1.03 seconds
Started Aug 10 07:15:31 PM PDT 24
Finished Aug 10 07:15:32 PM PDT 24
Peak memory 207540 kb
Host smart-76f585aa-c637-4bb6-ba0e-6271051c6d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51859
8203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.518598203
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1028792944
Short name T870
Test name
Test status
Simulation time 214034978 ps
CPU time 0.87 seconds
Started Aug 10 07:15:32 PM PDT 24
Finished Aug 10 07:15:33 PM PDT 24
Peak memory 207576 kb
Host smart-763332fa-b6e3-4359-8666-ba4bd789f54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
92944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1028792944
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_rx_full.3834680652
Short name T677
Test name
Test status
Simulation time 399221093 ps
CPU time 1.35 seconds
Started Aug 10 07:15:27 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207528 kb
Host smart-82f0b9e3-1625-4888-a216-b9c47b2c2db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38346
80652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.3834680652
Directory /workspace/43.usbdev_rx_full/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1452414676
Short name T3229
Test name
Test status
Simulation time 167186732 ps
CPU time 0.86 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 207524 kb
Host smart-f50cfdb4-04ca-4e04-b7cc-aa32207826ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
14676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1452414676
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3469017154
Short name T1825
Test name
Test status
Simulation time 157503986 ps
CPU time 0.83 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 207560 kb
Host smart-175b3c6c-924f-46ef-aa5c-e118709a493e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
17154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3469017154
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.580223609
Short name T716
Test name
Test status
Simulation time 236256287 ps
CPU time 1.02 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207492 kb
Host smart-08f7faed-4c4b-4d53-a48c-ac038d214557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58022
3609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.580223609
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.894040568
Short name T170
Test name
Test status
Simulation time 2735328836 ps
CPU time 28.41 seconds
Started Aug 10 07:15:42 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 224280 kb
Host smart-6e6f5133-4053-40ab-ba53-50f1f66845d0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=894040568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.894040568
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3395066264
Short name T3210
Test name
Test status
Simulation time 152186748 ps
CPU time 0.86 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 207528 kb
Host smart-77c68a8f-9145-460a-9667-6e99fe94063e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33950
66264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3395066264
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2312473953
Short name T977
Test name
Test status
Simulation time 164127802 ps
CPU time 0.85 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:27 PM PDT 24
Peak memory 207592 kb
Host smart-1e1e3d0b-465f-4d33-8008-1be4c2ff4583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23124
73953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2312473953
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.534958299
Short name T3426
Test name
Test status
Simulation time 636002781 ps
CPU time 1.66 seconds
Started Aug 10 07:15:32 PM PDT 24
Finished Aug 10 07:15:34 PM PDT 24
Peak memory 207552 kb
Host smart-a14b0639-7f73-4fad-a18d-171fbd5d35d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53495
8299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.534958299
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.524451214
Short name T1394
Test name
Test status
Simulation time 3999989644 ps
CPU time 29.87 seconds
Started Aug 10 07:15:33 PM PDT 24
Finished Aug 10 07:16:03 PM PDT 24
Peak memory 217812 kb
Host smart-e700bbc5-9b17-4756-be7b-c895bb7ca505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52445
1214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.524451214
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.4026014651
Short name T927
Test name
Test status
Simulation time 1539237816 ps
CPU time 35.59 seconds
Started Aug 10 07:15:18 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207756 kb
Host smart-30e74364-6f2b-4387-8ae5-eff4090c2c37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026014651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.4026014651
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_tx_rx_disruption.4031167212
Short name T1687
Test name
Test status
Simulation time 582110350 ps
CPU time 1.66 seconds
Started Aug 10 07:15:26 PM PDT 24
Finished Aug 10 07:15:28 PM PDT 24
Peak memory 207500 kb
Host smart-61410863-c07a-449c-b8ea-284bb2aef578
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031167212 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.usbdev_tx_rx_disruption.4031167212
Directory /workspace/43.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/431.usbdev_tx_rx_disruption.2637038801
Short name T3167
Test name
Test status
Simulation time 598591980 ps
CPU time 1.8 seconds
Started Aug 10 07:18:30 PM PDT 24
Finished Aug 10 07:18:32 PM PDT 24
Peak memory 207572 kb
Host smart-2fc0289b-da40-40e2-ac04-47e353a61807
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637038801 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 431.usbdev_tx_rx_disruption.2637038801
Directory /workspace/431.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/432.usbdev_tx_rx_disruption.1130897272
Short name T81
Test name
Test status
Simulation time 489872109 ps
CPU time 1.65 seconds
Started Aug 10 07:18:28 PM PDT 24
Finished Aug 10 07:18:29 PM PDT 24
Peak memory 207564 kb
Host smart-e6345128-4d0e-4218-9435-ee4f17d99caf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130897272 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 432.usbdev_tx_rx_disruption.1130897272
Directory /workspace/432.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/433.usbdev_tx_rx_disruption.2460904305
Short name T2283
Test name
Test status
Simulation time 457140511 ps
CPU time 1.58 seconds
Started Aug 10 07:18:29 PM PDT 24
Finished Aug 10 07:18:31 PM PDT 24
Peak memory 207572 kb
Host smart-ad2b1fff-36db-4adf-9bdd-3435570b0b4d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460904305 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 433.usbdev_tx_rx_disruption.2460904305
Directory /workspace/433.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/434.usbdev_tx_rx_disruption.775074163
Short name T1655
Test name
Test status
Simulation time 495026835 ps
CPU time 1.5 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207532 kb
Host smart-da629b25-2988-4a79-b678-0e32ec997aff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775074163 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 434.usbdev_tx_rx_disruption.775074163
Directory /workspace/434.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/435.usbdev_tx_rx_disruption.1645593741
Short name T1223
Test name
Test status
Simulation time 641292187 ps
CPU time 1.69 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207516 kb
Host smart-aa66c690-1003-4c9d-951b-201c67917d99
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645593741 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 435.usbdev_tx_rx_disruption.1645593741
Directory /workspace/435.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/436.usbdev_tx_rx_disruption.2769611313
Short name T2355
Test name
Test status
Simulation time 670858616 ps
CPU time 1.83 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207532 kb
Host smart-b778c475-1c9e-4650-9c70-8ae6e475da0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769611313 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 436.usbdev_tx_rx_disruption.2769611313
Directory /workspace/436.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/437.usbdev_tx_rx_disruption.1645476898
Short name T2279
Test name
Test status
Simulation time 497534628 ps
CPU time 1.49 seconds
Started Aug 10 07:18:24 PM PDT 24
Finished Aug 10 07:18:26 PM PDT 24
Peak memory 207580 kb
Host smart-435ed290-1f4d-41bd-8617-613c2003f3df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645476898 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 437.usbdev_tx_rx_disruption.1645476898
Directory /workspace/437.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/438.usbdev_tx_rx_disruption.1300408043
Short name T190
Test name
Test status
Simulation time 427452566 ps
CPU time 1.38 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207568 kb
Host smart-5c6b7848-82e1-4239-b389-4c5d11818146
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300408043 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 438.usbdev_tx_rx_disruption.1300408043
Directory /workspace/438.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/439.usbdev_tx_rx_disruption.1153047294
Short name T991
Test name
Test status
Simulation time 469284071 ps
CPU time 1.48 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207588 kb
Host smart-bb068cdf-db62-40ed-b598-e1fcd2633e6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153047294 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 439.usbdev_tx_rx_disruption.1153047294
Directory /workspace/439.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2290821305
Short name T1778
Test name
Test status
Simulation time 49625046 ps
CPU time 0.7 seconds
Started Aug 10 07:15:52 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 207544 kb
Host smart-5ba9f008-bf36-4c85-9449-c40b6dd0017c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2290821305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2290821305
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3882240585
Short name T3232
Test name
Test status
Simulation time 12285914826 ps
CPU time 16.02 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207876 kb
Host smart-d232e984-f7aa-4994-afa6-a896e52ef209
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882240585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.3882240585
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1311551724
Short name T106
Test name
Test status
Simulation time 15913325951 ps
CPU time 17.94 seconds
Started Aug 10 07:15:33 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 216044 kb
Host smart-634755a7-86d1-40f1-ac2e-d88cd113c876
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311551724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1311551724
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3796725975
Short name T2248
Test name
Test status
Simulation time 28903264625 ps
CPU time 44.42 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 207812 kb
Host smart-081c6d23-0a29-4737-8b2b-919ec989ddd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796725975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.3796725975
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1975401269
Short name T1042
Test name
Test status
Simulation time 174937462 ps
CPU time 0.92 seconds
Started Aug 10 07:15:33 PM PDT 24
Finished Aug 10 07:15:34 PM PDT 24
Peak memory 207588 kb
Host smart-ac6e8a5d-aa89-4ee6-b46a-c3ef08b634da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
01269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1975401269
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1682133228
Short name T3303
Test name
Test status
Simulation time 146720985 ps
CPU time 0.87 seconds
Started Aug 10 07:15:33 PM PDT 24
Finished Aug 10 07:15:34 PM PDT 24
Peak memory 207548 kb
Host smart-fa4abe3c-df4b-4ce0-aa1c-c419fc301278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
33228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1682133228
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.4002989933
Short name T129
Test name
Test status
Simulation time 391162860 ps
CPU time 1.37 seconds
Started Aug 10 07:15:29 PM PDT 24
Finished Aug 10 07:15:30 PM PDT 24
Peak memory 207552 kb
Host smart-a7a1c049-6856-4cf7-936f-eeed96dcbbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
89933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.4002989933
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1470068613
Short name T1392
Test name
Test status
Simulation time 1132050817 ps
CPU time 2.9 seconds
Started Aug 10 07:15:42 PM PDT 24
Finished Aug 10 07:15:45 PM PDT 24
Peak memory 207732 kb
Host smart-aa0bbeb6-0a1e-4bcd-95c3-672f09c97852
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1470068613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1470068613
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.476619025
Short name T1920
Test name
Test status
Simulation time 4801997159 ps
CPU time 44.56 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 207832 kb
Host smart-f46a2f08-97d6-4632-b6b4-e4dfcdbdca86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476619025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.476619025
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3168253751
Short name T3430
Test name
Test status
Simulation time 415547957 ps
CPU time 1.42 seconds
Started Aug 10 07:15:40 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207532 kb
Host smart-42f56c69-9a18-4b84-b2fe-7d959f9975c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31682
53751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3168253751
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1051613088
Short name T1821
Test name
Test status
Simulation time 167015369 ps
CPU time 0.92 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 207516 kb
Host smart-ec2eb174-bab6-4c07-9a7c-57312e29f58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
13088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1051613088
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.766967877
Short name T634
Test name
Test status
Simulation time 34827011 ps
CPU time 0.71 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207528 kb
Host smart-59dba859-6e32-4181-b38d-93eee3ed4c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76696
7877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.766967877
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1558320070
Short name T2518
Test name
Test status
Simulation time 779301223 ps
CPU time 2.25 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207604 kb
Host smart-16c88497-a184-4ffd-913b-7e2dc0f761cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
20070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1558320070
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_types.556657783
Short name T3111
Test name
Test status
Simulation time 190519057 ps
CPU time 0.92 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 207516 kb
Host smart-42e93fd0-d73c-4cfd-a0af-a3879593045e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=556657783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.556657783
Directory /workspace/44.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1010895842
Short name T847
Test name
Test status
Simulation time 195123266 ps
CPU time 2.51 seconds
Started Aug 10 07:15:36 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 207780 kb
Host smart-635a587d-7f5a-48db-88a2-afe51f89e322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
95842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1010895842
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1128296656
Short name T3143
Test name
Test status
Simulation time 152635021 ps
CPU time 0.94 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:39 PM PDT 24
Peak memory 207524 kb
Host smart-44bf833b-b06e-442b-afae-3965fb18ed34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1128296656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1128296656
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3241550779
Short name T3184
Test name
Test status
Simulation time 149548331 ps
CPU time 0.84 seconds
Started Aug 10 07:15:41 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207552 kb
Host smart-fc1c8689-e0f4-4fdf-bd47-8af94246131d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
50779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3241550779
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3063449503
Short name T3523
Test name
Test status
Simulation time 182222745 ps
CPU time 0.87 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207512 kb
Host smart-62446ec2-3f8f-4e4b-a18f-dc8b00b5979b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30634
49503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3063449503
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.89130105
Short name T2996
Test name
Test status
Simulation time 4320709525 ps
CPU time 31.49 seconds
Started Aug 10 07:15:41 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 217468 kb
Host smart-dad913f9-c442-4756-9751-ff3d1d7b1dc2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=89130105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.89130105
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1857552881
Short name T2163
Test name
Test status
Simulation time 8790695642 ps
CPU time 61.57 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:16:41 PM PDT 24
Peak memory 207736 kb
Host smart-6e29de46-8baa-4ffd-9fa2-fa76ae46eef4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1857552881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1857552881
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.680468102
Short name T1704
Test name
Test status
Simulation time 204559065 ps
CPU time 0.95 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207480 kb
Host smart-86a57dad-d152-4611-9f72-c2eb8f60628d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68046
8102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.680468102
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.996506760
Short name T1082
Test name
Test status
Simulation time 24503574006 ps
CPU time 44.2 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 216828 kb
Host smart-52cd8750-7467-474c-8588-e9cb3d2a5231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99650
6760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.996506760
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3533284002
Short name T1828
Test name
Test status
Simulation time 8435313503 ps
CPU time 10.55 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207904 kb
Host smart-f9acd691-19a0-4ace-acc7-11f74406b73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
84002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3533284002
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1332567990
Short name T2896
Test name
Test status
Simulation time 3005216776 ps
CPU time 22.56 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 217368 kb
Host smart-ff9f0a17-03cc-4c9b-acb4-843e828e2482
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1332567990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1332567990
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.154448032
Short name T931
Test name
Test status
Simulation time 1533143813 ps
CPU time 14.42 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 216852 kb
Host smart-013b7f32-b007-4bce-9d2c-5bb4dd025667
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=154448032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.154448032
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1357023723
Short name T2962
Test name
Test status
Simulation time 286400705 ps
CPU time 1.08 seconds
Started Aug 10 07:15:38 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207520 kb
Host smart-56e44634-f897-471e-9457-5b2e2a6250e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1357023723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1357023723
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4067924003
Short name T2367
Test name
Test status
Simulation time 218090412 ps
CPU time 0.96 seconds
Started Aug 10 07:15:36 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207580 kb
Host smart-d55d5208-b0ae-41c4-9c3b-e9150f1c4553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40679
24003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4067924003
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1769952161
Short name T1292
Test name
Test status
Simulation time 2842656454 ps
CPU time 22.43 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 217908 kb
Host smart-cc2c17e4-c30e-440a-841a-539767893aca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1769952161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1769952161
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.536876768
Short name T648
Test name
Test status
Simulation time 145993917 ps
CPU time 0.84 seconds
Started Aug 10 07:15:40 PM PDT 24
Finished Aug 10 07:15:41 PM PDT 24
Peak memory 207604 kb
Host smart-534a7783-fe51-4aad-8133-d1d3f1131e7b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=536876768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.536876768
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1385806807
Short name T2098
Test name
Test status
Simulation time 140132759 ps
CPU time 0.83 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207496 kb
Host smart-82b40522-9ef2-457f-b91a-b97041ee2f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13858
06807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1385806807
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1011940610
Short name T147
Test name
Test status
Simulation time 204856473 ps
CPU time 0.92 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207556 kb
Host smart-b5672ffc-6b07-437f-aa14-3107f0523788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
40610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1011940610
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2593575453
Short name T1085
Test name
Test status
Simulation time 166578974 ps
CPU time 0.91 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207480 kb
Host smart-f06b5fcf-521a-48ee-97f1-eca11dc59e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25935
75453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2593575453
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3269523198
Short name T2898
Test name
Test status
Simulation time 167659421 ps
CPU time 0.91 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207540 kb
Host smart-04d6ddae-e3ec-4d39-943d-f5752a19b2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
23198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3269523198
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1654870313
Short name T2059
Test name
Test status
Simulation time 142395105 ps
CPU time 0.82 seconds
Started Aug 10 07:15:41 PM PDT 24
Finished Aug 10 07:15:42 PM PDT 24
Peak memory 207568 kb
Host smart-b95f9f82-9fee-4018-b412-ac385c558bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16548
70313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1654870313
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2109975087
Short name T1701
Test name
Test status
Simulation time 149549236 ps
CPU time 0.88 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207604 kb
Host smart-c6f3a248-e5d1-4334-b99d-6b6b3dcadf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
75087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2109975087
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.4193370919
Short name T2745
Test name
Test status
Simulation time 261592411 ps
CPU time 1.08 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:15:40 PM PDT 24
Peak memory 207604 kb
Host smart-39a86abb-5d8c-4d75-89fb-2d3e4f209288
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4193370919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.4193370919
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3766206979
Short name T3276
Test name
Test status
Simulation time 203961607 ps
CPU time 0.9 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:15:41 PM PDT 24
Peak memory 207484 kb
Host smart-cabc12e5-cfc2-403a-a517-7dbe26901f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37662
06979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3766206979
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2889049988
Short name T1399
Test name
Test status
Simulation time 60120979 ps
CPU time 0.72 seconds
Started Aug 10 07:15:37 PM PDT 24
Finished Aug 10 07:15:38 PM PDT 24
Peak memory 207564 kb
Host smart-622efd3d-df22-4693-9ea1-8b6d3ce6a24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28890
49988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2889049988
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.823120778
Short name T2199
Test name
Test status
Simulation time 16349417747 ps
CPU time 46.35 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:16:36 PM PDT 24
Peak memory 216072 kb
Host smart-6e2e0774-e8d0-411a-942b-fabfa3e0eec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82312
0778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.823120778
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3899139219
Short name T3165
Test name
Test status
Simulation time 182084205 ps
CPU time 0.91 seconds
Started Aug 10 07:15:48 PM PDT 24
Finished Aug 10 07:15:49 PM PDT 24
Peak memory 207536 kb
Host smart-39575200-1705-41f0-a6dd-d663232cefee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991
39219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3899139219
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.72454694
Short name T975
Test name
Test status
Simulation time 199060060 ps
CPU time 0.9 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207484 kb
Host smart-a35c3c06-5575-4ecb-b391-e2e34b561031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72454
694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.72454694
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1033100013
Short name T1621
Test name
Test status
Simulation time 205498666 ps
CPU time 0.99 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207504 kb
Host smart-c635be85-45ba-4d70-86e0-978b57dd689c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
00013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1033100013
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1145763485
Short name T1824
Test name
Test status
Simulation time 153091856 ps
CPU time 0.84 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207584 kb
Host smart-b55a433c-79fa-401c-af7d-d6493b23093b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11457
63485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1145763485
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.935028905
Short name T1278
Test name
Test status
Simulation time 209162392 ps
CPU time 0.99 seconds
Started Aug 10 07:15:55 PM PDT 24
Finished Aug 10 07:15:56 PM PDT 24
Peak memory 207560 kb
Host smart-ebaa4d4e-5732-4360-8c2d-218716d0ee2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93502
8905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.935028905
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_rx_full.923256544
Short name T1575
Test name
Test status
Simulation time 270172402 ps
CPU time 1.08 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207608 kb
Host smart-fcc94cc9-2abe-4d17-ad4c-db53a981d3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92325
6544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.923256544
Directory /workspace/44.usbdev_rx_full/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3740996116
Short name T2037
Test name
Test status
Simulation time 191093408 ps
CPU time 0.93 seconds
Started Aug 10 07:15:54 PM PDT 24
Finished Aug 10 07:15:55 PM PDT 24
Peak memory 207528 kb
Host smart-282e2624-c7af-4955-a99b-f5696fd5a1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37409
96116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3740996116
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1614706824
Short name T2758
Test name
Test status
Simulation time 153443991 ps
CPU time 0.81 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207572 kb
Host smart-4bf9b847-920b-4f98-936c-405dc82bac62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
06824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1614706824
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3564912225
Short name T3022
Test name
Test status
Simulation time 318348717 ps
CPU time 1.08 seconds
Started Aug 10 07:15:52 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 207544 kb
Host smart-f62e4403-b732-4c5a-a005-a6d71fc79cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649
12225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3564912225
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.413445431
Short name T1288
Test name
Test status
Simulation time 2743814032 ps
CPU time 82.67 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:17:12 PM PDT 24
Peak memory 218068 kb
Host smart-75417905-5398-406c-9427-cd7eea796263
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=413445431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.413445431
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1391929596
Short name T510
Test name
Test status
Simulation time 179145935 ps
CPU time 0.9 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207532 kb
Host smart-57580b8a-e310-457d-93f3-69ce213b2673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
29596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1391929596
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1797860706
Short name T1571
Test name
Test status
Simulation time 173229749 ps
CPU time 0.88 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207576 kb
Host smart-0dc95938-aa02-47a3-aea6-cdfa38835b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17978
60706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1797860706
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.450647670
Short name T849
Test name
Test status
Simulation time 786948818 ps
CPU time 1.95 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207668 kb
Host smart-bd3887dd-dc4d-4e7a-ad9c-f49a24889fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45064
7670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.450647670
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3811621372
Short name T2970
Test name
Test status
Simulation time 1851666323 ps
CPU time 18.63 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 217388 kb
Host smart-acd69b13-5bd0-4492-b8ca-1b352be1ee38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38116
21372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3811621372
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.3546478521
Short name T3178
Test name
Test status
Simulation time 6346386119 ps
CPU time 44.37 seconds
Started Aug 10 07:15:39 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 207864 kb
Host smart-8eb900c7-222a-4acb-81b9-4904826989e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546478521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.3546478521
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_tx_rx_disruption.585942857
Short name T124
Test name
Test status
Simulation time 507876349 ps
CPU time 1.59 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207564 kb
Host smart-039a47aa-ce34-45bf-b60d-14fd80f54618
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585942857 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.usbdev_tx_rx_disruption.585942857
Directory /workspace/44.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/440.usbdev_tx_rx_disruption.694406956
Short name T2686
Test name
Test status
Simulation time 566172400 ps
CPU time 1.7 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207548 kb
Host smart-9afc04a2-21fb-40ed-b07b-3e386dfb97fd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694406956 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 440.usbdev_tx_rx_disruption.694406956
Directory /workspace/440.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/441.usbdev_tx_rx_disruption.3978888729
Short name T577
Test name
Test status
Simulation time 447803761 ps
CPU time 1.54 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207572 kb
Host smart-71f02d07-b713-4942-8660-23130c45ab6b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978888729 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 441.usbdev_tx_rx_disruption.3978888729
Directory /workspace/441.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/442.usbdev_tx_rx_disruption.1181566609
Short name T2710
Test name
Test status
Simulation time 585689314 ps
CPU time 1.57 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207552 kb
Host smart-d8a3104b-c72c-44ba-b950-696db4a21344
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181566609 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 442.usbdev_tx_rx_disruption.1181566609
Directory /workspace/442.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/443.usbdev_tx_rx_disruption.2458537507
Short name T2038
Test name
Test status
Simulation time 522588671 ps
CPU time 1.52 seconds
Started Aug 10 07:18:38 PM PDT 24
Finished Aug 10 07:18:40 PM PDT 24
Peak memory 207528 kb
Host smart-3460cd5a-4260-4f60-8376-30225e13f95a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458537507 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 443.usbdev_tx_rx_disruption.2458537507
Directory /workspace/443.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/444.usbdev_tx_rx_disruption.650292969
Short name T268
Test name
Test status
Simulation time 511116157 ps
CPU time 1.67 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207596 kb
Host smart-0329e0c7-2c6d-402d-8a3d-7054143daa52
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650292969 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 444.usbdev_tx_rx_disruption.650292969
Directory /workspace/444.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/445.usbdev_tx_rx_disruption.1723810166
Short name T2628
Test name
Test status
Simulation time 471263233 ps
CPU time 1.51 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207760 kb
Host smart-c410efc7-e0db-44d2-b72c-a13abb6233ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723810166 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 445.usbdev_tx_rx_disruption.1723810166
Directory /workspace/445.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/446.usbdev_tx_rx_disruption.353224130
Short name T2400
Test name
Test status
Simulation time 527529429 ps
CPU time 1.56 seconds
Started Aug 10 07:18:37 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207520 kb
Host smart-1eb066a3-6495-452a-bba6-04b37df46b01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353224130 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 446.usbdev_tx_rx_disruption.353224130
Directory /workspace/446.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/447.usbdev_tx_rx_disruption.3712027686
Short name T744
Test name
Test status
Simulation time 507083794 ps
CPU time 1.69 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207592 kb
Host smart-3663999e-3307-4c2f-b112-671a667ab84c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712027686 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 447.usbdev_tx_rx_disruption.3712027686
Directory /workspace/447.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/448.usbdev_tx_rx_disruption.3297871782
Short name T3530
Test name
Test status
Simulation time 506872086 ps
CPU time 1.77 seconds
Started Aug 10 07:18:38 PM PDT 24
Finished Aug 10 07:18:40 PM PDT 24
Peak memory 207504 kb
Host smart-cc25ea3f-5191-45db-a4f0-a42ce7674e0c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297871782 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 448.usbdev_tx_rx_disruption.3297871782
Directory /workspace/448.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/449.usbdev_tx_rx_disruption.1099606309
Short name T1120
Test name
Test status
Simulation time 570299363 ps
CPU time 1.48 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207604 kb
Host smart-3ee5250f-60db-4bfd-b892-af855ff99a29
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099606309 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 449.usbdev_tx_rx_disruption.1099606309
Directory /workspace/449.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2217292263
Short name T825
Test name
Test status
Simulation time 55669199 ps
CPU time 0.69 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207616 kb
Host smart-e3bee521-c9c7-479e-9204-3cc1b08e6152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2217292263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2217292263
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1097180954
Short name T1058
Test name
Test status
Simulation time 5663500240 ps
CPU time 8.09 seconds
Started Aug 10 07:15:48 PM PDT 24
Finished Aug 10 07:15:56 PM PDT 24
Peak memory 216068 kb
Host smart-8db9e3f5-20a1-476f-8fa9-fe9f27075b72
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097180954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1097180954
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3858214775
Short name T7
Test name
Test status
Simulation time 15273930201 ps
CPU time 16.91 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 216000 kb
Host smart-76c3c3cb-dcbc-4f56-bd52-8554b986341c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858214775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3858214775
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.76166528
Short name T922
Test name
Test status
Simulation time 24230765656 ps
CPU time 29.39 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 215904 kb
Host smart-916b7159-7579-4017-b1be-033ef63afcee
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76166528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon
_wake_resume.76166528
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3622676710
Short name T3049
Test name
Test status
Simulation time 158766008 ps
CPU time 0.84 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207560 kb
Host smart-012464bd-d673-4968-a3fe-46463cbee40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
76710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3622676710
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3099855402
Short name T3617
Test name
Test status
Simulation time 182262557 ps
CPU time 0.91 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207516 kb
Host smart-62ce65b2-c072-4696-b844-168e37cbe45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
55402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3099855402
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2344221377
Short name T1216
Test name
Test status
Simulation time 202977577 ps
CPU time 0.88 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207628 kb
Host smart-933253a0-2a39-424a-837f-6b4d9826d5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23442
21377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2344221377
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.114280739
Short name T2335
Test name
Test status
Simulation time 1068037803 ps
CPU time 2.88 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207720 kb
Host smart-f7182eff-e059-4c73-9e6d-6c47fb09c1ca
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=114280739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.114280739
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.4257303092
Short name T2306
Test name
Test status
Simulation time 19516940227 ps
CPU time 36.61 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 207852 kb
Host smart-ee3c3182-9900-4150-81c6-de42733feba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42573
03092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.4257303092
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.1294439827
Short name T722
Test name
Test status
Simulation time 7039813004 ps
CPU time 45.88 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 207788 kb
Host smart-bad01f2a-e5e2-4903-98b2-9c09d7e758db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294439827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1294439827
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.235185974
Short name T782
Test name
Test status
Simulation time 673749911 ps
CPU time 1.71 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207524 kb
Host smart-693ef152-4694-4ac7-870c-3db6eaeca986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23518
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.235185974
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3639598107
Short name T804
Test name
Test status
Simulation time 139190883 ps
CPU time 0.82 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207472 kb
Host smart-549a6b65-5ce3-4751-9500-1438fa82c5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36395
98107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3639598107
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2181434041
Short name T2019
Test name
Test status
Simulation time 41401556 ps
CPU time 0.69 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207500 kb
Host smart-789a415c-163e-4342-9c02-41a3170edc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
34041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2181434041
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3294788211
Short name T658
Test name
Test status
Simulation time 884664028 ps
CPU time 2.22 seconds
Started Aug 10 07:15:48 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207728 kb
Host smart-52129778-ea9e-428e-ac39-ceac06f0fabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
88211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3294788211
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_types.332561782
Short name T500
Test name
Test status
Simulation time 521973936 ps
CPU time 1.39 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207452 kb
Host smart-ff5c5c50-d6c8-4aaa-a7ac-22fde1301cf2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=332561782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.332561782
Directory /workspace/45.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2666850665
Short name T3562
Test name
Test status
Simulation time 324409088 ps
CPU time 2.76 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207728 kb
Host smart-c01c2c23-1fba-4288-8543-96abb7dd9842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26668
50665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2666850665
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2483873408
Short name T784
Test name
Test status
Simulation time 232324345 ps
CPU time 1.07 seconds
Started Aug 10 07:15:54 PM PDT 24
Finished Aug 10 07:15:56 PM PDT 24
Peak memory 215928 kb
Host smart-8fcf04e9-3658-43c1-afcb-cf597f84821d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2483873408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2483873408
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1325767036
Short name T855
Test name
Test status
Simulation time 152193175 ps
CPU time 0.86 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 207616 kb
Host smart-8aa0f6ce-3396-409a-ba9d-f99e86454340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13257
67036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1325767036
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3892508135
Short name T2773
Test name
Test status
Simulation time 204344731 ps
CPU time 0.97 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207472 kb
Host smart-8472e070-e9eb-4661-a58a-fa92e4efafc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
08135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3892508135
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3136614459
Short name T3010
Test name
Test status
Simulation time 2695285986 ps
CPU time 19.89 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 217324 kb
Host smart-46c049ee-e7ad-4793-9cf2-3ef3222db875
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3136614459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3136614459
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1262569986
Short name T1313
Test name
Test status
Simulation time 9097469376 ps
CPU time 106.64 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:17:36 PM PDT 24
Peak memory 207892 kb
Host smart-db5760c6-d190-4ff7-9c89-0b59e63e60f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1262569986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1262569986
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3412687357
Short name T1358
Test name
Test status
Simulation time 223191542 ps
CPU time 0.93 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207552 kb
Host smart-15b2863d-8fee-4451-ae2f-734e3d58ae99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
87357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3412687357
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2666323072
Short name T954
Test name
Test status
Simulation time 31135264020 ps
CPU time 53.14 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 207820 kb
Host smart-c305af68-dc5e-423c-8107-fd2f147e5a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
23072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2666323072
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.447319726
Short name T3380
Test name
Test status
Simulation time 5798788516 ps
CPU time 7.89 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207680 kb
Host smart-ea11e603-9014-45d6-8dab-be94a823f55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44731
9726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.447319726
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1822585936
Short name T2818
Test name
Test status
Simulation time 3117812912 ps
CPU time 29.85 seconds
Started Aug 10 07:15:52 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 219416 kb
Host smart-f46dd4fd-5b9e-4ef1-86a1-31cea8f230a1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1822585936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1822585936
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.742546806
Short name T777
Test name
Test status
Simulation time 2303120560 ps
CPU time 18.64 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 217680 kb
Host smart-a2dac6e9-1d74-4e02-b3a4-3d05dc613713
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=742546806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.742546806
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3430605819
Short name T2852
Test name
Test status
Simulation time 238936305 ps
CPU time 1.02 seconds
Started Aug 10 07:15:52 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 207564 kb
Host smart-2cb13ebf-4e66-4c2d-a3ff-c948d1bdba11
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3430605819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3430605819
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.381151075
Short name T1963
Test name
Test status
Simulation time 216316381 ps
CPU time 0.98 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207576 kb
Host smart-e33e8045-d002-4e30-83f2-46d17e155849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
1075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.381151075
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1728304460
Short name T969
Test name
Test status
Simulation time 2434732861 ps
CPU time 18.2 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 224288 kb
Host smart-d9407f0d-71ac-4add-ab28-af4b10040d28
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1728304460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1728304460
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1305136367
Short name T1198
Test name
Test status
Simulation time 152273079 ps
CPU time 0.82 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:50 PM PDT 24
Peak memory 207544 kb
Host smart-1a46cd4b-1c7e-4273-9e17-c0a8b1d5e4f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1305136367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1305136367
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3262560671
Short name T827
Test name
Test status
Simulation time 140421037 ps
CPU time 0.84 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207552 kb
Host smart-26c7fdc3-31fb-4368-9521-d5484051b40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625
60671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3262560671
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.820974749
Short name T163
Test name
Test status
Simulation time 198948023 ps
CPU time 0.9 seconds
Started Aug 10 07:15:53 PM PDT 24
Finished Aug 10 07:15:54 PM PDT 24
Peak memory 207500 kb
Host smart-aa3bb14d-e2aa-423d-9ab5-1e7b6cf5fb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82097
4749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.820974749
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2714844792
Short name T964
Test name
Test status
Simulation time 154928808 ps
CPU time 0.88 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:52 PM PDT 24
Peak memory 207508 kb
Host smart-0f5f1a8f-b825-4029-96c6-0d629faab9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
44792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2714844792
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.543483988
Short name T1274
Test name
Test status
Simulation time 176511570 ps
CPU time 0.85 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207528 kb
Host smart-1bbc26a1-3100-417b-82d3-6497e34ed904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54348
3988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.543483988
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2638194452
Short name T3217
Test name
Test status
Simulation time 233981152 ps
CPU time 0.96 seconds
Started Aug 10 07:15:52 PM PDT 24
Finished Aug 10 07:15:53 PM PDT 24
Peak memory 207584 kb
Host smart-a8f96b88-acc5-427b-848d-2a066d03d02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26381
94452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2638194452
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.579926214
Short name T867
Test name
Test status
Simulation time 185748086 ps
CPU time 0.86 seconds
Started Aug 10 07:15:50 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207472 kb
Host smart-d5c74457-db2c-47e4-aebf-4162941e704a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57992
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.579926214
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3432491236
Short name T2939
Test name
Test status
Simulation time 224455206 ps
CPU time 1.03 seconds
Started Aug 10 07:15:49 PM PDT 24
Finished Aug 10 07:15:51 PM PDT 24
Peak memory 207572 kb
Host smart-05b04cfa-d08c-4a30-a2a6-d50a30bca223
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3432491236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3432491236
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3199449806
Short name T1882
Test name
Test status
Simulation time 145471131 ps
CPU time 0.89 seconds
Started Aug 10 07:15:55 PM PDT 24
Finished Aug 10 07:15:56 PM PDT 24
Peak memory 207532 kb
Host smart-cd273eeb-b24b-4424-a272-8c7be97e447a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
49806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3199449806
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.375222925
Short name T1161
Test name
Test status
Simulation time 34997091 ps
CPU time 0.72 seconds
Started Aug 10 07:16:03 PM PDT 24
Finished Aug 10 07:16:04 PM PDT 24
Peak memory 207384 kb
Host smart-5024999c-3fdf-46d2-9a6b-69696bcf19c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37522
2925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.375222925
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1669360470
Short name T3382
Test name
Test status
Simulation time 8492616641 ps
CPU time 21.47 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 224164 kb
Host smart-e43c1c7e-8b49-4d74-b32f-5e070146aae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16693
60470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1669360470
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.143961239
Short name T1648
Test name
Test status
Simulation time 172791399 ps
CPU time 0.88 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207480 kb
Host smart-f8d2106f-24e8-44cc-969c-5c576752e40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
1239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.143961239
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3194794687
Short name T3501
Test name
Test status
Simulation time 193356944 ps
CPU time 0.89 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207540 kb
Host smart-4d943f80-9b54-4abb-854f-56487a111e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31947
94687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3194794687
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.374371015
Short name T3420
Test name
Test status
Simulation time 161654867 ps
CPU time 0.93 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207540 kb
Host smart-7cf425cc-f94a-47fe-9289-2c25eb5f3278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37437
1015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.374371015
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3011950270
Short name T820
Test name
Test status
Simulation time 171972917 ps
CPU time 0.91 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207576 kb
Host smart-52773c1d-67de-49d0-9978-8a01c248bc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30119
50270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3011950270
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1153836307
Short name T3278
Test name
Test status
Simulation time 157985733 ps
CPU time 0.83 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207604 kb
Host smart-819e89fb-5153-48ec-aca8-792d0bac7e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
36307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1153836307
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_rx_full.3586687482
Short name T1407
Test name
Test status
Simulation time 248475972 ps
CPU time 1.07 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207500 kb
Host smart-574811d0-1448-4645-a8eb-3374ac51d6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35866
87482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.3586687482
Directory /workspace/45.usbdev_rx_full/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3513362620
Short name T755
Test name
Test status
Simulation time 175995748 ps
CPU time 0.93 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:03 PM PDT 24
Peak memory 207572 kb
Host smart-c1a20aef-56d5-401d-aa91-860476e0f518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35133
62620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3513362620
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2346762529
Short name T2482
Test name
Test status
Simulation time 150096619 ps
CPU time 0.86 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207516 kb
Host smart-e7e332a5-3de6-44c5-9e8f-5cb7731d4f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
62529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2346762529
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3462664063
Short name T2394
Test name
Test status
Simulation time 239134520 ps
CPU time 1.02 seconds
Started Aug 10 07:16:06 PM PDT 24
Finished Aug 10 07:16:07 PM PDT 24
Peak memory 207416 kb
Host smart-a55079e8-dae2-433f-8b53-66151d2f33eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
64063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3462664063
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.912903448
Short name T1894
Test name
Test status
Simulation time 1945792088 ps
CPU time 54.82 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:55 PM PDT 24
Peak memory 217636 kb
Host smart-f8734403-f5fc-4550-8b24-207ff296557d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=912903448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.912903448
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3764919073
Short name T3195
Test name
Test status
Simulation time 244374692 ps
CPU time 0.96 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207548 kb
Host smart-2f5925e8-7b22-4133-868c-6ddd53dacc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
19073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3764919073
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2167021463
Short name T1375
Test name
Test status
Simulation time 199864438 ps
CPU time 0.91 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207496 kb
Host smart-cba20f9c-ef5e-4a68-96f9-bf6a2914ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
21463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2167021463
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.3495705897
Short name T2267
Test name
Test status
Simulation time 230503923 ps
CPU time 0.99 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:03 PM PDT 24
Peak memory 207388 kb
Host smart-60190b5e-b4a4-4689-b1cd-aac2b7a9337e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
05897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.3495705897
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.3939059819
Short name T3389
Test name
Test status
Simulation time 2913670557 ps
CPU time 83.09 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:17:25 PM PDT 24
Peak memory 215972 kb
Host smart-2df76ae7-9f25-4941-972a-dbffe430dc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39390
59819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3939059819
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.2864262415
Short name T560
Test name
Test status
Simulation time 3388539153 ps
CPU time 28.93 seconds
Started Aug 10 07:15:51 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207804 kb
Host smart-14fcea33-ae39-4f01-9a48-7846c041de7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864262415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.2864262415
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_tx_rx_disruption.2495722890
Short name T3625
Test name
Test status
Simulation time 516954043 ps
CPU time 1.42 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207452 kb
Host smart-49b3cb39-30af-4920-b137-76c10fd3c66e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495722890 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.usbdev_tx_rx_disruption.2495722890
Directory /workspace/45.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/450.usbdev_tx_rx_disruption.3144564954
Short name T187
Test name
Test status
Simulation time 505016512 ps
CPU time 1.74 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207544 kb
Host smart-f801c95c-682f-4026-8460-98d428b27738
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144564954 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 450.usbdev_tx_rx_disruption.3144564954
Directory /workspace/450.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/451.usbdev_tx_rx_disruption.2516786660
Short name T612
Test name
Test status
Simulation time 419344884 ps
CPU time 1.3 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207604 kb
Host smart-8972b9cf-329a-4b6e-8395-7a09be8e8b31
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516786660 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 451.usbdev_tx_rx_disruption.2516786660
Directory /workspace/451.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/452.usbdev_tx_rx_disruption.3364259367
Short name T1981
Test name
Test status
Simulation time 628579770 ps
CPU time 1.67 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207492 kb
Host smart-17230927-7e2d-481e-9d79-888d10f79119
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364259367 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 452.usbdev_tx_rx_disruption.3364259367
Directory /workspace/452.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/453.usbdev_tx_rx_disruption.2262810256
Short name T667
Test name
Test status
Simulation time 474329643 ps
CPU time 1.5 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207608 kb
Host smart-3875382f-a553-4540-befa-dcfc5680f510
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262810256 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 453.usbdev_tx_rx_disruption.2262810256
Directory /workspace/453.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/454.usbdev_tx_rx_disruption.1080183724
Short name T2479
Test name
Test status
Simulation time 558748949 ps
CPU time 1.47 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207560 kb
Host smart-305a2036-2a1c-4ab2-946c-6f24774af2a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080183724 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 454.usbdev_tx_rx_disruption.1080183724
Directory /workspace/454.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/455.usbdev_tx_rx_disruption.2063812792
Short name T953
Test name
Test status
Simulation time 548534774 ps
CPU time 1.7 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207564 kb
Host smart-81310b2b-abd3-413f-b1f4-b8871ee4b13a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063812792 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 455.usbdev_tx_rx_disruption.2063812792
Directory /workspace/455.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/456.usbdev_tx_rx_disruption.280487230
Short name T2139
Test name
Test status
Simulation time 547648187 ps
CPU time 1.61 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207664 kb
Host smart-2b015c17-2039-45b1-801f-a63da6bf6c01
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280487230 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 456.usbdev_tx_rx_disruption.280487230
Directory /workspace/456.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/457.usbdev_tx_rx_disruption.2168089375
Short name T274
Test name
Test status
Simulation time 466364526 ps
CPU time 1.6 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207492 kb
Host smart-04fd4ca8-bc05-4ad3-891b-35834c30d6e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168089375 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 457.usbdev_tx_rx_disruption.2168089375
Directory /workspace/457.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/458.usbdev_tx_rx_disruption.2885673709
Short name T2734
Test name
Test status
Simulation time 531761651 ps
CPU time 1.53 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207596 kb
Host smart-3b07b935-52ef-4a9d-b984-1f4462a33df9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885673709 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 458.usbdev_tx_rx_disruption.2885673709
Directory /workspace/458.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/459.usbdev_tx_rx_disruption.4180616746
Short name T1389
Test name
Test status
Simulation time 508103168 ps
CPU time 1.66 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207560 kb
Host smart-fd2cc5a5-780d-428a-a625-59b0ee15cc7b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180616746 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 459.usbdev_tx_rx_disruption.4180616746
Directory /workspace/459.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1992835871
Short name T232
Test name
Test status
Simulation time 35525325 ps
CPU time 0.65 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 207588 kb
Host smart-ab7a89e5-ca04-4685-932b-845731ea6e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1992835871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1992835871
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1494533382
Short name T2967
Test name
Test status
Simulation time 4390869793 ps
CPU time 6.44 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 216024 kb
Host smart-4e2c43ab-77d3-4adb-be93-00b44cfd8e79
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494533382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.1494533382
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.4066324399
Short name T235
Test name
Test status
Simulation time 14723481348 ps
CPU time 17.44 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 216012 kb
Host smart-e291a48d-64c0-4ce2-905e-71416b0b7ee5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066324399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.4066324399
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.419147940
Short name T2597
Test name
Test status
Simulation time 24309257910 ps
CPU time 30.54 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:39 PM PDT 24
Peak memory 215968 kb
Host smart-2af159e9-def6-444c-bb4f-3f41002100e0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419147940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_resume.419147940
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1202879273
Short name T2276
Test name
Test status
Simulation time 161024516 ps
CPU time 0.91 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207528 kb
Host smart-ed7c61f3-271e-4c4c-9a8b-d94bcba8adf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
79273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1202879273
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.749037969
Short name T766
Test name
Test status
Simulation time 142009083 ps
CPU time 0.81 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207564 kb
Host smart-c8301135-44a6-46f9-a999-a82d2a8033f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74903
7969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.749037969
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.224893356
Short name T1735
Test name
Test status
Simulation time 228512592 ps
CPU time 1.03 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:03 PM PDT 24
Peak memory 207584 kb
Host smart-152fe6fa-634a-4c63-9bcc-21f51c4e3b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
3356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.224893356
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.4222648864
Short name T2481
Test name
Test status
Simulation time 313194322 ps
CPU time 1.16 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207436 kb
Host smart-818dad35-d994-4dbd-a7ec-5e704e157855
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4222648864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.4222648864
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2606836089
Short name T1318
Test name
Test status
Simulation time 29929681696 ps
CPU time 56.87 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207776 kb
Host smart-dbac84e0-83e4-4d1a-be94-1ef7a00d1d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
36089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2606836089
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.4175258874
Short name T1196
Test name
Test status
Simulation time 3408749820 ps
CPU time 29.13 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 207848 kb
Host smart-5a6cc775-5cb5-44ba-a821-ea3ef50db413
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175258874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.4175258874
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2845411424
Short name T528
Test name
Test status
Simulation time 830379179 ps
CPU time 2.03 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:04 PM PDT 24
Peak memory 207528 kb
Host smart-01c3587e-474b-4dfd-9b68-a94a8d21837c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28454
11424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2845411424
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1492001766
Short name T3545
Test name
Test status
Simulation time 137864850 ps
CPU time 0.85 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207420 kb
Host smart-83e2f241-7291-4892-9798-49761bf26589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14920
01766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1492001766
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2395823661
Short name T2774
Test name
Test status
Simulation time 36070862 ps
CPU time 0.75 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207496 kb
Host smart-ed7982db-7066-44c9-81e1-b67d4cb40cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
23661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2395823661
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3860018443
Short name T586
Test name
Test status
Simulation time 880897244 ps
CPU time 2.29 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207688 kb
Host smart-972196ca-8086-4f79-96fe-7fab469fdf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38600
18443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3860018443
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_types.2552590364
Short name T2993
Test name
Test status
Simulation time 355657393 ps
CPU time 1.36 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207468 kb
Host smart-13170327-b4e2-4bf1-810f-0bf7a490e2e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2552590364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.2552590364
Directory /workspace/46.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1454924822
Short name T3099
Test name
Test status
Simulation time 225666891 ps
CPU time 1.54 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207744 kb
Host smart-e1fde3a8-a823-484a-9ba9-b06c3ae94272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14549
24822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1454924822
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.947454442
Short name T2480
Test name
Test status
Simulation time 233999762 ps
CPU time 1.26 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 215984 kb
Host smart-86d0e948-cd11-471a-894a-f8bd89324656
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=947454442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.947454442
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3906472923
Short name T2193
Test name
Test status
Simulation time 145071185 ps
CPU time 0.8 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:03 PM PDT 24
Peak memory 207384 kb
Host smart-02f73826-d991-4d26-b71a-0dd02fd50537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
72923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3906472923
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2057876935
Short name T1635
Test name
Test status
Simulation time 159601276 ps
CPU time 0.89 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207532 kb
Host smart-db95dae4-42bf-42fe-85cd-232a307dac0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20578
76935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2057876935
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3956164775
Short name T754
Test name
Test status
Simulation time 4686587417 ps
CPU time 36.48 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 218480 kb
Host smart-e6c05c8c-3049-4b4f-b371-d666020d08a1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3956164775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3956164775
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.303305978
Short name T2010
Test name
Test status
Simulation time 10617746940 ps
CPU time 120.5 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:18:00 PM PDT 24
Peak memory 207860 kb
Host smart-9e5862b2-bb33-4ef6-aabd-9988608a1c97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=303305978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.303305978
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2379174523
Short name T853
Test name
Test status
Simulation time 220298068 ps
CPU time 0.98 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207564 kb
Host smart-e87c7f16-3d7d-45ef-9087-b25ef104c850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
74523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2379174523
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.3699948093
Short name T1112
Test name
Test status
Simulation time 11711344185 ps
CPU time 15.39 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:16 PM PDT 24
Peak memory 207740 kb
Host smart-1588678c-2b3d-45b4-ad66-9a898e6b8438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
48093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.3699948093
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3525720110
Short name T3285
Test name
Test status
Simulation time 9731974017 ps
CPU time 11.66 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207872 kb
Host smart-13604f37-5192-4bc4-9335-4ed92da1e1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35257
20110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3525720110
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1417111056
Short name T1998
Test name
Test status
Simulation time 3654368708 ps
CPU time 101.93 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:17:50 PM PDT 24
Peak memory 218728 kb
Host smart-924e9c93-9d1b-44b0-83b8-28691289566c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1417111056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1417111056
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.326903714
Short name T682
Test name
Test status
Simulation time 3048851647 ps
CPU time 31.43 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:33 PM PDT 24
Peak memory 217720 kb
Host smart-f4790134-1d25-4503-a739-ffcd42f229f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=326903714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.326903714
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3344936689
Short name T1612
Test name
Test status
Simulation time 284134283 ps
CPU time 1.05 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207524 kb
Host smart-9296f901-3f92-4199-97bd-62c7ec658143
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3344936689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3344936689
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.830464538
Short name T3600
Test name
Test status
Simulation time 193037250 ps
CPU time 1.02 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:00 PM PDT 24
Peak memory 207544 kb
Host smart-2dbe78ec-63e1-4203-9281-5bc672e8d974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83046
4538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.830464538
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3276726633
Short name T1294
Test name
Test status
Simulation time 2604753954 ps
CPU time 28.25 seconds
Started Aug 10 07:16:02 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 217288 kb
Host smart-f22d6653-908e-4236-9def-d4a0731db69a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3276726633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3276726633
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.457120816
Short name T3588
Test name
Test status
Simulation time 169873150 ps
CPU time 0.87 seconds
Started Aug 10 07:15:58 PM PDT 24
Finished Aug 10 07:15:59 PM PDT 24
Peak memory 207564 kb
Host smart-591a38dc-f0b0-4b5c-a50d-71b0988fe4b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=457120816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.457120816
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.191839475
Short name T3244
Test name
Test status
Simulation time 149030976 ps
CPU time 0.82 seconds
Started Aug 10 07:15:59 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207456 kb
Host smart-881018f6-6880-4123-a0a2-42de2cf9f2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
9475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.191839475
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1635394867
Short name T3556
Test name
Test status
Simulation time 224373757 ps
CPU time 1.02 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207520 kb
Host smart-7f776316-183b-4194-b46f-76d078c2f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16353
94867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1635394867
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1611007275
Short name T2880
Test name
Test status
Simulation time 169559443 ps
CPU time 0.98 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:02 PM PDT 24
Peak memory 207532 kb
Host smart-775d8af2-6685-4d47-87bb-35740fec3efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16110
07275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1611007275
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2253082303
Short name T3484
Test name
Test status
Simulation time 183621045 ps
CPU time 0.89 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207520 kb
Host smart-a99049e5-e01e-4cf7-9f01-e0c406514ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22530
82303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2253082303
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.4196309808
Short name T1327
Test name
Test status
Simulation time 174826482 ps
CPU time 0.9 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207484 kb
Host smart-0e21665b-efcb-45c9-94f8-581006b036b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
09808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.4196309808
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.4234862577
Short name T2891
Test name
Test status
Simulation time 158030357 ps
CPU time 0.87 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207556 kb
Host smart-c073fac1-72f8-4467-9314-fa5957ce1773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
62577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.4234862577
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3600434577
Short name T2979
Test name
Test status
Simulation time 182850911 ps
CPU time 0.95 seconds
Started Aug 10 07:16:00 PM PDT 24
Finished Aug 10 07:16:01 PM PDT 24
Peak memory 207568 kb
Host smart-19e5dedd-38ca-4620-8107-536f7da61f5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3600434577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3600434577
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2083927570
Short name T1034
Test name
Test status
Simulation time 163127357 ps
CPU time 0.88 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207452 kb
Host smart-107953a9-59c9-4db4-9ed6-a98bdc1a5ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20839
27570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2083927570
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1350710389
Short name T1174
Test name
Test status
Simulation time 32182664 ps
CPU time 0.67 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207552 kb
Host smart-3977b44c-5174-488c-8cfd-f3bb51484d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13507
10389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1350710389
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3408705815
Short name T1847
Test name
Test status
Simulation time 9549881195 ps
CPU time 24.03 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:32 PM PDT 24
Peak memory 215996 kb
Host smart-28dc4bcb-4b1b-43f0-b97b-9f32ca2838f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
05815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3408705815
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2282452300
Short name T2338
Test name
Test status
Simulation time 191021878 ps
CPU time 0.98 seconds
Started Aug 10 07:16:13 PM PDT 24
Finished Aug 10 07:16:14 PM PDT 24
Peak memory 207420 kb
Host smart-8428c174-e48a-4b88-af00-4dc5b3c7f445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22824
52300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2282452300
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3261427328
Short name T2559
Test name
Test status
Simulation time 250038042 ps
CPU time 1.04 seconds
Started Aug 10 07:16:12 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 207484 kb
Host smart-f8ca4877-b65a-428e-ad37-8e779c0f2309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
27328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3261427328
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2857121977
Short name T2385
Test name
Test status
Simulation time 235946412 ps
CPU time 1.04 seconds
Started Aug 10 07:16:11 PM PDT 24
Finished Aug 10 07:16:12 PM PDT 24
Peak memory 207512 kb
Host smart-805b08d6-37f4-45a7-95ab-a26acb050c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28571
21977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2857121977
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1258281927
Short name T2934
Test name
Test status
Simulation time 166591235 ps
CPU time 0.92 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207584 kb
Host smart-5a0b1349-e7c2-4e8f-8f1d-40f890b46269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
81927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1258281927
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3561010509
Short name T2077
Test name
Test status
Simulation time 210320471 ps
CPU time 0.89 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207572 kb
Host smart-9dafeab0-346e-482a-b367-97f77b7907d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35610
10509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3561010509
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_rx_full.2384870785
Short name T1842
Test name
Test status
Simulation time 252112136 ps
CPU time 1.16 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207544 kb
Host smart-a5606977-66bd-4268-bcc4-caf4b34a9691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
70785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.2384870785
Directory /workspace/46.usbdev_rx_full/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1597406708
Short name T3612
Test name
Test status
Simulation time 158947062 ps
CPU time 0.88 seconds
Started Aug 10 07:16:06 PM PDT 24
Finished Aug 10 07:16:07 PM PDT 24
Peak memory 207540 kb
Host smart-4a8da319-6fe0-465f-b71a-7a3abbb9a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15974
06708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1597406708
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3492492688
Short name T3172
Test name
Test status
Simulation time 149089811 ps
CPU time 0.84 seconds
Started Aug 10 07:16:12 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 207420 kb
Host smart-8bdf551d-147e-4855-89ff-bbcc56b49bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
92688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3492492688
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.542397941
Short name T553
Test name
Test status
Simulation time 209161463 ps
CPU time 0.97 seconds
Started Aug 10 07:16:09 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207520 kb
Host smart-b3ed8ddf-909b-4232-845c-cd1d7566f543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54239
7941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.542397941
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1610008418
Short name T2973
Test name
Test status
Simulation time 1903188422 ps
CPU time 53.15 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 217568 kb
Host smart-7b0e3270-2afb-4c5e-8cc4-3757a5c7aa8e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1610008418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1610008418
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1152830247
Short name T2927
Test name
Test status
Simulation time 222357331 ps
CPU time 0.9 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 207556 kb
Host smart-6f17f6d5-e358-43d2-9520-906f2f35b3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528
30247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1152830247
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3930113
Short name T2883
Test name
Test status
Simulation time 169379786 ps
CPU time 0.86 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207464 kb
Host smart-6961da9a-2513-436f-a92f-28cb469d5105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
13 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3930113
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3830687414
Short name T959
Test name
Test status
Simulation time 292502497 ps
CPU time 1.06 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207552 kb
Host smart-fefd6d08-6092-48b7-91f9-171f1f924a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
87414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3830687414
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3462256014
Short name T1936
Test name
Test status
Simulation time 2423950861 ps
CPU time 67.31 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:17:14 PM PDT 24
Peak memory 217864 kb
Host smart-ffac84c6-95ac-42dc-9cb4-39420f0793de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34622
56014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3462256014
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.336772966
Short name T1613
Test name
Test status
Simulation time 1137844119 ps
CPU time 24.81 seconds
Started Aug 10 07:16:01 PM PDT 24
Finished Aug 10 07:16:26 PM PDT 24
Peak memory 207744 kb
Host smart-2259a162-1174-41ba-97ac-6dfe7b57aefb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336772966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_host
_handshake.336772966
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_tx_rx_disruption.509870925
Short name T1338
Test name
Test status
Simulation time 487586749 ps
CPU time 1.48 seconds
Started Aug 10 07:16:09 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207420 kb
Host smart-11fc45d1-b7c6-49f1-9d88-b2b344d7ed2a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509870925 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.usbdev_tx_rx_disruption.509870925
Directory /workspace/46.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/460.usbdev_tx_rx_disruption.1256320339
Short name T2494
Test name
Test status
Simulation time 593580871 ps
CPU time 1.56 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207504 kb
Host smart-d663a7bf-d23f-40f7-8947-48199a660a68
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256320339 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 460.usbdev_tx_rx_disruption.1256320339
Directory /workspace/460.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/461.usbdev_tx_rx_disruption.280049660
Short name T2968
Test name
Test status
Simulation time 552701238 ps
CPU time 1.5 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207592 kb
Host smart-7eb3cba8-555a-4443-8844-a56be8fde9c7
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280049660 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 461.usbdev_tx_rx_disruption.280049660
Directory /workspace/461.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/462.usbdev_tx_rx_disruption.2181498873
Short name T3298
Test name
Test status
Simulation time 484681940 ps
CPU time 1.5 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207600 kb
Host smart-552404d3-20a4-42bf-8480-b9572f75f365
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181498873 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 462.usbdev_tx_rx_disruption.2181498873
Directory /workspace/462.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/463.usbdev_tx_rx_disruption.88255136
Short name T1266
Test name
Test status
Simulation time 490849777 ps
CPU time 1.47 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207440 kb
Host smart-9c2f69e2-09fc-44f4-81c8-12415c9b2d7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88255136 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 463.usbdev_tx_rx_disruption.88255136
Directory /workspace/463.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/464.usbdev_tx_rx_disruption.706052053
Short name T3503
Test name
Test status
Simulation time 556023534 ps
CPU time 1.61 seconds
Started Aug 10 07:18:37 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207524 kb
Host smart-195c1e57-8e85-4dab-945f-2425bf346519
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706052053 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 464.usbdev_tx_rx_disruption.706052053
Directory /workspace/464.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/465.usbdev_tx_rx_disruption.2591937026
Short name T1770
Test name
Test status
Simulation time 606347616 ps
CPU time 1.73 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207600 kb
Host smart-76833647-f504-4b5e-9538-55f50433aa82
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591937026 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 465.usbdev_tx_rx_disruption.2591937026
Directory /workspace/465.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/466.usbdev_tx_rx_disruption.7444554
Short name T1293
Test name
Test status
Simulation time 604951490 ps
CPU time 1.8 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207556 kb
Host smart-706d4fd5-d675-4dbc-ab7a-1d211b90cd39
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7444554 -assert nopostproc +UVM_TESTN
AME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 466.usbdev_tx_rx_disruption.7444554
Directory /workspace/466.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/467.usbdev_tx_rx_disruption.3020416281
Short name T1341
Test name
Test status
Simulation time 433754014 ps
CPU time 1.38 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207512 kb
Host smart-4f14633f-b28a-465d-860f-99bded60756a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020416281 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 467.usbdev_tx_rx_disruption.3020416281
Directory /workspace/467.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/468.usbdev_tx_rx_disruption.1459885499
Short name T676
Test name
Test status
Simulation time 586657112 ps
CPU time 1.64 seconds
Started Aug 10 07:18:37 PM PDT 24
Finished Aug 10 07:18:39 PM PDT 24
Peak memory 207548 kb
Host smart-8164b4b1-0f27-400e-b0e1-c1bb6a3e944f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459885499 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 468.usbdev_tx_rx_disruption.1459885499
Directory /workspace/468.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/469.usbdev_tx_rx_disruption.1415104995
Short name T1751
Test name
Test status
Simulation time 653696569 ps
CPU time 1.76 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207504 kb
Host smart-a2c0082a-f780-4860-82ef-db5f74f014ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415104995 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 469.usbdev_tx_rx_disruption.1415104995
Directory /workspace/469.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.1138617307
Short name T3211
Test name
Test status
Simulation time 52923617 ps
CPU time 0.7 seconds
Started Aug 10 07:16:20 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207504 kb
Host smart-eb8cf61f-903b-4609-aa28-91f0a31c659f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1138617307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1138617307
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1817509606
Short name T2225
Test name
Test status
Simulation time 9724115008 ps
CPU time 13.04 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 207808 kb
Host smart-5e0a8eff-431a-4606-a6de-fb91d282e029
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817509606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_disconnect.1817509606
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1425736016
Short name T2825
Test name
Test status
Simulation time 14806448884 ps
CPU time 21.27 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:32 PM PDT 24
Peak memory 216060 kb
Host smart-a0e73f3e-cdc1-44ad-9645-543a4d039c1c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425736016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1425736016
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1671660629
Short name T1187
Test name
Test status
Simulation time 25733511681 ps
CPU time 31.03 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:39 PM PDT 24
Peak memory 215992 kb
Host smart-90d3910a-d3a5-4fcc-8d38-e96ffd6affe5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671660629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.1671660629
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2489886847
Short name T1607
Test name
Test status
Simulation time 195432927 ps
CPU time 0.97 seconds
Started Aug 10 07:16:06 PM PDT 24
Finished Aug 10 07:16:07 PM PDT 24
Peak memory 207528 kb
Host smart-510bb458-70a5-4974-ad18-c4bcfe9e121f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24898
86847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2489886847
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2796568765
Short name T1153
Test name
Test status
Simulation time 155051765 ps
CPU time 0.86 seconds
Started Aug 10 07:16:09 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207480 kb
Host smart-d8362b07-71bc-4a05-8c37-98390a57c210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27965
68765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2796568765
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3681368011
Short name T1154
Test name
Test status
Simulation time 358785781 ps
CPU time 1.3 seconds
Started Aug 10 07:16:12 PM PDT 24
Finished Aug 10 07:16:13 PM PDT 24
Peak memory 207420 kb
Host smart-88b48369-7d21-4423-a022-84575f35a84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36813
68011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3681368011
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2363273758
Short name T357
Test name
Test status
Simulation time 1028184615 ps
CPU time 2.61 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 207768 kb
Host smart-3546b830-a3c5-4ede-aa41-09d4cf687d8e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2363273758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2363273758
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3421321571
Short name T444
Test name
Test status
Simulation time 41134401380 ps
CPU time 63.26 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207768 kb
Host smart-564ed188-1456-42af-8b71-6a8757b814d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34213
21571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3421321571
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.142273351
Short name T1582
Test name
Test status
Simulation time 1508708406 ps
CPU time 9.81 seconds
Started Aug 10 07:16:11 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207744 kb
Host smart-2dc7ae2b-25c0-4ba0-ad15-cd1028f41f88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142273351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.142273351
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1350084777
Short name T2868
Test name
Test status
Simulation time 735691185 ps
CPU time 1.9 seconds
Started Aug 10 07:16:13 PM PDT 24
Finished Aug 10 07:16:16 PM PDT 24
Peak memory 207392 kb
Host smart-11349edb-ceb9-4bc8-98d6-293e2aeb65f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13500
84777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1350084777
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3710350290
Short name T2269
Test name
Test status
Simulation time 141020500 ps
CPU time 0.85 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207528 kb
Host smart-b0d4091a-320d-454c-80ff-a5b165169e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37103
50290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3710350290
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3781869023
Short name T3324
Test name
Test status
Simulation time 46027205 ps
CPU time 0.74 seconds
Started Aug 10 07:16:11 PM PDT 24
Finished Aug 10 07:16:12 PM PDT 24
Peak memory 207472 kb
Host smart-ffdb57b0-300d-4908-9b97-2d8c158ba44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37818
69023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3781869023
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1358851792
Short name T1782
Test name
Test status
Simulation time 992765156 ps
CPU time 2.43 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:12 PM PDT 24
Peak memory 207720 kb
Host smart-9c925ac6-0c6d-423f-8a3e-a13665e94fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13588
51792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1358851792
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_types.2260978532
Short name T456
Test name
Test status
Simulation time 649309996 ps
CPU time 1.48 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 207472 kb
Host smart-8ce8247d-78d5-4a9a-b0cf-75406044f187
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2260978532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.2260978532
Directory /workspace/47.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2475227771
Short name T563
Test name
Test status
Simulation time 310959898 ps
CPU time 2.54 seconds
Started Aug 10 07:16:06 PM PDT 24
Finished Aug 10 07:16:09 PM PDT 24
Peak memory 207732 kb
Host smart-af34b707-2cf3-49d9-a2ba-5b12360e14d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24752
27771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2475227771
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.606375007
Short name T659
Test name
Test status
Simulation time 268036330 ps
CPU time 1.1 seconds
Started Aug 10 07:16:09 PM PDT 24
Finished Aug 10 07:16:10 PM PDT 24
Peak memory 215824 kb
Host smart-96f28fc4-30f2-430c-9c2e-270e6d4d5e09
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=606375007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.606375007
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3879892645
Short name T1254
Test name
Test status
Simulation time 142878471 ps
CPU time 0.84 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207516 kb
Host smart-b067a425-dd05-4608-ba6a-b82f1493bfa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
92645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3879892645
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.134331127
Short name T585
Test name
Test status
Simulation time 238454979 ps
CPU time 1.01 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:08 PM PDT 24
Peak memory 207528 kb
Host smart-f12e7394-2fd8-4aa7-83af-4e6db6318b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13433
1127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.134331127
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.2937968937
Short name T1554
Test name
Test status
Simulation time 3688079993 ps
CPU time 36.26 seconds
Started Aug 10 07:16:08 PM PDT 24
Finished Aug 10 07:16:44 PM PDT 24
Peak memory 224372 kb
Host smart-f5aed362-3468-45a3-b68d-650ce3dc4c60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2937968937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.2937968937
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.23698927
Short name T1512
Test name
Test status
Simulation time 7730356549 ps
CPU time 92.91 seconds
Started Aug 10 07:16:11 PM PDT 24
Finished Aug 10 07:17:44 PM PDT 24
Peak memory 207808 kb
Host smart-e76b2336-2d47-4fab-99f5-dc8ea54e39d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=23698927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.23698927
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3846554893
Short name T2609
Test name
Test status
Simulation time 176975217 ps
CPU time 0.91 seconds
Started Aug 10 07:16:10 PM PDT 24
Finished Aug 10 07:16:11 PM PDT 24
Peak memory 207488 kb
Host smart-dabe0919-c5e6-48d8-83b0-a92febdfdd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
54893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3846554893
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.208600418
Short name T236
Test name
Test status
Simulation time 27181682278 ps
CPU time 41.92 seconds
Started Aug 10 07:16:09 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207756 kb
Host smart-7cfc806e-d104-4226-9062-227269094397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
0418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.208600418
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.364115135
Short name T597
Test name
Test status
Simulation time 9923718389 ps
CPU time 11.5 seconds
Started Aug 10 07:16:13 PM PDT 24
Finished Aug 10 07:16:24 PM PDT 24
Peak memory 207716 kb
Host smart-e8045767-d020-4919-8dbb-ce8ff605f707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36411
5135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.364115135
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2965627584
Short name T1281
Test name
Test status
Simulation time 2867891250 ps
CPU time 23.03 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 219652 kb
Host smart-e898c179-3969-4fe3-98b9-4e066bb79c6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2965627584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2965627584
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.194543949
Short name T3062
Test name
Test status
Simulation time 2794512458 ps
CPU time 22.63 seconds
Started Aug 10 07:16:06 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 216084 kb
Host smart-7a2a071c-f1a1-4063-a6a4-fd3a6cdc1713
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=194543949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.194543949
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3771459575
Short name T1501
Test name
Test status
Simulation time 304440429 ps
CPU time 1.13 seconds
Started Aug 10 07:16:21 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 207416 kb
Host smart-8c08b3d9-7928-41b1-844e-80f97311fde9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3771459575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3771459575
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1655703271
Short name T3375
Test name
Test status
Simulation time 190267182 ps
CPU time 0.95 seconds
Started Aug 10 07:16:19 PM PDT 24
Finished Aug 10 07:16:20 PM PDT 24
Peak memory 207552 kb
Host smart-8c3b7555-0ba1-4010-94ac-b944d53016ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16557
03271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1655703271
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3855263155
Short name T2065
Test name
Test status
Simulation time 3232714348 ps
CPU time 32.74 seconds
Started Aug 10 07:16:20 PM PDT 24
Finished Aug 10 07:16:53 PM PDT 24
Peak memory 217560 kb
Host smart-38d7a3db-5e35-4280-a4c3-42d40126e43a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3855263155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3855263155
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.4127736969
Short name T1486
Test name
Test status
Simulation time 160471774 ps
CPU time 0.87 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207496 kb
Host smart-4d8534a4-5530-4be2-a49c-d062735e09a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4127736969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.4127736969
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3903683614
Short name T1561
Test name
Test status
Simulation time 207084701 ps
CPU time 0.92 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207540 kb
Host smart-a9205723-742d-4245-a588-e5310ff35afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39036
83614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3903683614
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.865675541
Short name T134
Test name
Test status
Simulation time 190932598 ps
CPU time 0.93 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207576 kb
Host smart-c05904dc-16a1-42b0-be36-c318cca97b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86567
5541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.865675541
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1675516584
Short name T225
Test name
Test status
Simulation time 219723537 ps
CPU time 0.9 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207544 kb
Host smart-efd1668d-7450-4350-b7ab-337ea4cf4cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755
16584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1675516584
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3316749016
Short name T1499
Test name
Test status
Simulation time 192936129 ps
CPU time 0.94 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207596 kb
Host smart-87870e9d-3b7c-4d5d-b39f-ad677abc01cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
49016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3316749016
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1438043359
Short name T2188
Test name
Test status
Simulation time 140730632 ps
CPU time 0.84 seconds
Started Aug 10 07:16:20 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207544 kb
Host smart-ca7fa701-5ad3-4a93-8b67-ab5f9c714c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14380
43359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1438043359
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3775209196
Short name T2368
Test name
Test status
Simulation time 149335655 ps
CPU time 0.88 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207564 kb
Host smart-9401a3ef-bfa4-442e-b28a-c8fecd61934b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37752
09196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3775209196
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2022761606
Short name T2564
Test name
Test status
Simulation time 307629502 ps
CPU time 1.16 seconds
Started Aug 10 07:16:20 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207536 kb
Host smart-5c55e15e-e921-4ceb-9f5d-35d6a757d827
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2022761606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2022761606
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1578215043
Short name T830
Test name
Test status
Simulation time 179299008 ps
CPU time 0.87 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207364 kb
Host smart-565de583-33ef-43f1-be1b-f1cd029ac2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15782
15043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1578215043
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.859209144
Short name T2977
Test name
Test status
Simulation time 47866716 ps
CPU time 0.75 seconds
Started Aug 10 07:16:21 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 207548 kb
Host smart-4ae0bf99-27eb-4706-bbe3-69c2bcecb6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85920
9144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.859209144
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1748051560
Short name T313
Test name
Test status
Simulation time 11622317191 ps
CPU time 33 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 216264 kb
Host smart-b6909b90-5648-41fd-9827-f15838f3369f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
51560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1748051560
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1538027310
Short name T3028
Test name
Test status
Simulation time 187668570 ps
CPU time 0.9 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207576 kb
Host smart-33b641eb-98e9-48d7-969a-7b6cd1f76ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
27310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1538027310
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1853608100
Short name T737
Test name
Test status
Simulation time 194703259 ps
CPU time 0.93 seconds
Started Aug 10 07:16:16 PM PDT 24
Finished Aug 10 07:16:17 PM PDT 24
Peak memory 207476 kb
Host smart-91e150f6-c015-41a8-a99c-c9321ad0aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
08100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1853608100
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.772081637
Short name T2689
Test name
Test status
Simulation time 210382850 ps
CPU time 0.98 seconds
Started Aug 10 07:16:21 PM PDT 24
Finished Aug 10 07:16:22 PM PDT 24
Peak memory 207588 kb
Host smart-c284c313-824c-40e6-9c79-5cf01f066a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77208
1637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.772081637
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1950912911
Short name T3482
Test name
Test status
Simulation time 164090481 ps
CPU time 0.87 seconds
Started Aug 10 07:16:20 PM PDT 24
Finished Aug 10 07:16:21 PM PDT 24
Peak memory 207552 kb
Host smart-bfacfd24-84e7-49dc-8d03-dec4f5284f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
12911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1950912911
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1089510910
Short name T2573
Test name
Test status
Simulation time 143066116 ps
CPU time 0.8 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:18 PM PDT 24
Peak memory 207516 kb
Host smart-5790b99a-d4d0-47d4-a0cc-96f80a499de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10895
10910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1089510910
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_rx_full.2301315731
Short name T351
Test name
Test status
Simulation time 260416803 ps
CPU time 1.17 seconds
Started Aug 10 07:16:16 PM PDT 24
Finished Aug 10 07:16:17 PM PDT 24
Peak memory 207500 kb
Host smart-bfc51c9c-5e2f-490d-bd3f-d4595311ea4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23013
15731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.2301315731
Directory /workspace/47.usbdev_rx_full/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.538347227
Short name T2011
Test name
Test status
Simulation time 169941893 ps
CPU time 0.84 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207500 kb
Host smart-ac4bb2ce-88d1-4d08-821e-a523c54d0b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53834
7227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.538347227
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1848594373
Short name T1814
Test name
Test status
Simulation time 154994069 ps
CPU time 0.92 seconds
Started Aug 10 07:16:22 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 207608 kb
Host smart-fd636098-2570-4830-922a-614fb80fb7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485
94373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1848594373
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.532980388
Short name T3265
Test name
Test status
Simulation time 288155049 ps
CPU time 1.12 seconds
Started Aug 10 07:16:23 PM PDT 24
Finished Aug 10 07:16:24 PM PDT 24
Peak memory 207504 kb
Host smart-92cce76a-1364-4b17-bedf-2cb3c75c9651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53298
0388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.532980388
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.681740375
Short name T878
Test name
Test status
Simulation time 2037162804 ps
CPU time 56.76 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:17:14 PM PDT 24
Peak memory 217448 kb
Host smart-51cf87ce-310e-4b7d-a9da-7814969fb66a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=681740375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.681740375
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.229643944
Short name T561
Test name
Test status
Simulation time 157141507 ps
CPU time 0.89 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207744 kb
Host smart-764d2cc0-0bd5-447b-8bd2-d89ef9379631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22964
3944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.229643944
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2405390054
Short name T2039
Test name
Test status
Simulation time 159008078 ps
CPU time 0.84 seconds
Started Aug 10 07:16:16 PM PDT 24
Finished Aug 10 07:16:17 PM PDT 24
Peak memory 207528 kb
Host smart-19271218-c9c4-4ca3-bcda-475e15777431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24053
90054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2405390054
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1898704819
Short name T3086
Test name
Test status
Simulation time 784356431 ps
CPU time 1.93 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207532 kb
Host smart-dfc66bec-fca0-4a1c-b723-1197ea4e83b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18987
04819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1898704819
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.3403694090
Short name T579
Test name
Test status
Simulation time 3936094454 ps
CPU time 28.36 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 216136 kb
Host smart-23a19f26-7bfe-4d3b-983e-d25ad4119a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34036
94090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.3403694090
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.1773040079
Short name T1224
Test name
Test status
Simulation time 7974380863 ps
CPU time 55.69 seconds
Started Aug 10 07:16:07 PM PDT 24
Finished Aug 10 07:17:03 PM PDT 24
Peak memory 207696 kb
Host smart-4c1bb087-44a6-4e3d-8e9b-1954af418a92
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773040079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos
t_handshake.1773040079
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_tx_rx_disruption.3545115334
Short name T973
Test name
Test status
Simulation time 520825315 ps
CPU time 1.7 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:20 PM PDT 24
Peak memory 207440 kb
Host smart-821533a5-ecaa-4eec-b11b-bc5d110b9d7d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545115334 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.usbdev_tx_rx_disruption.3545115334
Directory /workspace/47.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/470.usbdev_tx_rx_disruption.940809207
Short name T2485
Test name
Test status
Simulation time 498591957 ps
CPU time 1.52 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207600 kb
Host smart-0b2da401-70bb-4818-8823-3d0a7f604337
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940809207 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 470.usbdev_tx_rx_disruption.940809207
Directory /workspace/470.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/471.usbdev_tx_rx_disruption.1953319059
Short name T263
Test name
Test status
Simulation time 616761783 ps
CPU time 1.55 seconds
Started Aug 10 07:18:38 PM PDT 24
Finished Aug 10 07:18:40 PM PDT 24
Peak memory 207516 kb
Host smart-eb625775-2117-41ea-a01f-4847031fa3e8
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953319059 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 471.usbdev_tx_rx_disruption.1953319059
Directory /workspace/471.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/472.usbdev_tx_rx_disruption.4096682315
Short name T2624
Test name
Test status
Simulation time 506410832 ps
CPU time 1.6 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207544 kb
Host smart-272a7a42-14cf-42ad-9172-ab74a1b8c542
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096682315 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 472.usbdev_tx_rx_disruption.4096682315
Directory /workspace/472.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/473.usbdev_tx_rx_disruption.3726588666
Short name T3470
Test name
Test status
Simulation time 482793068 ps
CPU time 1.66 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207572 kb
Host smart-680fff82-17a9-48e1-a876-ab97ec269592
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726588666 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 473.usbdev_tx_rx_disruption.3726588666
Directory /workspace/473.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/474.usbdev_tx_rx_disruption.1665315707
Short name T3338
Test name
Test status
Simulation time 471917806 ps
CPU time 1.49 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207504 kb
Host smart-ebe1e595-ffe8-49f1-82b0-f40a238e67e5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665315707 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 474.usbdev_tx_rx_disruption.1665315707
Directory /workspace/474.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/475.usbdev_tx_rx_disruption.622655755
Short name T681
Test name
Test status
Simulation time 677407419 ps
CPU time 1.79 seconds
Started Aug 10 07:18:38 PM PDT 24
Finished Aug 10 07:18:40 PM PDT 24
Peak memory 207516 kb
Host smart-ebe9b7df-ada5-46af-9eab-f4bef895abfe
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622655755 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 475.usbdev_tx_rx_disruption.622655755
Directory /workspace/475.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/476.usbdev_tx_rx_disruption.695682317
Short name T1762
Test name
Test status
Simulation time 511424760 ps
CPU time 1.55 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207516 kb
Host smart-1b9f8996-cfd4-43d4-bcda-7b6c2c360329
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695682317 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 476.usbdev_tx_rx_disruption.695682317
Directory /workspace/476.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/477.usbdev_tx_rx_disruption.1903378144
Short name T1353
Test name
Test status
Simulation time 503577544 ps
CPU time 1.56 seconds
Started Aug 10 07:18:37 PM PDT 24
Finished Aug 10 07:18:39 PM PDT 24
Peak memory 207528 kb
Host smart-cdc10e51-9eda-409a-a685-c1b0da81874a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903378144 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 477.usbdev_tx_rx_disruption.1903378144
Directory /workspace/477.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/478.usbdev_tx_rx_disruption.2023518095
Short name T3613
Test name
Test status
Simulation time 511933190 ps
CPU time 1.56 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207572 kb
Host smart-28007c3e-995d-43c4-9aa6-c542dfd830a6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023518095 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 478.usbdev_tx_rx_disruption.2023518095
Directory /workspace/478.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/479.usbdev_tx_rx_disruption.425369006
Short name T3188
Test name
Test status
Simulation time 536850983 ps
CPU time 1.61 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207564 kb
Host smart-e836940d-425f-4bbf-9c0b-ebfcad0a56cf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425369006 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 479.usbdev_tx_rx_disruption.425369006
Directory /workspace/479.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2876652939
Short name T710
Test name
Test status
Simulation time 41230154 ps
CPU time 0.68 seconds
Started Aug 10 07:16:42 PM PDT 24
Finished Aug 10 07:16:43 PM PDT 24
Peak memory 207540 kb
Host smart-fc1f3fc2-fc7b-4bca-86e7-aadf8bb4c442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2876652939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2876652939
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.453738546
Short name T105
Test name
Test status
Simulation time 3937420037 ps
CPU time 5.98 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:23 PM PDT 24
Peak memory 216012 kb
Host smart-56e939a2-cbd0-4a30-9a54-7760ecf79af7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453738546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_disconnect.453738546
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2634624755
Short name T1000
Test name
Test status
Simulation time 21262403940 ps
CPU time 24.9 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:42 PM PDT 24
Peak memory 207888 kb
Host smart-8c13802c-3248-4ad8-854a-fd96d561ee8c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634624755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2634624755
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.549314564
Short name T887
Test name
Test status
Simulation time 28748910338 ps
CPU time 34.25 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:52 PM PDT 24
Peak memory 207712 kb
Host smart-6620fb41-212b-46f7-8b7f-19b8ccaa95ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549314564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_ao
n_wake_resume.549314564
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.73217371
Short name T2412
Test name
Test status
Simulation time 145893158 ps
CPU time 0.83 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207608 kb
Host smart-06b4b825-020b-4639-969a-a2b6793882ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73217
371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.73217371
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3530392593
Short name T985
Test name
Test status
Simulation time 187057988 ps
CPU time 0.86 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207548 kb
Host smart-2895ff7f-9e74-40d7-86a5-ffface7fe045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
92593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3530392593
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.843226396
Short name T3451
Test name
Test status
Simulation time 508561892 ps
CPU time 1.7 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:19 PM PDT 24
Peak memory 207436 kb
Host smart-60ad307f-3b24-4885-bc59-e0cf1627946e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84322
6396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.843226396
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3395746549
Short name T1408
Test name
Test status
Simulation time 663240279 ps
CPU time 1.88 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:20 PM PDT 24
Peak memory 207512 kb
Host smart-2ab5648f-718b-4383-8538-b2886a5edc0c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3395746549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3395746549
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3260421581
Short name T181
Test name
Test status
Simulation time 15240312480 ps
CPU time 24 seconds
Started Aug 10 07:16:17 PM PDT 24
Finished Aug 10 07:16:42 PM PDT 24
Peak memory 207864 kb
Host smart-bd5facb8-71a1-4e16-97ee-b3fd94d8cb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
21581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3260421581
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.31465320
Short name T583
Test name
Test status
Simulation time 1133349290 ps
CPU time 9.9 seconds
Started Aug 10 07:16:18 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 207748 kb
Host smart-38049dd1-50d4-4cf8-b4c2-4acf447658f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.31465320
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1783026189
Short name T1858
Test name
Test status
Simulation time 949192004 ps
CPU time 2.24 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207572 kb
Host smart-1f646ecc-a5a8-4bd4-bd97-d6d22d229209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17830
26189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1783026189
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.14137369
Short name T1797
Test name
Test status
Simulation time 161421424 ps
CPU time 0.86 seconds
Started Aug 10 07:16:29 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 207548 kb
Host smart-3c65ce0d-61f8-487a-9265-0a3134485bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.14137369
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3393940404
Short name T2414
Test name
Test status
Simulation time 38909530 ps
CPU time 0.71 seconds
Started Aug 10 07:16:25 PM PDT 24
Finished Aug 10 07:16:26 PM PDT 24
Peak memory 207544 kb
Host smart-3a236890-bad2-4f21-a1a5-3e72b9819833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33939
40404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3393940404
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.78380348
Short name T2782
Test name
Test status
Simulation time 734852334 ps
CPU time 2.13 seconds
Started Aug 10 07:16:30 PM PDT 24
Finished Aug 10 07:16:32 PM PDT 24
Peak memory 207792 kb
Host smart-ddcbdff9-5d9b-4636-9672-c21b62ea92b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78380
348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.78380348
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_types.3084908639
Short name T401
Test name
Test status
Simulation time 503968874 ps
CPU time 1.44 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207480 kb
Host smart-6f17b177-41ae-465b-b4c6-d2c3c0fddc80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3084908639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.3084908639
Directory /workspace/48.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4179136354
Short name T2318
Test name
Test status
Simulation time 188274781 ps
CPU time 2.15 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207660 kb
Host smart-e4297ecf-c59a-47c5-8df0-34713ce00ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791
36354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4179136354
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.818202407
Short name T3085
Test name
Test status
Simulation time 201984343 ps
CPU time 1.06 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 215924 kb
Host smart-65d0234d-1129-4f99-ab6f-d190ef4c2ff9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=818202407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.818202407
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2252328495
Short name T2029
Test name
Test status
Simulation time 158628139 ps
CPU time 0.85 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207520 kb
Host smart-9a824eb2-2ae6-44af-a7b8-0d99d4f89389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
28495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2252328495
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4003398598
Short name T2907
Test name
Test status
Simulation time 231314883 ps
CPU time 0.99 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207512 kb
Host smart-621364db-dbb2-4c77-8b0a-1761f89aff1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4003398598
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2121864792
Short name T2337
Test name
Test status
Simulation time 4842512790 ps
CPU time 142.24 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:18:49 PM PDT 24
Peak memory 217672 kb
Host smart-4c2da6a9-96d7-43ee-89a8-63c559ee1f1d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2121864792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2121864792
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.1657980063
Short name T1850
Test name
Test status
Simulation time 13974494576 ps
CPU time 90.5 seconds
Started Aug 10 07:16:29 PM PDT 24
Finished Aug 10 07:18:00 PM PDT 24
Peak memory 207800 kb
Host smart-69ee72ab-6f03-4688-8e9d-c563e2da4e34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1657980063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.1657980063
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3663702373
Short name T1441
Test name
Test status
Simulation time 156555993 ps
CPU time 0.85 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 207568 kb
Host smart-a2d1a373-c6d1-4728-b93e-7bb68a7af610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36637
02373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3663702373
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2420709794
Short name T1297
Test name
Test status
Simulation time 9285673879 ps
CPU time 12.64 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:41 PM PDT 24
Peak memory 216756 kb
Host smart-23f9b1a3-4ea6-4ebd-bce6-be8de7fb7f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
09794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2420709794
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.147281950
Short name T1954
Test name
Test status
Simulation time 6050346253 ps
CPU time 8.15 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 215884 kb
Host smart-8a03f88d-3c9d-42f1-bb75-e9488b1e61fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14728
1950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.147281950
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1189914566
Short name T1326
Test name
Test status
Simulation time 3432757275 ps
CPU time 35.06 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:17:03 PM PDT 24
Peak memory 219192 kb
Host smart-bb7c5a41-2892-42f7-b7ef-c6431c51ad2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1189914566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1189914566
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.1180329942
Short name T803
Test name
Test status
Simulation time 3710201270 ps
CPU time 28.65 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 217796 kb
Host smart-0c9d6cb7-62af-4aa0-9991-e261f4098321
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1180329942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.1180329942
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3863545853
Short name T892
Test name
Test status
Simulation time 243122614 ps
CPU time 1.06 seconds
Started Aug 10 07:16:24 PM PDT 24
Finished Aug 10 07:16:26 PM PDT 24
Peak memory 207532 kb
Host smart-77984c0e-c5b8-431f-b714-6c545591b302
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3863545853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3863545853
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1081297434
Short name T1708
Test name
Test status
Simulation time 215506774 ps
CPU time 0.96 seconds
Started Aug 10 07:16:30 PM PDT 24
Finished Aug 10 07:16:31 PM PDT 24
Peak memory 207528 kb
Host smart-6107a486-a270-4fa9-913a-4fc03ba782fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
97434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1081297434
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3021848246
Short name T1912
Test name
Test status
Simulation time 1532507898 ps
CPU time 11.46 seconds
Started Aug 10 07:16:29 PM PDT 24
Finished Aug 10 07:16:41 PM PDT 24
Peak memory 217428 kb
Host smart-ad359ee9-2c07-4247-b5e2-dce2d1c0caa1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3021848246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3021848246
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.969943289
Short name T2102
Test name
Test status
Simulation time 156569218 ps
CPU time 0.91 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 207536 kb
Host smart-c90c92ee-5e9f-41a7-9afa-c015eb6fedbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=969943289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.969943289
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.158065994
Short name T941
Test name
Test status
Simulation time 144553697 ps
CPU time 0.87 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 207552 kb
Host smart-9b8ba4b0-505a-44d0-aa81-a983aac5d5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
5994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.158065994
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.4072227271
Short name T149
Test name
Test status
Simulation time 288896475 ps
CPU time 1.11 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 207244 kb
Host smart-a535395c-5b97-4838-87e1-49efcaeecb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
27271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.4072227271
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2001050662
Short name T3602
Test name
Test status
Simulation time 184237492 ps
CPU time 0.96 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:28 PM PDT 24
Peak memory 207608 kb
Host smart-12ddd2a6-7277-47d8-8173-1cd13f4a5ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20010
50662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2001050662
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4218417492
Short name T2131
Test name
Test status
Simulation time 170290477 ps
CPU time 0.88 seconds
Started Aug 10 07:16:29 PM PDT 24
Finished Aug 10 07:16:30 PM PDT 24
Peak memory 207532 kb
Host smart-709ad734-90fd-4bdf-8dee-a6d960687644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42184
17492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4218417492
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2271951811
Short name T3190
Test name
Test status
Simulation time 206789543 ps
CPU time 0.95 seconds
Started Aug 10 07:16:28 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207564 kb
Host smart-53d03d6b-2ab2-471d-95bd-abb1f288de49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22719
51811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2271951811
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.248736919
Short name T2074
Test name
Test status
Simulation time 149397751 ps
CPU time 0.84 seconds
Started Aug 10 07:16:27 PM PDT 24
Finished Aug 10 07:16:29 PM PDT 24
Peak memory 207556 kb
Host smart-fd6fbcf8-6ce8-4094-ae9f-02b9955f8681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
6919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.248736919
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.340981920
Short name T761
Test name
Test status
Simulation time 229622246 ps
CPU time 1.04 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:38 PM PDT 24
Peak memory 207548 kb
Host smart-8f9f8aae-216a-41bf-b5f1-e257e88249c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=340981920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.340981920
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3978705162
Short name T1425
Test name
Test status
Simulation time 151038500 ps
CPU time 0.88 seconds
Started Aug 10 07:16:38 PM PDT 24
Finished Aug 10 07:16:39 PM PDT 24
Peak memory 207548 kb
Host smart-01ec4703-5bc3-406b-985b-5fce78daae5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39787
05162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3978705162
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1591012886
Short name T1237
Test name
Test status
Simulation time 39902368 ps
CPU time 0.66 seconds
Started Aug 10 07:16:35 PM PDT 24
Finished Aug 10 07:16:35 PM PDT 24
Peak memory 207468 kb
Host smart-55f8e893-d1ba-45a2-82a3-7dc6e56da454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15910
12886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1591012886
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1624997308
Short name T316
Test name
Test status
Simulation time 14744764750 ps
CPU time 33.62 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:17:19 PM PDT 24
Peak memory 224088 kb
Host smart-e0015905-218e-467e-8d08-81979c4a6079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
97308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1624997308
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.942050748
Short name T781
Test name
Test status
Simulation time 198147306 ps
CPU time 0.94 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 207608 kb
Host smart-7d9b899f-a5b2-46fc-ad96-dd96dd9a8f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94205
0748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.942050748
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3358210157
Short name T679
Test name
Test status
Simulation time 194211563 ps
CPU time 0.95 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 207580 kb
Host smart-63c06eec-8b0e-49cb-8460-8394ec7576b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33582
10157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3358210157
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1577031396
Short name T2983
Test name
Test status
Simulation time 238693966 ps
CPU time 1.02 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 207588 kb
Host smart-862560df-7142-48ac-b1e5-01fe39ad84e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15770
31396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1577031396
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1854064479
Short name T3378
Test name
Test status
Simulation time 229447245 ps
CPU time 0.9 seconds
Started Aug 10 07:16:42 PM PDT 24
Finished Aug 10 07:16:43 PM PDT 24
Peak memory 207608 kb
Host smart-a7b6f8b3-c8c9-4b00-90da-1c0081f910d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
64479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1854064479
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3445073219
Short name T3169
Test name
Test status
Simulation time 150851103 ps
CPU time 0.82 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:38 PM PDT 24
Peak memory 207436 kb
Host smart-b7755646-8e57-4919-b8b1-2fd43a44d937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450
73219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3445073219
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_rx_full.3594103007
Short name T2328
Test name
Test status
Simulation time 279196282 ps
CPU time 1.18 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207560 kb
Host smart-e4df26c9-4340-468b-8577-b9ed10156627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35941
03007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.3594103007
Directory /workspace/48.usbdev_rx_full/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1502018880
Short name T1012
Test name
Test status
Simulation time 186448055 ps
CPU time 0.86 seconds
Started Aug 10 07:16:35 PM PDT 24
Finished Aug 10 07:16:36 PM PDT 24
Peak memory 207476 kb
Host smart-c395cda6-1ec3-44f9-9a74-ea78a080a70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15020
18880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1502018880
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.792234820
Short name T1790
Test name
Test status
Simulation time 154302297 ps
CPU time 0.87 seconds
Started Aug 10 07:16:39 PM PDT 24
Finished Aug 10 07:16:40 PM PDT 24
Peak memory 207576 kb
Host smart-65c2fbac-1971-4644-96e6-626e0d6cf979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79223
4820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.792234820
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1736003226
Short name T3118
Test name
Test status
Simulation time 226167249 ps
CPU time 1.08 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:16:37 PM PDT 24
Peak memory 207552 kb
Host smart-a1fd51bc-6149-4d29-9d1b-9b6bd8ecb377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
03226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1736003226
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3320128763
Short name T1943
Test name
Test status
Simulation time 2907815238 ps
CPU time 85.51 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:18:12 PM PDT 24
Peak memory 216096 kb
Host smart-9e4211f6-8f0e-430c-a8a1-9703593b60be
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3320128763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3320128763
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1816443851
Short name T3050
Test name
Test status
Simulation time 193534160 ps
CPU time 0.89 seconds
Started Aug 10 07:16:43 PM PDT 24
Finished Aug 10 07:16:44 PM PDT 24
Peak memory 207528 kb
Host smart-f625576d-17c4-4218-911a-cb40c88d8e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18164
43851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1816443851
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1607817477
Short name T752
Test name
Test status
Simulation time 168703125 ps
CPU time 0.89 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207576 kb
Host smart-50410beb-2cbe-41e3-8025-e9f375207da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16078
17477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1607817477
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3582105754
Short name T2692
Test name
Test status
Simulation time 719751734 ps
CPU time 2 seconds
Started Aug 10 07:16:40 PM PDT 24
Finished Aug 10 07:16:42 PM PDT 24
Peak memory 207628 kb
Host smart-c75f3901-a42a-462b-b66e-cb9a3d07f40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35821
05754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3582105754
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.857050608
Short name T1993
Test name
Test status
Simulation time 2555071348 ps
CPU time 74.3 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:17:51 PM PDT 24
Peak memory 217652 kb
Host smart-afd15f47-af89-4f40-91d6-16ac2af70672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85705
0608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.857050608
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1316228828
Short name T3317
Test name
Test status
Simulation time 2930454047 ps
CPU time 18.06 seconds
Started Aug 10 07:16:25 PM PDT 24
Finished Aug 10 07:16:43 PM PDT 24
Peak memory 207876 kb
Host smart-73944a3e-40df-4f48-a15c-36c32039fb9a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316228828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.1316228828
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_tx_rx_disruption.2307782327
Short name T3560
Test name
Test status
Simulation time 664877690 ps
CPU time 1.63 seconds
Started Aug 10 07:16:43 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 207588 kb
Host smart-c7480c11-2e05-4863-84d3-4101d42074d6
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307782327 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.usbdev_tx_rx_disruption.2307782327
Directory /workspace/48.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/480.usbdev_tx_rx_disruption.4275390962
Short name T635
Test name
Test status
Simulation time 490501658 ps
CPU time 1.57 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207548 kb
Host smart-7cd2d4f2-75ca-4813-8ea5-c906e2f46eec
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275390962 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 480.usbdev_tx_rx_disruption.4275390962
Directory /workspace/480.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/481.usbdev_tx_rx_disruption.2682352845
Short name T683
Test name
Test status
Simulation time 435277157 ps
CPU time 1.38 seconds
Started Aug 10 07:18:32 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207528 kb
Host smart-c4ac2524-e841-4a9b-8135-6fd50e8fe925
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682352845 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 481.usbdev_tx_rx_disruption.2682352845
Directory /workspace/481.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/482.usbdev_tx_rx_disruption.1007967875
Short name T2832
Test name
Test status
Simulation time 611216917 ps
CPU time 1.76 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207440 kb
Host smart-683da0c7-18a2-466b-9afc-fc1c00dfc1cb
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007967875 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 482.usbdev_tx_rx_disruption.1007967875
Directory /workspace/482.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/483.usbdev_tx_rx_disruption.3796428109
Short name T1503
Test name
Test status
Simulation time 494783021 ps
CPU time 1.48 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207496 kb
Host smart-1376a7b1-5a4f-4798-955c-86df995ed27a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796428109 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 483.usbdev_tx_rx_disruption.3796428109
Directory /workspace/483.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/484.usbdev_tx_rx_disruption.3143613046
Short name T1807
Test name
Test status
Simulation time 517716075 ps
CPU time 1.44 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207564 kb
Host smart-0fe8d724-7768-49c0-a5ec-f684c419b7ce
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143613046 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 484.usbdev_tx_rx_disruption.3143613046
Directory /workspace/484.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/485.usbdev_tx_rx_disruption.4232589233
Short name T2162
Test name
Test status
Simulation time 583550190 ps
CPU time 1.6 seconds
Started Aug 10 07:18:38 PM PDT 24
Finished Aug 10 07:18:40 PM PDT 24
Peak memory 207504 kb
Host smart-da4b5f04-cd00-4b23-9aa0-aca1f55624b5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232589233 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 485.usbdev_tx_rx_disruption.4232589233
Directory /workspace/485.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/486.usbdev_tx_rx_disruption.377625721
Short name T3386
Test name
Test status
Simulation time 415777989 ps
CPU time 1.44 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:34 PM PDT 24
Peak memory 207536 kb
Host smart-8330ea08-2d73-40e8-acb5-733e1578c671
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377625721 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 486.usbdev_tx_rx_disruption.377625721
Directory /workspace/486.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/487.usbdev_tx_rx_disruption.805692632
Short name T2525
Test name
Test status
Simulation time 513574404 ps
CPU time 1.5 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207548 kb
Host smart-a392f932-7890-4cc5-ba38-e0fc05c89b55
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805692632 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 487.usbdev_tx_rx_disruption.805692632
Directory /workspace/487.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/488.usbdev_tx_rx_disruption.160266636
Short name T3247
Test name
Test status
Simulation time 497319869 ps
CPU time 1.6 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207560 kb
Host smart-1590f02d-010b-4f49-ae1d-91d33d8652a1
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160266636 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 488.usbdev_tx_rx_disruption.160266636
Directory /workspace/488.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/489.usbdev_tx_rx_disruption.1331371064
Short name T3400
Test name
Test status
Simulation time 452801908 ps
CPU time 1.37 seconds
Started Aug 10 07:18:33 PM PDT 24
Finished Aug 10 07:18:35 PM PDT 24
Peak memory 207576 kb
Host smart-3bd14139-f244-42be-aca8-6e5b0ff78019
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331371064 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 489.usbdev_tx_rx_disruption.1331371064
Directory /workspace/489.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.27928472
Short name T2599
Test name
Test status
Simulation time 41321576 ps
CPU time 0.71 seconds
Started Aug 10 07:16:54 PM PDT 24
Finished Aug 10 07:16:55 PM PDT 24
Peak memory 207572 kb
Host smart-cb67241f-6309-412d-a02e-c0a49c67a367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=27928472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.27928472
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.420010794
Short name T2964
Test name
Test status
Simulation time 10992957603 ps
CPU time 13.48 seconds
Started Aug 10 07:16:40 PM PDT 24
Finished Aug 10 07:16:54 PM PDT 24
Peak memory 207904 kb
Host smart-a7ce819c-b89a-4ae9-8829-918a7c3df7e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420010794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_ao
n_wake_disconnect.420010794
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1347563521
Short name T2143
Test name
Test status
Simulation time 20644525870 ps
CPU time 25.22 seconds
Started Aug 10 07:16:43 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207784 kb
Host smart-a6777d4f-b78b-4c2e-9b85-b81a487674cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347563521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1347563521
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1684839782
Short name T3214
Test name
Test status
Simulation time 31271327583 ps
CPU time 39.62 seconds
Started Aug 10 07:16:36 PM PDT 24
Finished Aug 10 07:17:15 PM PDT 24
Peak memory 207860 kb
Host smart-9887edb9-2c73-41d1-a991-68b1f4406d19
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684839782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1684839782
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.105611991
Short name T1747
Test name
Test status
Simulation time 161566940 ps
CPU time 0.88 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:38 PM PDT 24
Peak memory 207572 kb
Host smart-538b0a76-64a9-4922-b760-6c0b1c9c6ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
1991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.105611991
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1090649162
Short name T1659
Test name
Test status
Simulation time 158241626 ps
CPU time 0.83 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:47 PM PDT 24
Peak memory 207488 kb
Host smart-ae43f88b-dcac-415a-9c67-267d5138428b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
49162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1090649162
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1147872705
Short name T3549
Test name
Test status
Simulation time 416255596 ps
CPU time 1.48 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207576 kb
Host smart-3cb023ae-2a09-4093-a077-b2ce23ff8a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
72705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1147872705
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.1643745112
Short name T1100
Test name
Test status
Simulation time 507969053 ps
CPU time 1.47 seconds
Started Aug 10 07:16:43 PM PDT 24
Finished Aug 10 07:16:44 PM PDT 24
Peak memory 207596 kb
Host smart-907efebd-7e53-4f5a-b4a2-3b74b650b234
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1643745112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.1643745112
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2036740857
Short name T2088
Test name
Test status
Simulation time 32936475039 ps
CPU time 48.74 seconds
Started Aug 10 07:16:35 PM PDT 24
Finished Aug 10 07:17:24 PM PDT 24
Peak memory 207744 kb
Host smart-53502b4c-c624-47d6-89af-e3dfd23916e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20367
40857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2036740857
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.2840930201
Short name T1249
Test name
Test status
Simulation time 3599468868 ps
CPU time 23.82 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207840 kb
Host smart-56f2f98d-2960-48de-aa0c-9bd0bd8a31dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840930201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.2840930201
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1247087769
Short name T2132
Test name
Test status
Simulation time 637534701 ps
CPU time 1.54 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:39 PM PDT 24
Peak memory 207480 kb
Host smart-097798b3-7ae7-42bf-b2c8-60d5fed8bd75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
87769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1247087769
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.620899851
Short name T1792
Test name
Test status
Simulation time 139104436 ps
CPU time 0.79 seconds
Started Aug 10 07:16:35 PM PDT 24
Finished Aug 10 07:16:36 PM PDT 24
Peak memory 207572 kb
Host smart-bc211bfb-d161-45e0-9f75-c04f9a112f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62089
9851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.620899851
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.685938178
Short name T3423
Test name
Test status
Simulation time 61091572 ps
CPU time 0.77 seconds
Started Aug 10 07:16:42 PM PDT 24
Finished Aug 10 07:16:43 PM PDT 24
Peak memory 207532 kb
Host smart-1bae02f9-a776-4ac9-9529-c899e8cdfdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68593
8178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.685938178
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3819923241
Short name T2531
Test name
Test status
Simulation time 1018574981 ps
CPU time 2.82 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207716 kb
Host smart-bac09235-2710-486a-867a-b1363e2e4618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
23241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3819923241
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_types.1264377180
Short name T432
Test name
Test status
Simulation time 273070238 ps
CPU time 1.11 seconds
Started Aug 10 07:16:40 PM PDT 24
Finished Aug 10 07:16:41 PM PDT 24
Peak memory 207620 kb
Host smart-223d32bf-aad5-4448-af7a-89efb9ddf01d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1264377180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.1264377180
Directory /workspace/49.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3908141848
Short name T695
Test name
Test status
Simulation time 360886742 ps
CPU time 2.4 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207660 kb
Host smart-82b6e49a-ca91-4d9a-ab1c-c2ad47844d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
41848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3908141848
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1147643557
Short name T3589
Test name
Test status
Simulation time 218052381 ps
CPU time 1.12 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 215876 kb
Host smart-1f8093e4-ab70-4def-871c-0b6ca5c9e953
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1147643557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1147643557
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.855781278
Short name T2300
Test name
Test status
Simulation time 169788939 ps
CPU time 0.84 seconds
Started Aug 10 07:16:35 PM PDT 24
Finished Aug 10 07:16:36 PM PDT 24
Peak memory 207508 kb
Host smart-e84776a5-6068-4600-a7aa-d21d7b3fdbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85578
1278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.855781278
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4008743896
Short name T3192
Test name
Test status
Simulation time 208771956 ps
CPU time 0.96 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207552 kb
Host smart-ee82dc63-fc81-4de9-a553-908fd5868b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40087
43896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4008743896
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1905190071
Short name T1595
Test name
Test status
Simulation time 3058741123 ps
CPU time 31.55 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:17:16 PM PDT 24
Peak memory 218120 kb
Host smart-415ea465-afa7-4817-9b72-75edc608068e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1905190071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1905190071
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.276301917
Short name T1620
Test name
Test status
Simulation time 8223501665 ps
CPU time 55.09 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:17:32 PM PDT 24
Peak memory 207736 kb
Host smart-bc744b47-48d2-451e-956b-342e01e9e1f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=276301917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.276301917
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2354586051
Short name T1623
Test name
Test status
Simulation time 194149069 ps
CPU time 0.9 seconds
Started Aug 10 07:16:43 PM PDT 24
Finished Aug 10 07:16:44 PM PDT 24
Peak memory 207516 kb
Host smart-9fa4cb71-7971-486d-ac94-e61541eb6309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545
86051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2354586051
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3175940999
Short name T738
Test name
Test status
Simulation time 7935780955 ps
CPU time 11.75 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 216096 kb
Host smart-325fd681-b60e-4221-943d-bf369f190445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
40999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3175940999
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1842766234
Short name T1044
Test name
Test status
Simulation time 11431852543 ps
CPU time 13.26 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207820 kb
Host smart-7b8431d1-8d9b-478a-96b5-7312c52af0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
66234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1842766234
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3058364691
Short name T2605
Test name
Test status
Simulation time 2555641743 ps
CPU time 67.51 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:17:45 PM PDT 24
Peak memory 216096 kb
Host smart-663c21ee-8a0e-4390-8b7c-39026600bcf4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3058364691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3058364691
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4086498450
Short name T1752
Test name
Test status
Simulation time 2553810829 ps
CPU time 72.05 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:17:57 PM PDT 24
Peak memory 216084 kb
Host smart-5a8560be-558f-4c61-ad4e-69c2841b0fc7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4086498450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4086498450
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2144784534
Short name T3344
Test name
Test status
Simulation time 236495678 ps
CPU time 1.01 seconds
Started Aug 10 07:16:42 PM PDT 24
Finished Aug 10 07:16:44 PM PDT 24
Peak memory 207528 kb
Host smart-fa7d57e6-05b0-463f-9066-d9fffd8f0bbf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2144784534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2144784534
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.160716164
Short name T3538
Test name
Test status
Simulation time 187620255 ps
CPU time 0.9 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 207484 kb
Host smart-e2148666-9278-4305-829e-3de1a21fa293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16071
6164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.160716164
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1713753879
Short name T1323
Test name
Test status
Simulation time 2758005064 ps
CPU time 77.71 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:17:55 PM PDT 24
Peak memory 216032 kb
Host smart-72543643-4dfc-4d66-9556-5201729dd1d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1713753879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1713753879
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.4118841756
Short name T1095
Test name
Test status
Simulation time 178888447 ps
CPU time 0.89 seconds
Started Aug 10 07:16:52 PM PDT 24
Finished Aug 10 07:16:53 PM PDT 24
Peak memory 207604 kb
Host smart-9563cb1f-5d80-417f-a98e-cd43c00c7147
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4118841756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.4118841756
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3939565689
Short name T779
Test name
Test status
Simulation time 219277412 ps
CPU time 0.9 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:47 PM PDT 24
Peak memory 207552 kb
Host smart-d2173ddb-4610-4941-a082-3b31e32211a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
65689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3939565689
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1133560296
Short name T3176
Test name
Test status
Simulation time 206987573 ps
CPU time 0.94 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207456 kb
Host smart-d1e47b2f-2a8f-423c-adc8-d281d9e5017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
60296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1133560296
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1296088426
Short name T986
Test name
Test status
Simulation time 162699801 ps
CPU time 0.83 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207576 kb
Host smart-3ea9709c-f5d7-487d-8961-94770c2fe239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960
88426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1296088426
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1954691701
Short name T2671
Test name
Test status
Simulation time 179676963 ps
CPU time 0.9 seconds
Started Aug 10 07:16:54 PM PDT 24
Finished Aug 10 07:16:55 PM PDT 24
Peak memory 207560 kb
Host smart-1bca708e-181f-4d44-bcc3-aa2d7bca158e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546
91701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1954691701
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3807360817
Short name T504
Test name
Test status
Simulation time 163160551 ps
CPU time 0.86 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207524 kb
Host smart-5125b72e-3a1e-4136-9482-a71dbe9d6750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
60817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3807360817
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3012762322
Short name T3019
Test name
Test status
Simulation time 170579914 ps
CPU time 0.9 seconds
Started Aug 10 07:16:54 PM PDT 24
Finished Aug 10 07:16:55 PM PDT 24
Peak memory 207564 kb
Host smart-8c433a27-815f-4eff-92d0-0b11ae60985e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
62322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3012762322
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1072400937
Short name T1890
Test name
Test status
Simulation time 218415090 ps
CPU time 0.97 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:47 PM PDT 24
Peak memory 207508 kb
Host smart-2a6fe44a-272d-4bd7-961b-ffbffaa6e38f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1072400937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1072400937
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.175845138
Short name T1666
Test name
Test status
Simulation time 169900285 ps
CPU time 0.91 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207476 kb
Host smart-34a783b7-abd4-4ba3-ad37-10e6638836ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17584
5138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.175845138
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1444726358
Short name T1781
Test name
Test status
Simulation time 34945326 ps
CPU time 0.72 seconds
Started Aug 10 07:16:54 PM PDT 24
Finished Aug 10 07:16:55 PM PDT 24
Peak memory 207472 kb
Host smart-a142a1e3-0b05-4646-930b-008de84dd3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
26358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1444726358
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3617055182
Short name T1788
Test name
Test status
Simulation time 9564740773 ps
CPU time 23.61 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 224200 kb
Host smart-e19fa03f-7351-4e95-82d1-69316af15216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36170
55182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3617055182
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3070069203
Short name T3236
Test name
Test status
Simulation time 170752120 ps
CPU time 0.88 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207528 kb
Host smart-ab1c7a87-bc05-497a-88b8-a49cd5504798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30700
69203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3070069203
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.430310378
Short name T2061
Test name
Test status
Simulation time 227392784 ps
CPU time 0.97 seconds
Started Aug 10 07:16:51 PM PDT 24
Finished Aug 10 07:16:52 PM PDT 24
Peak memory 207436 kb
Host smart-c4d05b10-1699-4add-ad06-12e513dd9d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43031
0378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.430310378
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3251165349
Short name T1284
Test name
Test status
Simulation time 190068154 ps
CPU time 0.9 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207540 kb
Host smart-300d805d-8f05-4663-8f4f-fa51ac242c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32511
65349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3251165349
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.462009758
Short name T1946
Test name
Test status
Simulation time 157002369 ps
CPU time 0.86 seconds
Started Aug 10 07:16:45 PM PDT 24
Finished Aug 10 07:16:46 PM PDT 24
Peak memory 207548 kb
Host smart-87c4c8d4-723c-4d06-a760-3509910c205e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46200
9758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.462009758
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1614985905
Short name T2913
Test name
Test status
Simulation time 176455493 ps
CPU time 0.9 seconds
Started Aug 10 07:16:53 PM PDT 24
Finished Aug 10 07:16:54 PM PDT 24
Peak memory 207576 kb
Host smart-a7c04452-04a0-4e46-81bb-ddadc8ee1661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
85905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1614985905
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_rx_full.3696193569
Short name T2670
Test name
Test status
Simulation time 271053860 ps
CPU time 1.05 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207568 kb
Host smart-9933b2a7-af04-4f30-9b5b-61dabc008a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
93569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.3696193569
Directory /workspace/49.usbdev_rx_full/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2122508823
Short name T2378
Test name
Test status
Simulation time 208073368 ps
CPU time 0.96 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207472 kb
Host smart-84a1820c-fa0e-4d7a-ac6b-1f69bf1f3136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21225
08823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2122508823
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2702820490
Short name T222
Test name
Test status
Simulation time 158533995 ps
CPU time 0.87 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:47 PM PDT 24
Peak memory 207536 kb
Host smart-8fac23c7-4b19-4881-878a-12732406cff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27028
20490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2702820490
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4141133016
Short name T873
Test name
Test status
Simulation time 203040986 ps
CPU time 1.01 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207520 kb
Host smart-b1c8563d-2f7b-4210-9881-5ff33f9fe5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41411
33016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4141133016
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.333637257
Short name T2652
Test name
Test status
Simulation time 3191902242 ps
CPU time 27.1 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:17:14 PM PDT 24
Peak memory 216128 kb
Host smart-23470438-be52-42e4-8b75-c8a93b84f81b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=333637257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.333637257
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4243522716
Short name T2224
Test name
Test status
Simulation time 187512507 ps
CPU time 0.84 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207572 kb
Host smart-2a3dd854-4b9f-4729-9f4c-c325c8dd9833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42435
22716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4243522716
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.904074220
Short name T1572
Test name
Test status
Simulation time 169543666 ps
CPU time 0.87 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207604 kb
Host smart-95b1e495-4ace-4d8a-965c-4706afd4d15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90407
4220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.904074220
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2680678386
Short name T1803
Test name
Test status
Simulation time 705897850 ps
CPU time 1.98 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207556 kb
Host smart-50678cb1-1f4f-4552-bf54-1bbfc93b19f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
78386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2680678386
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1936882825
Short name T2881
Test name
Test status
Simulation time 3977722021 ps
CPU time 111.96 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:18:41 PM PDT 24
Peak memory 217488 kb
Host smart-32393dc9-0dce-45b7-9293-343777bf5cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368
82825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1936882825
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.3166343224
Short name T61
Test name
Test status
Simulation time 2218711438 ps
CPU time 14.04 seconds
Started Aug 10 07:16:37 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207832 kb
Host smart-c70a4e4d-8d6b-47e0-b6bc-26cac0d3a06b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166343224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.3166343224
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_tx_rx_disruption.2349449296
Short name T1818
Test name
Test status
Simulation time 449552993 ps
CPU time 1.42 seconds
Started Aug 10 07:16:44 PM PDT 24
Finished Aug 10 07:16:45 PM PDT 24
Peak memory 207584 kb
Host smart-a27f0fab-a6e8-4800-bc7a-2b8e44bdcfe0
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349449296 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.usbdev_tx_rx_disruption.2349449296
Directory /workspace/49.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/490.usbdev_tx_rx_disruption.2942941444
Short name T2830
Test name
Test status
Simulation time 534010453 ps
CPU time 1.57 seconds
Started Aug 10 07:18:36 PM PDT 24
Finished Aug 10 07:18:38 PM PDT 24
Peak memory 207564 kb
Host smart-877e53ce-2e5e-4110-91e5-a6845d38ad58
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942941444 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 490.usbdev_tx_rx_disruption.2942941444
Directory /workspace/490.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/491.usbdev_tx_rx_disruption.96406287
Short name T2103
Test name
Test status
Simulation time 578641572 ps
CPU time 1.57 seconds
Started Aug 10 07:18:34 PM PDT 24
Finished Aug 10 07:18:36 PM PDT 24
Peak memory 207544 kb
Host smart-08c62c90-f0bd-462f-8557-9a62145c43b3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96406287 -assert nopostproc +UVM_TEST
NAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 491.usbdev_tx_rx_disruption.96406287
Directory /workspace/491.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/492.usbdev_tx_rx_disruption.2406789195
Short name T3513
Test name
Test status
Simulation time 476412178 ps
CPU time 1.48 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207556 kb
Host smart-41a2e885-43b6-4926-aa58-6fd4cc8a5b4c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406789195 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 492.usbdev_tx_rx_disruption.2406789195
Directory /workspace/492.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/493.usbdev_tx_rx_disruption.383957828
Short name T2543
Test name
Test status
Simulation time 471661808 ps
CPU time 1.45 seconds
Started Aug 10 07:18:35 PM PDT 24
Finished Aug 10 07:18:37 PM PDT 24
Peak memory 207548 kb
Host smart-f52a60df-d7ac-4e2a-b675-c6bd9126a140
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383957828 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 493.usbdev_tx_rx_disruption.383957828
Directory /workspace/493.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/494.usbdev_tx_rx_disruption.1669914976
Short name T1071
Test name
Test status
Simulation time 536302898 ps
CPU time 1.62 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 207524 kb
Host smart-c9075965-988b-47ac-8d28-fecd6f695aca
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669914976 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 494.usbdev_tx_rx_disruption.1669914976
Directory /workspace/494.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/495.usbdev_tx_rx_disruption.2338765899
Short name T2209
Test name
Test status
Simulation time 541158844 ps
CPU time 1.76 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:47 PM PDT 24
Peak memory 207504 kb
Host smart-726094b1-9902-4fd6-bfd9-3ec24558e97f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338765899 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 495.usbdev_tx_rx_disruption.2338765899
Directory /workspace/495.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/496.usbdev_tx_rx_disruption.1090895958
Short name T933
Test name
Test status
Simulation time 579927597 ps
CPU time 1.73 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 207552 kb
Host smart-5aa85c60-4178-4866-b957-0d6331eb10a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090895958 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 496.usbdev_tx_rx_disruption.1090895958
Directory /workspace/496.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/497.usbdev_tx_rx_disruption.1790571090
Short name T2936
Test name
Test status
Simulation time 481525939 ps
CPU time 1.5 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 207548 kb
Host smart-f4dc84a3-22f1-4882-ac4e-22bc94c4b6a4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790571090 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 497.usbdev_tx_rx_disruption.1790571090
Directory /workspace/497.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/498.usbdev_tx_rx_disruption.3889032252
Short name T2003
Test name
Test status
Simulation time 520977600 ps
CPU time 1.62 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 207584 kb
Host smart-cf8b13c8-099b-487d-9fee-9c0e59014a63
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889032252 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 498.usbdev_tx_rx_disruption.3889032252
Directory /workspace/498.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/499.usbdev_tx_rx_disruption.2371304547
Short name T1569
Test name
Test status
Simulation time 515695601 ps
CPU time 1.63 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 207556 kb
Host smart-f7287cab-0ba6-4aac-933d-603efc8d542f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371304547 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 499.usbdev_tx_rx_disruption.2371304547
Directory /workspace/499.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2941171545
Short name T1678
Test name
Test status
Simulation time 34983523 ps
CPU time 0.66 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:48 PM PDT 24
Peak memory 207544 kb
Host smart-daca9f80-c144-4bfb-ae50-180a0b5742e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2941171545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2941171545
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2019297541
Short name T282
Test name
Test status
Simulation time 20845429596 ps
CPU time 24.27 seconds
Started Aug 10 07:03:08 PM PDT 24
Finished Aug 10 07:03:32 PM PDT 24
Peak memory 207868 kb
Host smart-09fc91c5-90b8-407e-b0fc-95e40545a699
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019297541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2019297541
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.4141708581
Short name T3166
Test name
Test status
Simulation time 25720056826 ps
CPU time 33.05 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:42 PM PDT 24
Peak memory 216060 kb
Host smart-f3734608-0bf0-4043-8c76-a01d331106a8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141708581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.4141708581
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2532739698
Short name T3002
Test name
Test status
Simulation time 184156740 ps
CPU time 0.96 seconds
Started Aug 10 07:03:10 PM PDT 24
Finished Aug 10 07:03:11 PM PDT 24
Peak memory 207464 kb
Host smart-4735a4c1-3cbc-4617-99a8-8421e3134ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
39698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2532739698
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.840717291
Short name T708
Test name
Test status
Simulation time 172327821 ps
CPU time 0.87 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 207424 kb
Host smart-ac3afbf9-3c03-4c34-a4c6-f269ab44c348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84071
7291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.840717291
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.611708055
Short name T1364
Test name
Test status
Simulation time 351402532 ps
CPU time 1.26 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 207532 kb
Host smart-9c57eb7d-a320-40f9-82cd-464163c30833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61170
8055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.611708055
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1924339971
Short name T2538
Test name
Test status
Simulation time 388644498 ps
CPU time 1.23 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:10 PM PDT 24
Peak memory 207496 kb
Host smart-38604bf3-f524-4da5-9c61-d2b432c49696
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1924339971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1924339971
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.452216587
Short name T1675
Test name
Test status
Simulation time 39548925113 ps
CPU time 61.24 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:04:10 PM PDT 24
Peak memory 207832 kb
Host smart-c5f2183b-c295-4dfb-b473-e964e1194014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45221
6587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.452216587
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.2852314584
Short name T572
Test name
Test status
Simulation time 2940259754 ps
CPU time 19.17 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:29 PM PDT 24
Peak memory 207740 kb
Host smart-09c0e4d1-f87b-4a67-84e9-4123a13e2708
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852314584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2852314584
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.4245329269
Short name T1268
Test name
Test status
Simulation time 776239174 ps
CPU time 1.77 seconds
Started Aug 10 07:03:07 PM PDT 24
Finished Aug 10 07:03:09 PM PDT 24
Peak memory 207376 kb
Host smart-50f171b2-46cd-43e5-91ed-75ae56b3d0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
29269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.4245329269
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1711020783
Short name T2570
Test name
Test status
Simulation time 139235437 ps
CPU time 0.87 seconds
Started Aug 10 07:03:12 PM PDT 24
Finished Aug 10 07:03:12 PM PDT 24
Peak memory 207544 kb
Host smart-de1875b5-63f4-478f-8fea-1d0f19f7161e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17110
20783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1711020783
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1145938177
Short name T2195
Test name
Test status
Simulation time 31392511 ps
CPU time 0.7 seconds
Started Aug 10 07:03:08 PM PDT 24
Finished Aug 10 07:03:09 PM PDT 24
Peak memory 207484 kb
Host smart-0f179abb-2640-473f-91c2-11e6344ade9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
38177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1145938177
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.700028583
Short name T3242
Test name
Test status
Simulation time 843362444 ps
CPU time 2.24 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:11 PM PDT 24
Peak memory 207660 kb
Host smart-a4666756-58f5-4f64-bce6-8173bc37304d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70002
8583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.700028583
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_types.2399381738
Short name T382
Test name
Test status
Simulation time 440775250 ps
CPU time 1.3 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:03:11 PM PDT 24
Peak memory 207404 kb
Host smart-7cbff125-c780-459f-b00b-23002883aa63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2399381738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.2399381738
Directory /workspace/5.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2982100397
Short name T3358
Test name
Test status
Simulation time 160329652 ps
CPU time 1.52 seconds
Started Aug 10 07:03:17 PM PDT 24
Finished Aug 10 07:03:18 PM PDT 24
Peak memory 207652 kb
Host smart-a9ccf3f0-dde7-4d5e-a1c1-183d730947e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29821
00397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2982100397
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2411614991
Short name T3469
Test name
Test status
Simulation time 249555439 ps
CPU time 1.14 seconds
Started Aug 10 07:03:18 PM PDT 24
Finished Aug 10 07:03:19 PM PDT 24
Peak memory 216952 kb
Host smart-fc416a88-4a9e-401f-8d1e-ebc7fe5b1437
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2411614991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2411614991
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1126120031
Short name T1552
Test name
Test status
Simulation time 143965494 ps
CPU time 0.8 seconds
Started Aug 10 07:03:19 PM PDT 24
Finished Aug 10 07:03:19 PM PDT 24
Peak memory 207544 kb
Host smart-fe80ea07-2af1-4367-b091-60571bfc40f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11261
20031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1126120031
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3857352842
Short name T914
Test name
Test status
Simulation time 224208014 ps
CPU time 0.99 seconds
Started Aug 10 07:03:18 PM PDT 24
Finished Aug 10 07:03:19 PM PDT 24
Peak memory 207536 kb
Host smart-50259457-ce3e-41c1-bdc5-82f91db69fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
52842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3857352842
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3441664417
Short name T3578
Test name
Test status
Simulation time 4328512401 ps
CPU time 29.63 seconds
Started Aug 10 07:03:17 PM PDT 24
Finished Aug 10 07:03:47 PM PDT 24
Peak memory 218244 kb
Host smart-87b7f49f-0030-44d0-8bcd-4cf1815414a9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3441664417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3441664417
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3812472658
Short name T1438
Test name
Test status
Simulation time 13025027183 ps
CPU time 147.67 seconds
Started Aug 10 07:03:19 PM PDT 24
Finished Aug 10 07:05:46 PM PDT 24
Peak memory 207812 kb
Host smart-8af2c692-22c6-4a2d-968e-4b2447e36b72
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3812472658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3812472658
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2292812062
Short name T1461
Test name
Test status
Simulation time 216609787 ps
CPU time 0.92 seconds
Started Aug 10 07:03:17 PM PDT 24
Finished Aug 10 07:03:19 PM PDT 24
Peak memory 207604 kb
Host smart-6c2dde57-5001-48af-82c4-c18ce48bc21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
12062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2292812062
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2630791637
Short name T898
Test name
Test status
Simulation time 9628888305 ps
CPU time 11.97 seconds
Started Aug 10 07:03:18 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 207904 kb
Host smart-ed3f8125-706d-4da3-b158-4b40beaaeda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
91637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2630791637
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.4288117620
Short name T2220
Test name
Test status
Simulation time 3039264853 ps
CPU time 89.91 seconds
Started Aug 10 07:03:17 PM PDT 24
Finished Aug 10 07:04:47 PM PDT 24
Peak memory 218656 kb
Host smart-4a7ab344-13b2-4c8d-ae83-569a36536d53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4288117620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.4288117620
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2792543269
Short name T1021
Test name
Test status
Simulation time 2843122216 ps
CPU time 83.94 seconds
Started Aug 10 07:03:26 PM PDT 24
Finished Aug 10 07:04:50 PM PDT 24
Peak memory 217500 kb
Host smart-1101dd2b-75e1-4e59-99db-e33b0a2c8101
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2792543269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2792543269
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.1154955487
Short name T2631
Test name
Test status
Simulation time 238429902 ps
CPU time 1.04 seconds
Started Aug 10 07:03:26 PM PDT 24
Finished Aug 10 07:03:27 PM PDT 24
Peak memory 207560 kb
Host smart-ec639195-017e-446f-b485-1058b86047c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1154955487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.1154955487
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3880997181
Short name T610
Test name
Test status
Simulation time 191004468 ps
CPU time 0.95 seconds
Started Aug 10 07:03:28 PM PDT 24
Finished Aug 10 07:03:29 PM PDT 24
Peak memory 207580 kb
Host smart-5c6de4dd-5e6c-433b-86f7-c0f7b1222e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
97181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3880997181
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.1402940842
Short name T1088
Test name
Test status
Simulation time 1874993404 ps
CPU time 15.3 seconds
Started Aug 10 07:03:29 PM PDT 24
Finished Aug 10 07:03:44 PM PDT 24
Peak memory 217148 kb
Host smart-efa7b23a-3f37-42bc-838f-7ba9e6dd4c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14029
40842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.1402940842
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3963778905
Short name T3394
Test name
Test status
Simulation time 1760708381 ps
CPU time 48.73 seconds
Started Aug 10 07:03:29 PM PDT 24
Finished Aug 10 07:04:18 PM PDT 24
Peak memory 217576 kb
Host smart-c290d637-f74a-4104-85f4-379e5d05eb48
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3963778905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3963778905
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.166108668
Short name T730
Test name
Test status
Simulation time 1976107583 ps
CPU time 54.8 seconds
Started Aug 10 07:03:26 PM PDT 24
Finished Aug 10 07:04:21 PM PDT 24
Peak memory 215964 kb
Host smart-c557c27c-d0a7-4f1f-a9fe-c2928b98f709
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=166108668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.166108668
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.826061950
Short name T2373
Test name
Test status
Simulation time 151246547 ps
CPU time 0.88 seconds
Started Aug 10 07:03:27 PM PDT 24
Finished Aug 10 07:03:28 PM PDT 24
Peak memory 207580 kb
Host smart-b0971a2d-2a26-4ede-b2a1-285c6bce92b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=826061950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.826061950
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2749712889
Short name T3351
Test name
Test status
Simulation time 140034724 ps
CPU time 0.88 seconds
Started Aug 10 07:03:28 PM PDT 24
Finished Aug 10 07:03:29 PM PDT 24
Peak memory 207508 kb
Host smart-9d67d623-1096-4fd0-a706-54f77bc713f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497
12889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2749712889
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2882848053
Short name T2171
Test name
Test status
Simulation time 205335442 ps
CPU time 0.99 seconds
Started Aug 10 07:03:28 PM PDT 24
Finished Aug 10 07:03:29 PM PDT 24
Peak memory 207492 kb
Host smart-08fb7db0-8d0f-4071-a43a-02dcf8579a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
48053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2882848053
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2394982915
Short name T2111
Test name
Test status
Simulation time 213812009 ps
CPU time 0.93 seconds
Started Aug 10 07:03:29 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 207536 kb
Host smart-5f13c0ed-2214-424a-a1ef-2379ea8ea97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
82915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2394982915
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.765715672
Short name T1192
Test name
Test status
Simulation time 181129275 ps
CPU time 0.9 seconds
Started Aug 10 07:03:29 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 207396 kb
Host smart-4dfb08ce-338f-4f87-9a47-f49eb758f4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76571
5672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.765715672
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.474021181
Short name T3146
Test name
Test status
Simulation time 193590346 ps
CPU time 0.89 seconds
Started Aug 10 07:03:29 PM PDT 24
Finished Aug 10 07:03:30 PM PDT 24
Peak memory 207420 kb
Host smart-e01ec8e9-404b-4fbd-959f-d250b71a08bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47402
1181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.474021181
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3195276956
Short name T3098
Test name
Test status
Simulation time 153851086 ps
CPU time 0.85 seconds
Started Aug 10 07:03:27 PM PDT 24
Finished Aug 10 07:03:28 PM PDT 24
Peak memory 207504 kb
Host smart-0aa3f485-4927-4cff-9ec3-c7d3f3a00c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31952
76956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3195276956
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.927394942
Short name T1311
Test name
Test status
Simulation time 300428299 ps
CPU time 1.13 seconds
Started Aug 10 07:03:40 PM PDT 24
Finished Aug 10 07:03:41 PM PDT 24
Peak memory 207576 kb
Host smart-8b45b56e-2a6c-455a-a1c6-a08eea4e4fc7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=927394942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.927394942
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2473204815
Short name T1901
Test name
Test status
Simulation time 156295612 ps
CPU time 0.85 seconds
Started Aug 10 07:03:38 PM PDT 24
Finished Aug 10 07:03:39 PM PDT 24
Peak memory 207504 kb
Host smart-b34a5579-2b18-45c3-bbc7-23abfe32d77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
04815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2473204815
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1508086074
Short name T2563
Test name
Test status
Simulation time 37179025 ps
CPU time 0.67 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:38 PM PDT 24
Peak memory 207512 kb
Host smart-05c02830-61b8-469d-838c-8096fdf6bade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
86074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1508086074
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2907799484
Short name T1234
Test name
Test status
Simulation time 21852720609 ps
CPU time 52.08 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:04:30 PM PDT 24
Peak memory 216008 kb
Host smart-4446495e-f71d-41e2-ac29-fc8db32ea6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
99484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2907799484
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3587425874
Short name T3252
Test name
Test status
Simulation time 141009193 ps
CPU time 0.8 seconds
Started Aug 10 07:03:36 PM PDT 24
Finished Aug 10 07:03:37 PM PDT 24
Peak memory 207548 kb
Host smart-b32e979d-37cf-402e-a043-2c793b465ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
25874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3587425874
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3888470418
Short name T1617
Test name
Test status
Simulation time 199199189 ps
CPU time 0.9 seconds
Started Aug 10 07:03:36 PM PDT 24
Finished Aug 10 07:03:37 PM PDT 24
Peak memory 207524 kb
Host smart-5732f3b3-c9ad-4306-b76f-d4775caf9b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38884
70418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3888470418
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2904210103
Short name T1468
Test name
Test status
Simulation time 3517931414 ps
CPU time 73.53 seconds
Started Aug 10 07:03:36 PM PDT 24
Finished Aug 10 07:04:50 PM PDT 24
Peak memory 218524 kb
Host smart-bd9847ba-dda1-497d-81c6-230875ca68ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904210103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2904210103
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.1866131522
Short name T3603
Test name
Test status
Simulation time 7434773036 ps
CPU time 50.36 seconds
Started Aug 10 07:03:36 PM PDT 24
Finished Aug 10 07:04:26 PM PDT 24
Peak memory 216036 kb
Host smart-6e706132-fb0f-4fd1-bcc1-e0afbb38847a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1866131522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.1866131522
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1713815566
Short name T2572
Test name
Test status
Simulation time 13933398242 ps
CPU time 310.78 seconds
Started Aug 10 07:03:39 PM PDT 24
Finished Aug 10 07:08:49 PM PDT 24
Peak memory 224176 kb
Host smart-ce068ca0-8286-46ad-ae84-87d96228c30f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713815566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1713815566
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3514117681
Short name T997
Test name
Test status
Simulation time 228962769 ps
CPU time 1 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:38 PM PDT 24
Peak memory 207584 kb
Host smart-f5b639eb-c4a0-4b9c-af7f-ddbd62c2ea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35141
17681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3514117681
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3759899445
Short name T906
Test name
Test status
Simulation time 153383035 ps
CPU time 0.87 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:38 PM PDT 24
Peak memory 207604 kb
Host smart-849c3e1a-6278-45ea-aa0b-d21544b1c4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37598
99445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3759899445
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_resume_link_active.3791680457
Short name T101
Test name
Test status
Simulation time 20169630155 ps
CPU time 27.65 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:04:05 PM PDT 24
Peak memory 207576 kb
Host smart-fd3d4332-c38a-47e6-85da-677009486ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
80457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_resume_link_active.3791680457
Directory /workspace/5.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2012082220
Short name T2064
Test name
Test status
Simulation time 164054231 ps
CPU time 0.83 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:38 PM PDT 24
Peak memory 207576 kb
Host smart-090d83a5-db43-443e-bc7b-d9e225aee0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
82220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2012082220
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_rx_full.1373953016
Short name T2568
Test name
Test status
Simulation time 344847918 ps
CPU time 1.19 seconds
Started Aug 10 07:03:36 PM PDT 24
Finished Aug 10 07:03:37 PM PDT 24
Peak memory 207544 kb
Host smart-7212270d-50d1-45f1-8704-4f8f6715c807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13739
53016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.1373953016
Directory /workspace/5.usbdev_rx_full/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.863253712
Short name T596
Test name
Test status
Simulation time 181301012 ps
CPU time 0.9 seconds
Started Aug 10 07:03:39 PM PDT 24
Finished Aug 10 07:03:40 PM PDT 24
Peak memory 207536 kb
Host smart-29c43de4-0d35-4084-822d-bb82090ff32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86325
3712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.863253712
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3371156263
Short name T1462
Test name
Test status
Simulation time 197623656 ps
CPU time 0.95 seconds
Started Aug 10 07:03:39 PM PDT 24
Finished Aug 10 07:03:41 PM PDT 24
Peak memory 207572 kb
Host smart-898b0476-f1b2-44e5-a487-4ac79b61b0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33711
56263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3371156263
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.4065310246
Short name T1705
Test name
Test status
Simulation time 201188405 ps
CPU time 0.97 seconds
Started Aug 10 07:03:39 PM PDT 24
Finished Aug 10 07:03:40 PM PDT 24
Peak memory 207504 kb
Host smart-f9ae4db2-95ed-4838-8bbb-d16b3babf611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
10246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4065310246
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1602367114
Short name T734
Test name
Test status
Simulation time 1691763784 ps
CPU time 15.39 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:52 PM PDT 24
Peak memory 224104 kb
Host smart-d8828961-5318-4762-abfd-7c1f18cb1bf9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1602367114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1602367114
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2714250750
Short name T3182
Test name
Test status
Simulation time 173545869 ps
CPU time 0.88 seconds
Started Aug 10 07:03:37 PM PDT 24
Finished Aug 10 07:03:38 PM PDT 24
Peak memory 207528 kb
Host smart-97fb513c-4b4d-417c-9cb9-d080ea00c549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
50750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2714250750
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3710260941
Short name T822
Test name
Test status
Simulation time 188983040 ps
CPU time 0.91 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:48 PM PDT 24
Peak memory 207532 kb
Host smart-465a01bb-a6e0-43ae-9634-0f46f4123931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
60941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3710260941
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2985976407
Short name T3323
Test name
Test status
Simulation time 1114632823 ps
CPU time 2.72 seconds
Started Aug 10 07:03:48 PM PDT 24
Finished Aug 10 07:03:51 PM PDT 24
Peak memory 207700 kb
Host smart-ff94ff84-c45e-4e29-9de1-826a5c984356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859
76407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2985976407
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1537166813
Short name T1204
Test name
Test status
Simulation time 3014153339 ps
CPU time 24.61 seconds
Started Aug 10 07:03:48 PM PDT 24
Finished Aug 10 07:04:12 PM PDT 24
Peak memory 207836 kb
Host smart-604ff7a8-c223-4575-af35-e50a274238ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
66813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1537166813
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.2433771871
Short name T3514
Test name
Test status
Simulation time 9113682118 ps
CPU time 60.14 seconds
Started Aug 10 07:03:09 PM PDT 24
Finished Aug 10 07:04:09 PM PDT 24
Peak memory 207804 kb
Host smart-5686eed5-e724-4dec-bf6f-afa1963b8e6e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433771871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.2433771871
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_tx_rx_disruption.3000263934
Short name T751
Test name
Test status
Simulation time 609439677 ps
CPU time 1.65 seconds
Started Aug 10 07:03:49 PM PDT 24
Finished Aug 10 07:03:51 PM PDT 24
Peak memory 206712 kb
Host smart-5f2b3ce3-7b0f-4a40-8060-abefa03281a5
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000263934 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.usbdev_tx_rx_disruption.3000263934
Directory /workspace/5.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/50.usbdev_endpoint_types.4166967446
Short name T435
Test name
Test status
Simulation time 351277748 ps
CPU time 1.2 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207572 kb
Host smart-d227f85b-efb4-4ebf-86d4-794466122ad1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4166967446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.4166967446
Directory /workspace/50.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/50.usbdev_tx_rx_disruption.3152953750
Short name T196
Test name
Test status
Simulation time 464418655 ps
CPU time 1.43 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207568 kb
Host smart-b4818b46-d3ad-4e80-9af0-2c1de387ff36
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152953750 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.usbdev_tx_rx_disruption.3152953750
Directory /workspace/50.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/51.usbdev_endpoint_types.3709548702
Short name T439
Test name
Test status
Simulation time 528235694 ps
CPU time 1.51 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207404 kb
Host smart-c68e514f-f949-44cf-a642-68e7abc43dbb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3709548702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.3709548702
Directory /workspace/51.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/51.usbdev_tx_rx_disruption.2476927183
Short name T2401
Test name
Test status
Simulation time 595226547 ps
CPU time 1.63 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207572 kb
Host smart-1d5706a5-aa0b-437b-a532-d3a3d03526de
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476927183 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.usbdev_tx_rx_disruption.2476927183
Directory /workspace/51.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/52.usbdev_endpoint_types.121719491
Short name T427
Test name
Test status
Simulation time 324852035 ps
CPU time 1.21 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207504 kb
Host smart-1b414ec5-9052-40fa-915f-14892576fb38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=121719491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.121719491
Directory /workspace/52.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/52.usbdev_tx_rx_disruption.4196548402
Short name T937
Test name
Test status
Simulation time 477666635 ps
CPU time 1.54 seconds
Started Aug 10 07:16:51 PM PDT 24
Finished Aug 10 07:16:52 PM PDT 24
Peak memory 207468 kb
Host smart-1d2ed6e9-0ac2-462a-8ec0-a9749f59b7a9
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196548402 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.usbdev_tx_rx_disruption.4196548402
Directory /workspace/52.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/53.usbdev_endpoint_types.3230687783
Short name T398
Test name
Test status
Simulation time 383077018 ps
CPU time 1.25 seconds
Started Aug 10 07:16:51 PM PDT 24
Finished Aug 10 07:16:52 PM PDT 24
Peak memory 207452 kb
Host smart-4699c08d-1a9e-4937-93c8-78719aa37529
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3230687783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.3230687783
Directory /workspace/53.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/53.usbdev_tx_rx_disruption.3543113020
Short name T211
Test name
Test status
Simulation time 617046383 ps
CPU time 1.71 seconds
Started Aug 10 07:16:52 PM PDT 24
Finished Aug 10 07:16:54 PM PDT 24
Peak memory 207604 kb
Host smart-dc0dce2e-3377-4814-a339-26cdf72bfc9d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543113020 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.usbdev_tx_rx_disruption.3543113020
Directory /workspace/53.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/54.usbdev_endpoint_types.1375043219
Short name T3516
Test name
Test status
Simulation time 486521430 ps
CPU time 1.52 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207436 kb
Host smart-8c449885-6a0d-437c-aa16-f01a4af086dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1375043219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.1375043219
Directory /workspace/54.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/54.usbdev_tx_rx_disruption.1337788857
Short name T615
Test name
Test status
Simulation time 595479832 ps
CPU time 1.64 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207540 kb
Host smart-0a8b5e8c-3e74-4d68-9d4c-f02bbd65950b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337788857 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.usbdev_tx_rx_disruption.1337788857
Directory /workspace/54.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/55.usbdev_endpoint_types.2660112628
Short name T410
Test name
Test status
Simulation time 288315551 ps
CPU time 1.15 seconds
Started Aug 10 07:16:53 PM PDT 24
Finished Aug 10 07:16:54 PM PDT 24
Peak memory 207568 kb
Host smart-b09409c9-7379-4852-b54e-c52df184c576
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2660112628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.2660112628
Directory /workspace/55.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/55.usbdev_tx_rx_disruption.3283603629
Short name T1671
Test name
Test status
Simulation time 694771444 ps
CPU time 1.73 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207560 kb
Host smart-945cc302-13ca-42b3-9bcf-32704529831e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283603629 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.usbdev_tx_rx_disruption.3283603629
Directory /workspace/55.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/56.usbdev_tx_rx_disruption.3131903784
Short name T1200
Test name
Test status
Simulation time 634274286 ps
CPU time 1.61 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207520 kb
Host smart-ad6f6ab2-f687-49de-867c-cf1a51cf49a3
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131903784 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.usbdev_tx_rx_disruption.3131903784
Directory /workspace/56.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/57.usbdev_endpoint_types.495432286
Short name T440
Test name
Test status
Simulation time 591105391 ps
CPU time 1.5 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:47 PM PDT 24
Peak memory 207516 kb
Host smart-2045bb6d-8083-4b2f-8816-e12f6b284016
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=495432286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.495432286
Directory /workspace/57.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/57.usbdev_tx_rx_disruption.1487748394
Short name T2301
Test name
Test status
Simulation time 625049293 ps
CPU time 1.6 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207504 kb
Host smart-454f474a-6ccf-4730-b832-f9ca3caaf610
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487748394 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.usbdev_tx_rx_disruption.1487748394
Directory /workspace/57.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/58.usbdev_endpoint_types.823020488
Short name T308
Test name
Test status
Simulation time 556291486 ps
CPU time 1.45 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207520 kb
Host smart-7ea093c7-a956-4de7-a3dd-6a50812f8c71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=823020488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.823020488
Directory /workspace/58.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/58.usbdev_tx_rx_disruption.711427613
Short name T3277
Test name
Test status
Simulation time 587889822 ps
CPU time 1.74 seconds
Started Aug 10 07:16:46 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207564 kb
Host smart-96578218-c3a7-4e6c-af1c-25e67066f23a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711427613 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.usbdev_tx_rx_disruption.711427613
Directory /workspace/58.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/59.usbdev_endpoint_types.1734232415
Short name T2919
Test name
Test status
Simulation time 228695058 ps
CPU time 1 seconds
Started Aug 10 07:16:47 PM PDT 24
Finished Aug 10 07:16:48 PM PDT 24
Peak memory 207528 kb
Host smart-6b565b29-6ca4-4b7c-a801-232b75146ecc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1734232415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.1734232415
Directory /workspace/59.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/59.usbdev_tx_rx_disruption.493652409
Short name T2289
Test name
Test status
Simulation time 553082200 ps
CPU time 1.59 seconds
Started Aug 10 07:16:48 PM PDT 24
Finished Aug 10 07:16:49 PM PDT 24
Peak memory 207548 kb
Host smart-ce1fdf88-7f40-4b7f-a34d-8e7ca1f19840
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493652409 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.usbdev_tx_rx_disruption.493652409
Directory /workspace/59.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.2235457622
Short name T3509
Test name
Test status
Simulation time 31623202 ps
CPU time 0.65 seconds
Started Aug 10 07:04:28 PM PDT 24
Finished Aug 10 07:04:28 PM PDT 24
Peak memory 207524 kb
Host smart-e6e24127-7f3b-4e3b-a92e-24ebf90bc226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2235457622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2235457622
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.2619925599
Short name T1315
Test name
Test status
Simulation time 4620898856 ps
CPU time 7.23 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:55 PM PDT 24
Peak memory 216048 kb
Host smart-fb02460d-7497-425a-9665-4c80a009dc31
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619925599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.2619925599
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1582033635
Short name T1745
Test name
Test status
Simulation time 14586635273 ps
CPU time 18.53 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 215996 kb
Host smart-a60d4d9a-7734-4023-8fb3-3493e43bcb3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582033635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1582033635
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.53123718
Short name T2478
Test name
Test status
Simulation time 29888161872 ps
CPU time 37.09 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 207796 kb
Host smart-d2093ae7-2e3b-4540-bef2-6e7a87b7c170
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53123718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_
wake_resume.53123718
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2441974564
Short name T2252
Test name
Test status
Simulation time 175762741 ps
CPU time 0.87 seconds
Started Aug 10 07:03:46 PM PDT 24
Finished Aug 10 07:03:47 PM PDT 24
Peak memory 207544 kb
Host smart-a40e0cc2-0e29-40a8-a498-d26a153acf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
74564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2441974564
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.67935044
Short name T1915
Test name
Test status
Simulation time 161425458 ps
CPU time 0.85 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:48 PM PDT 24
Peak memory 207512 kb
Host smart-75a2e61e-fa05-4ccc-ace7-5e51e379a587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67935
044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.67935044
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2811392513
Short name T2709
Test name
Test status
Simulation time 360529046 ps
CPU time 1.29 seconds
Started Aug 10 07:03:49 PM PDT 24
Finished Aug 10 07:03:51 PM PDT 24
Peak memory 206656 kb
Host smart-ae46adf8-6904-44c2-ac54-7f4385916038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28113
92513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2811392513
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2507739312
Short name T363
Test name
Test status
Simulation time 1031745799 ps
CPU time 2.5 seconds
Started Aug 10 07:03:48 PM PDT 24
Finished Aug 10 07:03:51 PM PDT 24
Peak memory 207572 kb
Host smart-11abb0f5-68a9-49b7-add5-c1db4e800248
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2507739312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2507739312
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3794654130
Short name T182
Test name
Test status
Simulation time 46896598870 ps
CPU time 81.46 seconds
Started Aug 10 07:03:48 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207868 kb
Host smart-dd5ce7c4-e213-4486-b801-b06af66b8222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37946
54130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3794654130
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.1553872066
Short name T1106
Test name
Test status
Simulation time 181991951 ps
CPU time 0.9 seconds
Started Aug 10 07:03:48 PM PDT 24
Finished Aug 10 07:03:49 PM PDT 24
Peak memory 207444 kb
Host smart-6c0f62ac-289e-458e-bc5d-770c938ae9d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553872066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1553872066
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1509694552
Short name T1667
Test name
Test status
Simulation time 722578548 ps
CPU time 1.76 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:49 PM PDT 24
Peak memory 207480 kb
Host smart-0b1fab7e-a6dc-448c-88b3-4ce1cd823252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
94552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1509694552
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2709215741
Short name T2897
Test name
Test status
Simulation time 158261719 ps
CPU time 0.87 seconds
Started Aug 10 07:03:47 PM PDT 24
Finished Aug 10 07:03:48 PM PDT 24
Peak memory 207384 kb
Host smart-21881244-0772-4d1b-a0d7-d0d3b83d9495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
15741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2709215741
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.711823255
Short name T3495
Test name
Test status
Simulation time 41044483 ps
CPU time 0.69 seconds
Started Aug 10 07:04:00 PM PDT 24
Finished Aug 10 07:04:01 PM PDT 24
Peak memory 207528 kb
Host smart-2e87db0c-fff9-4981-bd4e-aa3618dafc83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71182
3255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.711823255
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3089951521
Short name T1729
Test name
Test status
Simulation time 978239845 ps
CPU time 2.56 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:03:58 PM PDT 24
Peak memory 207820 kb
Host smart-be7f68bd-f8b4-42fb-84f5-7bd3b3fa16f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30899
51521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3089951521
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_types.429733347
Short name T449
Test name
Test status
Simulation time 620282802 ps
CPU time 1.52 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:03:58 PM PDT 24
Peak memory 207500 kb
Host smart-164de89f-35db-4d07-a960-1fbf18a8641b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=429733347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.429733347
Directory /workspace/6.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.331538490
Short name T229
Test name
Test status
Simulation time 309832018 ps
CPU time 2.64 seconds
Started Aug 10 07:04:00 PM PDT 24
Finished Aug 10 07:04:02 PM PDT 24
Peak memory 207708 kb
Host smart-51bd9823-776d-4805-be1e-eec4653bab2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33153
8490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.331538490
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.933319141
Short name T2001
Test name
Test status
Simulation time 202363388 ps
CPU time 1.05 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:03:57 PM PDT 24
Peak memory 215860 kb
Host smart-65192173-3afe-4400-bf23-841cd0f1914a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=933319141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.933319141
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.4080400867
Short name T1975
Test name
Test status
Simulation time 155833127 ps
CPU time 0.91 seconds
Started Aug 10 07:03:58 PM PDT 24
Finished Aug 10 07:03:59 PM PDT 24
Peak memory 207508 kb
Host smart-71e472d2-1cb6-4ceb-abcd-4b78ec3fbb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40804
00867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.4080400867
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.4022021658
Short name T613
Test name
Test status
Simulation time 171808463 ps
CPU time 0.83 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:03:57 PM PDT 24
Peak memory 207560 kb
Host smart-17bbffa3-dd2e-410a-bc18-f54f08857241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40220
21658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.4022021658
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1924487668
Short name T1584
Test name
Test status
Simulation time 3251519281 ps
CPU time 26.51 seconds
Started Aug 10 07:03:58 PM PDT 24
Finished Aug 10 07:04:25 PM PDT 24
Peak memory 218156 kb
Host smart-15ac6d8b-ddbe-4405-98b2-4e1d7b11dcd6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1924487668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1924487668
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.3529889998
Short name T2197
Test name
Test status
Simulation time 10722758242 ps
CPU time 124.17 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:06:00 PM PDT 24
Peak memory 207832 kb
Host smart-e30748a1-162f-4ac0-b40d-d29ecc70807c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3529889998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.3529889998
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.514887491
Short name T713
Test name
Test status
Simulation time 256074782 ps
CPU time 1.13 seconds
Started Aug 10 07:03:58 PM PDT 24
Finished Aug 10 07:03:59 PM PDT 24
Peak memory 207536 kb
Host smart-24ae41ef-0153-4329-a1ed-fe2f5c87e82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51488
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.514887491
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.748707880
Short name T2980
Test name
Test status
Simulation time 6666076262 ps
CPU time 11.7 seconds
Started Aug 10 07:03:55 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 216132 kb
Host smart-91ccb3c3-689b-48fc-8c71-fb3e1c43cf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74870
7880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.748707880
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3650662621
Short name T3235
Test name
Test status
Simulation time 3635201029 ps
CPU time 5.64 seconds
Started Aug 10 07:03:54 PM PDT 24
Finished Aug 10 07:04:00 PM PDT 24
Peak memory 216020 kb
Host smart-4a12957c-dece-4ba4-ab56-c09f52579a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506
62621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3650662621
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1243836007
Short name T1370
Test name
Test status
Simulation time 2246896242 ps
CPU time 22.55 seconds
Started Aug 10 07:03:55 PM PDT 24
Finished Aug 10 07:04:18 PM PDT 24
Peak memory 218732 kb
Host smart-e1b488d6-559b-4598-8a6e-355eb97f1fa5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1243836007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1243836007
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1855213461
Short name T1518
Test name
Test status
Simulation time 2742225815 ps
CPU time 25.16 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:04:21 PM PDT 24
Peak memory 215964 kb
Host smart-9d80a445-9f9a-4573-8db3-60500905c53e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1855213461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1855213461
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2124412062
Short name T3173
Test name
Test status
Simulation time 283003728 ps
CPU time 0.97 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:03:57 PM PDT 24
Peak memory 207568 kb
Host smart-7dc3543e-0dcf-4252-b003-75c97a249f32
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2124412062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2124412062
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1508622617
Short name T1932
Test name
Test status
Simulation time 199199329 ps
CPU time 0.92 seconds
Started Aug 10 07:03:55 PM PDT 24
Finished Aug 10 07:03:56 PM PDT 24
Peak memory 207516 kb
Host smart-9230da7a-6e55-40de-ba41-31164b3a7255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
22617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1508622617
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.2002313475
Short name T2250
Test name
Test status
Simulation time 1831935060 ps
CPU time 14.35 seconds
Started Aug 10 07:03:56 PM PDT 24
Finished Aug 10 07:04:10 PM PDT 24
Peak memory 217700 kb
Host smart-0b35170c-0fdd-4c72-8838-b4b8dc34bb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20023
13475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.2002313475
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.13461067
Short name T2391
Test name
Test status
Simulation time 2287922626 ps
CPU time 65.67 seconds
Started Aug 10 07:03:55 PM PDT 24
Finished Aug 10 07:05:01 PM PDT 24
Peak memory 216120 kb
Host smart-f3e8d663-580c-43d6-87ce-98d39d00ba63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=13461067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.13461067
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.658413483
Short name T2718
Test name
Test status
Simulation time 2788279794 ps
CPU time 27.01 seconds
Started Aug 10 07:03:59 PM PDT 24
Finished Aug 10 07:04:26 PM PDT 24
Peak memory 217780 kb
Host smart-a51adef1-f883-4270-8563-d21f42a1b608
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=658413483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.658413483
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3863022908
Short name T2201
Test name
Test status
Simulation time 157834061 ps
CPU time 0.88 seconds
Started Aug 10 07:04:00 PM PDT 24
Finished Aug 10 07:04:01 PM PDT 24
Peak memory 207560 kb
Host smart-a3754723-d0d6-42e1-8780-90ea1a49f1ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3863022908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3863022908
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2130436322
Short name T3580
Test name
Test status
Simulation time 152540794 ps
CPU time 0.82 seconds
Started Aug 10 07:04:06 PM PDT 24
Finished Aug 10 07:04:07 PM PDT 24
Peak memory 207608 kb
Host smart-adecedee-f974-4e1d-a44e-1e431b7d0b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
36322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2130436322
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1335362181
Short name T146
Test name
Test status
Simulation time 200973930 ps
CPU time 0.94 seconds
Started Aug 10 07:04:06 PM PDT 24
Finished Aug 10 07:04:07 PM PDT 24
Peak memory 207584 kb
Host smart-06a5e1a3-bbd4-48fb-9109-af46410b5dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13353
62181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1335362181
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.4200763496
Short name T968
Test name
Test status
Simulation time 147301640 ps
CPU time 0.86 seconds
Started Aug 10 07:04:04 PM PDT 24
Finished Aug 10 07:04:05 PM PDT 24
Peak memory 207512 kb
Host smart-e8be55a0-f810-47c7-9855-7c5505e1cffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42007
63496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.4200763496
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4155830263
Short name T1541
Test name
Test status
Simulation time 230388114 ps
CPU time 0.95 seconds
Started Aug 10 07:04:03 PM PDT 24
Finished Aug 10 07:04:04 PM PDT 24
Peak memory 207496 kb
Host smart-17cb002e-8c25-4b76-bff9-b04f04e82944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41558
30263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4155830263
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3563242127
Short name T1183
Test name
Test status
Simulation time 226451269 ps
CPU time 0.89 seconds
Started Aug 10 07:04:05 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 207560 kb
Host smart-f3f93ed1-d028-4954-bf03-9b1b8d589065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
42127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3563242127
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2979675305
Short name T1506
Test name
Test status
Simulation time 149332208 ps
CPU time 0.85 seconds
Started Aug 10 07:04:03 PM PDT 24
Finished Aug 10 07:04:04 PM PDT 24
Peak memory 207584 kb
Host smart-888c6231-fd82-47cc-b0aa-35310f31a089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
75305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2979675305
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1872450569
Short name T2673
Test name
Test status
Simulation time 225408577 ps
CPU time 0.98 seconds
Started Aug 10 07:04:04 PM PDT 24
Finished Aug 10 07:04:06 PM PDT 24
Peak memory 207500 kb
Host smart-a15e1534-d854-4831-9d75-f35e0bf5734b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1872450569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1872450569
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.292510706
Short name T1280
Test name
Test status
Simulation time 184957865 ps
CPU time 0.87 seconds
Started Aug 10 07:04:07 PM PDT 24
Finished Aug 10 07:04:08 PM PDT 24
Peak memory 207392 kb
Host smart-d7148f04-599f-4ac2-a135-e215901a4e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
0706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.292510706
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2234607188
Short name T1316
Test name
Test status
Simulation time 39318974 ps
CPU time 0.68 seconds
Started Aug 10 07:04:11 PM PDT 24
Finished Aug 10 07:04:12 PM PDT 24
Peak memory 207492 kb
Host smart-6460c62e-13a7-41c1-93ef-6fff90506199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346
07188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2234607188
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.751445599
Short name T2917
Test name
Test status
Simulation time 12234277465 ps
CPU time 29.48 seconds
Started Aug 10 07:04:11 PM PDT 24
Finished Aug 10 07:04:41 PM PDT 24
Peak memory 216088 kb
Host smart-b2abbaa9-8bdc-4495-bf04-ac09de4ca88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75144
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.751445599
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3795716914
Short name T2650
Test name
Test status
Simulation time 207817158 ps
CPU time 0.97 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:15 PM PDT 24
Peak memory 207524 kb
Host smart-625b07f8-efb0-4ff7-a463-0633f17cbabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
16914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3795716914
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2556034243
Short name T3254
Test name
Test status
Simulation time 171784245 ps
CPU time 0.95 seconds
Started Aug 10 07:04:15 PM PDT 24
Finished Aug 10 07:04:16 PM PDT 24
Peak memory 207516 kb
Host smart-e86403ed-2089-4c85-9f4a-a9f7d3d6f2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25560
34243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2556034243
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3668562234
Short name T3370
Test name
Test status
Simulation time 3721792394 ps
CPU time 38.51 seconds
Started Aug 10 07:04:15 PM PDT 24
Finished Aug 10 07:04:53 PM PDT 24
Peak memory 218460 kb
Host smart-791bb8ae-7635-4c2e-b5b3-5944348291d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668562234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3668562234
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.109276842
Short name T915
Test name
Test status
Simulation time 4033122815 ps
CPU time 26.18 seconds
Started Aug 10 07:04:12 PM PDT 24
Finished Aug 10 07:04:39 PM PDT 24
Peak memory 224332 kb
Host smart-af0b63f9-a3c2-4af7-a07f-49bc54f041db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=109276842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.109276842
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3526242268
Short name T617
Test name
Test status
Simulation time 6730973203 ps
CPU time 34.63 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:48 PM PDT 24
Peak memory 219024 kb
Host smart-4de8ebdd-f8b7-4c76-927f-a0a639ca31e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526242268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3526242268
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2398401844
Short name T3591
Test name
Test status
Simulation time 164682760 ps
CPU time 0.86 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:14 PM PDT 24
Peak memory 207608 kb
Host smart-39fca9f0-4510-45be-8271-f8d4dcfe7b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23984
01844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2398401844
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1836932059
Short name T3398
Test name
Test status
Simulation time 193344835 ps
CPU time 0.93 seconds
Started Aug 10 07:04:15 PM PDT 24
Finished Aug 10 07:04:16 PM PDT 24
Peak memory 207532 kb
Host smart-d32bc985-d70c-4a1a-9f40-926c75b5bd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18369
32059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1836932059
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_resume_link_active.3185017479
Short name T1197
Test name
Test status
Simulation time 20172927296 ps
CPU time 24.42 seconds
Started Aug 10 07:04:14 PM PDT 24
Finished Aug 10 07:04:38 PM PDT 24
Peak memory 207608 kb
Host smart-41db9959-ab9b-41ad-a6de-63c3b423529d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
17479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_resume_link_active.3185017479
Directory /workspace/6.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1589051139
Short name T1041
Test name
Test status
Simulation time 176379384 ps
CPU time 0.91 seconds
Started Aug 10 07:04:15 PM PDT 24
Finished Aug 10 07:04:16 PM PDT 24
Peak memory 207528 kb
Host smart-c81779a1-e9f3-4f0c-8d93-d88b41d5877f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
51139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1589051139
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_rx_full.1917798984
Short name T2063
Test name
Test status
Simulation time 299424874 ps
CPU time 1.13 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:14 PM PDT 24
Peak memory 207520 kb
Host smart-68df87a7-d1bf-4a01-a4f9-402787daaedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19177
98984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.1917798984
Directory /workspace/6.usbdev_rx_full/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.415900737
Short name T1423
Test name
Test status
Simulation time 160368972 ps
CPU time 0.84 seconds
Started Aug 10 07:04:12 PM PDT 24
Finished Aug 10 07:04:13 PM PDT 24
Peak memory 207492 kb
Host smart-6bad3a25-cac8-453f-90cb-a46123804c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41590
0737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.415900737
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.459231379
Short name T3038
Test name
Test status
Simulation time 146854108 ps
CPU time 0.84 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:14 PM PDT 24
Peak memory 207572 kb
Host smart-d186f31b-3e24-4f9f-b8a7-a60e31f050fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45923
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.459231379
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2497915794
Short name T787
Test name
Test status
Simulation time 246791613 ps
CPU time 1.07 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:15 PM PDT 24
Peak memory 207584 kb
Host smart-a180610a-cea6-44b9-9604-47f7792b652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24979
15794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2497915794
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2961184902
Short name T960
Test name
Test status
Simulation time 2431531919 ps
CPU time 18.56 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:32 PM PDT 24
Peak memory 224120 kb
Host smart-1fec767d-de41-4079-90bd-206c880a658b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2961184902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2961184902
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.364124981
Short name T1114
Test name
Test status
Simulation time 258850984 ps
CPU time 0.92 seconds
Started Aug 10 07:04:12 PM PDT 24
Finished Aug 10 07:04:13 PM PDT 24
Peak memory 207548 kb
Host smart-b80d4da9-4730-4df9-a06b-7aca240fe2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36412
4981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.364124981
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1386751488
Short name T2417
Test name
Test status
Simulation time 144796525 ps
CPU time 0.87 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:14 PM PDT 24
Peak memory 207516 kb
Host smart-1f953880-fb59-4843-86f4-3b38aca6e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13867
51488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1386751488
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.1042970702
Short name T2587
Test name
Test status
Simulation time 821750652 ps
CPU time 2.36 seconds
Started Aug 10 07:04:21 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 207728 kb
Host smart-cd244a12-1f81-4088-aafb-936b54f72aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10429
70702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.1042970702
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2619865156
Short name T1454
Test name
Test status
Simulation time 2447663277 ps
CPU time 19.6 seconds
Started Aug 10 07:04:13 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 218160 kb
Host smart-4714cff0-71e8-4157-a83d-5be38e1b0fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26198
65156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2619865156
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.439975838
Short name T1445
Test name
Test status
Simulation time 836336998 ps
CPU time 18.05 seconds
Started Aug 10 07:03:50 PM PDT 24
Finished Aug 10 07:04:08 PM PDT 24
Peak memory 207704 kb
Host smart-98711136-df56-45e7-8530-8ed0e84c733b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439975838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host_
handshake.439975838
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_tx_rx_disruption.3314724988
Short name T1760
Test name
Test status
Simulation time 616156361 ps
CPU time 1.54 seconds
Started Aug 10 07:04:27 PM PDT 24
Finished Aug 10 07:04:29 PM PDT 24
Peak memory 207540 kb
Host smart-17b08a34-8970-47f0-b039-440b5b92e16e
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314724988 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.usbdev_tx_rx_disruption.3314724988
Directory /workspace/6.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/60.usbdev_endpoint_types.2370750390
Short name T484
Test name
Test status
Simulation time 260763611 ps
CPU time 1.08 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:50 PM PDT 24
Peak memory 207508 kb
Host smart-524543ac-4bae-4bbf-a635-069717aa16ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2370750390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.2370750390
Directory /workspace/60.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/60.usbdev_tx_rx_disruption.445411997
Short name T895
Test name
Test status
Simulation time 454097119 ps
CPU time 1.46 seconds
Started Aug 10 07:16:49 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207604 kb
Host smart-4b90ccbe-c3a2-43f4-ac75-e593b74c2a98
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445411997 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.usbdev_tx_rx_disruption.445411997
Directory /workspace/60.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/61.usbdev_endpoint_types.4269698002
Short name T409
Test name
Test status
Simulation time 671997656 ps
CPU time 1.6 seconds
Started Aug 10 07:16:50 PM PDT 24
Finished Aug 10 07:16:51 PM PDT 24
Peak memory 207488 kb
Host smart-bcab829f-b4b8-4126-b8b6-fba2048cc390
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4269698002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.4269698002
Directory /workspace/61.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/61.usbdev_tx_rx_disruption.1378641915
Short name T3326
Test name
Test status
Simulation time 609310864 ps
CPU time 1.77 seconds
Started Aug 10 07:16:51 PM PDT 24
Finished Aug 10 07:16:53 PM PDT 24
Peak memory 207604 kb
Host smart-555a5681-0852-45b4-8c95-383fc4a18379
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378641915 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.usbdev_tx_rx_disruption.1378641915
Directory /workspace/61.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/62.usbdev_endpoint_types.2962604549
Short name T478
Test name
Test status
Simulation time 207633340 ps
CPU time 0.95 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 207540 kb
Host smart-540bae79-f50a-4862-a626-13aa2dec6a0a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2962604549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.2962604549
Directory /workspace/62.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/62.usbdev_tx_rx_disruption.1358510714
Short name T2922
Test name
Test status
Simulation time 443108427 ps
CPU time 1.51 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207476 kb
Host smart-140b31b5-c20c-4d0a-a223-f12878d13a04
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358510714 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.usbdev_tx_rx_disruption.1358510714
Directory /workspace/62.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/63.usbdev_endpoint_types.4006265611
Short name T1053
Test name
Test status
Simulation time 155964549 ps
CPU time 0.9 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:01 PM PDT 24
Peak memory 207380 kb
Host smart-919c548f-4e4d-4386-a5d9-d267d7584b62
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4006265611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.4006265611
Directory /workspace/63.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/63.usbdev_tx_rx_disruption.416074764
Short name T2623
Test name
Test status
Simulation time 424895084 ps
CPU time 1.41 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207524 kb
Host smart-4981e5dd-196c-4045-bd37-289977148778
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416074764 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 63.usbdev_tx_rx_disruption.416074764
Directory /workspace/63.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/64.usbdev_endpoint_types.3165181175
Short name T429
Test name
Test status
Simulation time 839196092 ps
CPU time 1.85 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207708 kb
Host smart-ec3e08df-52af-4922-98e9-a0df9f3f9086
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3165181175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.3165181175
Directory /workspace/64.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/64.usbdev_tx_rx_disruption.2226847700
Short name T1227
Test name
Test status
Simulation time 593080436 ps
CPU time 1.72 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207548 kb
Host smart-cd52bbb2-62e0-4b5c-80c3-ca4f27bc1197
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226847700 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.usbdev_tx_rx_disruption.2226847700
Directory /workspace/64.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/65.usbdev_endpoint_types.1795598683
Short name T445
Test name
Test status
Simulation time 603319827 ps
CPU time 1.58 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207572 kb
Host smart-2cae629f-cd5b-4192-9021-16bfee6b7f55
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1795598683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.1795598683
Directory /workspace/65.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/65.usbdev_tx_rx_disruption.724257599
Short name T172
Test name
Test status
Simulation time 638815422 ps
CPU time 1.73 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207588 kb
Host smart-ce346bc6-a621-4cc2-9261-5212d354e41d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724257599 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 65.usbdev_tx_rx_disruption.724257599
Directory /workspace/65.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/66.usbdev_endpoint_types.3666610712
Short name T1472
Test name
Test status
Simulation time 265232918 ps
CPU time 1.11 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207540 kb
Host smart-f4bb725f-01ee-470e-9712-c469b80079cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3666610712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.3666610712
Directory /workspace/66.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/66.usbdev_tx_rx_disruption.1861445691
Short name T2382
Test name
Test status
Simulation time 486088058 ps
CPU time 1.48 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207544 kb
Host smart-b6793d05-9dc3-4caa-bf98-187158568f75
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861445691 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.usbdev_tx_rx_disruption.1861445691
Directory /workspace/66.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/67.usbdev_endpoint_types.1135801122
Short name T3080
Test name
Test status
Simulation time 267538235 ps
CPU time 1.07 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207536 kb
Host smart-a700f472-ef72-4e40-b8f7-baa124ca11b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1135801122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.1135801122
Directory /workspace/67.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/67.usbdev_tx_rx_disruption.1681851652
Short name T217
Test name
Test status
Simulation time 627069889 ps
CPU time 1.7 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207532 kb
Host smart-0784d639-2a83-4b34-9035-421872f5e20f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681851652 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.usbdev_tx_rx_disruption.1681851652
Directory /workspace/67.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/68.usbdev_tx_rx_disruption.589152178
Short name T2208
Test name
Test status
Simulation time 492738821 ps
CPU time 1.47 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:01 PM PDT 24
Peak memory 207388 kb
Host smart-10da4178-f85f-41ff-b0d7-7d3414478f0d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589152178 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 68.usbdev_tx_rx_disruption.589152178
Directory /workspace/68.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/69.usbdev_tx_rx_disruption.2403313171
Short name T2440
Test name
Test status
Simulation time 561849941 ps
CPU time 1.88 seconds
Started Aug 10 07:17:00 PM PDT 24
Finished Aug 10 07:17:02 PM PDT 24
Peak memory 207440 kb
Host smart-3fc1fe3f-6e4e-4e37-9e09-8e5a1c56981b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403313171 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.usbdev_tx_rx_disruption.2403313171
Directory /workspace/69.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.2843296148
Short name T1289
Test name
Test status
Simulation time 65953814 ps
CPU time 0.69 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:04:51 PM PDT 24
Peak memory 207580 kb
Host smart-52d5dbca-1d2d-4e7e-94b6-29498f4e0f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2843296148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.2843296148
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2889762269
Short name T3563
Test name
Test status
Simulation time 12155504968 ps
CPU time 15.34 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:04:39 PM PDT 24
Peak memory 207852 kb
Host smart-8b338ab8-b058-45b0-94f2-275baf7d2e09
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889762269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.2889762269
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3039861449
Short name T1601
Test name
Test status
Simulation time 14687276914 ps
CPU time 16.74 seconds
Started Aug 10 07:04:22 PM PDT 24
Finished Aug 10 07:04:39 PM PDT 24
Peak memory 216040 kb
Host smart-f4e5668b-1c34-4cf0-b72d-2cab0397b3e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039861449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3039861449
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.435242060
Short name T916
Test name
Test status
Simulation time 30151357055 ps
CPU time 35.23 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:04:59 PM PDT 24
Peak memory 207928 kb
Host smart-7c3ba1c3-7529-4ac2-8c23-bbb4d5cd2038
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435242060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_resume.435242060
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3921564644
Short name T1711
Test name
Test status
Simulation time 173612033 ps
CPU time 0.88 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:04:25 PM PDT 24
Peak memory 207552 kb
Host smart-559e6092-8539-4256-9bf8-9af2eb15af8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
64644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3921564644
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2589765100
Short name T2180
Test name
Test status
Simulation time 148724708 ps
CPU time 0.8 seconds
Started Aug 10 07:04:20 PM PDT 24
Finished Aug 10 07:04:21 PM PDT 24
Peak memory 207532 kb
Host smart-44063d39-9f2f-4b46-a29b-0db27ded8912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
65100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2589765100
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2454455684
Short name T2004
Test name
Test status
Simulation time 306874078 ps
CPU time 1.08 seconds
Started Aug 10 07:04:22 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 207552 kb
Host smart-4d3fccdf-ebd6-4870-b382-76a2a8110559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24544
55684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2454455684
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2636931872
Short name T2950
Test name
Test status
Simulation time 748780317 ps
CPU time 1.96 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:04:26 PM PDT 24
Peak memory 207540 kb
Host smart-858badc5-269e-49d9-9a76-df8de31cd243
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2636931872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2636931872
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2850228120
Short name T2535
Test name
Test status
Simulation time 49597518735 ps
CPU time 73.13 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:05:37 PM PDT 24
Peak memory 207932 kb
Host smart-414270bc-5957-4673-b069-b240ca1cec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28502
28120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2850228120
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.2563344132
Short name T2706
Test name
Test status
Simulation time 1148401859 ps
CPU time 9.47 seconds
Started Aug 10 07:04:29 PM PDT 24
Finished Aug 10 07:04:38 PM PDT 24
Peak memory 207712 kb
Host smart-9f48d968-dfb3-4fa5-a5fd-6a7ba2e59784
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563344132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2563344132
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4186158669
Short name T2236
Test name
Test status
Simulation time 596227241 ps
CPU time 1.8 seconds
Started Aug 10 07:04:23 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 207488 kb
Host smart-5d0c6276-2147-48e0-a729-7b8e393f16ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861
58669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4186158669
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2642221583
Short name T2765
Test name
Test status
Simulation time 140125930 ps
CPU time 0.82 seconds
Started Aug 10 07:04:21 PM PDT 24
Finished Aug 10 07:04:22 PM PDT 24
Peak memory 207540 kb
Host smart-abcd51fa-5b65-413b-9fb4-fbc08933c85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
21583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2642221583
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3076765444
Short name T1064
Test name
Test status
Simulation time 49651445 ps
CPU time 0.71 seconds
Started Aug 10 07:04:23 PM PDT 24
Finished Aug 10 07:04:24 PM PDT 24
Peak memory 207552 kb
Host smart-86564acf-8bdf-4545-9de0-abf14e9ab342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
65444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3076765444
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.775453683
Short name T3493
Test name
Test status
Simulation time 854310562 ps
CPU time 2.12 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 207748 kb
Host smart-1f628489-a237-452c-a956-f3c4af11f060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77545
3683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.775453683
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_types.1501269421
Short name T465
Test name
Test status
Simulation time 311674455 ps
CPU time 1.1 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:04:32 PM PDT 24
Peak memory 207468 kb
Host smart-dcdc376d-236a-4bee-802e-195e820e7f34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1501269421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.1501269421
Directory /workspace/7.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1325144015
Short name T2386
Test name
Test status
Simulation time 266192321 ps
CPU time 1.69 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 207576 kb
Host smart-cf81e1ad-4617-4dcf-a85a-995c0942ca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13251
44015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1325144015
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1359950815
Short name T1851
Test name
Test status
Simulation time 274174418 ps
CPU time 1.19 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 223936 kb
Host smart-3cd589e7-ba99-47c8-8180-71337992a067
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1359950815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1359950815
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3913055893
Short name T3047
Test name
Test status
Simulation time 140772146 ps
CPU time 0.8 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:04:32 PM PDT 24
Peak memory 207476 kb
Host smart-a9bf47aa-83d9-4fad-87d2-e672c77c3167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
55893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3913055893
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1235160860
Short name T1629
Test name
Test status
Simulation time 242869115 ps
CPU time 0.99 seconds
Started Aug 10 07:04:33 PM PDT 24
Finished Aug 10 07:04:34 PM PDT 24
Peak memory 207584 kb
Host smart-b62a9e21-c18b-4fe1-9bad-1fa8cdbbb912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12351
60860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1235160860
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1254735361
Short name T1013
Test name
Test status
Simulation time 3593121148 ps
CPU time 101.75 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:06:14 PM PDT 24
Peak memory 218464 kb
Host smart-ba9f87dd-68d1-405e-8524-cd2fecb299f6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1254735361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1254735361
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.1558130597
Short name T2744
Test name
Test status
Simulation time 10016490559 ps
CPU time 117.8 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:06:30 PM PDT 24
Peak memory 207816 kb
Host smart-8744d88f-1152-410b-89be-396757845950
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1558130597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.1558130597
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.4087724333
Short name T3263
Test name
Test status
Simulation time 223420366 ps
CPU time 0.92 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 207600 kb
Host smart-1c307293-973a-4393-ba61-cc8e2ea44dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
24333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.4087724333
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2481729857
Short name T2532
Test name
Test status
Simulation time 10377583017 ps
CPU time 14.85 seconds
Started Aug 10 07:04:33 PM PDT 24
Finished Aug 10 07:04:48 PM PDT 24
Peak memory 216700 kb
Host smart-1363dbb3-6e3d-465f-8a65-1aee7065b740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24817
29857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2481729857
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1868891651
Short name T815
Test name
Test status
Simulation time 4935020413 ps
CPU time 6.74 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:04:39 PM PDT 24
Peak memory 216732 kb
Host smart-6de0a457-251e-4a7c-b687-9bfcea4aae79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18688
91651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1868891651
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.2945406239
Short name T859
Test name
Test status
Simulation time 4965485757 ps
CPU time 45.91 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:05:17 PM PDT 24
Peak memory 219400 kb
Host smart-c792ad23-2169-4ef9-b32d-f19d9d50bf88
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2945406239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.2945406239
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3432650905
Short name T2879
Test name
Test status
Simulation time 3893375527 ps
CPU time 39 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:05:11 PM PDT 24
Peak memory 217920 kb
Host smart-cfc93f05-c116-486a-97cd-fc7b990707d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3432650905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3432650905
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.831368148
Short name T2937
Test name
Test status
Simulation time 254993792 ps
CPU time 1.02 seconds
Started Aug 10 07:04:32 PM PDT 24
Finished Aug 10 07:04:33 PM PDT 24
Peak memory 207576 kb
Host smart-6fa87a6f-ac65-464d-8441-10c506d245ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=831368148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.831368148
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1676333378
Short name T669
Test name
Test status
Simulation time 275943585 ps
CPU time 1.09 seconds
Started Aug 10 07:04:33 PM PDT 24
Finished Aug 10 07:04:34 PM PDT 24
Peak memory 207576 kb
Host smart-93b5e742-d823-4a48-8162-3620ccd81f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
33378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1676333378
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3307825569
Short name T2656
Test name
Test status
Simulation time 3375668957 ps
CPU time 24.52 seconds
Started Aug 10 07:04:33 PM PDT 24
Finished Aug 10 07:04:57 PM PDT 24
Peak memory 218240 kb
Host smart-a76a7671-1323-41d4-b1be-54f21e963cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078
25569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3307825569
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2721716495
Short name T1286
Test name
Test status
Simulation time 3024684503 ps
CPU time 85.66 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:05:57 PM PDT 24
Peak memory 216000 kb
Host smart-af2dd2c7-9754-4ee8-b12f-41c508057de9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2721716495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2721716495
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2507438525
Short name T2721
Test name
Test status
Simulation time 2460870713 ps
CPU time 23.82 seconds
Started Aug 10 07:04:31 PM PDT 24
Finished Aug 10 07:04:55 PM PDT 24
Peak memory 217692 kb
Host smart-4153f00a-e8f2-4861-abfc-5903718329f1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2507438525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2507438525
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.255229529
Short name T2955
Test name
Test status
Simulation time 221013395 ps
CPU time 0.89 seconds
Started Aug 10 07:04:43 PM PDT 24
Finished Aug 10 07:04:44 PM PDT 24
Peak memory 207600 kb
Host smart-d73e6fbb-105f-44a7-8500-c17abbc12407
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=255229529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.255229529
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.461042531
Short name T1699
Test name
Test status
Simulation time 135124838 ps
CPU time 0.85 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207564 kb
Host smart-0f593c5a-0543-40ec-ba84-5199932c8109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46104
2531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.461042531
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.846531699
Short name T136
Test name
Test status
Simulation time 229664906 ps
CPU time 0.93 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:04:43 PM PDT 24
Peak memory 207580 kb
Host smart-04cecb89-bc42-42c7-9efe-5bb6cb8a7ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84653
1699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.846531699
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.69644895
Short name T742
Test name
Test status
Simulation time 181060421 ps
CPU time 0.94 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207512 kb
Host smart-f31b90a7-c76c-4167-9201-b59dbcbba361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69644
895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.69644895
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4176354257
Short name T1113
Test name
Test status
Simulation time 187681190 ps
CPU time 0.86 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207592 kb
Host smart-0c73e9e4-cc31-4369-ab1e-c408e173c209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41763
54257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4176354257
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2520087733
Short name T951
Test name
Test status
Simulation time 194309628 ps
CPU time 0.94 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207432 kb
Host smart-e48158cf-2fb3-4108-967c-824347846e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25200
87733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2520087733
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.378648776
Short name T2549
Test name
Test status
Simulation time 154636737 ps
CPU time 0.86 seconds
Started Aug 10 07:04:43 PM PDT 24
Finished Aug 10 07:04:44 PM PDT 24
Peak memory 207604 kb
Host smart-5595abb6-b4f7-45e2-b586-26e82b943d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37864
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.378648776
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.181756129
Short name T889
Test name
Test status
Simulation time 248519459 ps
CPU time 1.06 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:04:44 PM PDT 24
Peak memory 207412 kb
Host smart-a82d19cb-0ff3-4074-9ea5-e06c812a107a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=181756129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.181756129
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2215743425
Short name T1979
Test name
Test status
Simulation time 156061298 ps
CPU time 0.84 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:04:43 PM PDT 24
Peak memory 207480 kb
Host smart-2c1c63b9-def5-4fa9-bd60-8ee09b24b7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22157
43425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2215743425
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.45000114
Short name T1546
Test name
Test status
Simulation time 32933211 ps
CPU time 0.66 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:41 PM PDT 24
Peak memory 207544 kb
Host smart-a1944a72-ccfe-49d7-bf5e-ec01b0e9b3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45000
114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.45000114
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3281526587
Short name T3203
Test name
Test status
Simulation time 8557195267 ps
CPU time 21.32 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:05:03 PM PDT 24
Peak memory 216076 kb
Host smart-7088086c-4170-4dbe-ad1f-869fa263a9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32815
26587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3281526587
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3635384719
Short name T3627
Test name
Test status
Simulation time 171249098 ps
CPU time 0.95 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207600 kb
Host smart-2a797e13-7a91-4c95-9dbe-36adaa8f4b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
84719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3635384719
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4150997026
Short name T1845
Test name
Test status
Simulation time 175855764 ps
CPU time 0.87 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:04:43 PM PDT 24
Peak memory 207524 kb
Host smart-ed16065e-a411-4e24-bc9a-5ee8aa8f8369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
97026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4150997026
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.4261313468
Short name T3126
Test name
Test status
Simulation time 2513755952 ps
CPU time 54.79 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:05:36 PM PDT 24
Peak memory 224208 kb
Host smart-a29af7c0-a4a5-44d5-a15e-1d3c15253910
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261313468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.4261313468
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2877016045
Short name T3535
Test name
Test status
Simulation time 6744472248 ps
CPU time 32.29 seconds
Started Aug 10 07:04:40 PM PDT 24
Finished Aug 10 07:05:13 PM PDT 24
Peak memory 218536 kb
Host smart-efe2d455-cfd0-46cc-b051-6bbd6bb9692f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2877016045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2877016045
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.82698539
Short name T2009
Test name
Test status
Simulation time 6333642671 ps
CPU time 85.51 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:06:16 PM PDT 24
Peak memory 216044 kb
Host smart-a1049335-6a37-4646-bb85-9dbbbfce2a01
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=82698539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.82698539
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3414376662
Short name T2604
Test name
Test status
Simulation time 206824081 ps
CPU time 0.96 seconds
Started Aug 10 07:04:41 PM PDT 24
Finished Aug 10 07:04:42 PM PDT 24
Peak memory 207496 kb
Host smart-074a8f94-fd5d-460f-ac00-7a0c580b1dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34143
76662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3414376662
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2442565718
Short name T2663
Test name
Test status
Simulation time 176320497 ps
CPU time 0.9 seconds
Started Aug 10 07:04:42 PM PDT 24
Finished Aug 10 07:04:43 PM PDT 24
Peak memory 207584 kb
Host smart-d31f5ec6-13f4-4a01-8f00-6016d9d7ffd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425
65718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2442565718
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_resume_link_active.1038577017
Short name T2801
Test name
Test status
Simulation time 20161728065 ps
CPU time 26.37 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:05:16 PM PDT 24
Peak memory 207628 kb
Host smart-a74584d2-3fcd-42b0-89bc-808e4aadf9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
77017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_resume_link_active.1038577017
Directory /workspace/7.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.761900073
Short name T3208
Test name
Test status
Simulation time 142557509 ps
CPU time 0.8 seconds
Started Aug 10 07:04:49 PM PDT 24
Finished Aug 10 07:04:50 PM PDT 24
Peak memory 207576 kb
Host smart-235c88f2-4c22-4f78-96d3-92973107d388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76190
0073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.761900073
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_rx_full.4240207047
Short name T3486
Test name
Test status
Simulation time 382575427 ps
CPU time 1.34 seconds
Started Aug 10 07:04:54 PM PDT 24
Finished Aug 10 07:04:56 PM PDT 24
Peak memory 207452 kb
Host smart-30c48ee7-f7a0-4ea6-b24e-6f5639e86562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
07047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.4240207047
Directory /workspace/7.usbdev_rx_full/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.550142236
Short name T2828
Test name
Test status
Simulation time 170032242 ps
CPU time 0.88 seconds
Started Aug 10 07:04:51 PM PDT 24
Finished Aug 10 07:04:52 PM PDT 24
Peak memory 207544 kb
Host smart-4612f07d-b237-469b-8fdb-ee5e8cde9f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55014
2236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.550142236
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2286050911
Short name T2617
Test name
Test status
Simulation time 188367479 ps
CPU time 0.86 seconds
Started Aug 10 07:04:55 PM PDT 24
Finished Aug 10 07:04:56 PM PDT 24
Peak memory 207576 kb
Host smart-c935ed2b-0392-4efc-b7d0-8303ac43256b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860
50911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2286050911
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.632554784
Short name T2556
Test name
Test status
Simulation time 253635927 ps
CPU time 1.08 seconds
Started Aug 10 07:04:52 PM PDT 24
Finished Aug 10 07:04:53 PM PDT 24
Peak memory 207536 kb
Host smart-2131c1c1-3283-4f9a-ab45-f8ffbc4b59c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63255
4784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.632554784
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2610697841
Short name T1763
Test name
Test status
Simulation time 4300521932 ps
CPU time 43.71 seconds
Started Aug 10 07:04:55 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 216104 kb
Host smart-f3d81b53-96ea-4101-9b4d-fa289beeae19
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2610697841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2610697841
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2550566446
Short name T1669
Test name
Test status
Simulation time 214229302 ps
CPU time 0.95 seconds
Started Aug 10 07:04:55 PM PDT 24
Finished Aug 10 07:04:56 PM PDT 24
Peak memory 207476 kb
Host smart-d088eac0-dc1e-4276-9e3a-7347a2fe0b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25505
66446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2550566446
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3190576721
Short name T1067
Test name
Test status
Simulation time 150715880 ps
CPU time 0.86 seconds
Started Aug 10 07:04:51 PM PDT 24
Finished Aug 10 07:04:52 PM PDT 24
Peak memory 207496 kb
Host smart-28a6a69b-0cbd-47b6-ba46-9f4d666ee26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31905
76721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3190576721
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.2884141381
Short name T1365
Test name
Test status
Simulation time 1219663860 ps
CPU time 2.83 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:04:53 PM PDT 24
Peak memory 207728 kb
Host smart-c5b77082-2b89-4ba3-abed-2de2847ea640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28841
41381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2884141381
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3999855169
Short name T3057
Test name
Test status
Simulation time 1814494763 ps
CPU time 49.59 seconds
Started Aug 10 07:04:51 PM PDT 24
Finished Aug 10 07:05:40 PM PDT 24
Peak memory 215904 kb
Host smart-65c784e5-8cdd-4a5f-9cfc-6d62ca591431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39998
55169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3999855169
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.3276738153
Short name T2089
Test name
Test status
Simulation time 3412293764 ps
CPU time 29.42 seconds
Started Aug 10 07:04:24 PM PDT 24
Finished Aug 10 07:04:54 PM PDT 24
Peak memory 207948 kb
Host smart-707b4fba-ea7c-4866-b863-1e98e9d5f308
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276738153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.3276738153
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_tx_rx_disruption.978127047
Short name T2284
Test name
Test status
Simulation time 618946602 ps
CPU time 1.8 seconds
Started Aug 10 07:04:52 PM PDT 24
Finished Aug 10 07:04:54 PM PDT 24
Peak memory 207556 kb
Host smart-9194ddac-04b4-43fb-838b-525c34870748
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978127047 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.usbdev_tx_rx_disruption.978127047
Directory /workspace/7.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/70.usbdev_tx_rx_disruption.3483252229
Short name T778
Test name
Test status
Simulation time 512071456 ps
CPU time 1.52 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207508 kb
Host smart-e9e17dbc-73de-440e-b19c-a8ec48141472
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483252229 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.usbdev_tx_rx_disruption.3483252229
Directory /workspace/70.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/71.usbdev_tx_rx_disruption.3026852322
Short name T2851
Test name
Test status
Simulation time 549471795 ps
CPU time 1.64 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 207564 kb
Host smart-cb0ef55b-2bdd-4be9-b6a4-0c4937e27242
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026852322 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.usbdev_tx_rx_disruption.3026852322
Directory /workspace/71.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/72.usbdev_endpoint_types.1966236060
Short name T419
Test name
Test status
Simulation time 427236259 ps
CPU time 1.26 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:16:59 PM PDT 24
Peak memory 207520 kb
Host smart-58a69255-baf7-4c34-b1f2-47df386729f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1966236060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.1966236060
Directory /workspace/72.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/72.usbdev_tx_rx_disruption.626887641
Short name T1151
Test name
Test status
Simulation time 543336718 ps
CPU time 1.54 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207568 kb
Host smart-8e4133c0-5f10-4a34-9701-7a684bff1622
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626887641 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 72.usbdev_tx_rx_disruption.626887641
Directory /workspace/72.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/73.usbdev_endpoint_types.2473118398
Short name T386
Test name
Test status
Simulation time 467764967 ps
CPU time 1.31 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:16:59 PM PDT 24
Peak memory 207540 kb
Host smart-667e2f0f-c031-4864-8765-1d7ba8ea4d52
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2473118398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.2473118398
Directory /workspace/73.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/73.usbdev_tx_rx_disruption.1258291148
Short name T2247
Test name
Test status
Simulation time 496408881 ps
CPU time 1.53 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:06 PM PDT 24
Peak memory 207564 kb
Host smart-fb130ffa-26eb-42e8-b0d8-08ec6eb9e12d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258291148 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.usbdev_tx_rx_disruption.1258291148
Directory /workspace/73.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/74.usbdev_tx_rx_disruption.1365907270
Short name T1420
Test name
Test status
Simulation time 646208650 ps
CPU time 1.79 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207572 kb
Host smart-7457c172-9b42-4e7b-9194-a7e0a655e727
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365907270 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.usbdev_tx_rx_disruption.1365907270
Directory /workspace/74.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/75.usbdev_endpoint_types.408644963
Short name T3349
Test name
Test status
Simulation time 351101545 ps
CPU time 1.09 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 207512 kb
Host smart-9417960c-ca9b-4f02-b5b0-d4ee29353a25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=408644963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.408644963
Directory /workspace/75.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/75.usbdev_tx_rx_disruption.2872323620
Short name T3256
Test name
Test status
Simulation time 513308291 ps
CPU time 1.67 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207712 kb
Host smart-1f278de6-12be-48b4-9295-dbfcec8fad5c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872323620 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.usbdev_tx_rx_disruption.2872323620
Directory /workspace/75.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/76.usbdev_endpoint_types.254525581
Short name T2562
Test name
Test status
Simulation time 320923331 ps
CPU time 1.13 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207492 kb
Host smart-7e88fa74-f31b-44d4-b18b-84a8cd1f135d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=254525581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.254525581
Directory /workspace/76.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/76.usbdev_tx_rx_disruption.2625299955
Short name T2068
Test name
Test status
Simulation time 651388264 ps
CPU time 1.75 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207440 kb
Host smart-36c28962-b114-410b-8052-3b0e1d8bac4f
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625299955 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.usbdev_tx_rx_disruption.2625299955
Directory /workspace/76.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/77.usbdev_endpoint_types.2597366944
Short name T2396
Test name
Test status
Simulation time 293589454 ps
CPU time 1.08 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207540 kb
Host smart-e51376ef-070f-437e-8672-93d2fc99bda3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2597366944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.2597366944
Directory /workspace/77.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/77.usbdev_tx_rx_disruption.2628668643
Short name T2348
Test name
Test status
Simulation time 584367613 ps
CPU time 1.6 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207532 kb
Host smart-3f404610-01e6-47c5-a20b-86dc7f1d2774
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628668643 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.usbdev_tx_rx_disruption.2628668643
Directory /workspace/77.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/78.usbdev_endpoint_types.3859227026
Short name T3299
Test name
Test status
Simulation time 183240115 ps
CPU time 0.91 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207568 kb
Host smart-43fcff39-f480-4445-b64f-7e66623882d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3859227026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.3859227026
Directory /workspace/78.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/78.usbdev_tx_rx_disruption.3017682796
Short name T2653
Test name
Test status
Simulation time 546411740 ps
CPU time 1.57 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:56 PM PDT 24
Peak memory 207456 kb
Host smart-54e6104e-82d1-40b2-8fdf-ba323ba64961
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017682796 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.usbdev_tx_rx_disruption.3017682796
Directory /workspace/78.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/79.usbdev_endpoint_types.1593078580
Short name T441
Test name
Test status
Simulation time 326573518 ps
CPU time 1.11 seconds
Started Aug 10 07:17:00 PM PDT 24
Finished Aug 10 07:17:01 PM PDT 24
Peak memory 207404 kb
Host smart-c525e83e-00c1-4ad7-8a43-aa2be75686b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1593078580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.1593078580
Directory /workspace/79.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/79.usbdev_tx_rx_disruption.1753044022
Short name T164
Test name
Test status
Simulation time 500514874 ps
CPU time 1.61 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207480 kb
Host smart-5f04ff0f-4337-4c83-887d-16805b4befff
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753044022 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.usbdev_tx_rx_disruption.1753044022
Directory /workspace/79.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.692153985
Short name T670
Test name
Test status
Simulation time 41506779 ps
CPU time 0.66 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 207600 kb
Host smart-bdbd85d7-5fb7-40d3-b7b1-b3069293928d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=692153985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.692153985
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3139593790
Short name T1570
Test name
Test status
Simulation time 10353720234 ps
CPU time 13.98 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:05:05 PM PDT 24
Peak memory 207848 kb
Host smart-ac7978fe-03b7-4014-b167-428dad9f1698
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139593790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.3139593790
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1475075462
Short name T768
Test name
Test status
Simulation time 16241677384 ps
CPU time 22.2 seconds
Started Aug 10 07:04:52 PM PDT 24
Finished Aug 10 07:05:14 PM PDT 24
Peak memory 215992 kb
Host smart-43057081-8377-4375-b039-1d3c3416e182
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475075462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1475075462
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.252995011
Short name T3045
Test name
Test status
Simulation time 28412325399 ps
CPU time 34.98 seconds
Started Aug 10 07:04:56 PM PDT 24
Finished Aug 10 07:05:31 PM PDT 24
Peak memory 207728 kb
Host smart-d53d8dd1-2b2b-4818-8997-abd78423bbc9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252995011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_resume.252995011
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.962020472
Short name T1363
Test name
Test status
Simulation time 152599422 ps
CPU time 0.88 seconds
Started Aug 10 07:04:56 PM PDT 24
Finished Aug 10 07:04:57 PM PDT 24
Peak memory 207556 kb
Host smart-fa814fed-d187-43b5-a35f-36f6a22defbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96202
0472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.962020472
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3343765747
Short name T3043
Test name
Test status
Simulation time 188083310 ps
CPU time 0.89 seconds
Started Aug 10 07:04:56 PM PDT 24
Finished Aug 10 07:04:57 PM PDT 24
Peak memory 207560 kb
Host smart-9f11f1cb-9670-447f-8685-58f081d89e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33437
65747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3343765747
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.91558386
Short name T1972
Test name
Test status
Simulation time 232414800 ps
CPU time 0.99 seconds
Started Aug 10 07:04:52 PM PDT 24
Finished Aug 10 07:04:53 PM PDT 24
Peak memory 207608 kb
Host smart-2a3da9e1-a01a-47a5-b5ba-6046bfff6708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91558
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.91558386
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3512528976
Short name T2472
Test name
Test status
Simulation time 596989855 ps
CPU time 1.74 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:04:52 PM PDT 24
Peak memory 207540 kb
Host smart-fd3e670b-de74-42eb-b94a-9fdebbb0dc01
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3512528976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3512528976
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.137614173
Short name T2885
Test name
Test status
Simulation time 26935618328 ps
CPU time 44.35 seconds
Started Aug 10 07:04:51 PM PDT 24
Finished Aug 10 07:05:35 PM PDT 24
Peak memory 207760 kb
Host smart-96d26e6a-55cf-43a1-8aa6-3299ddd6b2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13761
4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.137614173
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.2221521507
Short name T2929
Test name
Test status
Simulation time 608372089 ps
CPU time 4.93 seconds
Started Aug 10 07:04:51 PM PDT 24
Finished Aug 10 07:04:56 PM PDT 24
Peak memory 207620 kb
Host smart-aa3beeb2-da3e-483a-a895-b031a4cef95e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221521507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.2221521507
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2777610174
Short name T2092
Test name
Test status
Simulation time 667588055 ps
CPU time 1.68 seconds
Started Aug 10 07:04:52 PM PDT 24
Finished Aug 10 07:04:53 PM PDT 24
Peak memory 207528 kb
Host smart-e3346e61-52c3-4cb1-8b30-a522bb1a98c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
10174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2777610174
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2346067588
Short name T2341
Test name
Test status
Simulation time 155070853 ps
CPU time 0.82 seconds
Started Aug 10 07:04:48 PM PDT 24
Finished Aug 10 07:04:49 PM PDT 24
Peak memory 207524 kb
Host smart-374732c1-981c-434d-bc26-64c2197320cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23460
67588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2346067588
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2732955850
Short name T1487
Test name
Test status
Simulation time 62140408 ps
CPU time 0.73 seconds
Started Aug 10 07:04:59 PM PDT 24
Finished Aug 10 07:05:00 PM PDT 24
Peak memory 207528 kb
Host smart-fa36a7c9-ecc9-4799-9f99-185d1fe1c637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27329
55850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2732955850
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3713993630
Short name T1406
Test name
Test status
Simulation time 816273392 ps
CPU time 2.5 seconds
Started Aug 10 07:05:00 PM PDT 24
Finished Aug 10 07:05:03 PM PDT 24
Peak memory 207732 kb
Host smart-2fd5a6b4-4b04-4879-b056-020cbc6c52dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
93630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3713993630
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_types.3280927295
Short name T442
Test name
Test status
Simulation time 413314911 ps
CPU time 1.3 seconds
Started Aug 10 07:04:58 PM PDT 24
Finished Aug 10 07:04:59 PM PDT 24
Peak memory 207528 kb
Host smart-f7275d2e-64a3-4e5d-b31b-b92e57de692a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3280927295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.3280927295
Directory /workspace/8.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.314633401
Short name T1523
Test name
Test status
Simulation time 151427845 ps
CPU time 1.41 seconds
Started Aug 10 07:05:03 PM PDT 24
Finished Aug 10 07:05:04 PM PDT 24
Peak memory 207604 kb
Host smart-6bd2f0e9-2569-4d0c-bd8b-713331fde855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
3401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.314633401
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3089576794
Short name T125
Test name
Test status
Simulation time 285930637 ps
CPU time 1.16 seconds
Started Aug 10 07:05:00 PM PDT 24
Finished Aug 10 07:05:01 PM PDT 24
Peak memory 215824 kb
Host smart-7e3d8e22-53c4-47a3-bba7-a83375f73dd1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3089576794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3089576794
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1252184625
Short name T1073
Test name
Test status
Simulation time 145243478 ps
CPU time 0.83 seconds
Started Aug 10 07:04:58 PM PDT 24
Finished Aug 10 07:04:59 PM PDT 24
Peak memory 207456 kb
Host smart-36f36042-00a8-4c4c-b26d-cfbff872cc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
84625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1252184625
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3138815210
Short name T3253
Test name
Test status
Simulation time 239068440 ps
CPU time 1.02 seconds
Started Aug 10 07:05:00 PM PDT 24
Finished Aug 10 07:05:01 PM PDT 24
Peak memory 207552 kb
Host smart-e0a19887-2f46-49c0-a20d-b74ac40353c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
15210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3138815210
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3003056325
Short name T680
Test name
Test status
Simulation time 3885679045 ps
CPU time 116.14 seconds
Started Aug 10 07:04:57 PM PDT 24
Finished Aug 10 07:06:54 PM PDT 24
Peak memory 217844 kb
Host smart-b9ff9adf-1df1-4065-8c1e-2ad1e3a342da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3003056325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3003056325
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.2642545666
Short name T701
Test name
Test status
Simulation time 8292330187 ps
CPU time 101.79 seconds
Started Aug 10 07:05:02 PM PDT 24
Finished Aug 10 07:06:44 PM PDT 24
Peak memory 207724 kb
Host smart-ab83e1e8-072a-4f98-aace-3abe40378a17
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2642545666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.2642545666
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1910440374
Short name T2333
Test name
Test status
Simulation time 279241606 ps
CPU time 0.99 seconds
Started Aug 10 07:04:59 PM PDT 24
Finished Aug 10 07:05:00 PM PDT 24
Peak memory 207512 kb
Host smart-0c2cc1bc-3764-4ed8-a364-925a64a3e752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
40374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1910440374
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1971436267
Short name T2346
Test name
Test status
Simulation time 5965085461 ps
CPU time 9.28 seconds
Started Aug 10 07:05:00 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207828 kb
Host smart-e53bc804-4e7f-432e-8f40-a0d1b8ccf6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
36267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1971436267
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2551268707
Short name T591
Test name
Test status
Simulation time 8755971664 ps
CPU time 11.29 seconds
Started Aug 10 07:04:59 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207824 kb
Host smart-edafd127-720b-47a9-9a85-d80c0ad6a273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
68707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2551268707
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1798041618
Short name T987
Test name
Test status
Simulation time 3322979532 ps
CPU time 95.17 seconds
Started Aug 10 07:05:00 PM PDT 24
Finished Aug 10 07:06:35 PM PDT 24
Peak memory 218596 kb
Host smart-f5433d7e-a6d4-4421-9812-8047b52b01c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1798041618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1798041618
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2373966744
Short name T1259
Test name
Test status
Simulation time 1954238657 ps
CPU time 18.49 seconds
Started Aug 10 07:05:03 PM PDT 24
Finished Aug 10 07:05:21 PM PDT 24
Peak memory 215912 kb
Host smart-6413f5ce-d684-4fb9-a2a3-551eaea18281
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2373966744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2373966744
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.4083014813
Short name T2941
Test name
Test status
Simulation time 252124176 ps
CPU time 1.14 seconds
Started Aug 10 07:05:03 PM PDT 24
Finished Aug 10 07:05:04 PM PDT 24
Peak memory 207480 kb
Host smart-5027000f-993b-4a50-9d78-f1a350e4fcdb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4083014813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.4083014813
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3714746989
Short name T2048
Test name
Test status
Simulation time 192844433 ps
CPU time 1.02 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:11 PM PDT 24
Peak memory 207520 kb
Host smart-14190e5c-61b9-48ef-92ae-8bb5d6538985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
46989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3714746989
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.4062284039
Short name T1258
Test name
Test status
Simulation time 1711447191 ps
CPU time 17.46 seconds
Started Aug 10 07:05:11 PM PDT 24
Finished Aug 10 07:05:29 PM PDT 24
Peak memory 224072 kb
Host smart-5d02c5e6-c54f-40ee-ac07-fc1736ab2e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40622
84039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.4062284039
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3481669264
Short name T2249
Test name
Test status
Simulation time 1773928017 ps
CPU time 49.04 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:59 PM PDT 24
Peak memory 224156 kb
Host smart-a313e50d-413c-4caf-b245-cdffe8565f38
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3481669264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3481669264
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1670769643
Short name T1585
Test name
Test status
Simulation time 3300125583 ps
CPU time 26.97 seconds
Started Aug 10 07:05:10 PM PDT 24
Finished Aug 10 07:05:37 PM PDT 24
Peak memory 217740 kb
Host smart-2df0305d-71f3-4c7e-b827-e593b8e7e95e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1670769643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1670769643
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.4294364188
Short name T2577
Test name
Test status
Simulation time 158895885 ps
CPU time 0.89 seconds
Started Aug 10 07:05:11 PM PDT 24
Finished Aug 10 07:05:12 PM PDT 24
Peak memory 207476 kb
Host smart-d60fa0ed-fd6a-41fe-8b94-49ba8feea0e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4294364188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.4294364188
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2131486946
Short name T2990
Test name
Test status
Simulation time 218482322 ps
CPU time 1 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207556 kb
Host smart-dc31d851-01a5-41e7-8e0b-4117261eff28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21314
86946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2131486946
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.230994596
Short name T3067
Test name
Test status
Simulation time 222505615 ps
CPU time 0.99 seconds
Started Aug 10 07:05:11 PM PDT 24
Finished Aug 10 07:05:12 PM PDT 24
Peak memory 207520 kb
Host smart-2425aba5-ed88-4693-8534-cf81d5166b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
4596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.230994596
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4009388748
Short name T1591
Test name
Test status
Simulation time 178156380 ps
CPU time 0.91 seconds
Started Aug 10 07:05:10 PM PDT 24
Finished Aug 10 07:05:11 PM PDT 24
Peak memory 207584 kb
Host smart-94f7f1cf-3ec5-44fa-b97c-dd440b5d6152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40093
88748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4009388748
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.340438699
Short name T1354
Test name
Test status
Simulation time 198011319 ps
CPU time 0.91 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207568 kb
Host smart-3edc20f0-4e1e-4a38-a9ff-b3f0add54693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34043
8699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.340438699
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3925985862
Short name T1973
Test name
Test status
Simulation time 215905678 ps
CPU time 0.95 seconds
Started Aug 10 07:05:08 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207532 kb
Host smart-0e8420c8-18a7-4aa3-b142-69eb57e33039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
85862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3925985862
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3568616146
Short name T193
Test name
Test status
Simulation time 156315986 ps
CPU time 0.82 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207512 kb
Host smart-165764ea-32bb-428d-93ae-279cc3be7993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35686
16146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3568616146
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2292898145
Short name T786
Test name
Test status
Simulation time 242633735 ps
CPU time 1.02 seconds
Started Aug 10 07:05:10 PM PDT 24
Finished Aug 10 07:05:11 PM PDT 24
Peak memory 207420 kb
Host smart-d9f6ee36-40db-4802-aa63-34cf2f558791
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2292898145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2292898145
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1053448195
Short name T2012
Test name
Test status
Simulation time 153109589 ps
CPU time 0.8 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207496 kb
Host smart-031820bc-c6e8-4671-bb77-d045b60f369b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10534
48195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1053448195
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.305279195
Short name T1349
Test name
Test status
Simulation time 42208540 ps
CPU time 0.72 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207700 kb
Host smart-011079ae-a3ef-4844-b5dc-4a46ca3e1e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
9195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.305279195
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.469962380
Short name T1384
Test name
Test status
Simulation time 8331169197 ps
CPU time 22.02 seconds
Started Aug 10 07:05:11 PM PDT 24
Finished Aug 10 07:05:33 PM PDT 24
Peak memory 215952 kb
Host smart-de968e07-864a-4d26-bf14-9598e2325880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46996
2380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.469962380
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1780218286
Short name T264
Test name
Test status
Simulation time 163108556 ps
CPU time 0.88 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207544 kb
Host smart-1fd66bbb-528a-4b75-b87b-679bc3bd9d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
18286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1780218286
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1738588082
Short name T1452
Test name
Test status
Simulation time 192047461 ps
CPU time 0.9 seconds
Started Aug 10 07:05:09 PM PDT 24
Finished Aug 10 07:05:10 PM PDT 24
Peak memory 207556 kb
Host smart-e8647625-f681-46c3-88d9-ead97326eb93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17385
88082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1738588082
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3961501854
Short name T3158
Test name
Test status
Simulation time 2948243609 ps
CPU time 20.34 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 216096 kb
Host smart-ffce1524-cfe3-4c79-b272-2cc85883b2d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961501854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3961501854
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3564820575
Short name T637
Test name
Test status
Simulation time 4026672379 ps
CPU time 32.62 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:52 PM PDT 24
Peak memory 218308 kb
Host smart-b8fefcbe-ec91-4d9b-9204-4456a8995c8b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3564820575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3564820575
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1438660806
Short name T1132
Test name
Test status
Simulation time 6600452237 ps
CPU time 27.84 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:46 PM PDT 24
Peak memory 215960 kb
Host smart-dd04e0a5-6697-4a85-9780-2180c882bf2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438660806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1438660806
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.857347744
Short name T1624
Test name
Test status
Simulation time 211502260 ps
CPU time 0.87 seconds
Started Aug 10 07:05:08 PM PDT 24
Finished Aug 10 07:05:09 PM PDT 24
Peak memory 207500 kb
Host smart-ab979d78-3ec5-4226-a195-6aee866db876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85734
7744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.857347744
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.355088306
Short name T2431
Test name
Test status
Simulation time 166861920 ps
CPU time 0.92 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 207596 kb
Host smart-534b7d4a-04bc-4eb1-a408-ac4848053b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
8306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.355088306
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_resume_link_active.3015180531
Short name T3417
Test name
Test status
Simulation time 20156666752 ps
CPU time 24.37 seconds
Started Aug 10 07:05:20 PM PDT 24
Finished Aug 10 07:05:45 PM PDT 24
Peak memory 207596 kb
Host smart-672fd513-789e-44e6-a7df-e8f83174cfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30151
80531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_resume_link_active.3015180531
Directory /workspace/8.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2649119509
Short name T2036
Test name
Test status
Simulation time 164264758 ps
CPU time 0.85 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 207496 kb
Host smart-17aa792d-8fed-4779-89c9-1fa0d36b9ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
19509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2649119509
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_rx_full.1330013732
Short name T52
Test name
Test status
Simulation time 408071671 ps
CPU time 1.36 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 207560 kb
Host smart-bbe91c2f-0fc0-49db-9717-10137aea9cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13300
13732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.1330013732
Directory /workspace/8.usbdev_rx_full/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2431929246
Short name T3053
Test name
Test status
Simulation time 151058608 ps
CPU time 0.83 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:20 PM PDT 24
Peak memory 207472 kb
Host smart-4e35321c-c757-4a8c-8db7-c250d60b960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24319
29246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2431929246
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2132779290
Short name T2682
Test name
Test status
Simulation time 156713460 ps
CPU time 0.85 seconds
Started Aug 10 07:05:16 PM PDT 24
Finished Aug 10 07:05:17 PM PDT 24
Peak memory 207608 kb
Host smart-299fb035-fa3d-4949-9665-59c0cc182137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
79290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2132779290
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1554469128
Short name T3036
Test name
Test status
Simulation time 188631241 ps
CPU time 0.91 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:20 PM PDT 24
Peak memory 207580 kb
Host smart-97c4130c-3f65-433f-8a3b-aa6cd12b95f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
69128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1554469128
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.342619060
Short name T930
Test name
Test status
Simulation time 3328822760 ps
CPU time 26.5 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:46 PM PDT 24
Peak memory 216100 kb
Host smart-24914b04-ebf0-4e49-b707-7c51e915c36b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=342619060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.342619060
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1439648097
Short name T1084
Test name
Test status
Simulation time 194307626 ps
CPU time 0.85 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:20 PM PDT 24
Peak memory 207580 kb
Host smart-0ef83bce-b7af-4b50-8657-bf71de71ba2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
48097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1439648097
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.863896828
Short name T2244
Test name
Test status
Simulation time 163710481 ps
CPU time 0.84 seconds
Started Aug 10 07:05:17 PM PDT 24
Finished Aug 10 07:05:18 PM PDT 24
Peak memory 207432 kb
Host smart-09f54d5b-d151-4188-83a5-2064378f11ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86389
6828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.863896828
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.415646125
Short name T923
Test name
Test status
Simulation time 630193477 ps
CPU time 1.81 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:21 PM PDT 24
Peak memory 207524 kb
Host smart-edcff6b4-f87b-4365-8b40-c14f0d919f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41564
6125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.415646125
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1943948834
Short name T1199
Test name
Test status
Simulation time 2460068996 ps
CPU time 70.34 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:06:28 PM PDT 24
Peak memory 224204 kb
Host smart-e2a89e27-77e3-464b-ab54-5169021fa1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19439
48834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1943948834
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.2174099137
Short name T1884
Test name
Test status
Simulation time 6996145886 ps
CPU time 44.3 seconds
Started Aug 10 07:04:50 PM PDT 24
Finished Aug 10 07:05:35 PM PDT 24
Peak memory 207804 kb
Host smart-fbf08d85-e601-4521-ab71-3602e2b10729
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174099137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.2174099137
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_tx_rx_disruption.2977670743
Short name T241
Test name
Test status
Simulation time 539261818 ps
CPU time 1.56 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:19 PM PDT 24
Peak memory 207588 kb
Host smart-6f2d0cff-9544-4ec8-b084-532526ab3085
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977670743 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.usbdev_tx_rx_disruption.2977670743
Directory /workspace/8.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/80.usbdev_endpoint_types.967806347
Short name T2854
Test name
Test status
Simulation time 171798460 ps
CPU time 0.91 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207552 kb
Host smart-f010a3db-1838-4393-99f2-9ddb61c9b629
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=967806347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.967806347
Directory /workspace/80.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/80.usbdev_tx_rx_disruption.771393570
Short name T1164
Test name
Test status
Simulation time 482640764 ps
CPU time 1.45 seconds
Started Aug 10 07:16:55 PM PDT 24
Finished Aug 10 07:16:57 PM PDT 24
Peak memory 207536 kb
Host smart-78893fea-8519-4e13-b935-a2e2aabda036
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771393570 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 80.usbdev_tx_rx_disruption.771393570
Directory /workspace/80.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/81.usbdev_tx_rx_disruption.2970402450
Short name T1719
Test name
Test status
Simulation time 593582195 ps
CPU time 1.64 seconds
Started Aug 10 07:16:58 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207552 kb
Host smart-662c928b-9af1-45c2-96b8-090f12ee08ae
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970402450 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.usbdev_tx_rx_disruption.2970402450
Directory /workspace/81.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/82.usbdev_endpoint_types.3454970461
Short name T494
Test name
Test status
Simulation time 476174993 ps
CPU time 1.4 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:59 PM PDT 24
Peak memory 207540 kb
Host smart-3cc42fcf-58e7-4e4a-bc49-13bd5ec0377e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3454970461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.3454970461
Directory /workspace/82.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/82.usbdev_tx_rx_disruption.2202056180
Short name T826
Test name
Test status
Simulation time 661659639 ps
CPU time 1.83 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207568 kb
Host smart-51243c2e-94a9-4dad-8315-75b0fa899473
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202056180 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.usbdev_tx_rx_disruption.2202056180
Directory /workspace/82.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/83.usbdev_endpoint_types.2553277492
Short name T3422
Test name
Test status
Simulation time 258314877 ps
CPU time 1.03 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:05 PM PDT 24
Peak memory 207492 kb
Host smart-a1d99781-88ec-46bc-adff-d84dbfdb2bfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2553277492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2553277492
Directory /workspace/83.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/83.usbdev_tx_rx_disruption.1878191192
Short name T210
Test name
Test status
Simulation time 516960073 ps
CPU time 1.55 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207668 kb
Host smart-0893555c-0615-4275-81ce-73094bb6d8df
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878191192 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.usbdev_tx_rx_disruption.1878191192
Directory /workspace/83.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/84.usbdev_endpoint_types.3041189025
Short name T3282
Test name
Test status
Simulation time 665432673 ps
CPU time 1.58 seconds
Started Aug 10 07:17:00 PM PDT 24
Finished Aug 10 07:17:01 PM PDT 24
Peak memory 207360 kb
Host smart-75c87251-c703-449e-a1f0-e375c9b0d6ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3041189025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.3041189025
Directory /workspace/84.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/84.usbdev_tx_rx_disruption.3349442452
Short name T1720
Test name
Test status
Simulation time 544855894 ps
CPU time 1.55 seconds
Started Aug 10 07:16:56 PM PDT 24
Finished Aug 10 07:16:58 PM PDT 24
Peak memory 207600 kb
Host smart-2783e6d6-fc01-4893-b893-6b6e2212e5bf
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349442452 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.usbdev_tx_rx_disruption.3349442452
Directory /workspace/84.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/85.usbdev_endpoint_types.2694380520
Short name T383
Test name
Test status
Simulation time 716968285 ps
CPU time 1.65 seconds
Started Aug 10 07:16:57 PM PDT 24
Finished Aug 10 07:16:59 PM PDT 24
Peak memory 207568 kb
Host smart-537fb813-f4af-476a-a08a-f0e0282f7780
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2694380520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.2694380520
Directory /workspace/85.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/85.usbdev_tx_rx_disruption.1947746532
Short name T1397
Test name
Test status
Simulation time 617711309 ps
CPU time 1.78 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:06 PM PDT 24
Peak memory 207536 kb
Host smart-5f94cce4-121e-4864-95c4-3fb580a5283d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947746532 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.usbdev_tx_rx_disruption.1947746532
Directory /workspace/85.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/86.usbdev_endpoint_types.2981534655
Short name T457
Test name
Test status
Simulation time 447340077 ps
CPU time 1.31 seconds
Started Aug 10 07:16:59 PM PDT 24
Finished Aug 10 07:17:00 PM PDT 24
Peak memory 207500 kb
Host smart-02e0f2a1-35fc-4a45-be87-ccba80cf0378
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2981534655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.2981534655
Directory /workspace/86.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/86.usbdev_tx_rx_disruption.2154554427
Short name T2390
Test name
Test status
Simulation time 485858348 ps
CPU time 1.58 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207560 kb
Host smart-b0e0f8f0-b6a2-42e8-8969-9025a57b70c2
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154554427 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.usbdev_tx_rx_disruption.2154554427
Directory /workspace/86.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/87.usbdev_endpoint_types.3962267630
Short name T475
Test name
Test status
Simulation time 790729215 ps
CPU time 2.02 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207336 kb
Host smart-11821c10-6d88-4c00-a78a-b31b0aea3a54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3962267630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.3962267630
Directory /workspace/87.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/87.usbdev_tx_rx_disruption.1409100033
Short name T608
Test name
Test status
Simulation time 618618051 ps
CPU time 1.65 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207532 kb
Host smart-388cd2bf-af21-48be-9ed0-aca52a456d91
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409100033 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.usbdev_tx_rx_disruption.1409100033
Directory /workspace/87.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/88.usbdev_endpoint_types.2542727366
Short name T2027
Test name
Test status
Simulation time 227705508 ps
CPU time 0.99 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207508 kb
Host smart-0032c6e1-42ff-444d-864f-bcafa661c5b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2542727366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.2542727366
Directory /workspace/88.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/88.usbdev_tx_rx_disruption.3596389173
Short name T1434
Test name
Test status
Simulation time 695671744 ps
CPU time 1.81 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:06 PM PDT 24
Peak memory 207560 kb
Host smart-65f29098-e359-41cf-a335-93c9adf48b11
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596389173 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.usbdev_tx_rx_disruption.3596389173
Directory /workspace/88.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/89.usbdev_endpoint_types.4090620364
Short name T116
Test name
Test status
Simulation time 381063600 ps
CPU time 1.27 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207524 kb
Host smart-1dc3cccd-b9e2-4ac6-8c6c-b9fc14d6a93a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4090620364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.4090620364
Directory /workspace/89.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/89.usbdev_tx_rx_disruption.171709887
Short name T195
Test name
Test status
Simulation time 483000922 ps
CPU time 1.64 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207564 kb
Host smart-c208c9b4-123e-4ebd-bdec-6d47a023f953
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171709887 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 89.usbdev_tx_rx_disruption.171709887
Directory /workspace/89.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2449589929
Short name T800
Test name
Test status
Simulation time 35509800 ps
CPU time 0.67 seconds
Started Aug 10 07:05:45 PM PDT 24
Finished Aug 10 07:05:46 PM PDT 24
Peak memory 207540 kb
Host smart-a2a1063c-efe8-47ba-a9ef-65b082ca2468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2449589929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2449589929
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.323701042
Short name T877
Test name
Test status
Simulation time 4248309080 ps
CPU time 6.4 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:26 PM PDT 24
Peak memory 215980 kb
Host smart-3825ed4f-7242-4302-a3bd-cf943ca6ef13
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323701042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_disconnect.323701042
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2494772145
Short name T1329
Test name
Test status
Simulation time 21108298465 ps
CPU time 23.32 seconds
Started Aug 10 07:05:20 PM PDT 24
Finished Aug 10 07:05:43 PM PDT 24
Peak memory 207796 kb
Host smart-e2934dda-7992-4979-a038-8dcb73561a5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494772145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2494772145
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1040774929
Short name T1568
Test name
Test status
Simulation time 29369075983 ps
CPU time 33.38 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:52 PM PDT 24
Peak memory 207864 kb
Host smart-d0f5a4f6-0ba3-48d9-bc58-df965a1319a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040774929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1040774929
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1434095080
Short name T1725
Test name
Test status
Simulation time 174815509 ps
CPU time 0.93 seconds
Started Aug 10 07:05:21 PM PDT 24
Finished Aug 10 07:05:22 PM PDT 24
Peak memory 207516 kb
Host smart-ebce5cc2-11e0-4c8a-a062-d9f4147e539f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
95080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1434095080
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.700512909
Short name T1844
Test name
Test status
Simulation time 151460625 ps
CPU time 0.86 seconds
Started Aug 10 07:05:19 PM PDT 24
Finished Aug 10 07:05:20 PM PDT 24
Peak memory 207576 kb
Host smart-11388539-3d17-47f2-a45c-51adecb06592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70051
2909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.700512909
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3261980297
Short name T1925
Test name
Test status
Simulation time 427130911 ps
CPU time 1.49 seconds
Started Aug 10 07:05:18 PM PDT 24
Finished Aug 10 07:05:20 PM PDT 24
Peak memory 207532 kb
Host smart-f6308e95-5dbc-4276-8271-a284d84b8900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32619
80297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3261980297
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3654038754
Short name T3215
Test name
Test status
Simulation time 392407458 ps
CPU time 1.37 seconds
Started Aug 10 07:05:30 PM PDT 24
Finished Aug 10 07:05:32 PM PDT 24
Peak memory 207584 kb
Host smart-e39d9c07-1e8f-4143-968e-7a994b6a66f8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3654038754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3654038754
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.1007924536
Short name T3032
Test name
Test status
Simulation time 192848943 ps
CPU time 0.88 seconds
Started Aug 10 07:05:27 PM PDT 24
Finished Aug 10 07:05:28 PM PDT 24
Peak memory 207568 kb
Host smart-38dae6e8-749a-4725-b2b9-57efdc5ba3a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007924536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1007924536
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.428725620
Short name T3624
Test name
Test status
Simulation time 1022551021 ps
CPU time 2.13 seconds
Started Aug 10 07:05:26 PM PDT 24
Finished Aug 10 07:05:28 PM PDT 24
Peak memory 207488 kb
Host smart-e397b6a8-4756-4b3f-8935-c0945d6f0e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42872
5620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.428725620
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.4149147317
Short name T2441
Test name
Test status
Simulation time 155508453 ps
CPU time 0.84 seconds
Started Aug 10 07:05:28 PM PDT 24
Finished Aug 10 07:05:29 PM PDT 24
Peak memory 207544 kb
Host smart-b6718611-46d5-4bc4-9d55-f0f48494bf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
47317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4149147317
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3004805920
Short name T1245
Test name
Test status
Simulation time 84145313 ps
CPU time 0.78 seconds
Started Aug 10 07:05:27 PM PDT 24
Finished Aug 10 07:05:27 PM PDT 24
Peak memory 207380 kb
Host smart-6391d23c-597c-44d1-bf21-327b2b3fffd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30048
05920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3004805920
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3482532076
Short name T1891
Test name
Test status
Simulation time 1017319256 ps
CPU time 2.63 seconds
Started Aug 10 07:05:26 PM PDT 24
Finished Aug 10 07:05:29 PM PDT 24
Peak memory 207792 kb
Host smart-e4bd1bbf-a039-428a-a1cf-93ab1033f1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
32076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3482532076
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_types.3642438405
Short name T2529
Test name
Test status
Simulation time 223755941 ps
CPU time 0.99 seconds
Started Aug 10 07:05:27 PM PDT 24
Finished Aug 10 07:05:28 PM PDT 24
Peak memory 207548 kb
Host smart-68a81ca7-8c7f-4ea5-8a68-73e8d6cc281a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3642438405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.3642438405
Directory /workspace/9.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3830344856
Short name T2548
Test name
Test status
Simulation time 297672568 ps
CPU time 2.21 seconds
Started Aug 10 07:05:30 PM PDT 24
Finished Aug 10 07:05:33 PM PDT 24
Peak memory 207728 kb
Host smart-8cd8739e-d7d8-4f12-aa22-ae8a733a10ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
44856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3830344856
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3199073277
Short name T2290
Test name
Test status
Simulation time 198226835 ps
CPU time 0.98 seconds
Started Aug 10 07:05:30 PM PDT 24
Finished Aug 10 07:05:31 PM PDT 24
Peak memory 215960 kb
Host smart-9b072a16-4568-46d8-a680-cf4a39dc205d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3199073277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3199073277
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2092096337
Short name T824
Test name
Test status
Simulation time 158770102 ps
CPU time 0.88 seconds
Started Aug 10 07:05:27 PM PDT 24
Finished Aug 10 07:05:28 PM PDT 24
Peak memory 207576 kb
Host smart-6a030c92-d4df-4296-8d0f-fb6d6af8d337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
96337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2092096337
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2992253532
Short name T1182
Test name
Test status
Simulation time 198342489 ps
CPU time 0.98 seconds
Started Aug 10 07:05:26 PM PDT 24
Finished Aug 10 07:05:27 PM PDT 24
Peak memory 207532 kb
Host smart-380a8dde-ac4d-4788-a2bc-f34a6758a728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
53532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2992253532
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3195962361
Short name T2690
Test name
Test status
Simulation time 3853720677 ps
CPU time 42.91 seconds
Started Aug 10 07:05:28 PM PDT 24
Finished Aug 10 07:06:11 PM PDT 24
Peak memory 224184 kb
Host smart-8628f56d-2c92-4350-a3ec-cd0465349f56
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3195962361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3195962361
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3788351017
Short name T3569
Test name
Test status
Simulation time 10572774784 ps
CPU time 75.69 seconds
Started Aug 10 07:05:27 PM PDT 24
Finished Aug 10 07:06:42 PM PDT 24
Peak memory 207796 kb
Host smart-e3b45bb5-dd7e-4f07-937c-1b542244b2be
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3788351017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3788351017
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1971815857
Short name T1136
Test name
Test status
Simulation time 232816599 ps
CPU time 0.99 seconds
Started Aug 10 07:05:39 PM PDT 24
Finished Aug 10 07:05:40 PM PDT 24
Peak memory 207552 kb
Host smart-8dbd7d47-c4ad-4bfe-80d1-8cb7b090f1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
15857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1971815857
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.155863192
Short name T3179
Test name
Test status
Simulation time 7246036837 ps
CPU time 11.21 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:05:48 PM PDT 24
Peak memory 216028 kb
Host smart-58f5b929-1469-4ef0-959b-34e8caafc65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.155863192
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.792813549
Short name T1089
Test name
Test status
Simulation time 11092288766 ps
CPU time 12.67 seconds
Started Aug 10 07:05:36 PM PDT 24
Finished Aug 10 07:05:49 PM PDT 24
Peak memory 207796 kb
Host smart-3a487dad-a438-44ef-92a3-47732626b30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79281
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.792813549
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3691099967
Short name T4
Test name
Test status
Simulation time 3263245200 ps
CPU time 33.29 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:06:11 PM PDT 24
Peak memory 218996 kb
Host smart-24a11083-ac14-4611-9f85-3f101b64f359
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3691099967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3691099967
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4213949379
Short name T993
Test name
Test status
Simulation time 2732541047 ps
CPU time 29.3 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:06:07 PM PDT 24
Peak memory 217908 kb
Host smart-6c23dbb3-495a-4cfe-aa37-3b4332d33f97
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4213949379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4213949379
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3890836139
Short name T3095
Test name
Test status
Simulation time 238149756 ps
CPU time 1.02 seconds
Started Aug 10 07:05:36 PM PDT 24
Finished Aug 10 07:05:37 PM PDT 24
Peak memory 207556 kb
Host smart-236e64e5-c344-4aa7-90d3-6089fd05bdfd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3890836139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3890836139
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4065388899
Short name T1002
Test name
Test status
Simulation time 203938986 ps
CPU time 0.94 seconds
Started Aug 10 07:05:36 PM PDT 24
Finished Aug 10 07:05:37 PM PDT 24
Peak memory 207576 kb
Host smart-9921d8de-c15b-4f18-adc2-b1f9551266a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40653
88899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4065388899
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.3883149768
Short name T2062
Test name
Test status
Simulation time 2064399294 ps
CPU time 21 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:05:58 PM PDT 24
Peak memory 217476 kb
Host smart-e901746b-1b58-45a6-ae6c-9048250f3d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38831
49768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.3883149768
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.163495347
Short name T1217
Test name
Test status
Simulation time 1731891329 ps
CPU time 47.87 seconds
Started Aug 10 07:05:40 PM PDT 24
Finished Aug 10 07:06:28 PM PDT 24
Peak memory 217548 kb
Host smart-e63d3223-2dd9-44f2-a7ba-3cf9325eab84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=163495347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.163495347
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1900709976
Short name T532
Test name
Test status
Simulation time 2322313479 ps
CPU time 64.81 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:06:43 PM PDT 24
Peak memory 217436 kb
Host smart-82205691-bbda-4a2b-aed0-72d048ec742f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1900709976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1900709976
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3661952992
Short name T3112
Test name
Test status
Simulation time 158026976 ps
CPU time 0.83 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 207604 kb
Host smart-ede3330a-bdfa-4389-9932-635dccfd0e00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3661952992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3661952992
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.716385269
Short name T1839
Test name
Test status
Simulation time 137349726 ps
CPU time 0.81 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 207612 kb
Host smart-2cf05607-53b9-4b71-8327-aee3123b8a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71638
5269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.716385269
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.594486482
Short name T160
Test name
Test status
Simulation time 270911298 ps
CPU time 1.08 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:05:38 PM PDT 24
Peak memory 207648 kb
Host smart-9498e8b4-f837-44a9-a762-3570ed629a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59448
6482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.594486482
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3996667697
Short name T2555
Test name
Test status
Simulation time 207342227 ps
CPU time 0.93 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:05:38 PM PDT 24
Peak memory 207444 kb
Host smart-242f3e55-774c-48a9-b3c6-8df638e6fb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39966
67697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3996667697
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.454556064
Short name T2612
Test name
Test status
Simulation time 194860758 ps
CPU time 0.95 seconds
Started Aug 10 07:05:34 PM PDT 24
Finished Aug 10 07:05:35 PM PDT 24
Peak memory 207480 kb
Host smart-84821b23-c465-4aaa-91f3-cd13db9d65ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45455
6064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.454556064
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1980989771
Short name T1553
Test name
Test status
Simulation time 186328371 ps
CPU time 0.84 seconds
Started Aug 10 07:05:35 PM PDT 24
Finished Aug 10 07:05:36 PM PDT 24
Peak memory 207572 kb
Host smart-432c52cc-2211-4379-a789-cb2bb73e799f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19809
89771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1980989771
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.158345991
Short name T178
Test name
Test status
Simulation time 157850894 ps
CPU time 0.86 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 207504 kb
Host smart-059d6cdc-0330-4c1b-a590-2c33cc9915ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
5991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.158345991
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3048349387
Short name T2601
Test name
Test status
Simulation time 249642746 ps
CPU time 1.09 seconds
Started Aug 10 07:05:35 PM PDT 24
Finished Aug 10 07:05:36 PM PDT 24
Peak memory 207536 kb
Host smart-0c5a38da-1cad-4655-a314-243ef44280e7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3048349387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3048349387
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.776695451
Short name T2090
Test name
Test status
Simulation time 163466557 ps
CPU time 0.85 seconds
Started Aug 10 07:05:41 PM PDT 24
Finished Aug 10 07:05:42 PM PDT 24
Peak memory 207548 kb
Host smart-c4c40a38-72c4-4bf2-aec0-8ce7547736ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77669
5451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.776695451
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2674237820
Short name T2858
Test name
Test status
Simulation time 36403625 ps
CPU time 0.69 seconds
Started Aug 10 07:05:34 PM PDT 24
Finished Aug 10 07:05:35 PM PDT 24
Peak memory 207472 kb
Host smart-d8bf6c76-9aad-4495-948a-e22a0256041d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26742
37820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2674237820
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3602950122
Short name T339
Test name
Test status
Simulation time 14298883013 ps
CPU time 35.1 seconds
Started Aug 10 07:05:36 PM PDT 24
Finished Aug 10 07:06:11 PM PDT 24
Peak memory 216096 kb
Host smart-d3594ef6-1bbc-4ccd-bdaa-7568f71823be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
50122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3602950122
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.4279989617
Short name T1768
Test name
Test status
Simulation time 148094220 ps
CPU time 0.88 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:05:38 PM PDT 24
Peak memory 207604 kb
Host smart-9b0af042-34e8-49a4-970b-52db2d840b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
89617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.4279989617
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1153934360
Short name T2861
Test name
Test status
Simulation time 178373443 ps
CPU time 0.85 seconds
Started Aug 10 07:05:36 PM PDT 24
Finished Aug 10 07:05:37 PM PDT 24
Peak memory 207536 kb
Host smart-a6d0527b-f858-4bf5-bf1d-58e2a1930f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11539
34360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1153934360
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2490472963
Short name T2422
Test name
Test status
Simulation time 6971018044 ps
CPU time 62.97 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:06:41 PM PDT 24
Peak memory 217836 kb
Host smart-a4da4ae3-3d89-4a6a-8faf-29d22243b883
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490472963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2490472963
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3544673371
Short name T2345
Test name
Test status
Simulation time 6680492989 ps
CPU time 41.43 seconds
Started Aug 10 07:05:37 PM PDT 24
Finished Aug 10 07:06:19 PM PDT 24
Peak memory 224332 kb
Host smart-f2a810dc-5914-4c3b-99ee-37045b7e5fe5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3544673371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3544673371
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4040545720
Short name T1682
Test name
Test status
Simulation time 10065735221 ps
CPU time 48.89 seconds
Started Aug 10 07:05:43 PM PDT 24
Finished Aug 10 07:06:32 PM PDT 24
Peak memory 224232 kb
Host smart-535b9d0d-edb5-44bb-abc0-1b0ed3bf6627
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040545720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4040545720
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2398152942
Short name T3175
Test name
Test status
Simulation time 189185039 ps
CPU time 0.88 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 207544 kb
Host smart-ac076054-f501-4eb4-983d-0514295dfa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
52942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2398152942
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.677996734
Short name T555
Test name
Test status
Simulation time 230949750 ps
CPU time 0.94 seconds
Started Aug 10 07:05:38 PM PDT 24
Finished Aug 10 07:05:39 PM PDT 24
Peak memory 207512 kb
Host smart-fd0de8c7-efa3-4f92-8931-3dbe0c0db8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67799
6734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.677996734
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_resume_link_active.4145685620
Short name T2770
Test name
Test status
Simulation time 20169757133 ps
CPU time 22.47 seconds
Started Aug 10 07:05:46 PM PDT 24
Finished Aug 10 07:06:08 PM PDT 24
Peak memory 207644 kb
Host smart-a7691409-fc8b-4872-a26b-0c7a0803051d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456
85620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_resume_link_active.4145685620
Directory /workspace/9.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4090686480
Short name T2430
Test name
Test status
Simulation time 149366793 ps
CPU time 0.84 seconds
Started Aug 10 07:05:44 PM PDT 24
Finished Aug 10 07:05:45 PM PDT 24
Peak memory 207528 kb
Host smart-88ccccb9-6876-4c1b-8f1b-4666e9279cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40906
86480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4090686480
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_rx_full.2959763807
Short name T3616
Test name
Test status
Simulation time 257587055 ps
CPU time 1.08 seconds
Started Aug 10 07:05:43 PM PDT 24
Finished Aug 10 07:05:45 PM PDT 24
Peak memory 207544 kb
Host smart-6b09b2de-7555-4fdb-b77d-50318955308a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597
63807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.2959763807
Directory /workspace/9.usbdev_rx_full/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2614294736
Short name T3129
Test name
Test status
Simulation time 212830735 ps
CPU time 0.9 seconds
Started Aug 10 07:05:47 PM PDT 24
Finished Aug 10 07:05:48 PM PDT 24
Peak memory 207428 kb
Host smart-598bf56e-efba-4f65-b777-0d05eba1814b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26142
94736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2614294736
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.170898595
Short name T1855
Test name
Test status
Simulation time 144177184 ps
CPU time 0.81 seconds
Started Aug 10 07:05:44 PM PDT 24
Finished Aug 10 07:05:45 PM PDT 24
Peak memory 207744 kb
Host smart-0383baaa-2b30-4d1b-b125-b4eeeed0904f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.170898595
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3355670798
Short name T2067
Test name
Test status
Simulation time 232197415 ps
CPU time 1.04 seconds
Started Aug 10 07:05:45 PM PDT 24
Finished Aug 10 07:05:46 PM PDT 24
Peak memory 207508 kb
Host smart-063d3be0-f07a-47db-b1da-fd7f6d06f360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33556
70798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3355670798
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.798687317
Short name T2505
Test name
Test status
Simulation time 2645297762 ps
CPU time 76.86 seconds
Started Aug 10 07:05:46 PM PDT 24
Finished Aug 10 07:07:03 PM PDT 24
Peak memory 216136 kb
Host smart-0f7de05d-3b20-44cd-b331-e00fc3527999
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=798687317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.798687317
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1283491867
Short name T1593
Test name
Test status
Simulation time 180342117 ps
CPU time 0.89 seconds
Started Aug 10 07:05:46 PM PDT 24
Finished Aug 10 07:05:47 PM PDT 24
Peak memory 207564 kb
Host smart-7a2a3e7b-5476-40d1-8dec-b1b533ca23ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834
91867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1283491867
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.546108575
Short name T828
Test name
Test status
Simulation time 166835625 ps
CPU time 0.84 seconds
Started Aug 10 07:05:43 PM PDT 24
Finished Aug 10 07:05:44 PM PDT 24
Peak memory 207492 kb
Host smart-8130788e-f431-4986-87b2-d4530f51f5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54610
8575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.546108575
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.234093753
Short name T310
Test name
Test status
Simulation time 797048522 ps
CPU time 1.95 seconds
Started Aug 10 07:05:46 PM PDT 24
Finished Aug 10 07:05:48 PM PDT 24
Peak memory 207500 kb
Host smart-5c893cc8-b048-4ec4-b3e2-9b246dea69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
3753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.234093753
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.567131478
Short name T1475
Test name
Test status
Simulation time 1631608080 ps
CPU time 16.37 seconds
Started Aug 10 07:05:46 PM PDT 24
Finished Aug 10 07:06:03 PM PDT 24
Peak memory 224108 kb
Host smart-b12a76e1-ba7f-4dd8-9f3f-9c52017e59b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56713
1478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.567131478
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.3932365821
Short name T1080
Test name
Test status
Simulation time 5308874088 ps
CPU time 45.81 seconds
Started Aug 10 07:05:25 PM PDT 24
Finished Aug 10 07:06:11 PM PDT 24
Peak memory 207784 kb
Host smart-1141aa40-ee17-4f1b-848b-ac09e7a7d691
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932365821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.3932365821
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_tx_rx_disruption.1723036918
Short name T910
Test name
Test status
Simulation time 552937017 ps
CPU time 1.61 seconds
Started Aug 10 07:05:43 PM PDT 24
Finished Aug 10 07:05:45 PM PDT 24
Peak memory 207532 kb
Host smart-47e06436-f160-4b7d-bd26-cead1eda70b4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723036918 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.usbdev_tx_rx_disruption.1723036918
Directory /workspace/9.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/90.usbdev_endpoint_types.3420038264
Short name T461
Test name
Test status
Simulation time 484998703 ps
CPU time 1.46 seconds
Started Aug 10 07:17:03 PM PDT 24
Finished Aug 10 07:17:05 PM PDT 24
Peak memory 207532 kb
Host smart-18e745c7-42dc-4435-be03-ca44fbe025f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3420038264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.3420038264
Directory /workspace/90.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/90.usbdev_tx_rx_disruption.161175782
Short name T240
Test name
Test status
Simulation time 495779572 ps
CPU time 1.5 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:09 PM PDT 24
Peak memory 207600 kb
Host smart-2e2dbcc7-34ef-472c-8d04-16897ed73aa4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161175782 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 90.usbdev_tx_rx_disruption.161175782
Directory /workspace/90.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/91.usbdev_endpoint_types.695784929
Short name T423
Test name
Test status
Simulation time 368753825 ps
CPU time 1.38 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207520 kb
Host smart-1d89848f-26c6-46f9-9a13-177859ba7992
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=695784929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.695784929
Directory /workspace/91.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/91.usbdev_tx_rx_disruption.3745862866
Short name T1360
Test name
Test status
Simulation time 680868089 ps
CPU time 1.71 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207416 kb
Host smart-dfbc403d-f8dc-4dc0-80e6-ce27790b9e4b
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745862866 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.usbdev_tx_rx_disruption.3745862866
Directory /workspace/91.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/92.usbdev_tx_rx_disruption.2071273543
Short name T3319
Test name
Test status
Simulation time 601940976 ps
CPU time 1.86 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207420 kb
Host smart-3c5db8d5-1071-4bbf-aaa7-f2b180e516fa
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071273543 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.usbdev_tx_rx_disruption.2071273543
Directory /workspace/92.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/93.usbdev_endpoint_types.235697955
Short name T3060
Test name
Test status
Simulation time 192225972 ps
CPU time 0.95 seconds
Started Aug 10 07:17:04 PM PDT 24
Finished Aug 10 07:17:05 PM PDT 24
Peak memory 207496 kb
Host smart-0e4186d4-2254-4050-9b34-8770d31a73f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=235697955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.235697955
Directory /workspace/93.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/93.usbdev_tx_rx_disruption.338617962
Short name T1231
Test name
Test status
Simulation time 489702385 ps
CPU time 1.55 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207564 kb
Host smart-b741d2c1-2c38-4e45-ae01-6e3cf50663d4
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338617962 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 93.usbdev_tx_rx_disruption.338617962
Directory /workspace/93.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/94.usbdev_tx_rx_disruption.3340276033
Short name T3115
Test name
Test status
Simulation time 515374134 ps
CPU time 1.67 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:06 PM PDT 24
Peak memory 207604 kb
Host smart-bb58af78-5692-47d4-a5a7-9fb8681f6c3d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340276033 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.usbdev_tx_rx_disruption.3340276033
Directory /workspace/94.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/95.usbdev_endpoint_types.3036080285
Short name T459
Test name
Test status
Simulation time 376497749 ps
CPU time 1.21 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207540 kb
Host smart-8599cbd2-ecfd-43c9-b9cf-305a689eecd7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3036080285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.3036080285
Directory /workspace/95.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/95.usbdev_tx_rx_disruption.1346146869
Short name T1446
Test name
Test status
Simulation time 632284325 ps
CPU time 1.64 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207536 kb
Host smart-7718b011-f97b-4c69-b69d-9c644916a1dd
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346146869 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.usbdev_tx_rx_disruption.1346146869
Directory /workspace/95.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/96.usbdev_endpoint_types.3255237495
Short name T1547
Test name
Test status
Simulation time 240079110 ps
CPU time 0.99 seconds
Started Aug 10 07:17:07 PM PDT 24
Finished Aug 10 07:17:08 PM PDT 24
Peak memory 207496 kb
Host smart-a9e6b01c-6fa5-426d-be97-6de1b27fd9c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3255237495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.3255237495
Directory /workspace/96.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/96.usbdev_tx_rx_disruption.3086314560
Short name T566
Test name
Test status
Simulation time 467044761 ps
CPU time 1.44 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207412 kb
Host smart-871becf0-a237-4bcb-8494-c870f0f92b97
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086314560 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.usbdev_tx_rx_disruption.3086314560
Directory /workspace/96.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/97.usbdev_endpoint_types.4252108358
Short name T511
Test name
Test status
Simulation time 197998853 ps
CPU time 0.95 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207532 kb
Host smart-b46410d4-e7ca-41f8-b9d2-55d1ef69a388
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4252108358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.4252108358
Directory /workspace/97.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/97.usbdev_tx_rx_disruption.770185994
Short name T3362
Test name
Test status
Simulation time 526841426 ps
CPU time 1.62 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207516 kb
Host smart-9aa1335f-5e79-48b7-b3c2-cd4c41f0a38c
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770185994 -assert nopostproc +UVM_TES
TNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 97.usbdev_tx_rx_disruption.770185994
Directory /workspace/97.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/98.usbdev_endpoint_types.2305377229
Short name T2133
Test name
Test status
Simulation time 227350732 ps
CPU time 0.97 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:10 PM PDT 24
Peak memory 207388 kb
Host smart-6513f7ee-0961-468a-89db-0d8ceeb2ef13
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2305377229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.2305377229
Directory /workspace/98.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/98.usbdev_tx_rx_disruption.3541967513
Short name T3199
Test name
Test status
Simulation time 653650258 ps
CPU time 1.82 seconds
Started Aug 10 07:17:05 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207520 kb
Host smart-86bf7984-3223-4a1f-84af-844ebdbd265a
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541967513 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.usbdev_tx_rx_disruption.3541967513
Directory /workspace/98.usbdev_tx_rx_disruption/latest

Test location /workspace/coverage/default/99.usbdev_endpoint_types.2901133297
Short name T492
Test name
Test status
Simulation time 178324060 ps
CPU time 0.89 seconds
Started Aug 10 07:17:06 PM PDT 24
Finished Aug 10 07:17:07 PM PDT 24
Peak memory 207508 kb
Host smart-72d47e0a-2385-4810-b4fe-a831e566d74b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2901133297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.2901133297
Directory /workspace/99.usbdev_endpoint_types/latest

Test location /workspace/coverage/default/99.usbdev_tx_rx_disruption.2208925487
Short name T3044
Test name
Test status
Simulation time 470138335 ps
CPU time 1.47 seconds
Started Aug 10 07:17:09 PM PDT 24
Finished Aug 10 07:17:11 PM PDT 24
Peak memory 207416 kb
Host smart-690ea54a-698e-49ef-8096-943622a5fb4d
User root
Command /workspace/default/simv +en_scb_rdchk_rx_pid_err=0 +en_scb_rdchk_rx_crc_err=0 +en_scb_rdchk_link_in_err=0 +en_scb_rdchk_rx_bitstuff_err=0 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208925487 -assert nopostproc +UVM_TE
STNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_tx_rx_disruption_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.usbdev_tx_rx_disruption.2208925487
Directory /workspace/99.usbdev_tx_rx_disruption/latest
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