Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171497	1			T1	2		T2	3		T3	2
all_values[1]	171497	1			T1	2		T2	3		T3	2
all_values[2]	171497	1			T1	2		T2	3		T3	2
all_values[3]	171497	1			T1	2		T2	3		T3	2
all_values[4]	171497	1			T1	2		T2	3		T3	2
all_values[5]	171497	1			T1	2		T2	3		T3	2
all_values[6]	171497	1			T1	2		T2	3		T3	2
all_values[7]	171497	1			T1	2		T2	3		T3	2
all_values[8]	171497	1			T1	2		T2	3		T3	2
all_values[9]	171497	1			T1	2		T2	3		T3	2
all_values[10]	171497	1			T1	2		T2	3		T3	2
all_values[11]	171497	1			T1	2		T2	3		T3	2
all_values[12]	171497	1			T1	2		T2	3		T3	2
all_values[13]	171497	1			T1	2		T2	3		T3	2
all_values[14]	171497	1			T1	2		T2	3		T3	2
all_values[15]	171497	1			T1	2		T2	3		T3	2
all_values[16]	171497	1			T1	2		T2	3		T3	2
all_values[17]	171497	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5478198

1

T1

64

T2

96

T3

64

auto[1]

9706

1

T29

3

T31

5

T40

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4703482

1

T1

61

T2

78

T3

55

auto[1]

784422

1

T1

3

T2

18

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142981	1			T1	2		T39	2		T33	3
all_values[0]	auto[0]	auto[1]	25197	1			T2	3		T3	2		T30	3
all_values[0]	auto[1]	auto[0]	3210	1			T29	3		T31	5		T35	5
all_values[0]	auto[1]	auto[1]	109	1			T22	1		T371	1		T372	1
all_values[1]	auto[0]	auto[0]	167001	1			T1	2		T3	2		T39	2
all_values[1]	auto[0]	auto[1]	3097	1			T2	3		T29	1		T30	3
all_values[1]	auto[1]	auto[0]	518	1			T47	2		T17	2		T24	2
all_values[1]	auto[1]	auto[1]	881	1			T47	12		T17	12		T24	1
all_values[2]	auto[0]	auto[0]	4219	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	167006	1			T1	1		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	136	1			T40	1		T45	1		T46	1
all_values[2]	auto[1]	auto[1]	136	1			T40	1		T45	1		T46	1
all_values[3]	auto[0]	auto[0]	169548	1			T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	290	1			T4	1		T37	1		T66	1
all_values[3]	auto[1]	auto[0]	1599	1			T67	1484		T231	1		T234	1
all_values[3]	auto[1]	auto[1]	60	1			T67	1		T231	1		T234	1
all_values[4]	auto[0]	auto[0]	4204	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	167122	1			T1	1		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	95	1			T68	1		T231	4		T235	1
all_values[4]	auto[1]	auto[1]	76	1			T68	1		T231	3		T234	2
all_values[5]	auto[0]	auto[0]	170998	1			T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	335	1			T7	1		T59	1		T8	1
all_values[5]	auto[1]	auto[0]	110	1			T231	2		T234	1		T235	3
all_values[5]	auto[1]	auto[1]	54	1			T231	4		T232	1		T369	1
all_values[6]	auto[0]	auto[0]	171047	1			T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	211	1			T7	1		T59	1		T8	1
all_values[6]	auto[1]	auto[0]	116	1			T231	2		T234	3		T235	3
all_values[6]	auto[1]	auto[1]	123	1			T69	1		T70	1		T71	1
all_values[7]	auto[0]	auto[0]	115075	1			T1	2		T39	2		T40	2
all_values[7]	auto[0]	auto[1]	56262	1			T2	3		T3	2		T29	3
all_values[7]	auto[1]	auto[0]	110	1			T48	1		T49	1		T50	1
all_values[7]	auto[1]	auto[1]	50	1			T48	1		T49	1		T50	1
all_values[8]	auto[0]	auto[0]	170765	1			T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	47	1			T231	3		T234	2		T232	1
all_values[8]	auto[1]	auto[0]	607	1			T51	10		T53	10		T52	10
all_values[8]	auto[1]	auto[1]	78	1			T51	1		T52	1		T56	1
all_values[9]	auto[0]	auto[0]	171249	1			T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	79	1			T231	4		T234	1		T236	3
all_values[9]	auto[1]	auto[0]	99	1			T63	3		T64	3		T65	3
all_values[9]	auto[1]	auto[1]	70	1			T63	2		T64	2		T65	2
all_values[10]	auto[0]	auto[0]	170941	1			T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	396	1			T60	1		T61	1		T62	1
all_values[10]	auto[1]	auto[0]	119	1			T231	5		T234	4		T235	3
all_values[10]	auto[1]	auto[1]	41	1			T231	1		T235	1		T233	1
all_values[11]	auto[0]	auto[0]	170556	1			T1	2		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	682	1			T21	1		T76	3		T79	1
all_values[11]	auto[1]	auto[0]	158	1			T72	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	101	1			T72	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	171130	1			T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	193	1			T31	3		T76	3		T80	3
all_values[12]	auto[1]	auto[0]	111	1			T81	2		T82	2		T83	2
all_values[12]	auto[1]	auto[1]	63	1			T81	1		T82	1		T83	1
all_values[13]	auto[0]	auto[0]	171188	1			T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	68	1			T85	1		T86	1		T87	1
all_values[13]	auto[1]	auto[0]	148	1			T21	1		T79	1		T84	1
all_values[13]	auto[1]	auto[1]	93	1			T21	1		T79	1		T84	1
all_values[14]	auto[0]	auto[0]	35392	1			T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	135925	1			T40	1		T4	1		T37	1
all_values[14]	auto[1]	auto[0]	104	1			T231	5		T234	2		T235	1
all_values[14]	auto[1]	auto[1]	76	1			T231	1		T234	3		T232	1
all_values[15]	auto[0]	auto[0]	4279	1			T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	167075	1			T1	1		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	101	1			T231	3		T234	4		T235	1
all_values[15]	auto[1]	auto[1]	42	1			T231	2		T232	3		T233	2
all_values[16]	auto[0]	auto[0]	170551	1			T1	2		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	780	1			T31	3		T72	1		T37	1
all_values[16]	auto[1]	auto[0]	103	1			T73	4		T74	4		T75	4
all_values[16]	auto[1]	auto[1]	63	1			T73	4		T74	4		T75	4
all_values[17]	auto[0]	auto[0]	113856	1			T1	2		T39	2		T4	2
all_values[17]	auto[0]	auto[1]	57495	1			T2	3		T3	2		T29	3
all_values[17]	auto[1]	auto[0]	100	1			T57	1		T58	1		T231	4
all_values[17]	auto[1]	auto[1]	46	1			T57	1		T58	1		T231	3