Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
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Group : usbdev_env_pkg::usbdev_env_cov::crc5_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_crc5 3 0 3 100.00 100 1 1 0
cp_dir 2 0 2 100.00 100 1 1 2


Crosses for Group usbdev_env_pkg::usbdev_env_cov::crc5_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_crc5_X_dir 6 0 6 100.00 100 1 1 0


Summary for Variable cp_crc5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_crc5

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones 5052 1 T37 23 T17 2 T401 1
leading_zero 5314 1 T37 8 T47 2 T6 1
trailing_zero 4967 1 T1 1 T35 6 T4 96



Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 114811 1 T1 5 T2 1 T3 1
auto[1] 69858 1 T1 1 T2 1 T29 1



Summary for Cross cr_crc5_X_dir

Samples crossed: cp_crc5 cp_dir
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for cr_crc5_X_dir

Bins
cp_crc5cp_dirCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_ones auto[0] 2865 1 T37 14 T17 1 T401 1
all_ones auto[1] 2187 1 T37 9 T17 1 T164 1
leading_zero auto[0] 3173 1 T37 4 T47 1 T6 1
leading_zero auto[1] 2141 1 T37 4 T47 1 T66 20
trailing_zero auto[0] 2729 1 T35 4 T37 4 T89 4
trailing_zero auto[1] 2238 1 T1 1 T35 2 T4 96

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