Summary for Variable cp_crc5
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_crc5
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
5052 |
1 |
|
|
T37 |
23 |
|
T17 |
2 |
|
T401 |
1 |
leading_zero |
5314 |
1 |
|
|
T37 |
8 |
|
T47 |
2 |
|
T6 |
1 |
trailing_zero |
4967 |
1 |
|
|
T1 |
1 |
|
T35 |
6 |
|
T4 |
96 |
Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
114811 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
69858 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T29 |
1 |
Summary for Cross cr_crc5_X_dir
Samples crossed: cp_crc5 cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for cr_crc5_X_dir
Bins
cp_crc5 | cp_dir | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_ones |
auto[0] |
2865 |
1 |
|
|
T37 |
14 |
|
T17 |
1 |
|
T401 |
1 |
all_ones |
auto[1] |
2187 |
1 |
|
|
T37 |
9 |
|
T17 |
1 |
|
T164 |
1 |
leading_zero |
auto[0] |
3173 |
1 |
|
|
T37 |
4 |
|
T47 |
1 |
|
T6 |
1 |
leading_zero |
auto[1] |
2141 |
1 |
|
|
T37 |
4 |
|
T47 |
1 |
|
T66 |
20 |
trailing_zero |
auto[0] |
2729 |
1 |
|
|
T35 |
4 |
|
T37 |
4 |
|
T89 |
4 |
trailing_zero |
auto[1] |
2238 |
1 |
|
|
T1 |
1 |
|
T35 |
2 |
|
T4 |
96 |