Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114683

1

T1

5

T2

1

T3

1

auto[1]

45654

1

T2

1

T29

1

T30

1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30002	1			T4	95		T18	1		T20	1
max_len_m1	775	1			T5	2		T6	4		T105	4
max_len_m2	864	1			T5	4		T6	2		T110	2
max_len_m3	892	1			T72	1		T35	1		T133	1
five	1099	1			T131	1		T5	2		T106	2
four	1177	1			T38	1		T110	4		T60	2
three	782	1			T6	1		T105	1		T94	9
one	865	1			T94	8		T257	1		T204	1
zero	11425	1			T32	2		T4	1		T18	1

---

Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24159	1			T18	1		T20	1		T92	1
max_len	auto[1]	5843	1			T4	95		T105	1		T106	1
max_len_m1	auto[0]	541	1			T5	1		T6	2		T105	2
max_len_m1	auto[1]	234	1			T5	1		T6	2		T105	2
max_len_m2	auto[0]	574	1			T5	2		T6	1		T110	1
max_len_m2	auto[1]	290	1			T5	2		T6	1		T110	1
max_len_m3	auto[0]	599	1			T72	1		T35	1		T133	1
max_len_m3	auto[1]	293	1			T110	1		T105	1		T204	1
five	auto[0]	579	1			T131	1		T5	1		T106	1
five	auto[1]	520	1			T5	1		T106	1		T59	1
four	auto[0]	601	1			T38	1		T110	2		T60	1
four	auto[1]	576	1			T110	2		T60	1		T106	1
three	auto[0]	401	1			T6	1		T105	1		T94	3
three	auto[1]	381	1			T94	6		T170	1		T277	5
one	auto[0]	388	1			T94	3		T204	1		T132	1
one	auto[1]	477	1			T94	5		T257	1		T277	8
zero	auto[0]	547	1			T32	1		T21	1		T79	1
zero	auto[1]	10878	1			T32	1		T4	1		T18	1