Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70134

1

T2

1

T3

1

T29

2

auto[1]

77198

1

T2

2

T29

2

T30

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	13357	1			T37	14		T38	1		T47	3
endpoints[0x1]	11183	1			T38	8		T47	3		T5	36
endpoints[0x2]	12966	1			T2	3		T3	1		T34	1
endpoints[0x3]	13752	1			T37	11		T89	4		T47	3
endpoints[0x4]	12405	1			T29	4		T37	17		T89	8
endpoints[0x5]	11028	1			T30	3		T36	1		T37	10
endpoints[0x6]	13585	1			T72	1		T47	3		T5	36
endpoints[0x7]	10377	1			T33	1		T37	6		T47	3
endpoints[0x8]	14035	1			T37	6		T47	3		T17	3
endpoints[0x9]	10636	1			T31	4		T37	18		T47	3
endpoints[0xa]	13089	1			T31	8		T32	3		T35	4
endpoints[0xb]	10919	1			T35	8		T88	1		T47	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	183	1			T60	8		T62	3		T102	7
ack	38011	1			T2	1		T29	1		T30	1
data1	50889	1			T29	2		T31	6		T35	6
data0	58183	1			T2	2		T3	1		T29	1

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	15	1			T60	3		T347	1		T348	1
nak	auto[1]	endpoints[0x1]	17	1			T60	2		T349	1		T350	1
nak	auto[1]	endpoints[0x2]	14	1			T60	1		T62	1		T102	2
nak	auto[1]	endpoints[0x3]	22	1			T62	1		T102	2		T351	3
nak	auto[1]	endpoints[0x4]	14	1			T351	1		T352	1		T347	1
nak	auto[1]	endpoints[0x5]	20	1			T102	1		T349	2		T351	2
nak	auto[1]	endpoints[0x6]	11	1			T351	1		T347	1		T353	1
nak	auto[1]	endpoints[0x7]	10	1			T354	1		T355	1		T356	1
nak	auto[1]	endpoints[0x8]	19	1			T60	2		T102	1		T357	3
nak	auto[1]	endpoints[0x9]	11	1			T349	2		T352	1		T347	1
nak	auto[1]	endpoints[0xa]	16	1			T102	1		T358	1		T348	1
nak	auto[1]	endpoints[0xb]	14	1			T62	1		T347	1		T348	1
ack	auto[1]	endpoints[0x0]	3273	1			T37	7		T47	1		T5	12
ack	auto[1]	endpoints[0x1]	3165	1			T47	1		T5	12		T17	1
ack	auto[1]	endpoints[0x2]	3084	1			T2	1		T47	1		T5	12
ack	auto[1]	endpoints[0x3]	2985	1			T89	1		T47	1		T5	12
ack	auto[1]	endpoints[0x4]	3260	1			T29	1		T37	4		T89	2
ack	auto[1]	endpoints[0x5]	3032	1			T30	1		T37	5		T47	1
ack	auto[1]	endpoints[0x6]	3122	1			T47	1		T5	12		T17	1
ack	auto[1]	endpoints[0x7]	3140	1			T37	3		T47	1		T17	1
ack	auto[1]	endpoints[0x8]	3166	1			T47	1		T17	1		T6	11
ack	auto[1]	endpoints[0x9]	3271	1			T31	1		T37	9		T47	1
ack	auto[1]	endpoints[0xa]	3474	1			T31	2		T32	1		T35	1
ack	auto[1]	endpoints[0xb]	3039	1			T35	2		T47	1		T17	1
data1	auto[0]	endpoints[0x0]	2921	1			T5	4		T6	5		T66	3
data1	auto[0]	endpoints[0x1]	1984	1			T38	4		T5	2		T92	1
data1	auto[0]	endpoints[0x2]	2888	1			T5	3		T18	1		T92	2
data1	auto[0]	endpoints[0x3]	3421	1			T37	4		T89	1		T5	4
data1	auto[0]	endpoints[0x4]	2429	1			T29	1		T89	2		T131	1
data1	auto[0]	endpoints[0x5]	2073	1			T164	2		T66	6		T165	1
data1	auto[0]	endpoints[0x6]	3201	1			T5	6		T66	2		T80	1
data1	auto[0]	endpoints[0x7]	1588	1			T66	6		T80	2		T106	16
data1	auto[0]	endpoints[0x8]	3327	1			T37	1		T6	3		T60	1
data1	auto[0]	endpoints[0x9]	1607	1			T31	1		T110	6		T60	1
data1	auto[0]	endpoints[0xa]	2514	1			T31	2		T35	1		T6	5
data1	auto[0]	endpoints[0xb]	1957	1			T35	2		T93	2		T60	2
data1	auto[1]	endpoints[0x0]	1770	1			T37	5		T5	8		T6	5
data1	auto[1]	endpoints[0x1]	1701	1			T5	10		T6	5		T92	1
data1	auto[1]	endpoints[0x2]	1753	1			T5	8		T18	1		T92	2
data1	auto[1]	endpoints[0x3]	1662	1			T89	1		T5	7		T76	1
data1	auto[1]	endpoints[0x4]	1792	1			T29	1		T37	2		T89	2
data1	auto[1]	endpoints[0x5]	1672	1			T37	3		T164	2		T66	5
data1	auto[1]	endpoints[0x6]	1708	1			T5	6		T66	6		T80	1
data1	auto[1]	endpoints[0x7]	1735	1			T37	2		T66	2		T80	2
data1	auto[1]	endpoints[0x8]	1759	1			T6	8		T66	4		T60	3
data1	auto[1]	endpoints[0x9]	1793	1			T31	1		T37	5		T110	6
data1	auto[1]	endpoints[0xa]	1960	1			T31	2		T35	1		T37	4
data1	auto[1]	endpoints[0xb]	1674	1			T35	2		T93	2		T66	8
data0	auto[0]	endpoints[0x0]	3787	1			T38	1		T47	1		T5	8
data0	auto[0]	endpoints[0x1]	2765	1			T38	4		T47	1		T5	10
data0	auto[0]	endpoints[0x2]	3798	1			T2	1		T3	1		T34	1
data0	auto[0]	endpoints[0x3]	4243	1			T37	7		T89	1		T47	1
data0	auto[0]	endpoints[0x4]	3372	1			T29	1		T37	9		T89	2
data0	auto[0]	endpoints[0x5]	2795	1			T30	1		T36	1		T47	1
data0	auto[0]	endpoints[0x6]	4076	1			T72	1		T47	1		T5	6
data0	auto[0]	endpoints[0x7]	2404	1			T33	1		T47	1		T17	1
data0	auto[0]	endpoints[0x8]	4260	1			T37	5		T47	1		T17	1
data0	auto[0]	endpoints[0x9]	2410	1			T31	1		T47	1		T17	1
data0	auto[0]	endpoints[0xa]	3485	1			T31	2		T32	1		T35	1
data0	auto[0]	endpoints[0xb]	2813	1			T35	2		T88	1		T47	1
data0	auto[1]	endpoints[0x0]	1583	1			T37	2		T47	1		T5	4
data0	auto[1]	endpoints[0x1]	1548	1			T47	1		T5	2		T17	1
data0	auto[1]	endpoints[0x2]	1428	1			T2	1		T47	1		T5	4
data0	auto[1]	endpoints[0x3]	1414	1			T47	1		T5	5		T17	1
data0	auto[1]	endpoints[0x4]	1534	1			T37	2		T47	1		T17	1
data0	auto[1]	endpoints[0x5]	1429	1			T30	1		T37	2		T47	1
data0	auto[1]	endpoints[0x6]	1463	1			T47	1		T5	6		T17	1
data0	auto[1]	endpoints[0x7]	1494	1			T37	1		T47	1		T17	1
data0	auto[1]	endpoints[0x8]	1494	1			T47	1		T17	1		T6	3
data0	auto[1]	endpoints[0x9]	1539	1			T37	4		T47	1		T17	1
data0	auto[1]	endpoints[0xa]	1632	1			T32	1		T37	1		T47	1
data0	auto[1]	endpoints[0xb]	1417	1			T47	1		T17	1		T66	5