Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9374

1

T1

1

T37

67

T6

1

auto[1]

54461

1

T2

1

T29

1

T30

1

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55884

1

T2

1

T29

1

T30

1

auto[1]

7951

1

T1

1

T36

1

T4

96

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56681

1

T2

1

T29

1

T30

1

auto[1]

7154

1

T1

1

T37

47

T66

30

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4926

1

T37

39

T6

1

T66

68

pkt_types[PidTypeInToken]

58909

1

T1

1

T2

1

T29

1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1580

1

T37

7

T66

22

T105

3

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

873

1

T37

6

T66

2

T104

19

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

71

1

T6

1

T128

1

T402

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

16

1

T403

1

T404

1

T405

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1399

1

T37

18

T66

40

T105

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

885

1

T37

8

T66

4

T104

9

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

88

1

T105

1

T128

1

T406

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

14

1

T407

1

T408

1

T409

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

4138

1

T37

40

T66

36

T319

5

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2598

1

T37

14

T66

18

T410

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

57

1

T410

1

T103

1

T411

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

41

1

T1

1

T403

4

T412

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41725

1

T2

1

T29

1

T30

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2686

1

T37

19

T66

6

T104

10

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7623

1

T36

1

T4

96

T6

24

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

41

1

T413

1

T414

1

T415

1