Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171497	1			T1	2		T2	3		T3	2
all_pins[1]	171497	1			T1	2		T2	3		T3	2
all_pins[2]	171497	1			T1	2		T2	3		T3	2
all_pins[3]	171497	1			T1	2		T2	3		T3	2
all_pins[4]	171497	1			T1	2		T2	3		T3	2
all_pins[5]	171497	1			T1	2		T2	3		T3	2
all_pins[6]	171497	1			T1	2		T2	3		T3	2
all_pins[7]	171497	1			T1	2		T2	3		T3	2
all_pins[8]	171497	1			T1	2		T2	3		T3	2
all_pins[9]	171497	1			T1	2		T2	3		T3	2
all_pins[10]	171497	1			T1	2		T2	3		T3	2
all_pins[11]	171497	1			T1	2		T2	3		T3	2
all_pins[12]	171497	1			T1	2		T2	3		T3	2
all_pins[13]	171497	1			T1	2		T2	3		T3	2
all_pins[14]	171497	1			T1	2		T2	3		T3	2
all_pins[15]	171497	1			T1	2		T2	3		T3	2
all_pins[16]	171497	1			T1	2		T2	3		T3	2
all_pins[17]	171497	1			T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5485742	1			T1	64		T2	96		T3	64
values[0x1]	2162	1			T40	1		T72	1		T47	12
transitions[0x0=>0x1]	1946	1			T40	1		T72	1		T47	12
transitions[0x1=>0x0]	1946	1			T40	1		T72	1		T47	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171388	1			T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	109	1			T22	1		T371	1		T372	1
all_pins[0]	transitions[0x0=>0x1]	96	1			T22	1		T371	1		T372	1
all_pins[0]	transitions[0x1=>0x0]	868	1			T47	12		T17	12		T24	1
all_pins[1]	values[0x0]	170616	1			T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	881	1			T47	12		T17	12		T24	1
all_pins[1]	transitions[0x0=>0x1]	863	1			T47	12		T17	12		T24	1
all_pins[1]	transitions[0x1=>0x0]	118	1			T40	1		T45	1		T46	1
all_pins[2]	values[0x0]	171361	1			T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	136	1			T40	1		T45	1		T46	1
all_pins[2]	transitions[0x0=>0x1]	119	1			T40	1		T45	1		T46	1
all_pins[2]	transitions[0x1=>0x0]	43	1			T67	1		T231	1		T234	1
all_pins[3]	values[0x0]	171437	1			T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	60	1			T67	1		T231	1		T234	1
all_pins[3]	transitions[0x0=>0x1]	40	1			T67	1		T234	1		T333	2
all_pins[3]	transitions[0x1=>0x0]	56	1			T68	1		T231	2		T234	2
all_pins[4]	values[0x0]	171421	1			T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	76	1			T68	1		T231	3		T234	2
all_pins[4]	transitions[0x0=>0x1]	63	1			T68	1		T231	2		T234	2
all_pins[4]	transitions[0x1=>0x0]	41	1			T231	3		T232	1		T369	1
all_pins[5]	values[0x0]	171443	1			T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	54	1			T231	4		T232	1		T369	1
all_pins[5]	transitions[0x0=>0x1]	37	1			T231	3		T369	1		T367	1
all_pins[5]	transitions[0x1=>0x0]	106	1			T69	1		T70	1		T71	1
all_pins[6]	values[0x0]	171374	1			T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	123	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x0=>0x1]	111	1			T69	1		T70	1		T71	1
all_pins[6]	transitions[0x1=>0x0]	38	1			T48	1		T49	1		T50	1
all_pins[7]	values[0x0]	171447	1			T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	50	1			T48	1		T49	1		T50	1
all_pins[7]	transitions[0x0=>0x1]	36	1			T48	1		T49	1		T50	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T51	1		T52	1		T56	1
all_pins[8]	values[0x0]	171419	1			T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	78	1			T51	1		T52	1		T56	1
all_pins[8]	transitions[0x0=>0x1]	68	1			T51	1		T52	1		T56	1
all_pins[8]	transitions[0x1=>0x0]	60	1			T63	2		T64	2		T65	2
all_pins[9]	values[0x0]	171427	1			T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	70	1			T63	2		T64	2		T65	2
all_pins[9]	transitions[0x0=>0x1]	54	1			T63	2		T64	2		T65	2
all_pins[9]	transitions[0x1=>0x0]	25	1			T235	1		T333	1		T335	1
all_pins[10]	values[0x0]	171456	1			T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	41	1			T231	1		T235	1		T233	1
all_pins[10]	transitions[0x0=>0x1]	36	1			T231	1		T233	1		T369	2
all_pins[10]	transitions[0x1=>0x0]	96	1			T72	1		T77	1		T78	1
all_pins[11]	values[0x0]	171396	1			T1	2		T2	3		T3	2
all_pins[11]	values[0x1]	101	1			T72	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	92	1			T72	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	54	1			T81	1		T82	1		T83	1
all_pins[12]	values[0x0]	171434	1			T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	63	1			T81	1		T82	1		T83	1
all_pins[12]	transitions[0x0=>0x1]	53	1			T81	1		T82	1		T83	1
all_pins[12]	transitions[0x1=>0x0]	83	1			T21	1		T79	1		T84	1
all_pins[13]	values[0x0]	171404	1			T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	93	1			T21	1		T79	1		T84	1
all_pins[13]	transitions[0x0=>0x1]	82	1			T21	1		T79	1		T84	1
all_pins[13]	transitions[0x1=>0x0]	65	1			T231	1		T233	3		T366	2
all_pins[14]	values[0x0]	171421	1			T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	76	1			T231	1		T234	3		T232	1
all_pins[14]	transitions[0x0=>0x1]	59	1			T231	1		T234	3		T233	3
all_pins[14]	transitions[0x1=>0x0]	25	1			T231	2		T232	2		T233	2
all_pins[15]	values[0x0]	171455	1			T1	2		T2	3		T3	2
all_pins[15]	values[0x1]	42	1			T231	2		T232	3		T233	2
all_pins[15]	transitions[0x0=>0x1]	34	1			T231	2		T232	3		T233	2
all_pins[15]	transitions[0x1=>0x0]	55	1			T73	4		T74	4		T75	4
all_pins[16]	values[0x0]	171434	1			T1	2		T2	3		T3	2
all_pins[16]	values[0x1]	63	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	57	1			T73	4		T74	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	40	1			T57	1		T58	1		T231	3
all_pins[17]	values[0x0]	171451	1			T1	2		T2	3		T3	2
all_pins[17]	values[0x1]	46	1			T57	1		T58	1		T231	3
all_pins[17]	transitions[0x0=>0x1]	46	1			T57	1		T58	1		T231	3