Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	5094	1			T37	37		T66	60		T103	2
invalid_ep[0xd]	5008	1			T1	1		T37	42		T66	69
invalid_ep[0xe]	4889	1			T37	43		T66	66		T103	1
invalid_ep[0xf]	4947	1			T1	1		T37	43		T66	66
endpoints[0x0]	14517	1			T1	1		T37	43		T38	1
endpoints[0x1]	12910	1			T37	46		T38	8		T47	2
endpoints[0x2]	14259	1			T2	2		T3	1		T34	1
endpoints[0x3]	15934	1			T37	42		T89	3		T47	2
endpoints[0x4]	13761	1			T29	3		T37	24		T89	6
endpoints[0x5]	12429	1			T30	2		T36	2		T37	34
endpoints[0x6]	15384	1			T1	1		T72	1		T37	47
endpoints[0x7]	11575	1			T33	1		T4	96		T37	46
endpoints[0x8]	15372	1			T37	39		T47	2		T17	2
endpoints[0x9]	12103	1			T1	1		T31	3		T37	46
endpoints[0xa]	14174	1			T1	1		T31	7		T32	2
endpoints[0xb]	12313	1			T35	6		T37	42		T88	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	24312	1			T1	1		T3	1		T29	1
pkt_types[PidTypeOutToken]	77848	1			T1	1		T2	1		T29	1
pkt_types[PidTypeInToken]	63423	1			T1	1		T2	1		T29	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1132	1			T37	9		T66	7		T103	2
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1128	1			T37	7		T66	24		T104	13
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1087	1			T37	8		T66	15		T104	14
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1070	1			T37	12		T66	16		T410	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1625	1			T37	14		T38	1		T5	6
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1581	1			T37	8		T5	8		T92	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1686	1			T3	1		T37	12		T5	6
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1628	1			T37	10		T89	1		T5	6
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1660	1			T29	1		T37	7		T89	2
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1620	1			T37	12		T164	2		T66	13
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1715	1			T37	11		T66	19		T80	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1623	1			T37	9		T66	14		T80	2
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1661	1			T37	9		T6	7		T66	16
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1604	1			T31	1		T37	7		T66	21
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1822	1			T1	1		T31	2		T35	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1670	1			T35	2		T37	15		T93	3
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1706	1			T37	11		T66	24		T125	11
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1618	1			T1	1		T37	14		T66	16
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1610	1			T37	8		T66	12		T125	10
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1656	1			T37	9		T66	25		T103	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	6942	1			T37	10		T47	1		T5	6
pkt_types[PidTypeOutToken]	endpoints[0x1]	5027	1			T37	13		T38	8		T47	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6665	1			T2	1		T34	1		T37	9
pkt_types[PidTypeOutToken]	endpoints[0x3]	7809	1			T37	9		T89	1		T47	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5896	1			T29	1		T37	3		T89	2
pkt_types[PidTypeOutToken]	endpoints[0x5]	5044	1			T30	1		T36	1		T37	6
pkt_types[PidTypeOutToken]	endpoints[0x6]	7357	1			T72	1		T37	11		T47	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4028	1			T33	1		T37	13		T47	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	7612	1			T37	6		T47	1		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	4195	1			T31	1		T37	15		T47	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5917	1			T31	3		T32	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	4766	1			T35	2		T37	6		T88	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1167	1			T37	9		T66	17		T104	18
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1173	1			T37	7		T66	13		T104	11
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1093	1			T37	9		T66	18		T104	18
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1081	1			T37	9		T66	13		T104	11
pkt_types[PidTypeInToken]	endpoints[0x0]	4763	1			T1	1		T37	10		T47	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5048	1			T37	14		T47	1		T5	13
pkt_types[PidTypeInToken]	endpoints[0x2]	4710	1			T2	1		T37	11		T47	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5207	1			T37	14		T89	1		T47	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4937	1			T29	1		T37	8		T89	2
pkt_types[PidTypeInToken]	endpoints[0x5]	4547	1			T30	1		T36	1		T37	11
pkt_types[PidTypeInToken]	endpoints[0x6]	5057	1			T37	14		T47	1		T5	13
pkt_types[PidTypeInToken]	endpoints[0x7]	4739	1			T4	96		T37	10		T47	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4925	1			T37	12		T47	1		T17	1
pkt_types[PidTypeInToken]	endpoints[0x9]	5118	1			T31	1		T37	15		T47	1
pkt_types[PidTypeInToken]	endpoints[0xa]	5200	1			T31	2		T32	1		T35	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4658	1			T35	2		T37	8		T47	1