Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T231	7		T234	7		T235	4
all_values[1]	269	1			T231	7		T234	7		T235	4
all_values[2]	269	1			T231	7		T234	7		T235	4
all_values[3]	269	1			T231	7		T234	7		T235	4
all_values[4]	269	1			T231	7		T234	7		T235	4
all_values[5]	269	1			T231	7		T234	7		T235	4
all_values[6]	269	1			T231	7		T234	7		T235	4
all_values[7]	269	1			T231	7		T234	7		T235	4
all_values[8]	269	1			T231	7		T234	7		T235	4
all_values[9]	269	1			T231	7		T234	7		T235	4
all_values[10]	269	1			T231	7		T234	7		T235	4
all_values[11]	269	1			T231	7		T234	7		T235	4
all_values[12]	269	1			T231	7		T234	7		T235	4
all_values[13]	269	1			T231	7		T234	7		T235	4
all_values[14]	269	1			T231	7		T234	7		T235	4
all_values[15]	269	1			T231	7		T234	7		T235	4
all_values[16]	269	1			T231	7		T234	7		T235	4
all_values[17]	269	1			T231	7		T234	7		T235	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6462

1

T231

163

T234

182

T235

99

auto[1]

2146

1

T231

61

T234

42

T235

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5945

1

T231

155

T234

145

T235

96

auto[1]

2663

1

T231

69

T234

79

T235

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5100

1

T231

135

T234

126

T235

79

auto[1]

3508

1

T231

89

T234

98

T235

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	90	1			T231	3		T234	2		T235	2
all_values[0]	auto[0]	auto[1]	auto[0]	54	1			T231	1		T234	2		T235	2
all_values[0]	auto[1]	auto[0]	auto[1]	64	1			T231	3		T234	2		T232	2
all_values[0]	auto[1]	auto[1]	auto[1]	61	1			T234	1		T236	1		T232	1
all_values[1]	auto[0]	auto[0]	auto[0]	90	1			T231	2		T234	1		T235	1
all_values[1]	auto[0]	auto[1]	auto[0]	60	1			T231	1		T234	1		T235	1
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T231	4		T234	4		T235	2
all_values[1]	auto[1]	auto[1]	auto[1]	39	1			T234	1		T236	1		T233	1
all_values[2]	auto[0]	auto[0]	auto[0]	37	1			T231	1		T234	2		T235	1
all_values[2]	auto[0]	auto[0]	auto[1]	54	1			T231	2		T234	1		T235	1
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T231	2		T232	1		T334	1
all_values[2]	auto[0]	auto[1]	auto[1]	44	1			T234	1		T235	1		T232	1
all_values[2]	auto[1]	auto[0]	auto[1]	53	1			T231	1		T236	1		T232	4
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T231	1		T234	3		T235	1
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T231	1		T234	1		T235	1
all_values[3]	auto[0]	auto[0]	auto[1]	23	1			T231	2		T234	1		T235	1
all_values[3]	auto[0]	auto[1]	auto[0]	54	1			T231	2		T235	1		T236	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1			T366	1		T367	2		T333	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1			T231	2		T234	5		T236	2
all_values[3]	auto[1]	auto[1]	auto[1]	56	1			T235	1		T232	2		T233	2
all_values[4]	auto[0]	auto[0]	auto[0]	53	1			T234	1		T232	3		T233	2
all_values[4]	auto[0]	auto[0]	auto[1]	24	1			T234	1		T333	3		T368	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1			T231	2		T236	4		T233	1
all_values[4]	auto[0]	auto[1]	auto[1]	32	1			T231	2		T235	1		T233	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1			T231	1		T234	2		T235	3
all_values[4]	auto[1]	auto[1]	auto[1]	50	1			T231	2		T234	3		T232	2
all_values[5]	auto[0]	auto[0]	auto[0]	73	1			T234	3		T236	1		T232	3
all_values[5]	auto[0]	auto[0]	auto[1]	21	1			T231	1		T234	1		T235	1
all_values[5]	auto[0]	auto[1]	auto[0]	46	1			T235	1		T236	1		T233	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1			T231	3		T369	1		T368	1
all_values[5]	auto[1]	auto[0]	auto[1]	53	1			T231	1		T234	3		T235	2
all_values[5]	auto[1]	auto[1]	auto[1]	51	1			T231	2		T232	1		T233	2
all_values[6]	auto[0]	auto[0]	auto[0]	52	1			T231	2		T234	2		T236	1
all_values[6]	auto[0]	auto[0]	auto[1]	24	1			T233	1		T366	1		T368	1
all_values[6]	auto[0]	auto[1]	auto[0]	52	1			T231	1		T234	2		T235	2
all_values[6]	auto[0]	auto[1]	auto[1]	30	1			T236	1		T232	1		T369	2
all_values[6]	auto[1]	auto[0]	auto[1]	50	1			T234	2		T235	2		T232	1
all_values[6]	auto[1]	auto[1]	auto[1]	61	1			T231	4		T234	1		T236	1
all_values[7]	auto[0]	auto[0]	auto[0]	83	1			T231	3		T234	1		T232	3
all_values[7]	auto[0]	auto[1]	auto[0]	74	1			T231	1		T235	2		T236	1
all_values[7]	auto[1]	auto[0]	auto[1]	72	1			T231	2		T234	2		T235	1
all_values[7]	auto[1]	auto[1]	auto[1]	40	1			T231	1		T234	4		T235	1
all_values[8]	auto[0]	auto[0]	auto[0]	89	1			T231	2		T234	3		T236	3
all_values[8]	auto[0]	auto[1]	auto[0]	76	1			T231	1		T235	3		T236	1
all_values[8]	auto[1]	auto[0]	auto[1]	56	1			T231	3		T234	2		T235	1
all_values[8]	auto[1]	auto[1]	auto[1]	48	1			T231	1		T234	2		T232	1
all_values[9]	auto[0]	auto[0]	auto[0]	53	1			T231	1		T234	4		T235	1
all_values[9]	auto[0]	auto[0]	auto[1]	33	1			T231	3		T234	1		T236	1
all_values[9]	auto[0]	auto[1]	auto[0]	37	1			T231	1		T235	2		T232	1
all_values[9]	auto[0]	auto[1]	auto[1]	26	1			T234	1		T369	2		T333	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T231	1		T234	1		T235	1
all_values[9]	auto[1]	auto[1]	auto[1]	46	1			T231	1		T233	1		T333	3
all_values[10]	auto[0]	auto[0]	auto[0]	72	1			T234	2		T236	3		T232	2
all_values[10]	auto[0]	auto[0]	auto[1]	24	1			T231	1		T232	1		T367	1
all_values[10]	auto[0]	auto[1]	auto[0]	61	1			T231	3		T234	2		T235	1
all_values[10]	auto[0]	auto[1]	auto[1]	14	1			T369	1		T333	1		T336	1
all_values[10]	auto[1]	auto[0]	auto[1]	49	1			T231	1		T234	3		T235	2
all_values[10]	auto[1]	auto[1]	auto[1]	49	1			T231	2		T235	1		T236	1
all_values[11]	auto[0]	auto[0]	auto[0]	59	1			T231	1		T234	1		T232	2
all_values[11]	auto[0]	auto[0]	auto[1]	28	1			T234	1		T235	1		T236	1
all_values[11]	auto[0]	auto[1]	auto[0]	53	1			T231	2		T234	2		T236	2
all_values[11]	auto[0]	auto[1]	auto[1]	22	1			T231	2		T234	1		T233	1
all_values[11]	auto[1]	auto[0]	auto[1]	66	1			T234	1		T235	1		T236	1
all_values[11]	auto[1]	auto[1]	auto[1]	41	1			T231	2		T234	1		T235	2
all_values[12]	auto[0]	auto[0]	auto[0]	56	1			T231	1		T234	4		T235	1
all_values[12]	auto[0]	auto[0]	auto[1]	28	1			T231	1		T236	1		T233	1
all_values[12]	auto[0]	auto[1]	auto[0]	49	1			T231	4		T235	1		T369	1
all_values[12]	auto[0]	auto[1]	auto[1]	23	1			T235	1		T233	1		T333	1
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T231	1		T234	1		T236	2
all_values[12]	auto[1]	auto[1]	auto[1]	51	1			T234	2		T235	1		T236	1
all_values[13]	auto[0]	auto[0]	auto[0]	76	1			T231	1		T234	1		T235	4
all_values[13]	auto[0]	auto[0]	auto[1]	24	1			T233	2		T366	2		T369	2
all_values[13]	auto[0]	auto[1]	auto[0]	48	1			T231	1		T236	2		T233	1
all_values[13]	auto[0]	auto[1]	auto[1]	22	1			T231	2		T234	2		T232	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1			T231	2		T234	2		T232	1
all_values[13]	auto[1]	auto[1]	auto[1]	33	1			T231	1		T234	2		T232	1
all_values[14]	auto[0]	auto[0]	auto[0]	55	1			T234	1		T235	3		T236	1
all_values[14]	auto[0]	auto[0]	auto[1]	20	1			T234	1		T236	1		T233	2
all_values[14]	auto[0]	auto[1]	auto[0]	47	1			T231	5		T235	1		T232	2
all_values[14]	auto[0]	auto[1]	auto[1]	39	1			T231	1		T234	1		T233	1
all_values[14]	auto[1]	auto[0]	auto[1]	54	1			T231	1		T234	2		T236	1
all_values[14]	auto[1]	auto[1]	auto[1]	54	1			T234	2		T236	1		T232	2
all_values[15]	auto[0]	auto[0]	auto[0]	70	1			T231	2		T234	2		T235	3
all_values[15]	auto[0]	auto[0]	auto[1]	26	1			T234	1		T232	1		T233	2
all_values[15]	auto[0]	auto[1]	auto[0]	54	1			T231	1		T234	2		T235	1
all_values[15]	auto[0]	auto[1]	auto[1]	14	1			T231	1		T232	2		T233	1
all_values[15]	auto[1]	auto[0]	auto[1]	63	1			T231	2		T234	2		T236	1
all_values[15]	auto[1]	auto[1]	auto[1]	42	1			T231	1		T232	2		T367	3
all_values[16]	auto[0]	auto[0]	auto[0]	68	1			T231	5		T234	3		T235	2
all_values[16]	auto[0]	auto[0]	auto[1]	23	1			T234	1		T235	1		T236	1
all_values[16]	auto[0]	auto[1]	auto[0]	47	1			T236	2		T233	2		T366	1
all_values[16]	auto[0]	auto[1]	auto[1]	20	1			T335	1		T336	2		T370	1
all_values[16]	auto[1]	auto[0]	auto[1]	77	1			T231	2		T234	2		T235	1
all_values[16]	auto[1]	auto[1]	auto[1]	34	1			T234	1		T232	1		T333	1
all_values[17]	auto[0]	auto[0]	auto[0]	89	1			T231	1		T234	2		T235	2
all_values[17]	auto[0]	auto[1]	auto[0]	74	1			T231	3		T235	1		T236	1
all_values[17]	auto[1]	auto[0]	auto[1]	66	1			T231	2		T234	3		T235	1
all_values[17]	auto[1]	auto[1]	auto[1]	40	1			T231	1		T234	2		T236	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal